Module Definition
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Module : usb_fs_nb_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe 100.00 100.00 100.00 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.50 96.68 91.32 70.27 94.24 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.06 96.55 92.77 90.91 100.00 usbdev_impl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_usb_fs_nb_in_pe 90.08 95.83 89.57 75.00 90.00 100.00
u_usb_fs_nb_out_pe 90.91 93.65 82.84 87.50 90.57 100.00
u_usb_fs_rx 99.03 100.00 97.09 100.00
u_usb_fs_tx 87.66 95.61 91.38 58.82 92.50 100.00
u_usb_fs_tx_mux 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_pe
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN16611100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
166 1 1
169 1 1
171 1 1
172 1 1
176 1 1


Cond Coverage for Module : usb_fs_nb_pe
TotalCoveredPercent
Conditions1212100.00
Logical1212100.00
Non-Logical00
Event00

 LINE       166
 EXPRESSION (rx_pkt_end & rx_pid_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------
-1--2--3-StatusTests
011CoveredT25,T27,T33
101CoveredT74,T61
110CoveredT1,T2,T3
111CoveredT18,T48,T49

 LINE       166
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T27,T33

 LINE       169
 EXPRESSION (rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------
-1--2--3-StatusTests
011CoveredT18,T48,T49
101CoveredT74,T61
110CoveredT1,T2,T3
111CoveredT18,T48,T49

 LINE       169
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T27,T33

Assert Coverage for Module : usb_fs_nb_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumOutEpsEqualsNumInEps_A 1867 1867 0 0
ParamMaxPktSizeByteValid 1867 1867 0 0
ParamNumEpsOutAndInEqual 1867 1867 0 0
ParamNumInEpsValid 1867 1867 0 0
ParamNumOutEpsValid 1867 1867 0 0


NumOutEpsEqualsNumInEps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1867 1867 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

ParamMaxPktSizeByteValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 1867 1867 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

ParamNumEpsOutAndInEqual
NameAttemptsReal SuccessesFailuresIncomplete
Total 1867 1867 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

ParamNumInEpsValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 1867 1867 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

ParamNumOutEpsValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 1867 1867 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T25 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T39 1 1 0 0
T40 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%