Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.59 97.44 92.03 97.86 70.31 95.72 98.17 96.58


Total test records in report: 2042
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T1823 /workspace/coverage/default/44.usbdev_out_iso.3940979143 May 26 01:38:08 PM PDT 24 May 26 01:38:24 PM PDT 24 10087811476 ps
T1824 /workspace/coverage/default/22.usbdev_out_iso.3607524238 May 26 01:34:41 PM PDT 24 May 26 01:34:57 PM PDT 24 10143124532 ps
T1825 /workspace/coverage/default/41.usbdev_out_trans_nak.15774275 May 26 01:37:38 PM PDT 24 May 26 01:37:55 PM PDT 24 10092639563 ps
T1826 /workspace/coverage/default/5.usbdev_aon_wake_resume.3539937346 May 26 01:28:42 PM PDT 24 May 26 01:29:02 PM PDT 24 13296157217 ps
T1827 /workspace/coverage/default/48.usbdev_link_suspend.1564430207 May 26 01:38:42 PM PDT 24 May 26 01:39:03 PM PDT 24 13161889588 ps
T1828 /workspace/coverage/default/38.usbdev_endpoint_access.1269934767 May 26 01:37:19 PM PDT 24 May 26 01:37:36 PM PDT 24 10701207190 ps
T1829 /workspace/coverage/default/30.usbdev_fifo_rst.2248353923 May 26 01:35:53 PM PDT 24 May 26 01:36:09 PM PDT 24 10051680949 ps
T1830 /workspace/coverage/default/21.usbdev_pkt_sent.1454470018 May 26 01:34:39 PM PDT 24 May 26 01:34:55 PM PDT 24 10074114556 ps
T1831 /workspace/coverage/default/42.usbdev_smoke.2815687664 May 26 01:37:42 PM PDT 24 May 26 01:37:58 PM PDT 24 10123758673 ps
T1832 /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.1953999808 May 26 01:34:46 PM PDT 24 May 26 01:35:03 PM PDT 24 10085589235 ps
T1833 /workspace/coverage/default/37.usbdev_pkt_buffer.3799373258 May 26 01:37:04 PM PDT 24 May 26 01:37:55 PM PDT 24 25817905276 ps
T180 /workspace/coverage/default/35.usbdev_pending_in_trans.3469651193 May 26 01:36:42 PM PDT 24 May 26 01:36:59 PM PDT 24 10074731158 ps
T1834 /workspace/coverage/default/26.usbdev_in_trans.1984081170 May 26 01:35:20 PM PDT 24 May 26 01:35:36 PM PDT 24 10180725505 ps
T1835 /workspace/coverage/default/48.max_length_in_transaction.2433705045 May 26 01:38:43 PM PDT 24 May 26 01:38:57 PM PDT 24 10163536099 ps
T1836 /workspace/coverage/default/21.usbdev_max_length_out_transaction.3925311936 May 26 01:34:30 PM PDT 24 May 26 01:34:46 PM PDT 24 10103237534 ps
T1837 /workspace/coverage/default/3.usbdev_bitstuff_err.1033946904 May 26 01:27:49 PM PDT 24 May 26 01:28:05 PM PDT 24 10116152990 ps
T1838 /workspace/coverage/default/31.max_length_in_transaction.678723958 May 26 01:36:19 PM PDT 24 May 26 01:36:33 PM PDT 24 10134741724 ps
T1839 /workspace/coverage/default/35.usbdev_disconnected.4106802842 May 26 01:36:41 PM PDT 24 May 26 01:36:57 PM PDT 24 10032433072 ps
T1840 /workspace/coverage/default/40.usbdev_random_length_out_trans.3930933676 May 26 01:37:33 PM PDT 24 May 26 01:37:48 PM PDT 24 10109596853 ps
T1841 /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.486163193 May 26 01:35:40 PM PDT 24 May 26 01:35:55 PM PDT 24 10115410636 ps
T1842 /workspace/coverage/default/7.usbdev_pending_in_trans.4107053085 May 26 01:29:53 PM PDT 24 May 26 01:30:07 PM PDT 24 10059128169 ps
T1843 /workspace/coverage/default/46.usbdev_pkt_buffer.1750241593 May 26 01:38:32 PM PDT 24 May 26 01:39:34 PM PDT 24 32423537250 ps
T1844 /workspace/coverage/default/21.usbdev_enable.2907860627 May 26 01:34:29 PM PDT 24 May 26 01:34:47 PM PDT 24 10056157002 ps
T1845 /workspace/coverage/default/13.usbdev_aon_wake_reset.728204664 May 26 01:32:06 PM PDT 24 May 26 01:32:26 PM PDT 24 13309722709 ps
T1846 /workspace/coverage/default/31.usbdev_aon_wake_reset.1869300260 May 26 01:36:05 PM PDT 24 May 26 01:36:23 PM PDT 24 13191600401 ps
T1847 /workspace/coverage/default/2.usbdev_pending_in_trans.3607094943 May 26 01:27:28 PM PDT 24 May 26 01:27:43 PM PDT 24 10095202007 ps
T1848 /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1990888605 May 26 01:38:32 PM PDT 24 May 26 01:38:50 PM PDT 24 13720523373 ps
T1849 /workspace/coverage/default/8.usbdev_out_stall.69350124 May 26 01:30:03 PM PDT 24 May 26 01:30:18 PM PDT 24 10104941724 ps
T1850 /workspace/coverage/default/22.usbdev_aon_wake_reset.3301345844 May 26 01:34:39 PM PDT 24 May 26 01:34:57 PM PDT 24 13367621246 ps
T1851 /workspace/coverage/default/24.usbdev_setup_trans_ignored.3893000814 May 26 01:35:03 PM PDT 24 May 26 01:35:18 PM PDT 24 10059326675 ps
T1852 /workspace/coverage/default/4.usbdev_aon_wake_resume.3080529130 May 26 01:28:16 PM PDT 24 May 26 01:28:38 PM PDT 24 13268758637 ps
T1853 /workspace/coverage/default/43.usbdev_fifo_rst.1449956309 May 26 01:38:02 PM PDT 24 May 26 01:38:17 PM PDT 24 10055728187 ps
T1854 /workspace/coverage/default/1.usbdev_pkt_sent.1964181896 May 26 01:26:56 PM PDT 24 May 26 01:27:12 PM PDT 24 10087987344 ps
T1855 /workspace/coverage/default/15.usbdev_setup_trans_ignored.259796945 May 26 01:33:10 PM PDT 24 May 26 01:33:26 PM PDT 24 10102587852 ps
T1856 /workspace/coverage/default/12.usbdev_min_length_out_transaction.384300538 May 26 01:31:43 PM PDT 24 May 26 01:32:00 PM PDT 24 10062154777 ps
T1857 /workspace/coverage/default/45.usbdev_setup_trans_ignored.2565336779 May 26 01:38:20 PM PDT 24 May 26 01:38:36 PM PDT 24 10042866344 ps
T1858 /workspace/coverage/default/29.usbdev_aon_wake_resume.2536788864 May 26 01:35:48 PM PDT 24 May 26 01:36:09 PM PDT 24 13425675073 ps
T1859 /workspace/coverage/default/13.usbdev_phy_pins_sense.4081119327 May 26 01:32:22 PM PDT 24 May 26 01:32:36 PM PDT 24 10042191597 ps
T1860 /workspace/coverage/default/3.usbdev_in_stall.1787347346 May 26 01:28:08 PM PDT 24 May 26 01:28:26 PM PDT 24 10057127603 ps
T1861 /workspace/coverage/default/44.usbdev_pending_in_trans.4088840991 May 26 01:38:08 PM PDT 24 May 26 01:38:25 PM PDT 24 10113329672 ps
T1862 /workspace/coverage/default/42.usbdev_setup_stage.4097692647 May 26 01:37:54 PM PDT 24 May 26 01:38:08 PM PDT 24 10073070767 ps
T1863 /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4079251279 May 26 01:38:20 PM PDT 24 May 26 01:38:40 PM PDT 24 14045979764 ps
T1864 /workspace/coverage/default/41.usbdev_smoke.688801679 May 26 01:37:37 PM PDT 24 May 26 01:37:55 PM PDT 24 10187060552 ps
T1865 /workspace/coverage/default/12.usbdev_out_stall.398132877 May 26 01:31:47 PM PDT 24 May 26 01:32:04 PM PDT 24 10098989474 ps
T1866 /workspace/coverage/default/23.usbdev_link_in_err.8310452 May 26 01:34:47 PM PDT 24 May 26 01:35:03 PM PDT 24 10056041630 ps
T1867 /workspace/coverage/default/13.usbdev_pkt_sent.1149024665 May 26 01:32:17 PM PDT 24 May 26 01:32:36 PM PDT 24 10137486776 ps
T1868 /workspace/coverage/default/3.usbdev_out_iso.426526790 May 26 01:28:15 PM PDT 24 May 26 01:28:30 PM PDT 24 10119904089 ps
T1869 /workspace/coverage/default/35.usbdev_random_length_out_trans.596108323 May 26 01:36:44 PM PDT 24 May 26 01:36:58 PM PDT 24 10099504581 ps
T1870 /workspace/coverage/default/26.usbdev_data_toggle_restore.3407543872 May 26 01:35:26 PM PDT 24 May 26 01:35:42 PM PDT 24 11258606101 ps
T1871 /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.429768281 May 26 01:37:27 PM PDT 24 May 26 01:37:43 PM PDT 24 10092065477 ps
T1872 /workspace/coverage/default/19.random_length_in_trans.3903735926 May 26 01:34:14 PM PDT 24 May 26 01:34:30 PM PDT 24 10103063342 ps
T1873 /workspace/coverage/default/32.usbdev_aon_wake_resume.2345434144 May 26 01:36:18 PM PDT 24 May 26 01:36:36 PM PDT 24 13214750573 ps
T1874 /workspace/coverage/default/5.usbdev_pkt_received.626225504 May 26 01:28:50 PM PDT 24 May 26 01:29:05 PM PDT 24 10064180714 ps
T165 /workspace/coverage/default/26.usbdev_pending_in_trans.384037945 May 26 01:35:24 PM PDT 24 May 26 01:35:37 PM PDT 24 10079008478 ps
T1875 /workspace/coverage/default/21.usbdev_smoke.3167867471 May 26 01:34:28 PM PDT 24 May 26 01:34:43 PM PDT 24 10131337249 ps
T1876 /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3657537551 May 26 01:30:12 PM PDT 24 May 26 01:30:26 PM PDT 24 10039482058 ps
T1877 /workspace/coverage/default/2.usbdev_endpoint_access.3693289013 May 26 01:27:14 PM PDT 24 May 26 01:27:30 PM PDT 24 10806356949 ps
T1878 /workspace/coverage/default/14.usbdev_nak_trans.261024951 May 26 01:32:37 PM PDT 24 May 26 01:32:52 PM PDT 24 10122692844 ps
T1879 /workspace/coverage/default/24.usbdev_enable.2208501451 May 26 01:35:06 PM PDT 24 May 26 01:35:19 PM PDT 24 10066500484 ps
T1880 /workspace/coverage/default/45.usbdev_pkt_received.3636720857 May 26 01:38:20 PM PDT 24 May 26 01:38:36 PM PDT 24 10081865218 ps
T1881 /workspace/coverage/default/0.usbdev_pkt_sent.1707811236 May 26 01:26:23 PM PDT 24 May 26 01:26:41 PM PDT 24 10056214061 ps
T1882 /workspace/coverage/default/23.usbdev_min_length_out_transaction.2668672146 May 26 01:34:47 PM PDT 24 May 26 01:35:02 PM PDT 24 10053511359 ps
T1883 /workspace/coverage/default/23.usbdev_setup_stage.1221143548 May 26 01:34:55 PM PDT 24 May 26 01:35:11 PM PDT 24 10046964236 ps
T1884 /workspace/coverage/default/29.usbdev_phy_pins_sense.4280866527 May 26 01:35:56 PM PDT 24 May 26 01:36:10 PM PDT 24 10042530943 ps
T1885 /workspace/coverage/default/19.usbdev_pending_in_trans.687773593 May 26 01:34:11 PM PDT 24 May 26 01:34:28 PM PDT 24 10090736329 ps
T1886 /workspace/coverage/default/40.usbdev_in_trans.3767039343 May 26 01:37:42 PM PDT 24 May 26 01:37:58 PM PDT 24 10141358969 ps
T1887 /workspace/coverage/default/26.usbdev_pkt_received.239332426 May 26 01:35:21 PM PDT 24 May 26 01:35:38 PM PDT 24 10077176672 ps
T1888 /workspace/coverage/default/36.usbdev_stall_trans.1006859355 May 26 01:36:52 PM PDT 24 May 26 01:37:07 PM PDT 24 10086921265 ps
T1889 /workspace/coverage/default/33.random_length_in_trans.2502537166 May 26 01:36:37 PM PDT 24 May 26 01:36:53 PM PDT 24 10104282601 ps
T1890 /workspace/coverage/default/21.usbdev_in_iso.21393133 May 26 01:34:44 PM PDT 24 May 26 01:34:58 PM PDT 24 10114183994 ps
T1891 /workspace/coverage/default/37.usbdev_in_stall.3089582760 May 26 01:37:08 PM PDT 24 May 26 01:37:22 PM PDT 24 10038758654 ps
T1892 /workspace/coverage/default/29.max_length_in_transaction.3280433443 May 26 01:35:54 PM PDT 24 May 26 01:36:12 PM PDT 24 10157745005 ps
T1893 /workspace/coverage/default/26.usbdev_aon_wake_reset.3362536734 May 26 01:35:22 PM PDT 24 May 26 01:35:41 PM PDT 24 13237167274 ps
T1894 /workspace/coverage/default/2.max_length_in_transaction.2433059508 May 26 01:27:39 PM PDT 24 May 26 01:27:57 PM PDT 24 10194532837 ps
T1895 /workspace/coverage/default/49.usbdev_av_buffer.1544912484 May 26 01:38:48 PM PDT 24 May 26 01:39:05 PM PDT 24 10050975628 ps
T1896 /workspace/coverage/default/1.usbdev_data_toggle_restore.3220674848 May 26 01:26:42 PM PDT 24 May 26 01:26:57 PM PDT 24 10625961888 ps
T1897 /workspace/coverage/default/37.usbdev_link_in_err.3449234176 May 26 01:37:00 PM PDT 24 May 26 01:37:14 PM PDT 24 10123702071 ps
T1898 /workspace/coverage/default/4.max_length_in_transaction.1100935143 May 26 01:28:32 PM PDT 24 May 26 01:28:49 PM PDT 24 10221007674 ps
T1899 /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.1547771749 May 26 01:37:20 PM PDT 24 May 26 01:37:33 PM PDT 24 10067664341 ps
T1900 /workspace/coverage/default/41.usbdev_pending_in_trans.3736491980 May 26 01:37:42 PM PDT 24 May 26 01:37:59 PM PDT 24 10082880249 ps
T1901 /workspace/coverage/default/15.usbdev_stall_priority_over_nak.692815597 May 26 01:33:11 PM PDT 24 May 26 01:33:26 PM PDT 24 10083487853 ps
T1902 /workspace/coverage/default/23.usbdev_phy_pins_sense.1729363203 May 26 01:34:56 PM PDT 24 May 26 01:35:11 PM PDT 24 10042519558 ps
T1903 /workspace/coverage/default/34.usbdev_smoke.128462511 May 26 01:36:34 PM PDT 24 May 26 01:36:51 PM PDT 24 10123710528 ps
T1904 /workspace/coverage/default/19.usbdev_av_buffer.6148391 May 26 01:34:11 PM PDT 24 May 26 01:34:29 PM PDT 24 10057881978 ps
T1905 /workspace/coverage/default/40.usbdev_av_buffer.915121691 May 26 01:37:28 PM PDT 24 May 26 01:37:43 PM PDT 24 10069276116 ps
T1906 /workspace/coverage/default/1.usbdev_endpoint_access.3155491852 May 26 01:26:39 PM PDT 24 May 26 01:26:56 PM PDT 24 10747597761 ps
T1907 /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2741702141 May 26 01:35:55 PM PDT 24 May 26 01:36:11 PM PDT 24 10072133222 ps
T1908 /workspace/coverage/default/47.usbdev_av_buffer.2573055036 May 26 01:38:33 PM PDT 24 May 26 01:38:49 PM PDT 24 10049586924 ps
T1909 /workspace/coverage/default/16.usbdev_min_length_out_transaction.3091004764 May 26 01:33:30 PM PDT 24 May 26 01:33:46 PM PDT 24 10045167746 ps
T1910 /workspace/coverage/default/19.usbdev_aon_wake_reset.454447452 May 26 01:34:12 PM PDT 24 May 26 01:34:32 PM PDT 24 13295393417 ps
T1911 /workspace/coverage/default/2.usbdev_nak_trans.1217521691 May 26 01:27:23 PM PDT 24 May 26 01:27:38 PM PDT 24 10148649532 ps
T1912 /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2465806386 May 26 01:38:44 PM PDT 24 May 26 01:38:59 PM PDT 24 10100121282 ps
T1913 /workspace/coverage/default/43.usbdev_out_iso.1248996094 May 26 01:37:52 PM PDT 24 May 26 01:38:08 PM PDT 24 10093502201 ps
T1914 /workspace/coverage/default/22.usbdev_phy_pins_sense.357167196 May 26 01:34:45 PM PDT 24 May 26 01:34:59 PM PDT 24 10058786126 ps
T1915 /workspace/coverage/default/24.usbdev_min_length_out_transaction.605617643 May 26 01:35:03 PM PDT 24 May 26 01:35:20 PM PDT 24 10070083348 ps
T1916 /workspace/coverage/default/38.usbdev_in_stall.562976838 May 26 01:37:18 PM PDT 24 May 26 01:37:33 PM PDT 24 10060570137 ps
T1917 /workspace/coverage/default/16.usbdev_setup_stage.1612550570 May 26 01:33:34 PM PDT 24 May 26 01:33:48 PM PDT 24 10079922219 ps
T1918 /workspace/coverage/default/48.usbdev_setup_stage.258404408 May 26 01:38:46 PM PDT 24 May 26 01:39:02 PM PDT 24 10062418530 ps
T1919 /workspace/coverage/default/7.usbdev_pkt_sent.1786488610 May 26 01:29:47 PM PDT 24 May 26 01:30:04 PM PDT 24 10151045138 ps
T1920 /workspace/coverage/default/30.usbdev_av_buffer.4201560553 May 26 01:35:52 PM PDT 24 May 26 01:36:07 PM PDT 24 10057265736 ps
T1921 /workspace/coverage/default/47.usbdev_max_length_out_transaction.240031421 May 26 01:38:33 PM PDT 24 May 26 01:38:50 PM PDT 24 10083015064 ps
T1922 /workspace/coverage/default/38.usbdev_out_trans_nak.2508428662 May 26 01:37:16 PM PDT 24 May 26 01:37:34 PM PDT 24 10059525734 ps
T126 /workspace/coverage/default/0.usbdev_nak_trans.2905353848 May 26 01:26:17 PM PDT 24 May 26 01:26:34 PM PDT 24 10153645854 ps
T1923 /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1189938128 May 26 01:28:25 PM PDT 24 May 26 01:28:41 PM PDT 24 10078141898 ps
T1924 /workspace/coverage/default/7.usbdev_link_suspend.2861180309 May 26 01:29:32 PM PDT 24 May 26 01:29:56 PM PDT 24 13252130272 ps
T1925 /workspace/coverage/default/8.usbdev_data_toggle_restore.2018361773 May 26 01:30:03 PM PDT 24 May 26 01:30:21 PM PDT 24 11128120457 ps
T1926 /workspace/coverage/default/30.usbdev_in_stall.3584564393 May 26 01:36:06 PM PDT 24 May 26 01:36:23 PM PDT 24 10087152141 ps
T1927 /workspace/coverage/default/46.usbdev_out_trans_nak.2118468481 May 26 01:38:31 PM PDT 24 May 26 01:38:46 PM PDT 24 10097241550 ps
T1928 /workspace/coverage/default/16.random_length_in_trans.712783374 May 26 01:33:45 PM PDT 24 May 26 01:34:00 PM PDT 24 10128700399 ps
T1929 /workspace/coverage/default/45.usbdev_out_iso.1632680537 May 26 01:38:18 PM PDT 24 May 26 01:38:34 PM PDT 24 10081004208 ps
T1930 /workspace/coverage/default/5.usbdev_out_iso.2994151733 May 26 01:28:50 PM PDT 24 May 26 01:29:06 PM PDT 24 10082057333 ps
T1931 /workspace/coverage/default/46.usbdev_data_toggle_restore.842719163 May 26 01:38:17 PM PDT 24 May 26 01:38:35 PM PDT 24 10648560336 ps
T1932 /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2979554257 May 26 01:31:10 PM PDT 24 May 26 01:31:32 PM PDT 24 13781453626 ps
T1933 /workspace/coverage/default/45.random_length_in_trans.2792737941 May 26 01:38:20 PM PDT 24 May 26 01:38:36 PM PDT 24 10121407100 ps
T1934 /workspace/coverage/default/30.usbdev_smoke.367524848 May 26 01:35:54 PM PDT 24 May 26 01:36:10 PM PDT 24 10162222334 ps
T1935 /workspace/coverage/default/34.usbdev_fifo_rst.2867450448 May 26 01:36:35 PM PDT 24 May 26 01:36:55 PM PDT 24 10253917212 ps
T1936 /workspace/coverage/default/36.usbdev_enable.4248293350 May 26 01:36:52 PM PDT 24 May 26 01:37:07 PM PDT 24 10079309183 ps
T96 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3217659337 May 26 02:18:38 PM PDT 24 May 26 02:18:39 PM PDT 24 41896566 ps
T207 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2502444267 May 26 02:18:50 PM PDT 24 May 26 02:18:53 PM PDT 24 211110918 ps
T97 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4175550154 May 26 02:18:56 PM PDT 24 May 26 02:18:58 PM PDT 24 48448124 ps
T208 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.433900680 May 26 02:18:41 PM PDT 24 May 26 02:18:43 PM PDT 24 110017693 ps
T210 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.222216301 May 26 02:18:36 PM PDT 24 May 26 02:18:38 PM PDT 24 248463305 ps
T212 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2160736398 May 26 02:18:42 PM PDT 24 May 26 02:18:44 PM PDT 24 57656253 ps
T211 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2784762219 May 26 02:18:27 PM PDT 24 May 26 02:18:33 PM PDT 24 841365080 ps
T98 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2835020962 May 26 02:18:29 PM PDT 24 May 26 02:18:31 PM PDT 24 261814272 ps
T209 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4020840145 May 26 02:18:34 PM PDT 24 May 26 02:18:37 PM PDT 24 178888958 ps
T228 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1215653789 May 26 02:18:33 PM PDT 24 May 26 02:18:36 PM PDT 24 80585136 ps
T99 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2058501558 May 26 02:19:03 PM PDT 24 May 26 02:19:05 PM PDT 24 65605747 ps
T214 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1595070378 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 35873628 ps
T215 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.667163951 May 26 02:18:50 PM PDT 24 May 26 02:18:52 PM PDT 24 39951372 ps
T213 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3054580857 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 63449004 ps
T234 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1859638614 May 26 02:19:04 PM PDT 24 May 26 02:19:07 PM PDT 24 252231174 ps
T231 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3736222050 May 26 02:18:36 PM PDT 24 May 26 02:18:40 PM PDT 24 884202818 ps
T273 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.389185097 May 26 02:18:44 PM PDT 24 May 26 02:18:47 PM PDT 24 215952467 ps
T261 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1650140049 May 26 02:18:27 PM PDT 24 May 26 02:18:30 PM PDT 24 63771547 ps
T262 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.527191267 May 26 02:18:31 PM PDT 24 May 26 02:18:34 PM PDT 24 83384683 ps
T281 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.627697986 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 58775682 ps
T263 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1917623432 May 26 02:18:33 PM PDT 24 May 26 02:18:35 PM PDT 24 41343642 ps
T282 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.389193412 May 26 02:18:29 PM PDT 24 May 26 02:18:31 PM PDT 24 43986741 ps
T283 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2588103152 May 26 02:18:48 PM PDT 24 May 26 02:18:49 PM PDT 24 69973276 ps
T274 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1427696776 May 26 02:18:40 PM PDT 24 May 26 02:18:42 PM PDT 24 167761530 ps
T264 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.552700616 May 26 02:18:34 PM PDT 24 May 26 02:18:37 PM PDT 24 195453676 ps
T232 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2006812505 May 26 02:18:28 PM PDT 24 May 26 02:18:33 PM PDT 24 536572394 ps
T265 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.720136363 May 26 02:18:34 PM PDT 24 May 26 02:18:37 PM PDT 24 164336174 ps
T266 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4001540773 May 26 02:18:45 PM PDT 24 May 26 02:18:47 PM PDT 24 119443953 ps
T284 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4081081351 May 26 02:18:49 PM PDT 24 May 26 02:18:51 PM PDT 24 35594495 ps
T275 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3614623261 May 26 02:18:41 PM PDT 24 May 26 02:18:44 PM PDT 24 274919783 ps
T287 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2071614353 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 33586919 ps
T237 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1237361743 May 26 02:18:46 PM PDT 24 May 26 02:18:50 PM PDT 24 100224585 ps
T276 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3449514391 May 26 02:18:33 PM PDT 24 May 26 02:18:36 PM PDT 24 265811310 ps
T290 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2747193468 May 26 02:18:29 PM PDT 24 May 26 02:18:31 PM PDT 24 58579892 ps
T267 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3628014466 May 26 02:18:34 PM PDT 24 May 26 02:18:38 PM PDT 24 381370729 ps
T235 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3338576420 May 26 02:18:46 PM PDT 24 May 26 02:18:51 PM PDT 24 801556811 ps
T277 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1375892036 May 26 02:18:34 PM PDT 24 May 26 02:18:36 PM PDT 24 88378421 ps
T242 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3643659440 May 26 02:18:35 PM PDT 24 May 26 02:18:40 PM PDT 24 494229909 ps
T268 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.777636180 May 26 02:18:35 PM PDT 24 May 26 02:18:37 PM PDT 24 121696914 ps
T272 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.975101898 May 26 02:18:50 PM PDT 24 May 26 02:18:51 PM PDT 24 101999395 ps
T269 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1110035762 May 26 02:18:51 PM PDT 24 May 26 02:18:54 PM PDT 24 136235874 ps
T238 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.61030590 May 26 02:18:27 PM PDT 24 May 26 02:18:31 PM PDT 24 114332878 ps
T239 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3649585428 May 26 02:18:28 PM PDT 24 May 26 02:18:33 PM PDT 24 102595779 ps
T270 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.4275138115 May 26 02:18:28 PM PDT 24 May 26 02:18:30 PM PDT 24 45404284 ps
T285 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3560467374 May 26 02:18:56 PM PDT 24 May 26 02:18:58 PM PDT 24 94115826 ps
T286 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.348634608 May 26 02:18:43 PM PDT 24 May 26 02:18:46 PM PDT 24 58617933 ps
T1937 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1297661320 May 26 02:18:33 PM PDT 24 May 26 02:18:34 PM PDT 24 33031921 ps
T1938 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.132558129 May 26 02:18:43 PM PDT 24 May 26 02:18:45 PM PDT 24 43311750 ps
T1939 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3453178431 May 26 02:18:59 PM PDT 24 May 26 02:19:02 PM PDT 24 56199219 ps
T299 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.20708397 May 26 02:18:31 PM PDT 24 May 26 02:18:35 PM PDT 24 490844970 ps
T1940 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.276537699 May 26 02:18:57 PM PDT 24 May 26 02:18:59 PM PDT 24 49649694 ps
T243 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2915560147 May 26 02:18:46 PM PDT 24 May 26 02:18:48 PM PDT 24 111937361 ps
T1941 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.625710171 May 26 02:18:43 PM PDT 24 May 26 02:18:46 PM PDT 24 36252898 ps
T244 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3998354380 May 26 02:18:30 PM PDT 24 May 26 02:18:36 PM PDT 24 1061694390 ps
T245 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.946388703 May 26 02:18:36 PM PDT 24 May 26 02:18:38 PM PDT 24 134657927 ps
T305 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.482088414 May 26 02:18:49 PM PDT 24 May 26 02:18:53 PM PDT 24 445047872 ps
T291 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3624579164 May 26 02:18:57 PM PDT 24 May 26 02:18:58 PM PDT 24 55106208 ps
T288 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1198936428 May 26 02:18:52 PM PDT 24 May 26 02:18:53 PM PDT 24 61630364 ps
T1942 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3614071748 May 26 02:18:31 PM PDT 24 May 26 02:18:32 PM PDT 24 110488921 ps
T240 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3809013841 May 26 02:18:35 PM PDT 24 May 26 02:18:39 PM PDT 24 347191605 ps
T1943 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.861385125 May 26 02:18:35 PM PDT 24 May 26 02:18:38 PM PDT 24 91584431 ps
T295 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2628980661 May 26 02:18:57 PM PDT 24 May 26 02:18:59 PM PDT 24 46358889 ps
T1944 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2600997295 May 26 02:18:25 PM PDT 24 May 26 02:18:27 PM PDT 24 68245168 ps
T289 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1822532450 May 26 02:18:28 PM PDT 24 May 26 02:18:30 PM PDT 24 35850226 ps
T296 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1764859290 May 26 02:18:42 PM PDT 24 May 26 02:18:44 PM PDT 24 74089575 ps
T294 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3387300688 May 26 02:18:58 PM PDT 24 May 26 02:19:00 PM PDT 24 48088698 ps
T1945 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.802990168 May 26 02:18:29 PM PDT 24 May 26 02:18:33 PM PDT 24 485595089 ps
T1946 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3714581587 May 26 02:18:43 PM PDT 24 May 26 02:18:46 PM PDT 24 109179874 ps
T1947 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3678456390 May 26 02:18:42 PM PDT 24 May 26 02:18:48 PM PDT 24 1290607615 ps
T271 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2371372440 May 26 02:18:34 PM PDT 24 May 26 02:18:37 PM PDT 24 132741994 ps
T1948 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.496685173 May 26 02:18:27 PM PDT 24 May 26 02:18:29 PM PDT 24 116298748 ps
T1949 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4036382327 May 26 02:18:51 PM PDT 24 May 26 02:18:55 PM PDT 24 201459335 ps
T1950 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2484345796 May 26 02:18:25 PM PDT 24 May 26 02:18:29 PM PDT 24 180625908 ps
T1951 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1152476939 May 26 02:18:44 PM PDT 24 May 26 02:18:47 PM PDT 24 145307447 ps
T1952 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.568445437 May 26 02:18:37 PM PDT 24 May 26 02:18:39 PM PDT 24 70059115 ps
T1953 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.998733312 May 26 02:18:27 PM PDT 24 May 26 02:18:31 PM PDT 24 307952918 ps
T303 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3279500575 May 26 02:18:43 PM PDT 24 May 26 02:18:49 PM PDT 24 718734203 ps
T1954 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2530353804 May 26 02:18:46 PM PDT 24 May 26 02:18:48 PM PDT 24 84319523 ps
T1955 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2105652842 May 26 02:18:56 PM PDT 24 May 26 02:18:58 PM PDT 24 74093615 ps
T1956 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.282336986 May 26 02:18:39 PM PDT 24 May 26 02:18:41 PM PDT 24 131057088 ps
T1957 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1669128662 May 26 02:18:50 PM PDT 24 May 26 02:18:53 PM PDT 24 65430605 ps
T292 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2308325989 May 26 02:18:48 PM PDT 24 May 26 02:18:50 PM PDT 24 48653123 ps
T1958 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3623666814 May 26 02:18:51 PM PDT 24 May 26 02:18:54 PM PDT 24 153774321 ps
T1959 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.217226168 May 26 02:18:34 PM PDT 24 May 26 02:18:40 PM PDT 24 1355593675 ps
T1960 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1533265867 May 26 02:18:58 PM PDT 24 May 26 02:19:00 PM PDT 24 32861507 ps
T302 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3091085705 May 26 02:19:04 PM PDT 24 May 26 02:19:10 PM PDT 24 909526797 ps
T1961 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1909406841 May 26 02:19:03 PM PDT 24 May 26 02:19:04 PM PDT 24 108362679 ps
T1962 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4046629358 May 26 02:18:32 PM PDT 24 May 26 02:18:36 PM PDT 24 177433240 ps
T1963 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1805472585 May 26 02:18:34 PM PDT 24 May 26 02:18:38 PM PDT 24 147381208 ps
T300 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2621468711 May 26 02:19:04 PM PDT 24 May 26 02:19:10 PM PDT 24 635853563 ps
T1964 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.503755370 May 26 02:18:52 PM PDT 24 May 26 02:18:54 PM PDT 24 100709752 ps
T1965 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3712361851 May 26 02:18:42 PM PDT 24 May 26 02:18:45 PM PDT 24 68127400 ps
T1966 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3857968580 May 26 02:18:43 PM PDT 24 May 26 02:18:47 PM PDT 24 177227877 ps
T297 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3177056349 May 26 02:18:51 PM PDT 24 May 26 02:18:55 PM PDT 24 391443102 ps
T1967 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.459126582 May 26 02:18:27 PM PDT 24 May 26 02:18:30 PM PDT 24 126306819 ps
T241 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1055142400 May 26 02:18:46 PM PDT 24 May 26 02:18:52 PM PDT 24 867359919 ps
T1968 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3169993937 May 26 02:18:52 PM PDT 24 May 26 02:18:54 PM PDT 24 57622221 ps
T1969 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1789414213 May 26 02:18:43 PM PDT 24 May 26 02:18:46 PM PDT 24 235222145 ps
T1970 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3735353604 May 26 02:18:48 PM PDT 24 May 26 02:18:51 PM PDT 24 234582181 ps
T1971 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1371510925 May 26 02:19:04 PM PDT 24 May 26 02:19:05 PM PDT 24 73489023 ps
T1972 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.193678624 May 26 02:18:33 PM PDT 24 May 26 02:18:35 PM PDT 24 81546267 ps
T1973 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.837518692 May 26 02:18:25 PM PDT 24 May 26 02:18:27 PM PDT 24 66721949 ps
T1974 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.341194512 May 26 02:18:44 PM PDT 24 May 26 02:18:46 PM PDT 24 44938858 ps
T1975 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4047027810 May 26 02:18:35 PM PDT 24 May 26 02:18:37 PM PDT 24 65137113 ps
T1976 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2868796551 May 26 02:18:38 PM PDT 24 May 26 02:18:40 PM PDT 24 129775609 ps
T1977 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1029007530 May 26 02:18:45 PM PDT 24 May 26 02:18:49 PM PDT 24 111133484 ps
T1978 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.914826250 May 26 02:18:49 PM PDT 24 May 26 02:18:51 PM PDT 24 75672472 ps
T298 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3800316142 May 26 02:19:04 PM PDT 24 May 26 02:19:11 PM PDT 24 1720423878 ps
T1979 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3443545867 May 26 02:18:44 PM PDT 24 May 26 02:18:51 PM PDT 24 1204718244 ps
T1980 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1493258954 May 26 02:18:28 PM PDT 24 May 26 02:18:30 PM PDT 24 97983951 ps
T1981 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.133537426 May 26 02:18:34 PM PDT 24 May 26 02:18:36 PM PDT 24 66151682 ps
T1982 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1872623805 May 26 02:18:43 PM PDT 24 May 26 02:18:48 PM PDT 24 289596835 ps
T1983 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.215453962 May 26 02:18:26 PM PDT 24 May 26 02:18:28 PM PDT 24 195590470 ps
T1984 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3190208697 May 26 02:18:38 PM PDT 24 May 26 02:18:42 PM PDT 24 107028396 ps
T1985 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1146747137 May 26 02:18:29 PM PDT 24 May 26 02:18:38 PM PDT 24 587958120 ps
T1986 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2922252054 May 26 02:18:43 PM PDT 24 May 26 02:18:46 PM PDT 24 54804478 ps
T1987 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3835077308 May 26 02:18:48 PM PDT 24 May 26 02:18:49 PM PDT 24 64463577 ps
T1988 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.700916815 May 26 02:18:47 PM PDT 24 May 26 02:18:49 PM PDT 24 142914844 ps
T1989 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2332981726 May 26 02:18:28 PM PDT 24 May 26 02:18:32 PM PDT 24 341853041 ps
T1990 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1833181527 May 26 02:18:42 PM PDT 24 May 26 02:18:48 PM PDT 24 545998484 ps
T1991 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3489479949 May 26 02:18:48 PM PDT 24 May 26 02:18:51 PM PDT 24 190193837 ps
T1992 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2517122764 May 26 02:18:27 PM PDT 24 May 26 02:18:34 PM PDT 24 736874202 ps
T1993 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1546916619 May 26 02:18:42 PM PDT 24 May 26 02:18:45 PM PDT 24 151470003 ps
T1994 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.964519850 May 26 02:18:38 PM PDT 24 May 26 02:18:42 PM PDT 24 170236361 ps
T1995 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2828068780 May 26 02:18:28 PM PDT 24 May 26 02:18:30 PM PDT 24 81880218 ps
T1996 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3149740126 May 26 02:18:59 PM PDT 24 May 26 02:19:02 PM PDT 24 98998027 ps
T1997 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3982940106 May 26 02:18:38 PM PDT 24 May 26 02:18:39 PM PDT 24 111357868 ps
T1998 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.286758488 May 26 02:18:43 PM PDT 24 May 26 02:18:46 PM PDT 24 191189077 ps
T1999 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1676556483 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 50130370 ps
T2000 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.686161975 May 26 02:18:34 PM PDT 24 May 26 02:18:44 PM PDT 24 1113977608 ps
T2001 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2418874626 May 26 02:19:00 PM PDT 24 May 26 02:19:02 PM PDT 24 43208853 ps
T2002 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4165368639 May 26 02:19:04 PM PDT 24 May 26 02:19:06 PM PDT 24 135824921 ps
T2003 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1446563776 May 26 02:18:55 PM PDT 24 May 26 02:18:57 PM PDT 24 64058266 ps
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