Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.59 97.44 92.03 97.86 70.31 95.72 98.17 96.58


Total test records in report: 2042
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html
T2004 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1224810988 May 26 02:18:50 PM PDT 24 May 26 02:18:52 PM PDT 24 77098131 ps
T293 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2134442917 May 26 02:18:45 PM PDT 24 May 26 02:18:47 PM PDT 24 46813712 ps
T2005 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1984295021 May 26 02:18:41 PM PDT 24 May 26 02:18:43 PM PDT 24 154674211 ps
T2006 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.671401218 May 26 02:18:49 PM PDT 24 May 26 02:18:52 PM PDT 24 81344951 ps
T2007 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.175194472 May 26 02:18:44 PM PDT 24 May 26 02:18:47 PM PDT 24 135595112 ps
T2008 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2547602435 May 26 02:18:39 PM PDT 24 May 26 02:18:41 PM PDT 24 42185204 ps
T2009 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2482452771 May 26 02:18:41 PM PDT 24 May 26 02:18:43 PM PDT 24 94507384 ps
T2010 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1482197298 May 26 02:18:35 PM PDT 24 May 26 02:18:37 PM PDT 24 145237259 ps
T2011 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1099219839 May 26 02:18:56 PM PDT 24 May 26 02:18:58 PM PDT 24 54402001 ps
T2012 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4242168375 May 26 02:19:03 PM PDT 24 May 26 02:19:05 PM PDT 24 219052677 ps
T2013 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3300409549 May 26 02:18:47 PM PDT 24 May 26 02:18:49 PM PDT 24 181442232 ps
T2014 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3732938493 May 26 02:18:43 PM PDT 24 May 26 02:18:47 PM PDT 24 145268655 ps
T2015 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.317892763 May 26 02:18:59 PM PDT 24 May 26 02:19:02 PM PDT 24 35776229 ps
T2016 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2823378749 May 26 02:18:26 PM PDT 24 May 26 02:18:32 PM PDT 24 480392938 ps
T2017 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3761656192 May 26 02:18:56 PM PDT 24 May 26 02:18:57 PM PDT 24 75941964 ps
T2018 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4238699338 May 26 02:18:28 PM PDT 24 May 26 02:18:32 PM PDT 24 148667076 ps
T2019 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2911794218 May 26 02:18:31 PM PDT 24 May 26 02:18:35 PM PDT 24 384569268 ps
T2020 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3427936720 May 26 02:18:41 PM PDT 24 May 26 02:18:44 PM PDT 24 201767366 ps
T2021 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2880657218 May 26 02:18:33 PM PDT 24 May 26 02:18:35 PM PDT 24 66320564 ps
T2022 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.852407294 May 26 02:18:34 PM PDT 24 May 26 02:18:37 PM PDT 24 99959155 ps
T2023 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4027531698 May 26 02:18:33 PM PDT 24 May 26 02:18:34 PM PDT 24 134287615 ps
T2024 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3446684735 May 26 02:18:42 PM PDT 24 May 26 02:18:46 PM PDT 24 85442447 ps
T2025 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2447577588 May 26 02:18:34 PM PDT 24 May 26 02:18:37 PM PDT 24 439731932 ps
T2026 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1607118984 May 26 02:18:49 PM PDT 24 May 26 02:18:51 PM PDT 24 90393691 ps
T2027 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.903381028 May 26 02:18:58 PM PDT 24 May 26 02:19:00 PM PDT 24 39427111 ps
T2028 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4112776900 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 63705128 ps
T2029 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.674029434 May 26 02:18:33 PM PDT 24 May 26 02:18:34 PM PDT 24 83048470 ps
T2030 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.955847174 May 26 02:18:49 PM PDT 24 May 26 02:18:53 PM PDT 24 227609363 ps
T2031 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2992648405 May 26 02:18:26 PM PDT 24 May 26 02:18:39 PM PDT 24 2687561122 ps
T2032 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1859813197 May 26 02:18:43 PM PDT 24 May 26 02:18:45 PM PDT 24 36089272 ps
T2033 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1489352567 May 26 02:18:57 PM PDT 24 May 26 02:18:58 PM PDT 24 39483713 ps
T2034 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3192137111 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 36968014 ps
T2035 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3154482432 May 26 02:18:50 PM PDT 24 May 26 02:18:55 PM PDT 24 313900802 ps
T2036 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1614886000 May 26 02:18:51 PM PDT 24 May 26 02:18:54 PM PDT 24 250014539 ps
T2037 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.114956931 May 26 02:18:49 PM PDT 24 May 26 02:18:52 PM PDT 24 200148691 ps
T2038 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1091585548 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 55582987 ps
T2039 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.110427688 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 75812868 ps
T304 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1115796178 May 26 02:18:34 PM PDT 24 May 26 02:18:40 PM PDT 24 841377908 ps
T301 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.89189051 May 26 02:18:42 PM PDT 24 May 26 02:18:49 PM PDT 24 1275833643 ps
T2040 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3575045298 May 26 02:19:04 PM PDT 24 May 26 02:19:08 PM PDT 24 234312561 ps
T2041 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2699175713 May 26 02:18:58 PM PDT 24 May 26 02:19:01 PM PDT 24 76531241 ps
T2042 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.479152671 May 26 02:18:33 PM PDT 24 May 26 02:18:34 PM PDT 24 46715769 ps

Test location /workspace/coverage/default/3.usbdev_pkt_sent.1564194
Short name T25
Test name
Test status
Simulation time 10162892281 ps
CPU time 15.73 seconds
Started May 26 01:28:00 PM PDT 24
Finished May 26 01:28:16 PM PDT 24
Peak memory 205260 kb
Host smart-42a2b626-20b4-4790-bb87-7be360ecd2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
94 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.1564194
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4081081351
Short name T284
Test name
Test status
Simulation time 35594495 ps
CPU time 0.69 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204564 kb
Host smart-de1d72af-0e73-46f7-9028-1a59d3ff7694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4081081351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4081081351
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1246288596
Short name T34
Test name
Test status
Simulation time 25017278939 ps
CPU time 45.98 seconds
Started May 26 01:30:29 PM PDT 24
Finished May 26 01:31:15 PM PDT 24
Peak memory 205316 kb
Host smart-94b2cb46-d97d-4cd4-992a-ff7db9609aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12462
88596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1246288596
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3000192110
Short name T11
Test name
Test status
Simulation time 13276111106 ps
CPU time 19.91 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:16 PM PDT 24
Peak memory 205240 kb
Host smart-62c59b95-594e-4f1f-bf0c-f21f5f464d12
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3000192110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3000192110
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1859638614
Short name T234
Test name
Test status
Simulation time 252231174 ps
CPU time 1.88 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:07 PM PDT 24
Peak memory 213076 kb
Host smart-b7592ff8-4f8a-43fb-819b-2bd5ba6d4087
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859638614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1859638614
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1410397154
Short name T35
Test name
Test status
Simulation time 10080271368 ps
CPU time 13.96 seconds
Started May 26 01:35:19 PM PDT 24
Finished May 26 01:35:34 PM PDT 24
Peak memory 205328 kb
Host smart-6c0073f6-6989-4162-b973-c6a8339dfa7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14103
97154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1410397154
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2058501558
Short name T99
Test name
Test status
Simulation time 65605747 ps
CPU time 0.71 seconds
Started May 26 02:19:03 PM PDT 24
Finished May 26 02:19:05 PM PDT 24
Peak memory 204544 kb
Host smart-a1ac9458-08d6-4225-9bdf-bae5f8dcfbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2058501558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2058501558
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.3934462298
Short name T39
Test name
Test status
Simulation time 10097510285 ps
CPU time 15.19 seconds
Started May 26 01:33:32 PM PDT 24
Finished May 26 01:33:48 PM PDT 24
Peak memory 205264 kb
Host smart-6839608a-096a-4cb4-adae-25d80d7049d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39344
62298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3934462298
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.187234522
Short name T62
Test name
Test status
Simulation time 10043720038 ps
CPU time 12.31 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205280 kb
Host smart-195d5a48-4d4d-4d21-9ead-41b06ec665a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18723
4522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.187234522
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.408224075
Short name T492
Test name
Test status
Simulation time 10114856177 ps
CPU time 15.29 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:54 PM PDT 24
Peak memory 205248 kb
Host smart-ee49dbe0-1fc5-4d25-917e-804c7e0daddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40822
4075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.408224075
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3248344120
Short name T67
Test name
Test status
Simulation time 10042196624 ps
CPU time 16.85 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:13 PM PDT 24
Peak memory 205260 kb
Host smart-3b8361ff-8dde-4a05-b670-31466876827c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32483
44120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3248344120
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3643659440
Short name T242
Test name
Test status
Simulation time 494229909 ps
CPU time 4.23 seconds
Started May 26 02:18:35 PM PDT 24
Finished May 26 02:18:40 PM PDT 24
Peak memory 204860 kb
Host smart-16ddf078-f2fa-4529-b263-5b0a47e6a631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3643659440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3643659440
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1539521824
Short name T30
Test name
Test status
Simulation time 10109721301 ps
CPU time 12.95 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:56 PM PDT 24
Peak memory 205248 kb
Host smart-d6534f20-cd5e-441d-8027-4c58eb516cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15395
21824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1539521824
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3876468125
Short name T8
Test name
Test status
Simulation time 13864418774 ps
CPU time 19.59 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:49 PM PDT 24
Peak memory 205348 kb
Host smart-d3ef350c-5ae3-480d-8377-ccf51edc9b9b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3876468125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.3876468125
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.4289011221
Short name T27
Test name
Test status
Simulation time 10943358962 ps
CPU time 14.98 seconds
Started May 26 01:27:54 PM PDT 24
Finished May 26 01:28:09 PM PDT 24
Peak memory 205284 kb
Host smart-00647296-f4c6-461b-b8dd-2e06caf19de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
11221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.4289011221
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3978859653
Short name T46
Test name
Test status
Simulation time 10040193974 ps
CPU time 14.82 seconds
Started May 26 01:36:06 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205260 kb
Host smart-d38c4f8e-db4b-475e-8e0a-54e7374cf69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39788
59653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3978859653
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1157615916
Short name T74
Test name
Test status
Simulation time 10054796899 ps
CPU time 13.87 seconds
Started May 26 01:35:46 PM PDT 24
Finished May 26 01:36:01 PM PDT 24
Peak memory 205152 kb
Host smart-193abe9a-5686-40d8-9f00-ae9ebc03dddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11576
15916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1157615916
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1309187431
Short name T205
Test name
Test status
Simulation time 614879637 ps
CPU time 1.54 seconds
Started May 26 01:26:41 PM PDT 24
Finished May 26 01:26:43 PM PDT 24
Peak memory 221416 kb
Host smart-62375723-4604-4346-82cc-e79605c395de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1309187431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1309187431
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2689298202
Short name T85
Test name
Test status
Simulation time 10138222650 ps
CPU time 16.29 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:31:11 PM PDT 24
Peak memory 205252 kb
Host smart-bf413759-1952-4d0a-baa2-ffd275b57ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26892
98202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2689298202
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1082486929
Short name T200
Test name
Test status
Simulation time 13289983107 ps
CPU time 18.85 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:48 PM PDT 24
Peak memory 205260 kb
Host smart-13d0892c-598b-4394-b5a8-c9b0dd2aff21
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1082486929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1082486929
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1533265867
Short name T1960
Test name
Test status
Simulation time 32861507 ps
CPU time 0.65 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:00 PM PDT 24
Peak memory 204712 kb
Host smart-0618074f-73a4-4a22-86b1-e05f133db035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1533265867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1533265867
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1650140049
Short name T261
Test name
Test status
Simulation time 63771547 ps
CPU time 1.45 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 213084 kb
Host smart-54aec657-79db-4dc0-888e-12368d209a7e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1650140049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1650140049
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.627697986
Short name T281
Test name
Test status
Simulation time 58775682 ps
CPU time 0.77 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204572 kb
Host smart-d0e766f4-8a9d-4105-bc26-3774cd364dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=627697986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.627697986
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3996251352
Short name T56
Test name
Test status
Simulation time 10045460821 ps
CPU time 13.84 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:09 PM PDT 24
Peak memory 205284 kb
Host smart-04aaa695-5c21-4a08-87d2-08000b05d254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
51352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3996251352
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.61030590
Short name T238
Test name
Test status
Simulation time 114332878 ps
CPU time 2.76 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:31 PM PDT 24
Peak memory 220456 kb
Host smart-6e09d75b-aa48-4b45-b6a3-f97c85d33957
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=61030590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.61030590
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/15.usbdev_enable.2361337892
Short name T72
Test name
Test status
Simulation time 10052068669 ps
CPU time 16.39 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:20 PM PDT 24
Peak memory 205236 kb
Host smart-6e71b29e-2522-416f-9417-9301fdc993ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613
37892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2361337892
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3800316142
Short name T298
Test name
Test status
Simulation time 1720423878 ps
CPU time 6.08 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:11 PM PDT 24
Peak memory 204852 kb
Host smart-23358832-3db0-4676-94d3-5c5e048cf0a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3800316142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3800316142
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.89189051
Short name T301
Test name
Test status
Simulation time 1275833643 ps
CPU time 5.77 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 204784 kb
Host smart-525cb25a-aa8e-48b9-9b09-0daa97fa297a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=89189051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.89189051
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2134442917
Short name T293
Test name
Test status
Simulation time 46813712 ps
CPU time 0.67 seconds
Started May 26 02:18:45 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 204496 kb
Host smart-01adc072-65fb-4319-9024-5367f0f5ff37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2134442917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2134442917
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.4213742294
Short name T227
Test name
Test status
Simulation time 5106515740 ps
CPU time 37.04 seconds
Started May 26 01:26:12 PM PDT 24
Finished May 26 01:26:49 PM PDT 24
Peak memory 205344 kb
Host smart-7c7f6b5e-58e6-4259-8162-44c6dcdde20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42137
42294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.4213742294
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.508103996
Short name T189
Test name
Test status
Simulation time 28615962526 ps
CPU time 50.76 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:29:09 PM PDT 24
Peak memory 205344 kb
Host smart-c85e79b0-f899-4584-8d52-1e9ecbef2d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50810
3996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.508103996
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3715785357
Short name T131
Test name
Test status
Simulation time 10595761906 ps
CPU time 18.77 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:29:03 PM PDT 24
Peak memory 205276 kb
Host smart-0b9408dd-967c-4b8c-af35-6105493c0b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37157
85357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3715785357
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.348634608
Short name T286
Test name
Test status
Simulation time 58617933 ps
CPU time 0.76 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204480 kb
Host smart-856af39a-7ba0-4b74-b9ca-b6b5a43d4d11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=348634608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.348634608
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.4181072074
Short name T65
Test name
Test status
Simulation time 10100001139 ps
CPU time 14.77 seconds
Started May 26 01:33:46 PM PDT 24
Finished May 26 01:34:02 PM PDT 24
Peak memory 205300 kb
Host smart-0fb737d2-fa90-4d24-8dc1-ecc5f3dcaf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41810
72074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.4181072074
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.636195600
Short name T49
Test name
Test status
Simulation time 10068412699 ps
CPU time 13.98 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:42 PM PDT 24
Peak memory 205280 kb
Host smart-b8585142-6474-4bd1-8894-6e1f4e55c39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63619
5600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.636195600
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3246294306
Short name T162
Test name
Test status
Simulation time 10065847758 ps
CPU time 16.39 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:41 PM PDT 24
Peak memory 205228 kb
Host smart-3c77d735-2253-46b4-ae78-173c39f580c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32462
94306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3246294306
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4184291844
Short name T144
Test name
Test status
Simulation time 10052161057 ps
CPU time 13.33 seconds
Started May 26 01:27:04 PM PDT 24
Finished May 26 01:27:18 PM PDT 24
Peak memory 205304 kb
Host smart-b6cf7af4-8c22-4659-8a56-12b811ea681f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41842
91844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4184291844
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1241573121
Short name T149
Test name
Test status
Simulation time 10140434578 ps
CPU time 16.88 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:21 PM PDT 24
Peak memory 205324 kb
Host smart-5ee8866a-8645-42a5-a074-726a589ec808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12415
73121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1241573121
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.4012311441
Short name T188
Test name
Test status
Simulation time 10073727300 ps
CPU time 14.45 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:43 PM PDT 24
Peak memory 205316 kb
Host smart-32a2d530-0613-4e34-8cc8-e09758600c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40123
11441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.4012311441
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3167398742
Short name T192
Test name
Test status
Simulation time 10153355798 ps
CPU time 16.85 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:16 PM PDT 24
Peak memory 205356 kb
Host smart-575135dc-1bfc-41ee-97dd-570aad0d9413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31673
98742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3167398742
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.490634355
Short name T186
Test name
Test status
Simulation time 10089837787 ps
CPU time 15.23 seconds
Started May 26 01:34:37 PM PDT 24
Finished May 26 01:34:53 PM PDT 24
Peak memory 205292 kb
Host smart-5b20aa0f-38f1-40d9-b764-71958c39e3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49063
4355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.490634355
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.736855857
Short name T177
Test name
Test status
Simulation time 10064599804 ps
CPU time 14.17 seconds
Started May 26 01:34:49 PM PDT 24
Finished May 26 01:35:04 PM PDT 24
Peak memory 205272 kb
Host smart-bdc1b721-b488-4908-82c8-3a070958e413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73685
5857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.736855857
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3435725616
Short name T191
Test name
Test status
Simulation time 10082676398 ps
CPU time 13.88 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205252 kb
Host smart-d462cea8-2b4d-45d6-aa61-377471e07455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34357
25616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3435725616
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1279392078
Short name T195
Test name
Test status
Simulation time 10089953011 ps
CPU time 15.59 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205268 kb
Host smart-d1485a01-8159-42c6-bb10-4df89e1e2f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12793
92078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1279392078
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.533471955
Short name T331
Test name
Test status
Simulation time 10071494900 ps
CPU time 13.93 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:53 PM PDT 24
Peak memory 205264 kb
Host smart-465f4b56-824d-4dbf-a857-0be5cd128a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53347
1955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.533471955
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4001540773
Short name T266
Test name
Test status
Simulation time 119443953 ps
CPU time 0.93 seconds
Started May 26 02:18:45 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 204512 kb
Host smart-064dfe7e-8612-4be9-94bd-88b6a4b35bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4001540773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4001540773
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.138748143
Short name T81
Test name
Test status
Simulation time 10049338571 ps
CPU time 13.57 seconds
Started May 26 01:26:58 PM PDT 24
Finished May 26 01:27:13 PM PDT 24
Peak memory 205284 kb
Host smart-84095308-d93f-4786-93b0-0704c2c2c2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13874
8143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.138748143
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3607285186
Short name T983
Test name
Test status
Simulation time 10858736661 ps
CPU time 18.68 seconds
Started May 26 01:31:38 PM PDT 24
Finished May 26 01:31:57 PM PDT 24
Peak memory 205208 kb
Host smart-28bce769-fa2b-49c4-916d-fa90b86a0a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
85186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3607285186
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.4027951759
Short name T1785
Test name
Test status
Simulation time 11149491927 ps
CPU time 15.36 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:46 PM PDT 24
Peak memory 205412 kb
Host smart-d1551de3-d7aa-4da2-9d09-fa037f32a6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
51759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.4027951759
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1454255962
Short name T61
Test name
Test status
Simulation time 10127986095 ps
CPU time 14.18 seconds
Started May 26 01:34:43 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205328 kb
Host smart-1e0bb07e-8a70-4b86-8551-06d9f4c15113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14542
55962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1454255962
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2352402195
Short name T871
Test name
Test status
Simulation time 10037864509 ps
CPU time 14.94 seconds
Started May 26 01:37:41 PM PDT 24
Finished May 26 01:37:57 PM PDT 24
Peak memory 205260 kb
Host smart-fd35aaa2-2180-48ac-80c1-ade2d0c59a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23524
02195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2352402195
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3649585428
Short name T239
Test name
Test status
Simulation time 102595779 ps
CPU time 2.84 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:33 PM PDT 24
Peak memory 220556 kb
Host smart-daa32409-8c53-43c3-b877-4f4feb666424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3649585428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3649585428
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1055142400
Short name T241
Test name
Test status
Simulation time 867359919 ps
CPU time 5.63 seconds
Started May 26 02:18:46 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 204824 kb
Host smart-8a088cf6-f9cb-430f-a108-6da209bc66b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1055142400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1055142400
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2905353848
Short name T126
Test name
Test status
Simulation time 10153645854 ps
CPU time 16.35 seconds
Started May 26 01:26:17 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 205228 kb
Host smart-c0e48b53-aa38-4ba3-a8f2-acab42d32d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053
53848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2905353848
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1394353651
Short name T103
Test name
Test status
Simulation time 10129544480 ps
CPU time 14.88 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:02 PM PDT 24
Peak memory 205296 kb
Host smart-ec903806-0af8-4a7c-b121-2f83464a774d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13943
53651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1394353651
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3393569594
Short name T108
Test name
Test status
Simulation time 10112032984 ps
CPU time 13.17 seconds
Started May 26 01:31:20 PM PDT 24
Finished May 26 01:31:34 PM PDT 24
Peak memory 205236 kb
Host smart-628d6cb4-6b0c-4332-a3de-b7e2c211b6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33935
69594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3393569594
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.4058921489
Short name T1779
Test name
Test status
Simulation time 10101996871 ps
CPU time 14.86 seconds
Started May 26 01:31:44 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 205220 kb
Host smart-089522bd-7df6-47ae-b01b-9eaa526c84e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40589
21489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.4058921489
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.261024951
Short name T1878
Test name
Test status
Simulation time 10122692844 ps
CPU time 14.66 seconds
Started May 26 01:32:37 PM PDT 24
Finished May 26 01:32:52 PM PDT 24
Peak memory 205300 kb
Host smart-44c9ede8-1571-4c1e-9e02-aaae2699991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
4951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.261024951
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2038016729
Short name T169
Test name
Test status
Simulation time 10078192043 ps
CPU time 15.83 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 205292 kb
Host smart-ed6fb485-aa85-4b11-8a87-19b3d5d297f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20380
16729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2038016729
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3927501017
Short name T115
Test name
Test status
Simulation time 10120489186 ps
CPU time 14.86 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:18 PM PDT 24
Peak memory 205204 kb
Host smart-ac019603-516e-436c-8cf2-5c19d8bd56df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
01017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3927501017
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3450385874
Short name T118
Test name
Test status
Simulation time 10131460549 ps
CPU time 15.11 seconds
Started May 26 01:33:30 PM PDT 24
Finished May 26 01:33:45 PM PDT 24
Peak memory 205288 kb
Host smart-4e03d192-e68e-4122-ab1d-e153d6f6365d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
85874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3450385874
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2224587080
Short name T128
Test name
Test status
Simulation time 10070479515 ps
CPU time 14.28 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:29 PM PDT 24
Peak memory 205264 kb
Host smart-fd1b7baf-3c7c-46dd-b4e3-b3d92303ba64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22245
87080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2224587080
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1217521691
Short name T1911
Test name
Test status
Simulation time 10148649532 ps
CPU time 14.48 seconds
Started May 26 01:27:23 PM PDT 24
Finished May 26 01:27:38 PM PDT 24
Peak memory 205252 kb
Host smart-08c547c1-0370-4a3a-940e-f75301f01d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12175
21691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1217521691
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.253420484
Short name T79
Test name
Test status
Simulation time 10102948277 ps
CPU time 17.36 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205236 kb
Host smart-ac183fb8-b41d-449a-b5d0-702a976e7f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25342
0484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.253420484
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.1046794920
Short name T91
Test name
Test status
Simulation time 23815651469 ps
CPU time 42.05 seconds
Started May 26 01:34:43 PM PDT 24
Finished May 26 01:35:26 PM PDT 24
Peak memory 205248 kb
Host smart-6508344f-fc70-45f6-8331-637acd6d65d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10467
94920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.1046794920
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.384037945
Short name T165
Test name
Test status
Simulation time 10079008478 ps
CPU time 13.26 seconds
Started May 26 01:35:24 PM PDT 24
Finished May 26 01:35:37 PM PDT 24
Peak memory 205264 kb
Host smart-c007a5c1-bd03-47be-b76c-2177bb4fbd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38403
7945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.384037945
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.764797687
Short name T122
Test name
Test status
Simulation time 10128939939 ps
CPU time 16.95 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:48 PM PDT 24
Peak memory 205308 kb
Host smart-38a0c5d1-50d2-4e79-9c40-9d5b02e70c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76479
7687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.764797687
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2561853950
Short name T106
Test name
Test status
Simulation time 10150407698 ps
CPU time 12.64 seconds
Started May 26 01:27:56 PM PDT 24
Finished May 26 01:28:09 PM PDT 24
Peak memory 205328 kb
Host smart-db629af7-f157-4aec-995d-f932316a8549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25618
53950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2561853950
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3903008622
Short name T179
Test name
Test status
Simulation time 10074666290 ps
CPU time 17.26 seconds
Started May 26 01:28:07 PM PDT 24
Finished May 26 01:28:25 PM PDT 24
Peak memory 205236 kb
Host smart-e558557a-5608-4360-9a97-4dfcf822c326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
08622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3903008622
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3158816903
Short name T60
Test name
Test status
Simulation time 10149627001 ps
CPU time 13.27 seconds
Started May 26 01:28:44 PM PDT 24
Finished May 26 01:28:58 PM PDT 24
Peak memory 205240 kb
Host smart-5027c02f-74d6-4e8d-8426-ad76ce3411fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
16903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3158816903
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2484345796
Short name T1950
Test name
Test status
Simulation time 180625908 ps
CPU time 3.35 seconds
Started May 26 02:18:25 PM PDT 24
Finished May 26 02:18:29 PM PDT 24
Peak memory 204792 kb
Host smart-e6a85037-0a88-4448-b9bc-e58acad5e630
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2484345796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2484345796
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2992648405
Short name T2031
Test name
Test status
Simulation time 2687561122 ps
CPU time 11.97 seconds
Started May 26 02:18:26 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 204800 kb
Host smart-992c2210-2ba3-4ac8-bf05-37ab5488d65f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2992648405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2992648405
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2828068780
Short name T1995
Test name
Test status
Simulation time 81880218 ps
CPU time 0.89 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 204536 kb
Host smart-0427eb83-a51c-4d7f-a8e4-ba2e6505e488
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2828068780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2828068780
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4238699338
Short name T2018
Test name
Test status
Simulation time 148667076 ps
CPU time 2.38 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:32 PM PDT 24
Peak memory 213012 kb
Host smart-3e7135ad-562e-4310-b2a6-27a172903431
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238699338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.4238699338
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1493258954
Short name T1980
Test name
Test status
Simulation time 97983951 ps
CPU time 1.03 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 204716 kb
Host smart-733924d2-a1a3-4891-972d-e0c91907a162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1493258954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1493258954
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1822532450
Short name T289
Test name
Test status
Simulation time 35850226 ps
CPU time 0.7 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 204588 kb
Host smart-893e4062-8c56-4329-9cef-93769eb308b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1822532450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1822532450
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.837518692
Short name T1973
Test name
Test status
Simulation time 66721949 ps
CPU time 1.36 seconds
Started May 26 02:18:25 PM PDT 24
Finished May 26 02:18:27 PM PDT 24
Peak memory 213056 kb
Host smart-8874051c-8c2f-4425-8ba4-62d803e8790a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=837518692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.837518692
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2823378749
Short name T2016
Test name
Test status
Simulation time 480392938 ps
CPU time 4.58 seconds
Started May 26 02:18:26 PM PDT 24
Finished May 26 02:18:32 PM PDT 24
Peak memory 204744 kb
Host smart-17ae6044-cb83-4547-b11f-f4fb26c64591
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2823378749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2823378749
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.998733312
Short name T1953
Test name
Test status
Simulation time 307952918 ps
CPU time 1.72 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:31 PM PDT 24
Peak memory 205032 kb
Host smart-a891a7ed-be8a-428b-9f16-6d36e6c5aa59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=998733312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.998733312
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3998354380
Short name T244
Test name
Test status
Simulation time 1061694390 ps
CPU time 5.34 seconds
Started May 26 02:18:30 PM PDT 24
Finished May 26 02:18:36 PM PDT 24
Peak memory 204816 kb
Host smart-0746920e-0783-411a-9346-db8132877fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3998354380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3998354380
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.215453962
Short name T1983
Test name
Test status
Simulation time 195590470 ps
CPU time 2 seconds
Started May 26 02:18:26 PM PDT 24
Finished May 26 02:18:28 PM PDT 24
Peak memory 204784 kb
Host smart-4024c270-9488-425a-8e1d-9fbc9bf822b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=215453962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.215453962
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2784762219
Short name T211
Test name
Test status
Simulation time 841365080 ps
CPU time 4.57 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:33 PM PDT 24
Peak memory 204800 kb
Host smart-15bc169e-d33e-4e5f-a9ee-7d702d004eec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2784762219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2784762219
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.496685173
Short name T1948
Test name
Test status
Simulation time 116298748 ps
CPU time 0.91 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:29 PM PDT 24
Peak memory 204556 kb
Host smart-a9c3aa57-d687-4e81-aa0b-a0caf9405c02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=496685173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.496685173
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2600997295
Short name T1944
Test name
Test status
Simulation time 68245168 ps
CPU time 1.47 seconds
Started May 26 02:18:25 PM PDT 24
Finished May 26 02:18:27 PM PDT 24
Peak memory 213140 kb
Host smart-7be4a19d-2269-4e35-982f-760b3940b2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600997295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2600997295
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.459126582
Short name T1967
Test name
Test status
Simulation time 126306819 ps
CPU time 1.08 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 204828 kb
Host smart-05bbf7f3-e175-492d-a651-c79822c132e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=459126582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.459126582
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2747193468
Short name T290
Test name
Test status
Simulation time 58579892 ps
CPU time 0.71 seconds
Started May 26 02:18:29 PM PDT 24
Finished May 26 02:18:31 PM PDT 24
Peak memory 204460 kb
Host smart-fd4b8604-bab7-4696-bda6-6e1c9eaf4f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2747193468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2747193468
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.527191267
Short name T262
Test name
Test status
Simulation time 83384683 ps
CPU time 2.24 seconds
Started May 26 02:18:31 PM PDT 24
Finished May 26 02:18:34 PM PDT 24
Peak memory 212900 kb
Host smart-d31d5e5c-f79d-4ef3-a105-5030f9ba4cf4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=527191267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.527191267
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2332981726
Short name T1989
Test name
Test status
Simulation time 341853041 ps
CPU time 2.57 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:32 PM PDT 24
Peak memory 204740 kb
Host smart-12e7bb91-c1f3-4c08-b5e1-1d6e2f0d4b97
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2332981726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2332981726
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3614071748
Short name T1942
Test name
Test status
Simulation time 110488921 ps
CPU time 1.15 seconds
Started May 26 02:18:31 PM PDT 24
Finished May 26 02:18:32 PM PDT 24
Peak memory 204696 kb
Host smart-20cfb9f5-38ef-422e-98d8-b1b42a43ee93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3614071748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3614071748
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2006812505
Short name T232
Test name
Test status
Simulation time 536572394 ps
CPU time 3.21 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:33 PM PDT 24
Peak memory 204880 kb
Host smart-d7977ce0-f68c-4451-9298-dac949dfd262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2006812505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2006812505
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2915560147
Short name T243
Test name
Test status
Simulation time 111937361 ps
CPU time 1.27 seconds
Started May 26 02:18:46 PM PDT 24
Finished May 26 02:18:48 PM PDT 24
Peak memory 213056 kb
Host smart-164f58b8-eb8f-4f59-b004-3297b2a61fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915560147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2915560147
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.341194512
Short name T1974
Test name
Test status
Simulation time 44938858 ps
CPU time 0.81 seconds
Started May 26 02:18:44 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204600 kb
Host smart-7e2a51a5-b0e3-4c3e-b2c7-cb631d22b496
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=341194512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.341194512
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2588103152
Short name T283
Test name
Test status
Simulation time 69973276 ps
CPU time 0.72 seconds
Started May 26 02:18:48 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 204492 kb
Host smart-482454b0-67fe-40f9-a5d6-1d5d5aef5f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2588103152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2588103152
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.286758488
Short name T1998
Test name
Test status
Simulation time 191189077 ps
CPU time 1.68 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204884 kb
Host smart-fa7efe19-4a2e-489f-ae63-7b049cef34ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=286758488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.286758488
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3712361851
Short name T1965
Test name
Test status
Simulation time 68127400 ps
CPU time 1.62 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:45 PM PDT 24
Peak memory 204892 kb
Host smart-bac3fe3a-59c6-48c3-b3f1-dd91f43d05db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3712361851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3712361851
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1833181527
Short name T1990
Test name
Test status
Simulation time 545998484 ps
CPU time 4.29 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:48 PM PDT 24
Peak memory 204844 kb
Host smart-fa9560bb-6f77-4075-beb8-cc871ad6aa91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1833181527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1833181527
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3427936720
Short name T2020
Test name
Test status
Simulation time 201767366 ps
CPU time 2 seconds
Started May 26 02:18:41 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 216784 kb
Host smart-903842b7-fbef-4c1d-aa34-477c61ce4f6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427936720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3427936720
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2530353804
Short name T1954
Test name
Test status
Simulation time 84319523 ps
CPU time 1.04 seconds
Started May 26 02:18:46 PM PDT 24
Finished May 26 02:18:48 PM PDT 24
Peak memory 204728 kb
Host smart-283c262a-18cb-40e7-8fa9-b31ef06046a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2530353804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2530353804
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1859813197
Short name T2032
Test name
Test status
Simulation time 36089272 ps
CPU time 0.74 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:45 PM PDT 24
Peak memory 204512 kb
Host smart-3b3535fd-a482-4939-b469-bb52320030ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1859813197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1859813197
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.389185097
Short name T273
Test name
Test status
Simulation time 215952467 ps
CPU time 1.38 seconds
Started May 26 02:18:44 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 204840 kb
Host smart-588941ec-94b1-47f8-8492-6163ef9b24d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=389185097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.389185097
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1029007530
Short name T1977
Test name
Test status
Simulation time 111133484 ps
CPU time 3.07 seconds
Started May 26 02:18:45 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 220432 kb
Host smart-2e1c8678-dcf2-4342-a3f8-39db59a11b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1029007530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1029007530
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3678456390
Short name T1947
Test name
Test status
Simulation time 1290607615 ps
CPU time 5.16 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:48 PM PDT 24
Peak memory 204848 kb
Host smart-da7a528f-1c98-423c-acd5-367a8e3eb363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3678456390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3678456390
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1984295021
Short name T2005
Test name
Test status
Simulation time 154674211 ps
CPU time 1.51 seconds
Started May 26 02:18:41 PM PDT 24
Finished May 26 02:18:43 PM PDT 24
Peak memory 221428 kb
Host smart-a20b1c81-d518-4a84-ac1d-1a47c8582507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984295021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1984295021
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1427696776
Short name T274
Test name
Test status
Simulation time 167761530 ps
CPU time 0.96 seconds
Started May 26 02:18:40 PM PDT 24
Finished May 26 02:18:42 PM PDT 24
Peak memory 204548 kb
Host smart-5fd53cef-ef97-4465-b0b2-21a8e770fac8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1427696776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1427696776
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3732938493
Short name T2014
Test name
Test status
Simulation time 145268655 ps
CPU time 1.78 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 204884 kb
Host smart-5f0ec9a5-2f2f-4f59-8fdf-0e933568dd9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3732938493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3732938493
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3446684735
Short name T2024
Test name
Test status
Simulation time 85442447 ps
CPU time 2.21 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204936 kb
Host smart-7fb2e84e-46c0-4883-9ebd-b992d361523a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3446684735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3446684735
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.175194472
Short name T2007
Test name
Test status
Simulation time 135595112 ps
CPU time 1.85 seconds
Started May 26 02:18:44 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 212492 kb
Host smart-d699318d-a90d-45cc-8685-3a2c3faaf7e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175194472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.175194472
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2922252054
Short name T1986
Test name
Test status
Simulation time 54804478 ps
CPU time 0.9 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204600 kb
Host smart-863d1bc5-7249-4ace-bf99-71da7141e4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2922252054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2922252054
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.625710171
Short name T1941
Test name
Test status
Simulation time 36252898 ps
CPU time 0.73 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204528 kb
Host smart-22290a8e-6773-46d8-a5dd-1f02f7674b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=625710171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.625710171
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3300409549
Short name T2013
Test name
Test status
Simulation time 181442232 ps
CPU time 1.58 seconds
Started May 26 02:18:47 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 204848 kb
Host smart-0da25921-3932-4af5-87f3-ddd9f08ae14c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3300409549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3300409549
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1237361743
Short name T237
Test name
Test status
Simulation time 100224585 ps
CPU time 2.7 seconds
Started May 26 02:18:46 PM PDT 24
Finished May 26 02:18:50 PM PDT 24
Peak memory 220424 kb
Host smart-ada5d032-d92b-4bc5-8b0c-9b31dafe4aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1237361743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1237361743
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3443545867
Short name T1979
Test name
Test status
Simulation time 1204718244 ps
CPU time 5.23 seconds
Started May 26 02:18:44 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204216 kb
Host smart-4f4983c6-5595-4c6b-b9ab-df52621c4e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3443545867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3443545867
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2502444267
Short name T207
Test name
Test status
Simulation time 211110918 ps
CPU time 1.93 seconds
Started May 26 02:18:50 PM PDT 24
Finished May 26 02:18:53 PM PDT 24
Peak memory 217012 kb
Host smart-8335fe78-7b5a-4f5e-baa8-6f68a0c53ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502444267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2502444267
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1607118984
Short name T2026
Test name
Test status
Simulation time 90393691 ps
CPU time 1.1 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204868 kb
Host smart-b560e6d3-7c29-421f-8cac-003242968b80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1607118984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1607118984
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3857968580
Short name T1966
Test name
Test status
Simulation time 177227877 ps
CPU time 2.26 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 204908 kb
Host smart-be0d80c9-5b0e-4103-a9f2-68bf0d515fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3857968580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3857968580
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4036382327
Short name T1949
Test name
Test status
Simulation time 201459335 ps
CPU time 2.15 seconds
Started May 26 02:18:51 PM PDT 24
Finished May 26 02:18:55 PM PDT 24
Peak memory 213268 kb
Host smart-142beb70-40d2-4008-bb07-b452fe1346b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036382327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.4036382327
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.503755370
Short name T1964
Test name
Test status
Simulation time 100709752 ps
CPU time 1.06 seconds
Started May 26 02:18:52 PM PDT 24
Finished May 26 02:18:54 PM PDT 24
Peak memory 204812 kb
Host smart-a42c2b19-35b1-47e7-90cd-a14ce91a2bab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=503755370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.503755370
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1224810988
Short name T2004
Test name
Test status
Simulation time 77098131 ps
CPU time 0.76 seconds
Started May 26 02:18:50 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 204568 kb
Host smart-fd45622a-7b44-48ba-9a3a-0928e8bafa77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1224810988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1224810988
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.700916815
Short name T1988
Test name
Test status
Simulation time 142914844 ps
CPU time 1.28 seconds
Started May 26 02:18:47 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 204872 kb
Host smart-70ff9021-3498-410b-9b9e-20da513a59fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=700916815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.700916815
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3154482432
Short name T2035
Test name
Test status
Simulation time 313900802 ps
CPU time 3.17 seconds
Started May 26 02:18:50 PM PDT 24
Finished May 26 02:18:55 PM PDT 24
Peak memory 204880 kb
Host smart-c3b46099-d978-4d40-a4a3-be7d272764f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154482432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3154482432
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.482088414
Short name T305
Test name
Test status
Simulation time 445047872 ps
CPU time 2.78 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:53 PM PDT 24
Peak memory 204840 kb
Host smart-5be9cd60-a259-4aee-9137-ebb2c6e296f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=482088414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.482088414
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1110035762
Short name T269
Test name
Test status
Simulation time 136235874 ps
CPU time 1.15 seconds
Started May 26 02:18:51 PM PDT 24
Finished May 26 02:18:54 PM PDT 24
Peak memory 204776 kb
Host smart-362371a4-76fd-4258-a7cf-523fc39529e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1110035762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1110035762
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4165368639
Short name T2002
Test name
Test status
Simulation time 135824921 ps
CPU time 1.54 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:06 PM PDT 24
Peak memory 204876 kb
Host smart-ddc5e06b-26f7-48d0-b807-87a6eb5fd5f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4165368639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.4165368639
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3575045298
Short name T2040
Test name
Test status
Simulation time 234312561 ps
CPU time 3 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:08 PM PDT 24
Peak memory 213072 kb
Host smart-bdc0ce17-2b19-4c92-bda8-685acd67a022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575045298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3575045298
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.914826250
Short name T1978
Test name
Test status
Simulation time 75672472 ps
CPU time 1.23 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 213056 kb
Host smart-2ba143c6-5546-4e92-a1d1-75b95c546188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914826250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.914826250
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.975101898
Short name T272
Test name
Test status
Simulation time 101999395 ps
CPU time 1.02 seconds
Started May 26 02:18:50 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204776 kb
Host smart-aaf53e45-c40b-4893-8ddd-44bbd101d947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=975101898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.975101898
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1371510925
Short name T1971
Test name
Test status
Simulation time 73489023 ps
CPU time 0.74 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:05 PM PDT 24
Peak memory 204520 kb
Host smart-76aba167-33fe-4f37-b25e-580861f331d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1371510925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1371510925
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1614886000
Short name T2036
Test name
Test status
Simulation time 250014539 ps
CPU time 1.36 seconds
Started May 26 02:18:51 PM PDT 24
Finished May 26 02:18:54 PM PDT 24
Peak memory 204884 kb
Host smart-c24af2c7-c267-4bc2-a0f0-40568368cb31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1614886000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1614886000
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3489479949
Short name T1991
Test name
Test status
Simulation time 190193837 ps
CPU time 1.98 seconds
Started May 26 02:18:48 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204840 kb
Host smart-e5b50af6-f300-4f9f-8983-2dd8f8ee67ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489479949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3489479949
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3091085705
Short name T302
Test name
Test status
Simulation time 909526797 ps
CPU time 5.2 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:10 PM PDT 24
Peak memory 204800 kb
Host smart-8b7c07a5-a8d0-4f4a-a6aa-d7d38db97591
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3091085705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3091085705
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3623666814
Short name T1958
Test name
Test status
Simulation time 153774321 ps
CPU time 1.85 seconds
Started May 26 02:18:51 PM PDT 24
Finished May 26 02:18:54 PM PDT 24
Peak memory 213104 kb
Host smart-51011f4b-240a-45f6-bb5d-0d2648d9e323
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623666814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3623666814
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3169993937
Short name T1968
Test name
Test status
Simulation time 57622221 ps
CPU time 0.97 seconds
Started May 26 02:18:52 PM PDT 24
Finished May 26 02:18:54 PM PDT 24
Peak memory 204824 kb
Host smart-4cd27aa4-e11d-4256-bb18-d48382b00d9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3169993937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3169993937
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1909406841
Short name T1961
Test name
Test status
Simulation time 108362679 ps
CPU time 0.71 seconds
Started May 26 02:19:03 PM PDT 24
Finished May 26 02:19:04 PM PDT 24
Peak memory 204516 kb
Host smart-ee9b975c-4692-4529-b37e-bc312d8c0373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1909406841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1909406841
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.4242168375
Short name T2012
Test name
Test status
Simulation time 219052677 ps
CPU time 1.55 seconds
Started May 26 02:19:03 PM PDT 24
Finished May 26 02:19:05 PM PDT 24
Peak memory 204796 kb
Host smart-4cdb6163-9efd-4e32-91cc-176fd082ee4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4242168375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.4242168375
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.671401218
Short name T2006
Test name
Test status
Simulation time 81344951 ps
CPU time 2.27 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 204968 kb
Host smart-52d206e6-5a22-4714-8bc4-eea0132b7160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=671401218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.671401218
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2621468711
Short name T300
Test name
Test status
Simulation time 635853563 ps
CPU time 4.91 seconds
Started May 26 02:19:04 PM PDT 24
Finished May 26 02:19:10 PM PDT 24
Peak memory 204840 kb
Host smart-c21b098f-4a71-4246-a346-1dadd417db0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2621468711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2621468711
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1669128662
Short name T1957
Test name
Test status
Simulation time 65430605 ps
CPU time 1.59 seconds
Started May 26 02:18:50 PM PDT 24
Finished May 26 02:18:53 PM PDT 24
Peak memory 213144 kb
Host smart-9f584736-8030-4b4f-9a47-2c0ffc2085f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669128662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1669128662
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3835077308
Short name T1987
Test name
Test status
Simulation time 64463577 ps
CPU time 0.99 seconds
Started May 26 02:18:48 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 204824 kb
Host smart-1f66bdd3-8404-43c1-b2bb-d997d376e3c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3835077308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3835077308
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1198936428
Short name T288
Test name
Test status
Simulation time 61630364 ps
CPU time 0.65 seconds
Started May 26 02:18:52 PM PDT 24
Finished May 26 02:18:53 PM PDT 24
Peak memory 204564 kb
Host smart-0b893952-b888-49eb-b750-c8d03830cdba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1198936428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1198936428
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.114956931
Short name T2037
Test name
Test status
Simulation time 200148691 ps
CPU time 1.65 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 204976 kb
Host smart-3ba6d030-9cfe-4f8a-a167-bdbfdde73522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=114956931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.114956931
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.955847174
Short name T2030
Test name
Test status
Simulation time 227609363 ps
CPU time 2.92 seconds
Started May 26 02:18:49 PM PDT 24
Finished May 26 02:18:53 PM PDT 24
Peak memory 220496 kb
Host smart-dabe5ed2-a690-4a03-a867-bbb302447e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=955847174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.955847174
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3177056349
Short name T297
Test name
Test status
Simulation time 391443102 ps
CPU time 2.86 seconds
Started May 26 02:18:51 PM PDT 24
Finished May 26 02:18:55 PM PDT 24
Peak memory 204992 kb
Host smart-1bbfdb0e-670e-4f4e-a241-9aadec9a41bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3177056349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3177056349
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1215653789
Short name T228
Test name
Test status
Simulation time 80585136 ps
CPU time 1.99 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:36 PM PDT 24
Peak memory 204680 kb
Host smart-79f70667-171e-4e69-96c0-b5e6023f7f97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1215653789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1215653789
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1146747137
Short name T1985
Test name
Test status
Simulation time 587958120 ps
CPU time 8.19 seconds
Started May 26 02:18:29 PM PDT 24
Finished May 26 02:18:38 PM PDT 24
Peak memory 204932 kb
Host smart-e611ce77-9331-44f9-813f-f92a53177ff5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1146747137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1146747137
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2835020962
Short name T98
Test name
Test status
Simulation time 261814272 ps
CPU time 1.03 seconds
Started May 26 02:18:29 PM PDT 24
Finished May 26 02:18:31 PM PDT 24
Peak memory 204568 kb
Host smart-3594ca95-3a76-4110-b1cf-3823353051b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2835020962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2835020962
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.852407294
Short name T2022
Test name
Test status
Simulation time 99959155 ps
CPU time 1.35 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 213072 kb
Host smart-70bd12ab-5f7b-4cfd-afa1-616df06ccd14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852407294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.852407294
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.4275138115
Short name T270
Test name
Test status
Simulation time 45404284 ps
CPU time 0.78 seconds
Started May 26 02:18:28 PM PDT 24
Finished May 26 02:18:30 PM PDT 24
Peak memory 204624 kb
Host smart-3d260ce1-5ae3-4898-87d1-cf3832c9de55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4275138115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.4275138115
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.389193412
Short name T282
Test name
Test status
Simulation time 43986741 ps
CPU time 0.67 seconds
Started May 26 02:18:29 PM PDT 24
Finished May 26 02:18:31 PM PDT 24
Peak memory 204528 kb
Host smart-452585f5-7840-471a-9da4-cec0d3419dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=389193412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.389193412
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2517122764
Short name T1992
Test name
Test status
Simulation time 736874202 ps
CPU time 5.16 seconds
Started May 26 02:18:27 PM PDT 24
Finished May 26 02:18:34 PM PDT 24
Peak memory 204748 kb
Host smart-1edd030d-d481-4d61-9c43-0fe640a5d6e1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2517122764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2517122764
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3449514391
Short name T276
Test name
Test status
Simulation time 265811310 ps
CPU time 1.92 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:36 PM PDT 24
Peak memory 204856 kb
Host smart-1a0a0dd7-bb37-4cfc-8a01-b0df586bee79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3449514391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3449514391
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2911794218
Short name T2019
Test name
Test status
Simulation time 384569268 ps
CPU time 3.47 seconds
Started May 26 02:18:31 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 220540 kb
Host smart-8e2a31cd-722e-4f25-9de9-b75541d557fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2911794218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2911794218
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.802990168
Short name T1945
Test name
Test status
Simulation time 485595089 ps
CPU time 2.48 seconds
Started May 26 02:18:29 PM PDT 24
Finished May 26 02:18:33 PM PDT 24
Peak memory 204836 kb
Host smart-09ec8bf8-1f1b-4343-af16-394f45a70916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=802990168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.802990168
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.667163951
Short name T215
Test name
Test status
Simulation time 39951372 ps
CPU time 0.64 seconds
Started May 26 02:18:50 PM PDT 24
Finished May 26 02:18:52 PM PDT 24
Peak memory 204520 kb
Host smart-045b56de-dea1-4bde-8767-858942d5dda4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=667163951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.667163951
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2308325989
Short name T292
Test name
Test status
Simulation time 48653123 ps
CPU time 0.68 seconds
Started May 26 02:18:48 PM PDT 24
Finished May 26 02:18:50 PM PDT 24
Peak memory 204576 kb
Host smart-350620f1-dd6a-44a5-a197-7ff372ae73ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2308325989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2308325989
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1446563776
Short name T2003
Test name
Test status
Simulation time 64058266 ps
CPU time 0.73 seconds
Started May 26 02:18:55 PM PDT 24
Finished May 26 02:18:57 PM PDT 24
Peak memory 204504 kb
Host smart-cb6f9d50-ae9d-421f-b1b5-fec20cd7e3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1446563776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1446563776
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1099219839
Short name T2011
Test name
Test status
Simulation time 54402001 ps
CPU time 0.71 seconds
Started May 26 02:18:56 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 204568 kb
Host smart-741146cf-564d-44fd-ae62-8309d2ec9057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1099219839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1099219839
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.3560467374
Short name T285
Test name
Test status
Simulation time 94115826 ps
CPU time 0.74 seconds
Started May 26 02:18:56 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 204568 kb
Host smart-9efa94dc-5864-41cf-8319-03ca5532479d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3560467374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3560467374
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3149740126
Short name T1996
Test name
Test status
Simulation time 98998027 ps
CPU time 0.74 seconds
Started May 26 02:18:59 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 204572 kb
Host smart-896c9aec-bf28-48a4-8f9d-7ff52849acb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149740126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3149740126
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1676556483
Short name T1999
Test name
Test status
Simulation time 50130370 ps
CPU time 0.72 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204576 kb
Host smart-bceefb64-7095-4a37-8503-d7d26a48120b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1676556483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1676556483
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1091585548
Short name T2038
Test name
Test status
Simulation time 55582987 ps
CPU time 0.68 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204560 kb
Host smart-8b529b53-6b84-44a0-8d22-f63d8b3ec8fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1091585548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1091585548
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3628014466
Short name T267
Test name
Test status
Simulation time 381370729 ps
CPU time 3.74 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:38 PM PDT 24
Peak memory 204752 kb
Host smart-0bfb79da-655e-4672-ae84-5135d81d35f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3628014466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3628014466
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.686161975
Short name T2000
Test name
Test status
Simulation time 1113977608 ps
CPU time 9.7 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 204744 kb
Host smart-e2c6d1b3-59be-48f8-bfd9-3d64458e5c18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=686161975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.686161975
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4027531698
Short name T2023
Test name
Test status
Simulation time 134287615 ps
CPU time 1.07 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:34 PM PDT 24
Peak memory 204580 kb
Host smart-ef8f6436-41df-4f78-bc4c-10fd0bdd1a94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4027531698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4027531698
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.861385125
Short name T1943
Test name
Test status
Simulation time 91584431 ps
CPU time 2.15 seconds
Started May 26 02:18:35 PM PDT 24
Finished May 26 02:18:38 PM PDT 24
Peak memory 213004 kb
Host smart-5b5f8018-04be-42b1-bede-068127f408bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861385125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.861385125
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3982940106
Short name T1997
Test name
Test status
Simulation time 111357868 ps
CPU time 1.02 seconds
Started May 26 02:18:38 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 204748 kb
Host smart-a9315a81-90f7-4af9-b8ff-7f2a94313568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3982940106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3982940106
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.479152671
Short name T2042
Test name
Test status
Simulation time 46715769 ps
CPU time 0.72 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:34 PM PDT 24
Peak memory 204580 kb
Host smart-a945762f-d99f-4103-b504-3abdcc3df6db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=479152671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.479152671
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2371372440
Short name T271
Test name
Test status
Simulation time 132741994 ps
CPU time 2.19 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 213032 kb
Host smart-92615927-559a-401c-be42-e0a9d09b2771
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2371372440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2371372440
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.964519850
Short name T1994
Test name
Test status
Simulation time 170236361 ps
CPU time 3.73 seconds
Started May 26 02:18:38 PM PDT 24
Finished May 26 02:18:42 PM PDT 24
Peak memory 204712 kb
Host smart-d357c821-80e0-499d-82bb-5861e4031271
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=964519850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.964519850
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.674029434
Short name T2029
Test name
Test status
Simulation time 83048470 ps
CPU time 1.09 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:34 PM PDT 24
Peak memory 204876 kb
Host smart-225dcf2d-fb2e-42ac-950e-01c2a00277b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=674029434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.674029434
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2880657218
Short name T2021
Test name
Test status
Simulation time 66320564 ps
CPU time 1.69 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 213084 kb
Host smart-38120d49-0a2f-4348-9b87-b78daa70e406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2880657218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2880657218
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2699175713
Short name T2041
Test name
Test status
Simulation time 76531241 ps
CPU time 0.7 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204548 kb
Host smart-1b7d3c31-1166-4ac6-b208-a902d4c9cfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2699175713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2699175713
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2105652842
Short name T1955
Test name
Test status
Simulation time 74093615 ps
CPU time 0.75 seconds
Started May 26 02:18:56 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 204528 kb
Host smart-85087ac3-c722-4d7f-b1f0-e7690f2f2cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2105652842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2105652842
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2071614353
Short name T287
Test name
Test status
Simulation time 33586919 ps
CPU time 0.74 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204536 kb
Host smart-1f196f13-780c-4a84-a19f-23c9c91b7a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2071614353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2071614353
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2418874626
Short name T2001
Test name
Test status
Simulation time 43208853 ps
CPU time 0.7 seconds
Started May 26 02:19:00 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 204564 kb
Host smart-78370b5a-7a49-4766-bf4e-74965228c3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2418874626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2418874626
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2628980661
Short name T295
Test name
Test status
Simulation time 46358889 ps
CPU time 0.69 seconds
Started May 26 02:18:57 PM PDT 24
Finished May 26 02:18:59 PM PDT 24
Peak memory 204572 kb
Host smart-4b79b8c8-d4a8-478d-b1e2-254dbf0cfe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2628980661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2628980661
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4175550154
Short name T97
Test name
Test status
Simulation time 48448124 ps
CPU time 0.7 seconds
Started May 26 02:18:56 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 204536 kb
Host smart-2cc25063-21ce-4b08-9be4-4b63cab1ffe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4175550154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4175550154
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3761656192
Short name T2017
Test name
Test status
Simulation time 75941964 ps
CPU time 0.7 seconds
Started May 26 02:18:56 PM PDT 24
Finished May 26 02:18:57 PM PDT 24
Peak memory 204556 kb
Host smart-c663445f-9ded-4a2c-af2d-50fa86b779db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3761656192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3761656192
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.903381028
Short name T2027
Test name
Test status
Simulation time 39427111 ps
CPU time 0.68 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:00 PM PDT 24
Peak memory 204572 kb
Host smart-a81ecce1-f412-4cad-a840-9a29b5ee7716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=903381028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.903381028
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.4112776900
Short name T2028
Test name
Test status
Simulation time 63705128 ps
CPU time 0.71 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204524 kb
Host smart-3a330d8a-dff5-4029-9e17-55b8156ac72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4112776900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.4112776900
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.720136363
Short name T265
Test name
Test status
Simulation time 164336174 ps
CPU time 2.04 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 204744 kb
Host smart-a898ae08-5e6c-49ea-a01e-54b84f5e2089
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=720136363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.720136363
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.217226168
Short name T1959
Test name
Test status
Simulation time 1355593675 ps
CPU time 5.05 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:40 PM PDT 24
Peak memory 204788 kb
Host smart-d6c818b7-97f2-40d9-97eb-22b8660b020a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=217226168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.217226168
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.282336986
Short name T1956
Test name
Test status
Simulation time 131057088 ps
CPU time 0.86 seconds
Started May 26 02:18:39 PM PDT 24
Finished May 26 02:18:41 PM PDT 24
Peak memory 204548 kb
Host smart-ed7adb6f-c80d-4b17-b2f0-842529fa1a68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=282336986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.282336986
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.568445437
Short name T1952
Test name
Test status
Simulation time 70059115 ps
CPU time 1.65 seconds
Started May 26 02:18:37 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 213064 kb
Host smart-fe577847-0d08-40e5-884b-113f7d336a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568445437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.568445437
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1375892036
Short name T277
Test name
Test status
Simulation time 88378421 ps
CPU time 0.84 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:36 PM PDT 24
Peak memory 204588 kb
Host smart-72beab35-a3be-4dcf-91f0-5ddaf52ec1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1375892036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1375892036
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1297661320
Short name T1937
Test name
Test status
Simulation time 33031921 ps
CPU time 0.67 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:34 PM PDT 24
Peak memory 204560 kb
Host smart-8fa4777a-d5ba-4ef8-a395-f5a009fd1cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1297661320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1297661320
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.552700616
Short name T264
Test name
Test status
Simulation time 195453676 ps
CPU time 2.39 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 213116 kb
Host smart-2e96810e-db29-4f27-94e2-3065a3b13f98
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=552700616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.552700616
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4046629358
Short name T1962
Test name
Test status
Simulation time 177433240 ps
CPU time 4.04 seconds
Started May 26 02:18:32 PM PDT 24
Finished May 26 02:18:36 PM PDT 24
Peak memory 204760 kb
Host smart-3c558a2c-fc68-43c2-a000-bf5ca50af606
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4046629358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4046629358
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.222216301
Short name T210
Test name
Test status
Simulation time 248463305 ps
CPU time 1.71 seconds
Started May 26 02:18:36 PM PDT 24
Finished May 26 02:18:38 PM PDT 24
Peak memory 204876 kb
Host smart-848ab5c9-ee91-4d49-b943-3101a81c1a19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=222216301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.222216301
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4020840145
Short name T209
Test name
Test status
Simulation time 178888958 ps
CPU time 2.29 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 204908 kb
Host smart-8201256c-4734-455c-ad50-b5da7c9a0c14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4020840145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.4020840145
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3736222050
Short name T231
Test name
Test status
Simulation time 884202818 ps
CPU time 3.18 seconds
Started May 26 02:18:36 PM PDT 24
Finished May 26 02:18:40 PM PDT 24
Peak memory 204792 kb
Host smart-870c3a0e-1613-4ccc-88d9-4ae391bbea5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3736222050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3736222050
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1595070378
Short name T214
Test name
Test status
Simulation time 35873628 ps
CPU time 0.68 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204564 kb
Host smart-7142b404-34cf-4829-80fb-bb85cbe8a92c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1595070378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1595070378
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3624579164
Short name T291
Test name
Test status
Simulation time 55106208 ps
CPU time 0.71 seconds
Started May 26 02:18:57 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 204560 kb
Host smart-73261ca3-690f-4a19-a200-cb8ca083bc36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3624579164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3624579164
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3453178431
Short name T1939
Test name
Test status
Simulation time 56199219 ps
CPU time 0.7 seconds
Started May 26 02:18:59 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 204564 kb
Host smart-3b899ce8-114a-4d11-b05e-b4d93d39ce62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3453178431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3453178431
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3387300688
Short name T294
Test name
Test status
Simulation time 48088698 ps
CPU time 0.68 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:00 PM PDT 24
Peak memory 204564 kb
Host smart-b643f505-5a02-4926-82eb-b5faca02f7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3387300688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3387300688
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1489352567
Short name T2033
Test name
Test status
Simulation time 39483713 ps
CPU time 0.71 seconds
Started May 26 02:18:57 PM PDT 24
Finished May 26 02:18:58 PM PDT 24
Peak memory 204528 kb
Host smart-59469bca-3d5e-46d6-9fe4-530bed1b60ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1489352567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1489352567
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.317892763
Short name T2015
Test name
Test status
Simulation time 35776229 ps
CPU time 0.68 seconds
Started May 26 02:18:59 PM PDT 24
Finished May 26 02:19:02 PM PDT 24
Peak memory 204560 kb
Host smart-28479844-68fd-4804-92db-f837212a5cc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=317892763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.317892763
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3192137111
Short name T2034
Test name
Test status
Simulation time 36968014 ps
CPU time 0.75 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204476 kb
Host smart-0cac1d2e-47fb-44ad-a237-994fe2199e42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192137111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3192137111
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.110427688
Short name T2039
Test name
Test status
Simulation time 75812868 ps
CPU time 0.72 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204568 kb
Host smart-00a758da-ba2d-4598-b98a-bc8767a26b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=110427688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.110427688
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.276537699
Short name T1940
Test name
Test status
Simulation time 49649694 ps
CPU time 0.73 seconds
Started May 26 02:18:57 PM PDT 24
Finished May 26 02:18:59 PM PDT 24
Peak memory 204564 kb
Host smart-bd950e83-df89-4429-ada1-aaa44b83831c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276537699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.276537699
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3054580857
Short name T213
Test name
Test status
Simulation time 63449004 ps
CPU time 0.76 seconds
Started May 26 02:18:58 PM PDT 24
Finished May 26 02:19:01 PM PDT 24
Peak memory 204496 kb
Host smart-2e9bbfc6-0f47-49b6-83ee-edccd0031b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3054580857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3054580857
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2868796551
Short name T1976
Test name
Test status
Simulation time 129775609 ps
CPU time 2.03 seconds
Started May 26 02:18:38 PM PDT 24
Finished May 26 02:18:40 PM PDT 24
Peak memory 212972 kb
Host smart-84cb2d54-084e-4f9a-b9a3-0e09e004bacd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868796551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2868796551
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1917623432
Short name T263
Test name
Test status
Simulation time 41343642 ps
CPU time 0.95 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 204820 kb
Host smart-a010fc44-5ba0-4626-bb11-f2a5b32d694d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1917623432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1917623432
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2547602435
Short name T2008
Test name
Test status
Simulation time 42185204 ps
CPU time 0.68 seconds
Started May 26 02:18:39 PM PDT 24
Finished May 26 02:18:41 PM PDT 24
Peak memory 204460 kb
Host smart-69034fb0-cb74-4e89-a3b2-72c1cbdeb7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2547602435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2547602435
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.193678624
Short name T1972
Test name
Test status
Simulation time 81546267 ps
CPU time 1.02 seconds
Started May 26 02:18:33 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 204860 kb
Host smart-bdbd1ce8-57fc-40cd-a801-173d780724ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=193678624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.193678624
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3809013841
Short name T240
Test name
Test status
Simulation time 347191605 ps
CPU time 3.13 seconds
Started May 26 02:18:35 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 213076 kb
Host smart-a4bb5992-42f9-4df0-a542-5a1ce45602fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3809013841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3809013841
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2447577588
Short name T2025
Test name
Test status
Simulation time 439731932 ps
CPU time 2.86 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 204872 kb
Host smart-7dbd6536-10c5-4765-8475-4f027a929de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2447577588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2447577588
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.946388703
Short name T245
Test name
Test status
Simulation time 134657927 ps
CPU time 1.32 seconds
Started May 26 02:18:36 PM PDT 24
Finished May 26 02:18:38 PM PDT 24
Peak memory 214568 kb
Host smart-3a6df197-2e45-4f86-a571-a3487ad6d2f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946388703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.946388703
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.777636180
Short name T268
Test name
Test status
Simulation time 121696914 ps
CPU time 0.9 seconds
Started May 26 02:18:35 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 204592 kb
Host smart-f328d654-f34c-4b2a-a35b-5c938720f85e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=777636180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.777636180
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.133537426
Short name T1981
Test name
Test status
Simulation time 66151682 ps
CPU time 0.7 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:36 PM PDT 24
Peak memory 204576 kb
Host smart-7b7be7e0-9d2c-452c-8443-c45e25a17f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=133537426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.133537426
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1482197298
Short name T2010
Test name
Test status
Simulation time 145237259 ps
CPU time 1.19 seconds
Started May 26 02:18:35 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 204840 kb
Host smart-2b3216fb-7d87-4246-a868-5005d8437033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1482197298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1482197298
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3190208697
Short name T1984
Test name
Test status
Simulation time 107028396 ps
CPU time 2.84 seconds
Started May 26 02:18:38 PM PDT 24
Finished May 26 02:18:42 PM PDT 24
Peak memory 204928 kb
Host smart-1ee108c8-6980-497e-8cb7-4a7cee415cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3190208697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3190208697
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.20708397
Short name T299
Test name
Test status
Simulation time 490844970 ps
CPU time 2.87 seconds
Started May 26 02:18:31 PM PDT 24
Finished May 26 02:18:35 PM PDT 24
Peak memory 204848 kb
Host smart-0477e4f1-9e68-4ac7-bd3e-ddb8c3e642df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=20708397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.20708397
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3714581587
Short name T1946
Test name
Test status
Simulation time 109179874 ps
CPU time 1.41 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 221220 kb
Host smart-4012e10f-7efb-47a5-9067-5f67db24d2bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714581587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3714581587
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4047027810
Short name T1975
Test name
Test status
Simulation time 65137113 ps
CPU time 1.01 seconds
Started May 26 02:18:35 PM PDT 24
Finished May 26 02:18:37 PM PDT 24
Peak memory 204812 kb
Host smart-d738faa0-73f5-488b-92b7-0732b253a897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4047027810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.4047027810
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3217659337
Short name T96
Test name
Test status
Simulation time 41896566 ps
CPU time 0.66 seconds
Started May 26 02:18:38 PM PDT 24
Finished May 26 02:18:39 PM PDT 24
Peak memory 204568 kb
Host smart-899e2fb6-d183-43a5-9824-7dd656da54f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217659337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3217659337
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3614623261
Short name T275
Test name
Test status
Simulation time 274919783 ps
CPU time 1.98 seconds
Started May 26 02:18:41 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 204844 kb
Host smart-31e7e899-2d0a-412b-b1d3-0372b3ed3758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3614623261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3614623261
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1805472585
Short name T1963
Test name
Test status
Simulation time 147381208 ps
CPU time 2.07 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:38 PM PDT 24
Peak memory 220548 kb
Host smart-9ff416d8-1b09-42f5-9db2-28bd9b97bc56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1805472585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1805472585
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1115796178
Short name T304
Test name
Test status
Simulation time 841377908 ps
CPU time 4.79 seconds
Started May 26 02:18:34 PM PDT 24
Finished May 26 02:18:40 PM PDT 24
Peak memory 204920 kb
Host smart-c064c13c-3ab8-4605-9171-3e717544b7c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1115796178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1115796178
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1546916619
Short name T1993
Test name
Test status
Simulation time 151470003 ps
CPU time 1.82 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:45 PM PDT 24
Peak memory 213056 kb
Host smart-81d9800e-493b-48f0-a2c2-ec77bfce5b05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546916619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1546916619
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2160736398
Short name T212
Test name
Test status
Simulation time 57656253 ps
CPU time 0.81 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 204552 kb
Host smart-b47f6bfe-0ec8-42b1-98e8-4adce48a2a35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2160736398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2160736398
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1764859290
Short name T296
Test name
Test status
Simulation time 74089575 ps
CPU time 0.73 seconds
Started May 26 02:18:42 PM PDT 24
Finished May 26 02:18:44 PM PDT 24
Peak memory 204568 kb
Host smart-1f9dc438-3da0-46d7-a627-7becba8a884b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764859290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1764859290
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3735353604
Short name T1970
Test name
Test status
Simulation time 234582181 ps
CPU time 2.01 seconds
Started May 26 02:18:48 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204824 kb
Host smart-9e97f5d8-19c2-406d-a7b8-99a97fa641a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3735353604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3735353604
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1872623805
Short name T1982
Test name
Test status
Simulation time 289596835 ps
CPU time 3.25 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:48 PM PDT 24
Peak memory 204976 kb
Host smart-139d9684-2781-4401-91e1-62ca8cdbe913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872623805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1872623805
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3279500575
Short name T303
Test name
Test status
Simulation time 718734203 ps
CPU time 4.65 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:49 PM PDT 24
Peak memory 204856 kb
Host smart-b717cab3-48de-4fac-947a-0e413ae9c043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3279500575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3279500575
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2482452771
Short name T2009
Test name
Test status
Simulation time 94507384 ps
CPU time 1.24 seconds
Started May 26 02:18:41 PM PDT 24
Finished May 26 02:18:43 PM PDT 24
Peak memory 213084 kb
Host smart-e6a5d48a-cf97-4ea6-94ff-f2df1252fb37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482452771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2482452771
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1152476939
Short name T1951
Test name
Test status
Simulation time 145307447 ps
CPU time 1.16 seconds
Started May 26 02:18:44 PM PDT 24
Finished May 26 02:18:47 PM PDT 24
Peak memory 204732 kb
Host smart-083310a6-7c92-4f46-b94a-3bb8c16cb3ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1152476939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1152476939
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.132558129
Short name T1938
Test name
Test status
Simulation time 43311750 ps
CPU time 0.67 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:45 PM PDT 24
Peak memory 204548 kb
Host smart-b778b75e-a744-47dc-8e82-fad526aba21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=132558129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.132558129
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1789414213
Short name T1969
Test name
Test status
Simulation time 235222145 ps
CPU time 1.64 seconds
Started May 26 02:18:43 PM PDT 24
Finished May 26 02:18:46 PM PDT 24
Peak memory 204868 kb
Host smart-4cd3f01c-b156-49d8-a3bd-ab7e2893e9bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1789414213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1789414213
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.433900680
Short name T208
Test name
Test status
Simulation time 110017693 ps
CPU time 1.61 seconds
Started May 26 02:18:41 PM PDT 24
Finished May 26 02:18:43 PM PDT 24
Peak memory 204880 kb
Host smart-8e4a3a70-db74-4ed8-a440-f0bed7f1fb34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=433900680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.433900680
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3338576420
Short name T235
Test name
Test status
Simulation time 801556811 ps
CPU time 3.88 seconds
Started May 26 02:18:46 PM PDT 24
Finished May 26 02:18:51 PM PDT 24
Peak memory 204872 kb
Host smart-dcdf3c66-79b9-45cd-9458-e94af44ca1b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3338576420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3338576420
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.1140912239
Short name T468
Test name
Test status
Simulation time 10133922552 ps
CPU time 15.55 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:26:48 PM PDT 24
Peak memory 205188 kb
Host smart-4565df8e-de47-4ff6-abdf-10c3a4b7a827
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1140912239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.1140912239
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.993132128
Short name T947
Test name
Test status
Simulation time 10066111728 ps
CPU time 17.66 seconds
Started May 26 01:26:31 PM PDT 24
Finished May 26 01:26:50 PM PDT 24
Peak memory 205256 kb
Host smart-13bf7e2c-9552-4f15-a848-fb745172980a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=993132128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.993132128
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.757125683
Short name T332
Test name
Test status
Simulation time 10121164491 ps
CPU time 14.68 seconds
Started May 26 01:26:34 PM PDT 24
Finished May 26 01:26:49 PM PDT 24
Peak memory 205320 kb
Host smart-756e7485-ee41-47b5-8bf8-6c4e5368396e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75712
5683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.757125683
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3611032552
Short name T719
Test name
Test status
Simulation time 14206610699 ps
CPU time 18.15 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:26 PM PDT 24
Peak memory 205364 kb
Host smart-f97aac98-c9de-479f-afc6-742b339c57d8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3611032552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3611032552
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.12512646
Short name T726
Test name
Test status
Simulation time 13275151669 ps
CPU time 20.78 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:29 PM PDT 24
Peak memory 205304 kb
Host smart-7c891379-8561-4e94-a282-6033be49dfa2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=12512646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.12512646
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3285752673
Short name T1300
Test name
Test status
Simulation time 13438951523 ps
CPU time 18 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:26 PM PDT 24
Peak memory 205276 kb
Host smart-8cd006e9-6aa7-4349-b49f-7cf83d697307
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3285752673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3285752673
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.4110756718
Short name T1344
Test name
Test status
Simulation time 10048066134 ps
CPU time 18.09 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:26 PM PDT 24
Peak memory 205276 kb
Host smart-5d610963-93cf-4b66-bcce-5e178127253d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41107
56718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.4110756718
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.919947735
Short name T36
Test name
Test status
Simulation time 11029326234 ps
CPU time 16.83 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:24 PM PDT 24
Peak memory 205280 kb
Host smart-c163a518-5187-47bd-8204-9be9d977e973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91994
7735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.919947735
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1269529561
Short name T1218
Test name
Test status
Simulation time 10040851623 ps
CPU time 14.04 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:26:31 PM PDT 24
Peak memory 205332 kb
Host smart-03fea888-6992-42cb-b143-ac08e4bccef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12695
29561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1269529561
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2920127559
Short name T1063
Test name
Test status
Simulation time 10090258233 ps
CPU time 14.42 seconds
Started May 26 01:26:10 PM PDT 24
Finished May 26 01:26:25 PM PDT 24
Peak memory 205356 kb
Host smart-9c635698-5001-43d8-8974-0852a945aceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
27559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2920127559
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3756291610
Short name T593
Test name
Test status
Simulation time 10840318008 ps
CPU time 15.85 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:23 PM PDT 24
Peak memory 205300 kb
Host smart-2416eaf3-b4f2-4f7f-8706-f98cbadab025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562
91610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3756291610
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.916477411
Short name T1618
Test name
Test status
Simulation time 10145092091 ps
CPU time 14.29 seconds
Started May 26 01:26:06 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 205292 kb
Host smart-3e8b3c4a-8092-4f03-8694-93f850026184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91647
7411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.916477411
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.912559575
Short name T937
Test name
Test status
Simulation time 10115795703 ps
CPU time 14.41 seconds
Started May 26 01:26:31 PM PDT 24
Finished May 26 01:26:46 PM PDT 24
Peak memory 205208 kb
Host smart-dbed54f6-8256-4b4c-adfb-5a500dba0611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91255
9575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.912559575
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.106050730
Short name T1172
Test name
Test status
Simulation time 10037229078 ps
CPU time 13.78 seconds
Started May 26 01:26:32 PM PDT 24
Finished May 26 01:26:46 PM PDT 24
Peak memory 205336 kb
Host smart-609c155f-abfc-4955-b268-c0879dfc8775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10605
0730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.106050730
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2085367661
Short name T1208
Test name
Test status
Simulation time 10125645679 ps
CPU time 14.96 seconds
Started May 26 01:26:14 PM PDT 24
Finished May 26 01:26:29 PM PDT 24
Peak memory 205220 kb
Host smart-54671748-0d81-44a3-8783-edcfd74908a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20853
67661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2085367661
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.886915863
Short name T473
Test name
Test status
Simulation time 10076885716 ps
CPU time 13.39 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:26:30 PM PDT 24
Peak memory 205256 kb
Host smart-2850bb4e-2c60-484a-b00e-5f99f9ecbcb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88691
5863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.886915863
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3635903467
Short name T491
Test name
Test status
Simulation time 13182541459 ps
CPU time 18.55 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:26:34 PM PDT 24
Peak memory 205292 kb
Host smart-3068bacd-8a66-4a8a-925f-a97ae74efc27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36359
03467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3635903467
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2116153751
Short name T765
Test name
Test status
Simulation time 10097308187 ps
CPU time 15.78 seconds
Started May 26 01:26:17 PM PDT 24
Finished May 26 01:26:33 PM PDT 24
Peak memory 205344 kb
Host smart-1428b9a4-007b-41ea-a1c9-2411590245ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21161
53751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2116153751
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.259813212
Short name T589
Test name
Test status
Simulation time 10070064414 ps
CPU time 17.29 seconds
Started May 26 01:26:14 PM PDT 24
Finished May 26 01:26:32 PM PDT 24
Peak memory 205284 kb
Host smart-38b390ee-47e1-4f32-8a15-6a9f2a598df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
3212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.259813212
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2814040185
Short name T1501
Test name
Test status
Simulation time 10102610086 ps
CPU time 16.11 seconds
Started May 26 01:26:17 PM PDT 24
Finished May 26 01:26:33 PM PDT 24
Peak memory 205352 kb
Host smart-a3ea5562-1b88-47ad-94eb-e2eb59731891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
40185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2814040185
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1569761511
Short name T1665
Test name
Test status
Simulation time 10076186342 ps
CPU time 14.71 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:26:31 PM PDT 24
Peak memory 205296 kb
Host smart-0146fb17-5779-4f4d-97c0-27c1e3d7244b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
61511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1569761511
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1004811699
Short name T1057
Test name
Test status
Simulation time 10095889245 ps
CPU time 17.97 seconds
Started May 26 01:26:21 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 205348 kb
Host smart-b89e0437-6292-42b0-ba4f-80a0ec4723bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10048
11699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1004811699
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.797688140
Short name T1346
Test name
Test status
Simulation time 10076561626 ps
CPU time 14.31 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:26:38 PM PDT 24
Peak memory 205256 kb
Host smart-83fcb147-13b2-4f03-b68c-52410e90065a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79768
8140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.797688140
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2042205555
Short name T917
Test name
Test status
Simulation time 10045372658 ps
CPU time 13.72 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:38 PM PDT 24
Peak memory 205328 kb
Host smart-891bc532-4afa-4238-906e-924bb53e4ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20422
05555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2042205555
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2530435528
Short name T633
Test name
Test status
Simulation time 10038575233 ps
CPU time 14.68 seconds
Started May 26 01:26:30 PM PDT 24
Finished May 26 01:26:45 PM PDT 24
Peak memory 205204 kb
Host smart-e9ee2c89-2c43-49db-8ddf-8479e214ffcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304
35528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2530435528
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.377428542
Short name T258
Test name
Test status
Simulation time 25024333125 ps
CPU time 47.95 seconds
Started May 26 01:26:15 PM PDT 24
Finished May 26 01:27:04 PM PDT 24
Peak memory 205352 kb
Host smart-40e32741-859a-4df8-8fbc-85507fb97491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
8542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.377428542
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1423486908
Short name T347
Test name
Test status
Simulation time 10054500299 ps
CPU time 14.33 seconds
Started May 26 01:26:16 PM PDT 24
Finished May 26 01:26:31 PM PDT 24
Peak memory 205256 kb
Host smart-744cc714-bae5-486a-9893-df870fd914cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
86908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1423486908
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1707811236
Short name T1881
Test name
Test status
Simulation time 10056214061 ps
CPU time 16.62 seconds
Started May 26 01:26:23 PM PDT 24
Finished May 26 01:26:41 PM PDT 24
Peak memory 205208 kb
Host smart-2e3c04fd-0921-4463-9991-349e1c4c2ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17078
11236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1707811236
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3307917812
Short name T1280
Test name
Test status
Simulation time 10126395970 ps
CPU time 14.23 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 205268 kb
Host smart-6f787f55-cc1e-42f6-b33f-585ad78efca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33079
17812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3307917812
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.178960196
Short name T1467
Test name
Test status
Simulation time 10047589571 ps
CPU time 14.26 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 205248 kb
Host smart-050871b5-438b-43d7-8d74-20f8c94e2804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17896
0196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.178960196
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.262043306
Short name T714
Test name
Test status
Simulation time 10057943504 ps
CPU time 13.77 seconds
Started May 26 01:26:25 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 205336 kb
Host smart-b9175a39-780d-4c8d-ba02-e6b56a979470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26204
3306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.262043306
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2384187426
Short name T1262
Test name
Test status
Simulation time 10089562116 ps
CPU time 13.49 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:38 PM PDT 24
Peak memory 205356 kb
Host smart-f8efd190-b5fb-47ee-b9f2-0e290204dbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23841
87426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2384187426
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1702853104
Short name T1592
Test name
Test status
Simulation time 10145036235 ps
CPU time 14.5 seconds
Started May 26 01:26:07 PM PDT 24
Finished May 26 01:26:22 PM PDT 24
Peak memory 205328 kb
Host smart-54e4551a-1260-4270-a097-a311634d41ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17028
53104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1702853104
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.4193529321
Short name T1316
Test name
Test status
Simulation time 10084149873 ps
CPU time 16.26 seconds
Started May 26 01:26:22 PM PDT 24
Finished May 26 01:26:39 PM PDT 24
Peak memory 205288 kb
Host smart-6371faab-fc5d-457b-a601-5987a2bab9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41935
29321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.4193529321
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3664536728
Short name T525
Test name
Test status
Simulation time 10061493864 ps
CPU time 17.1 seconds
Started May 26 01:26:24 PM PDT 24
Finished May 26 01:26:42 PM PDT 24
Peak memory 205316 kb
Host smart-4c86615e-fb1d-4615-8653-c1847663e66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
36728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3664536728
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.169947435
Short name T15
Test name
Test status
Simulation time 10138783704 ps
CPU time 15.91 seconds
Started May 26 01:27:06 PM PDT 24
Finished May 26 01:27:23 PM PDT 24
Peak memory 205312 kb
Host smart-0d4bb50c-35fd-4a42-a1f6-21417befc420
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=169947435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.169947435
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.2262686223
Short name T1213
Test name
Test status
Simulation time 10071642942 ps
CPU time 14.64 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:21 PM PDT 24
Peak memory 205344 kb
Host smart-dab53337-d4c8-46dc-895f-1a24f458cdde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2262686223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.2262686223
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.480755540
Short name T796
Test name
Test status
Simulation time 10131226240 ps
CPU time 15.57 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:22 PM PDT 24
Peak memory 205304 kb
Host smart-d3af7a6e-10e6-4424-891f-db7b18237aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48075
5540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.480755540
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3907141122
Short name T201
Test name
Test status
Simulation time 14171615631 ps
CPU time 22.42 seconds
Started May 26 01:26:39 PM PDT 24
Finished May 26 01:27:02 PM PDT 24
Peak memory 205316 kb
Host smart-6fb63ba0-bdf9-41ff-b726-c6e38a51212e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3907141122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3907141122
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.115836825
Short name T1088
Test name
Test status
Simulation time 13305143704 ps
CPU time 18.93 seconds
Started May 26 01:26:39 PM PDT 24
Finished May 26 01:26:58 PM PDT 24
Peak memory 205324 kb
Host smart-5d29ca88-7981-43c5-bbad-5fc34e1f8bf0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=115836825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.115836825
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3665683957
Short name T1173
Test name
Test status
Simulation time 13213101986 ps
CPU time 17.45 seconds
Started May 26 01:26:40 PM PDT 24
Finished May 26 01:26:58 PM PDT 24
Peak memory 205276 kb
Host smart-1b3c90ce-d0e0-49dc-8e02-b18ca450a794
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3665683957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3665683957
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.697449203
Short name T1347
Test name
Test status
Simulation time 10048861378 ps
CPU time 17.96 seconds
Started May 26 01:26:42 PM PDT 24
Finished May 26 01:27:00 PM PDT 24
Peak memory 205216 kb
Host smart-a25b8f8d-eace-4dec-8cfe-de76857d8602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69744
9203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.697449203
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.3220674848
Short name T1896
Test name
Test status
Simulation time 10625961888 ps
CPU time 14.26 seconds
Started May 26 01:26:42 PM PDT 24
Finished May 26 01:26:57 PM PDT 24
Peak memory 205276 kb
Host smart-0492b716-f2cb-4914-821a-860d26dba3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32206
74848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3220674848
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3089295791
Short name T950
Test name
Test status
Simulation time 10049382728 ps
CPU time 14.9 seconds
Started May 26 01:26:50 PM PDT 24
Finished May 26 01:27:06 PM PDT 24
Peak memory 205232 kb
Host smart-57113c60-b6db-462f-8255-368d936fe207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
95791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3089295791
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3926055578
Short name T836
Test name
Test status
Simulation time 10048042765 ps
CPU time 13.96 seconds
Started May 26 01:26:52 PM PDT 24
Finished May 26 01:27:07 PM PDT 24
Peak memory 205304 kb
Host smart-bd4beb7a-c655-4f06-9d43-9a88ee5f627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39260
55578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3926055578
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3155491852
Short name T1906
Test name
Test status
Simulation time 10747597761 ps
CPU time 16.14 seconds
Started May 26 01:26:39 PM PDT 24
Finished May 26 01:26:56 PM PDT 24
Peak memory 205208 kb
Host smart-1301e4aa-7c30-4ddf-94c7-f2f8bf6f9b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31554
91852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3155491852
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.798224525
Short name T731
Test name
Test status
Simulation time 10069019136 ps
CPU time 15.87 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:27:05 PM PDT 24
Peak memory 205172 kb
Host smart-f70028f5-3d5f-4d71-b8b6-a58f753f868d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79822
4525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.798224525
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3276035665
Short name T1487
Test name
Test status
Simulation time 10106330887 ps
CPU time 15.2 seconds
Started May 26 01:27:04 PM PDT 24
Finished May 26 01:27:20 PM PDT 24
Peak memory 205188 kb
Host smart-e72b1aac-a5c0-4b1f-9573-e5328c7f8016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
35665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3276035665
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3069353823
Short name T1723
Test name
Test status
Simulation time 10058407186 ps
CPU time 15.46 seconds
Started May 26 01:27:04 PM PDT 24
Finished May 26 01:27:21 PM PDT 24
Peak memory 205312 kb
Host smart-acea7927-6c00-4239-a25f-efde95629aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30693
53823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3069353823
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.321324253
Short name T1713
Test name
Test status
Simulation time 10095629171 ps
CPU time 15.62 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:03 PM PDT 24
Peak memory 205272 kb
Host smart-dcbe01c2-7643-402a-b2c0-aceb789b7631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32132
4253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.321324253
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3906160405
Short name T1307
Test name
Test status
Simulation time 10078489583 ps
CPU time 14.3 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 01:27:04 PM PDT 24
Peak memory 205260 kb
Host smart-94669e63-7679-42fa-84b3-01a72130149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39061
60405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3906160405
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1136830766
Short name T1227
Test name
Test status
Simulation time 13160816507 ps
CPU time 17.34 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:05 PM PDT 24
Peak memory 205244 kb
Host smart-0b240766-5498-4d52-896f-ae8617e7d44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368
30766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1136830766
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4075464237
Short name T723
Test name
Test status
Simulation time 10100975308 ps
CPU time 14.55 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 01:27:04 PM PDT 24
Peak memory 205284 kb
Host smart-d1acd065-5f25-4898-b6a5-1e6910d7783d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40754
64237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4075464237
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2647914140
Short name T562
Test name
Test status
Simulation time 10065190816 ps
CPU time 13.7 seconds
Started May 26 01:26:49 PM PDT 24
Finished May 26 01:27:03 PM PDT 24
Peak memory 205240 kb
Host smart-c0127a6b-8d30-412c-9776-9ee1ce1779ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26479
14140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2647914140
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.4125977551
Short name T1774
Test name
Test status
Simulation time 10104528980 ps
CPU time 13.09 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:00 PM PDT 24
Peak memory 205176 kb
Host smart-ebf9b380-6628-477f-8170-48092a03485d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41259
77551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.4125977551
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2277605185
Short name T1042
Test name
Test status
Simulation time 10080351039 ps
CPU time 15.93 seconds
Started May 26 01:26:50 PM PDT 24
Finished May 26 01:27:06 PM PDT 24
Peak memory 205288 kb
Host smart-edf47927-79a4-46ed-b6bd-69d1ea291458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22776
05185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2277605185
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1651360541
Short name T1304
Test name
Test status
Simulation time 10077391728 ps
CPU time 13.79 seconds
Started May 26 01:26:47 PM PDT 24
Finished May 26 01:27:02 PM PDT 24
Peak memory 205260 kb
Host smart-0631e01c-77d6-4839-8b62-ce46b442527c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16513
60541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1651360541
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3458682652
Short name T1382
Test name
Test status
Simulation time 10138939911 ps
CPU time 12.89 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:19 PM PDT 24
Peak memory 205260 kb
Host smart-fd684b5e-9b77-45cd-923c-c0cf073fc128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
82652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3458682652
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.2364669618
Short name T1327
Test name
Test status
Simulation time 10068364901 ps
CPU time 14.36 seconds
Started May 26 01:26:57 PM PDT 24
Finished May 26 01:27:12 PM PDT 24
Peak memory 205228 kb
Host smart-734cf1ae-6a19-4c46-b774-c85aeaeb6ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23646
69618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.2364669618
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2074820457
Short name T1589
Test name
Test status
Simulation time 10046229961 ps
CPU time 14.46 seconds
Started May 26 01:26:57 PM PDT 24
Finished May 26 01:27:12 PM PDT 24
Peak memory 205308 kb
Host smart-675a2286-9b35-401e-b3ad-abc9aae3f61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20748
20457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2074820457
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.91766673
Short name T45
Test name
Test status
Simulation time 10034545025 ps
CPU time 14.66 seconds
Started May 26 01:27:05 PM PDT 24
Finished May 26 01:27:21 PM PDT 24
Peak memory 205248 kb
Host smart-fd44d49f-08da-40ae-8a06-b5155863961d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91766
673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.91766673
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3145726054
Short name T978
Test name
Test status
Simulation time 20364127073 ps
CPU time 42.35 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:27:31 PM PDT 24
Peak memory 205336 kb
Host smart-e7160be1-f306-4c4a-a41c-b544bd91f96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
26054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3145726054
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3172867454
Short name T767
Test name
Test status
Simulation time 10104536100 ps
CPU time 15.34 seconds
Started May 26 01:26:48 PM PDT 24
Finished May 26 01:27:05 PM PDT 24
Peak memory 205264 kb
Host smart-bc2c8e6d-7d80-41d1-9f29-bb4a862f7f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31728
67454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3172867454
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1964181896
Short name T1854
Test name
Test status
Simulation time 10087987344 ps
CPU time 15.81 seconds
Started May 26 01:26:56 PM PDT 24
Finished May 26 01:27:12 PM PDT 24
Peak memory 205244 kb
Host smart-27dbdc6c-0a00-41e5-921b-385b4e897c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19641
81896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1964181896
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.923797795
Short name T847
Test name
Test status
Simulation time 10092504915 ps
CPU time 14 seconds
Started May 26 01:26:56 PM PDT 24
Finished May 26 01:27:11 PM PDT 24
Peak memory 205292 kb
Host smart-ec1b1b79-093b-4cb4-be81-8ce512d058b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92379
7795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.923797795
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3955047228
Short name T1733
Test name
Test status
Simulation time 10047869660 ps
CPU time 17.54 seconds
Started May 26 01:26:58 PM PDT 24
Finished May 26 01:27:16 PM PDT 24
Peak memory 205332 kb
Host smart-be9d97f6-5062-40fa-8345-796cc5d0decc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
47228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3955047228
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3441244781
Short name T204
Test name
Test status
Simulation time 341770037 ps
CPU time 1.14 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:16 PM PDT 24
Peak memory 221488 kb
Host smart-f24e2620-9ab4-4e3f-851e-a356f1352bfb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3441244781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3441244781
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3752320724
Short name T967
Test name
Test status
Simulation time 10110628284 ps
CPU time 13.48 seconds
Started May 26 01:26:39 PM PDT 24
Finished May 26 01:26:53 PM PDT 24
Peak memory 205196 kb
Host smart-5391a979-405f-4331-8bfa-8a7b005f7373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37523
20724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3752320724
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.747089907
Short name T1705
Test name
Test status
Simulation time 10084065282 ps
CPU time 14.02 seconds
Started May 26 01:26:59 PM PDT 24
Finished May 26 01:27:13 PM PDT 24
Peak memory 205236 kb
Host smart-a007878d-7938-41cf-8df2-3fb547a87294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74708
9907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.747089907
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1158998152
Short name T880
Test name
Test status
Simulation time 10080123675 ps
CPU time 18.17 seconds
Started May 26 01:26:56 PM PDT 24
Finished May 26 01:27:15 PM PDT 24
Peak memory 205336 kb
Host smart-116f396a-61f5-4318-9a2b-bb23692325b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11589
98152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1158998152
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3768220907
Short name T536
Test name
Test status
Simulation time 10161288073 ps
CPU time 17.18 seconds
Started May 26 01:31:11 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 205216 kb
Host smart-3057baf0-5e85-4812-a134-88f46e88f4dc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3768220907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3768220907
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.3533192548
Short name T1583
Test name
Test status
Simulation time 10091450186 ps
CPU time 13.32 seconds
Started May 26 01:31:04 PM PDT 24
Finished May 26 01:31:18 PM PDT 24
Peak memory 205260 kb
Host smart-16808305-3e92-43d6-808e-a64209586551
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3533192548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.3533192548
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.1378920880
Short name T549
Test name
Test status
Simulation time 10093978284 ps
CPU time 13.66 seconds
Started May 26 01:31:06 PM PDT 24
Finished May 26 01:31:21 PM PDT 24
Peak memory 205228 kb
Host smart-9d7d6ccc-e2ea-4f6b-bd3b-03cf05c51e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13789
20880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.1378920880
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2747102997
Short name T632
Test name
Test status
Simulation time 14259060584 ps
CPU time 18.54 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:31:04 PM PDT 24
Peak memory 205276 kb
Host smart-b21b42b9-5246-44d6-98d9-f96e356a7663
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2747102997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2747102997
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1070768624
Short name T5
Test name
Test status
Simulation time 13293522270 ps
CPU time 15.87 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:31:02 PM PDT 24
Peak memory 205292 kb
Host smart-850ab71b-5463-444c-98d7-4368fbd33a0c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1070768624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1070768624
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3527800064
Short name T609
Test name
Test status
Simulation time 13341379026 ps
CPU time 19.66 seconds
Started May 26 01:30:46 PM PDT 24
Finished May 26 01:31:06 PM PDT 24
Peak memory 205300 kb
Host smart-32dd3e47-c83a-4bd7-bce5-4c5d81847557
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3527800064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3527800064
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1856469910
Short name T1795
Test name
Test status
Simulation time 10072617539 ps
CPU time 15.65 seconds
Started May 26 01:30:43 PM PDT 24
Finished May 26 01:30:59 PM PDT 24
Peak memory 205228 kb
Host smart-56207fab-ae27-4f20-b278-89cd58fe8ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18564
69910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1856469910
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2156763632
Short name T919
Test name
Test status
Simulation time 10105369878 ps
CPU time 14.46 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:31:00 PM PDT 24
Peak memory 205360 kb
Host smart-62fc20ee-83f4-4025-b342-1d9c1c96daf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567
63632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2156763632
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2767715563
Short name T1763
Test name
Test status
Simulation time 10044727615 ps
CPU time 14.82 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:31:09 PM PDT 24
Peak memory 205456 kb
Host smart-328f3ba1-1836-4f8d-a9e5-5c0e929e5501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27677
15563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2767715563
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3152050452
Short name T423
Test name
Test status
Simulation time 10048572904 ps
CPU time 15.79 seconds
Started May 26 01:30:52 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 205320 kb
Host smart-19b8baff-aaec-45c4-963d-020d5ac3f564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31520
50452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3152050452
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3947288381
Short name T1045
Test name
Test status
Simulation time 10869424461 ps
CPU time 16.71 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:31:10 PM PDT 24
Peak memory 205264 kb
Host smart-de41954c-0240-4783-9b6e-3c22c4182ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472
88381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3947288381
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.26883990
Short name T989
Test name
Test status
Simulation time 10062674344 ps
CPU time 13.77 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:17 PM PDT 24
Peak memory 205232 kb
Host smart-3faa0e36-2aa0-4938-a98a-b97b4542a47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26883
990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.26883990
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2002753090
Short name T1230
Test name
Test status
Simulation time 10053535801 ps
CPU time 14.78 seconds
Started May 26 01:31:07 PM PDT 24
Finished May 26 01:31:23 PM PDT 24
Peak memory 205280 kb
Host smart-362615e0-f810-462f-9b31-e631801f1ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
53090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2002753090
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.291984272
Short name T906
Test name
Test status
Simulation time 10090694424 ps
CPU time 13.43 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 205300 kb
Host smart-92f52a02-8dba-4a6b-b2d4-13caf90fcbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
4272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.291984272
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1196217779
Short name T580
Test name
Test status
Simulation time 10099557091 ps
CPU time 17.55 seconds
Started May 26 01:30:55 PM PDT 24
Finished May 26 01:31:13 PM PDT 24
Peak memory 205452 kb
Host smart-992109b5-e9de-4a78-a0b4-4b2c42391ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11962
17779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1196217779
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3355901434
Short name T756
Test name
Test status
Simulation time 13169436946 ps
CPU time 18.58 seconds
Started May 26 01:30:51 PM PDT 24
Finished May 26 01:31:11 PM PDT 24
Peak memory 205280 kb
Host smart-9ffbcdba-e794-4c54-86b8-c5ec10c10d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33559
01434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3355901434
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2299468536
Short name T666
Test name
Test status
Simulation time 10124621956 ps
CPU time 13.75 seconds
Started May 26 01:30:53 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 205284 kb
Host smart-61fb7a6a-d0cc-43fd-bcbd-c5df1cb90498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22994
68536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2299468536
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2874571647
Short name T628
Test name
Test status
Simulation time 10054855795 ps
CPU time 15.59 seconds
Started May 26 01:30:54 PM PDT 24
Finished May 26 01:31:10 PM PDT 24
Peak memory 205312 kb
Host smart-0f705023-e4f1-4f32-9f4b-ab7f370e23a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28745
71647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2874571647
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.4059098413
Short name T220
Test name
Test status
Simulation time 10117872305 ps
CPU time 15.03 seconds
Started May 26 01:30:52 PM PDT 24
Finished May 26 01:31:08 PM PDT 24
Peak memory 205268 kb
Host smart-4af676a3-637a-4526-8611-0b3c6ceeba14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40590
98413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.4059098413
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3372590235
Short name T537
Test name
Test status
Simulation time 10097275955 ps
CPU time 14.34 seconds
Started May 26 01:31:00 PM PDT 24
Finished May 26 01:31:15 PM PDT 24
Peak memory 205292 kb
Host smart-13da79fc-fdc5-413d-b0b7-5ed86d1af88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
90235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3372590235
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.3871703833
Short name T618
Test name
Test status
Simulation time 10107865616 ps
CPU time 17.01 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:19 PM PDT 24
Peak memory 205300 kb
Host smart-f044d453-abc3-4622-9492-cb64431dace3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
03833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.3871703833
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2533560897
Short name T325
Test name
Test status
Simulation time 10095493765 ps
CPU time 14.88 seconds
Started May 26 01:31:04 PM PDT 24
Finished May 26 01:31:19 PM PDT 24
Peak memory 205296 kb
Host smart-102432a9-a04e-40f1-9e7b-e3371e005898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25335
60897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2533560897
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.1006438856
Short name T1006
Test name
Test status
Simulation time 10084728859 ps
CPU time 16.5 seconds
Started May 26 01:31:02 PM PDT 24
Finished May 26 01:31:20 PM PDT 24
Peak memory 205224 kb
Host smart-07e9961c-38b8-4792-bf48-490eaa6b583f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10064
38856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.1006438856
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2792684714
Short name T1071
Test name
Test status
Simulation time 10044573574 ps
CPU time 15.33 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:19 PM PDT 24
Peak memory 205272 kb
Host smart-12d6a06c-24ec-4832-ad12-0f9b3ce32308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27926
84714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2792684714
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2322263931
Short name T47
Test name
Test status
Simulation time 10046339847 ps
CPU time 16.76 seconds
Started May 26 01:31:05 PM PDT 24
Finished May 26 01:31:22 PM PDT 24
Peak memory 205260 kb
Host smart-6322b4fb-f0c1-402c-9bb1-b6b25cc2c310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23222
63931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2322263931
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.342631496
Short name T1744
Test name
Test status
Simulation time 28516473640 ps
CPU time 52.82 seconds
Started May 26 01:31:00 PM PDT 24
Finished May 26 01:31:54 PM PDT 24
Peak memory 205248 kb
Host smart-9e2a4b2d-71e0-4e67-85e8-609ee0c6c1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263
1496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.342631496
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1031544867
Short name T1684
Test name
Test status
Simulation time 10090023588 ps
CPU time 17.16 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:19 PM PDT 24
Peak memory 205208 kb
Host smart-ade095c2-307e-481c-888c-212a2d78677c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10315
44867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1031544867
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2647651887
Short name T412
Test name
Test status
Simulation time 10101784701 ps
CPU time 18.21 seconds
Started May 26 01:31:00 PM PDT 24
Finished May 26 01:31:19 PM PDT 24
Peak memory 205288 kb
Host smart-26a386a8-2e31-4519-ada4-dce5ca023a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
51887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2647651887
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.11196944
Short name T1419
Test name
Test status
Simulation time 10095097396 ps
CPU time 14.39 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:16 PM PDT 24
Peak memory 205240 kb
Host smart-2a871238-7406-4eab-adf6-b234d43dfd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.11196944
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3904546796
Short name T851
Test name
Test status
Simulation time 10037156369 ps
CPU time 16.12 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:20 PM PDT 24
Peak memory 205320 kb
Host smart-8dadbb30-4819-4274-b267-0dc5e52e686e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39045
46796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3904546796
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.934190941
Short name T14
Test name
Test status
Simulation time 10058358465 ps
CPU time 15.85 seconds
Started May 26 01:31:01 PM PDT 24
Finished May 26 01:31:18 PM PDT 24
Peak memory 205292 kb
Host smart-9591ebcb-5384-43a5-a885-e55742857eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93419
0941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.934190941
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.833429202
Short name T706
Test name
Test status
Simulation time 10046210318 ps
CPU time 17.26 seconds
Started May 26 01:31:05 PM PDT 24
Finished May 26 01:31:22 PM PDT 24
Peak memory 205356 kb
Host smart-b4a871b0-1e11-464b-b9f3-b0ae9a854c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83342
9202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.833429202
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2510014283
Short name T158
Test name
Test status
Simulation time 10126918235 ps
CPU time 13.77 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:31:00 PM PDT 24
Peak memory 205272 kb
Host smart-345fd94a-dbc4-40ae-b791-71ce8ff03bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100
14283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2510014283
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1848479928
Short name T445
Test name
Test status
Simulation time 10086547910 ps
CPU time 13.65 seconds
Started May 26 01:31:00 PM PDT 24
Finished May 26 01:31:15 PM PDT 24
Peak memory 205244 kb
Host smart-2c744597-98f3-437c-8d72-0c145fff9ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
79928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1848479928
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3736691032
Short name T1370
Test name
Test status
Simulation time 10093851836 ps
CPU time 17.68 seconds
Started May 26 01:31:03 PM PDT 24
Finished May 26 01:31:22 PM PDT 24
Peak memory 205276 kb
Host smart-65713f1b-954b-4e66-bb6d-ef8565eaa8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37366
91032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3736691032
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.78515029
Short name T734
Test name
Test status
Simulation time 10165472662 ps
CPU time 13.58 seconds
Started May 26 01:31:31 PM PDT 24
Finished May 26 01:31:45 PM PDT 24
Peak memory 205296 kb
Host smart-7a1e0666-171e-4c5d-8c4f-573cbd5aa047
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=78515029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.78515029
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.4039886033
Short name T457
Test name
Test status
Simulation time 10061940600 ps
CPU time 15.14 seconds
Started May 26 01:31:32 PM PDT 24
Finished May 26 01:31:48 PM PDT 24
Peak memory 205248 kb
Host smart-03555b4d-c2b1-4e6c-935b-c646dfbceb7b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4039886033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.4039886033
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.808869018
Short name T425
Test name
Test status
Simulation time 10107164194 ps
CPU time 13.63 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:42 PM PDT 24
Peak memory 205236 kb
Host smart-0b02b54e-d843-42ff-8b00-d4fe56cefd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80886
9018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.808869018
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2979554257
Short name T1932
Test name
Test status
Simulation time 13781453626 ps
CPU time 21.35 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:32 PM PDT 24
Peak memory 205348 kb
Host smart-3e0985a5-7004-4fd9-8489-7a8644727748
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2979554257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2979554257
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3729961967
Short name T12
Test name
Test status
Simulation time 13264527322 ps
CPU time 18.28 seconds
Started May 26 01:31:11 PM PDT 24
Finished May 26 01:31:31 PM PDT 24
Peak memory 205192 kb
Host smart-478ceb9b-212b-4ddd-9c3b-ad28b3d5427a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3729961967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3729961967
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3817230553
Short name T229
Test name
Test status
Simulation time 13311619108 ps
CPU time 18.2 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 205324 kb
Host smart-e7a3afad-f324-4474-a88f-555b51a651b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3817230553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3817230553
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2912734083
Short name T1639
Test name
Test status
Simulation time 10074608660 ps
CPU time 14.02 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 205216 kb
Host smart-6fe75600-8cd6-4b12-bbd7-b7b8e5f32ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29127
34083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2912734083
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2999451270
Short name T1442
Test name
Test status
Simulation time 11043085937 ps
CPU time 16.96 seconds
Started May 26 01:31:11 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 205316 kb
Host smart-832441f0-f347-4c11-b1fa-987b582081ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
51270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2999451270
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3450327503
Short name T1130
Test name
Test status
Simulation time 10052359348 ps
CPU time 16.37 seconds
Started May 26 01:31:17 PM PDT 24
Finished May 26 01:31:34 PM PDT 24
Peak memory 205248 kb
Host smart-6d66aab3-bbce-4feb-8fbb-c0a4b369c919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34503
27503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3450327503
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1462791919
Short name T887
Test name
Test status
Simulation time 10075786099 ps
CPU time 16.08 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:26 PM PDT 24
Peak memory 205276 kb
Host smart-1e4ec8c3-c1b5-4305-9d93-ce340991e6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14627
91919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1462791919
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3030254001
Short name T1485
Test name
Test status
Simulation time 10817654794 ps
CPU time 15.99 seconds
Started May 26 01:31:12 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 205168 kb
Host smart-933c00f6-6da5-44d9-96f5-00f79e1ada19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30302
54001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3030254001
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3364861560
Short name T1747
Test name
Test status
Simulation time 10193232725 ps
CPU time 17.17 seconds
Started May 26 01:31:14 PM PDT 24
Finished May 26 01:31:32 PM PDT 24
Peak memory 205268 kb
Host smart-512cdcd1-4e1a-44de-920f-1711ceae0c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33648
61560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3364861560
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2864380625
Short name T1272
Test name
Test status
Simulation time 10149353867 ps
CPU time 15.49 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:43 PM PDT 24
Peak memory 205328 kb
Host smart-7ad0f49e-5bd0-433e-95ff-23f29cec8f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28643
80625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2864380625
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3126953198
Short name T916
Test name
Test status
Simulation time 10044470710 ps
CPU time 14.92 seconds
Started May 26 01:31:28 PM PDT 24
Finished May 26 01:31:44 PM PDT 24
Peak memory 205236 kb
Host smart-07e8fa62-24ac-4130-bcb8-661bcbdf1c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31269
53198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3126953198
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3308217004
Short name T1679
Test name
Test status
Simulation time 10207367029 ps
CPU time 15.44 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:25 PM PDT 24
Peak memory 205180 kb
Host smart-6d93e899-f2e4-4dc2-8725-90087b31149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
17004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3308217004
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3386483234
Short name T1018
Test name
Test status
Simulation time 10058536705 ps
CPU time 14.91 seconds
Started May 26 01:31:13 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 205212 kb
Host smart-9db32ddc-f143-4538-beba-7e5c5641d6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33864
83234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3386483234
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1281346652
Short name T1568
Test name
Test status
Simulation time 13245993757 ps
CPU time 17.32 seconds
Started May 26 01:31:10 PM PDT 24
Finished May 26 01:31:28 PM PDT 24
Peak memory 205212 kb
Host smart-0e31ff77-273b-48fb-a1bb-11606a252e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12813
46652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1281346652
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3045866333
Short name T1274
Test name
Test status
Simulation time 10096613671 ps
CPU time 16.76 seconds
Started May 26 01:31:12 PM PDT 24
Finished May 26 01:31:29 PM PDT 24
Peak memory 205312 kb
Host smart-647ca08f-6a1f-4528-ab41-c0e8de5ddf97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30458
66333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3045866333
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2510198169
Short name T528
Test name
Test status
Simulation time 10052233167 ps
CPU time 14.29 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 205192 kb
Host smart-8d0c80e1-2609-4de9-9bb6-ba15da6f1d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25101
98169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2510198169
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2479222625
Short name T1721
Test name
Test status
Simulation time 10105993466 ps
CPU time 13.99 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 205312 kb
Host smart-07bd21ba-96fc-4af8-b1ec-bd441ac21720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24792
22625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2479222625
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.4267795074
Short name T739
Test name
Test status
Simulation time 10093786549 ps
CPU time 15.47 seconds
Started May 26 01:31:19 PM PDT 24
Finished May 26 01:31:36 PM PDT 24
Peak memory 205296 kb
Host smart-bac82dfe-440a-4525-b246-8a5a401d7ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42677
95074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.4267795074
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3584042757
Short name T335
Test name
Test status
Simulation time 10086603477 ps
CPU time 15.42 seconds
Started May 26 01:31:25 PM PDT 24
Finished May 26 01:31:41 PM PDT 24
Peak memory 205248 kb
Host smart-75bdc873-74ac-4a4e-b1c0-e75939ce00c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35840
42757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3584042757
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.2786124964
Short name T1517
Test name
Test status
Simulation time 10084989004 ps
CPU time 13.49 seconds
Started May 26 01:31:32 PM PDT 24
Finished May 26 01:31:46 PM PDT 24
Peak memory 205204 kb
Host smart-72a5d3b4-1536-48d8-9303-82c89b9c8254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27861
24964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.2786124964
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.4159142421
Short name T743
Test name
Test status
Simulation time 10037378748 ps
CPU time 17.17 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:46 PM PDT 24
Peak memory 205200 kb
Host smart-3558ec06-d759-4941-b438-1c920b34a80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591
42421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.4159142421
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2189106172
Short name T1326
Test name
Test status
Simulation time 20666646669 ps
CPU time 37.35 seconds
Started May 26 01:31:17 PM PDT 24
Finished May 26 01:31:56 PM PDT 24
Peak memory 205364 kb
Host smart-660e0606-1c82-403f-b625-35b841f647a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21891
06172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2189106172
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.4118461366
Short name T1096
Test name
Test status
Simulation time 10067714812 ps
CPU time 14.16 seconds
Started May 26 01:31:19 PM PDT 24
Finished May 26 01:31:34 PM PDT 24
Peak memory 205208 kb
Host smart-a3bb2872-4c74-4854-a94f-0305720cea2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41184
61366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.4118461366
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4226592312
Short name T1486
Test name
Test status
Simulation time 10104928074 ps
CPU time 14.08 seconds
Started May 26 01:31:17 PM PDT 24
Finished May 26 01:31:32 PM PDT 24
Peak memory 205260 kb
Host smart-635e1cb5-102f-46e5-9f27-b5fbb43c8c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265
92312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4226592312
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.1755131655
Short name T1732
Test name
Test status
Simulation time 10079400605 ps
CPU time 13.58 seconds
Started May 26 01:31:20 PM PDT 24
Finished May 26 01:31:34 PM PDT 24
Peak memory 205304 kb
Host smart-b9636b6a-614d-4d03-a3da-6b0d6586420d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
31655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.1755131655
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1941122011
Short name T930
Test name
Test status
Simulation time 10054856357 ps
CPU time 14.25 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 205344 kb
Host smart-a91f71b3-a3ac-4878-8d83-3d40116af268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19411
22011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1941122011
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1679508561
Short name T157
Test name
Test status
Simulation time 10051231153 ps
CPU time 15.26 seconds
Started May 26 01:31:31 PM PDT 24
Finished May 26 01:31:47 PM PDT 24
Peak memory 205288 kb
Host smart-23b22eb1-3565-441e-a96a-8da16a0be96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16795
08561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1679508561
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.468399713
Short name T1315
Test name
Test status
Simulation time 10054744514 ps
CPU time 15.15 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:44 PM PDT 24
Peak memory 205276 kb
Host smart-9ef287fe-1e13-4579-8d76-859f118c04e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46839
9713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.468399713
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3022984032
Short name T921
Test name
Test status
Simulation time 10080371225 ps
CPU time 13.54 seconds
Started May 26 01:31:09 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 205288 kb
Host smart-b13a8256-cea9-4181-8fe2-3ca32c18471a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
84032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3022984032
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.4250897535
Short name T1355
Test name
Test status
Simulation time 10047204256 ps
CPU time 14.8 seconds
Started May 26 01:31:27 PM PDT 24
Finished May 26 01:31:44 PM PDT 24
Peak memory 205452 kb
Host smart-fd6b1350-0cb1-4258-832d-b4af33f16e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42508
97535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.4250897535
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1989104918
Short name T1109
Test name
Test status
Simulation time 10086469267 ps
CPU time 14.86 seconds
Started May 26 01:31:18 PM PDT 24
Finished May 26 01:31:33 PM PDT 24
Peak memory 205168 kb
Host smart-f1cbf85a-67bd-4760-b8f7-5de9650a395e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
04918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1989104918
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.1899212117
Short name T1798
Test name
Test status
Simulation time 10171748010 ps
CPU time 13.31 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 205240 kb
Host smart-bf8b76be-8fcc-49df-9e4b-fa99df1afbce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1899212117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.1899212117
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.321661421
Short name T877
Test name
Test status
Simulation time 10146368804 ps
CPU time 13.53 seconds
Started May 26 01:31:59 PM PDT 24
Finished May 26 01:32:13 PM PDT 24
Peak memory 205232 kb
Host smart-5c27c3a7-a772-4344-9d04-2f1205fb0285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32166
1421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.321661421
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.69634713
Short name T1314
Test name
Test status
Simulation time 13360209343 ps
CPU time 17.13 seconds
Started May 26 01:31:37 PM PDT 24
Finished May 26 01:31:55 PM PDT 24
Peak memory 205220 kb
Host smart-0bb9bc1e-373b-48d2-8d50-c3aeb20ac91a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=69634713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.69634713
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4149403757
Short name T219
Test name
Test status
Simulation time 13311225075 ps
CPU time 20.11 seconds
Started May 26 01:31:39 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 205276 kb
Host smart-0778fe36-db09-4957-a5f8-e03b8e0b43b0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4149403757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4149403757
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3339482055
Short name T398
Test name
Test status
Simulation time 13234653343 ps
CPU time 17.33 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:31:54 PM PDT 24
Peak memory 205356 kb
Host smart-e0cb0469-56ac-4357-82b8-0b74848706f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3339482055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.3339482055
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1335084344
Short name T1816
Test name
Test status
Simulation time 10048871918 ps
CPU time 15.24 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:31:52 PM PDT 24
Peak memory 205308 kb
Host smart-c732e5e1-7c94-4990-ae22-b548fa693417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350
84344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1335084344
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.642414754
Short name T1098
Test name
Test status
Simulation time 10048928741 ps
CPU time 15.82 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:31:52 PM PDT 24
Peak memory 205276 kb
Host smart-c1d3f451-ee53-4a11-8704-d6be39f97910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64241
4754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.642414754
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2166404230
Short name T1489
Test name
Test status
Simulation time 10036120065 ps
CPU time 14.02 seconds
Started May 26 01:31:44 PM PDT 24
Finished May 26 01:31:58 PM PDT 24
Peak memory 205272 kb
Host smart-a4151ed3-24ab-4fee-a78a-f7f058ce1719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21664
04230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2166404230
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.468135132
Short name T1391
Test name
Test status
Simulation time 10131549547 ps
CPU time 13.04 seconds
Started May 26 01:31:35 PM PDT 24
Finished May 26 01:31:48 PM PDT 24
Peak memory 205336 kb
Host smart-b91a76c9-deb2-4b2b-99c6-eabcd9254249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46813
5132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.468135132
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2226190010
Short name T1690
Test name
Test status
Simulation time 10686450355 ps
CPU time 14.23 seconds
Started May 26 01:31:38 PM PDT 24
Finished May 26 01:31:53 PM PDT 24
Peak memory 205316 kb
Host smart-e6663406-c2fa-4a13-871c-1845dd6e66f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22261
90010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2226190010
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3356034441
Short name T1640
Test name
Test status
Simulation time 10185170708 ps
CPU time 15.42 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:31:52 PM PDT 24
Peak memory 205280 kb
Host smart-17a29f8b-b86f-43e5-9302-4b326358d223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33560
34441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3356034441
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2958433934
Short name T1515
Test name
Test status
Simulation time 10104366132 ps
CPU time 15.49 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:13 PM PDT 24
Peak memory 205256 kb
Host smart-7f656750-e122-4137-a00e-d14290648187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
33934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2958433934
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1906760498
Short name T1617
Test name
Test status
Simulation time 10069349569 ps
CPU time 14.7 seconds
Started May 26 01:31:59 PM PDT 24
Finished May 26 01:32:15 PM PDT 24
Peak memory 205288 kb
Host smart-5f8d4800-faa3-4ca5-85a2-90bf582b30f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19067
60498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1906760498
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1564761302
Short name T1342
Test name
Test status
Simulation time 10103897522 ps
CPU time 13.09 seconds
Started May 26 01:31:42 PM PDT 24
Finished May 26 01:31:56 PM PDT 24
Peak memory 205332 kb
Host smart-983d95ea-0359-4201-9332-012f350cfcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
61302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1564761302
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2728714974
Short name T631
Test name
Test status
Simulation time 10078948442 ps
CPU time 14.24 seconds
Started May 26 01:31:45 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 205236 kb
Host smart-563c06db-40ba-44a6-8218-7140c174c8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27287
14974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2728714974
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.4283353494
Short name T812
Test name
Test status
Simulation time 13237910156 ps
CPU time 15.99 seconds
Started May 26 01:31:47 PM PDT 24
Finished May 26 01:32:04 PM PDT 24
Peak memory 205228 kb
Host smart-007e3887-9933-418e-9165-71018f8261a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42833
53494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.4283353494
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3881186791
Short name T1013
Test name
Test status
Simulation time 10200679920 ps
CPU time 13.92 seconds
Started May 26 01:31:44 PM PDT 24
Finished May 26 01:31:58 PM PDT 24
Peak memory 205252 kb
Host smart-016d0969-6803-4385-a294-1fda734d460a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811
86791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3881186791
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.384300538
Short name T1856
Test name
Test status
Simulation time 10062154777 ps
CPU time 15.87 seconds
Started May 26 01:31:43 PM PDT 24
Finished May 26 01:32:00 PM PDT 24
Peak memory 205216 kb
Host smart-bcb1c864-9afc-4a16-bc55-72f223a98454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38430
0538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.384300538
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1165709752
Short name T673
Test name
Test status
Simulation time 10149693247 ps
CPU time 16.39 seconds
Started May 26 01:31:45 PM PDT 24
Finished May 26 01:32:02 PM PDT 24
Peak memory 205268 kb
Host smart-829aa765-0788-4ed7-9aba-d3a397ffe4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11657
09752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1165709752
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.398132877
Short name T1865
Test name
Test status
Simulation time 10098989474 ps
CPU time 16.5 seconds
Started May 26 01:31:47 PM PDT 24
Finished May 26 01:32:04 PM PDT 24
Peak memory 205292 kb
Host smart-755cccf2-d758-43eb-8933-eb683d2cb4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39813
2877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.398132877
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3708277143
Short name T770
Test name
Test status
Simulation time 10086030688 ps
CPU time 14.44 seconds
Started May 26 01:31:44 PM PDT 24
Finished May 26 01:31:59 PM PDT 24
Peak memory 205460 kb
Host smart-1a20a101-c68c-4df5-96bf-203b85c30cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37082
77143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3708277143
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.3091301031
Short name T421
Test name
Test status
Simulation time 10056070917 ps
CPU time 13.78 seconds
Started May 26 01:31:55 PM PDT 24
Finished May 26 01:32:09 PM PDT 24
Peak memory 205304 kb
Host smart-8acdf7cb-0628-4774-a369-89df8d290142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30913
01031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.3091301031
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2083929144
Short name T779
Test name
Test status
Simulation time 10047425631 ps
CPU time 14.14 seconds
Started May 26 01:31:56 PM PDT 24
Finished May 26 01:32:10 PM PDT 24
Peak memory 205472 kb
Host smart-cd7ea698-a34d-4ec0-b1f9-6167c95e129d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20839
29144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2083929144
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3183222516
Short name T1768
Test name
Test status
Simulation time 10032354570 ps
CPU time 14.91 seconds
Started May 26 01:31:59 PM PDT 24
Finished May 26 01:32:15 PM PDT 24
Peak memory 205308 kb
Host smart-65c1207f-b591-4827-b027-967bd5b58556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
22516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3183222516
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.356822928
Short name T1725
Test name
Test status
Simulation time 23432023479 ps
CPU time 52.68 seconds
Started May 26 01:31:43 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 205272 kb
Host smart-9f242a7f-84ea-4845-97d2-d8cad0f2b875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682
2928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.356822928
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3031888344
Short name T1780
Test name
Test status
Simulation time 10073549893 ps
CPU time 13.77 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 205196 kb
Host smart-f78b330c-ccc3-4ca8-93ef-0e613b0cb51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
88344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3031888344
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2650131721
Short name T1509
Test name
Test status
Simulation time 10120250956 ps
CPU time 14.34 seconds
Started May 26 01:31:55 PM PDT 24
Finished May 26 01:32:10 PM PDT 24
Peak memory 205252 kb
Host smart-542d8b31-5d51-4864-816f-7e1bac5775b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26501
31721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2650131721
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.1659573645
Short name T1134
Test name
Test status
Simulation time 10060621016 ps
CPU time 13.89 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:13 PM PDT 24
Peak memory 205196 kb
Host smart-74996828-b4b0-44ce-9366-9d80a2be36e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16595
73645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.1659573645
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3121828982
Short name T936
Test name
Test status
Simulation time 10086233663 ps
CPU time 13.59 seconds
Started May 26 01:32:01 PM PDT 24
Finished May 26 01:32:15 PM PDT 24
Peak memory 205280 kb
Host smart-1a58095f-3e58-4c99-b6bc-12c299c085b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31218
28982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3121828982
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.909293516
Short name T1349
Test name
Test status
Simulation time 10051054576 ps
CPU time 13.56 seconds
Started May 26 01:31:59 PM PDT 24
Finished May 26 01:32:13 PM PDT 24
Peak memory 205340 kb
Host smart-e131601c-6b65-4dd0-a6d8-881b642458d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90929
3516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.909293516
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.462712764
Short name T829
Test name
Test status
Simulation time 10064785427 ps
CPU time 14.16 seconds
Started May 26 01:31:57 PM PDT 24
Finished May 26 01:32:12 PM PDT 24
Peak memory 205492 kb
Host smart-6dfe7199-29db-4965-958e-a1a82062f67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46271
2764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.462712764
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2968127280
Short name T1597
Test name
Test status
Simulation time 10106019005 ps
CPU time 14.1 seconds
Started May 26 01:31:36 PM PDT 24
Finished May 26 01:31:50 PM PDT 24
Peak memory 205200 kb
Host smart-92fbe2d3-30d5-464b-9d58-35192e5d281c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29681
27280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2968127280
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1859992855
Short name T615
Test name
Test status
Simulation time 10079167988 ps
CPU time 16.12 seconds
Started May 26 01:32:02 PM PDT 24
Finished May 26 01:32:19 PM PDT 24
Peak memory 205268 kb
Host smart-22b71518-5062-48e1-91d6-69c7ec1b0fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18599
92855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1859992855
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3013384933
Short name T250
Test name
Test status
Simulation time 10048869336 ps
CPU time 16.86 seconds
Started May 26 01:31:58 PM PDT 24
Finished May 26 01:32:16 PM PDT 24
Peak memory 205288 kb
Host smart-3f87d981-20f3-4e09-9330-a5c70fe019fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30133
84933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3013384933
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.2313262246
Short name T1334
Test name
Test status
Simulation time 10159344699 ps
CPU time 15.19 seconds
Started May 26 01:32:20 PM PDT 24
Finished May 26 01:32:35 PM PDT 24
Peak memory 205252 kb
Host smart-b583ca49-159a-46af-9635-61d37878efe2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2313262246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.2313262246
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.2953779575
Short name T962
Test name
Test status
Simulation time 10055657479 ps
CPU time 15.12 seconds
Started May 26 01:32:23 PM PDT 24
Finished May 26 01:32:39 PM PDT 24
Peak memory 205276 kb
Host smart-1ecf8363-efbe-46ca-bbab-8808dcdd2520
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953779575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.2953779575
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.984643657
Short name T1152
Test name
Test status
Simulation time 10057042247 ps
CPU time 13.84 seconds
Started May 26 01:32:23 PM PDT 24
Finished May 26 01:32:37 PM PDT 24
Peak memory 205216 kb
Host smart-b7893165-419c-431b-9b4d-5cbb1b5b571d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98464
3657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.984643657
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3148410947
Short name T1158
Test name
Test status
Simulation time 14192439371 ps
CPU time 18.4 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:25 PM PDT 24
Peak memory 205316 kb
Host smart-8df67684-5e30-4674-8ad5-3eab959891aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3148410947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3148410947
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.728204664
Short name T1845
Test name
Test status
Simulation time 13309722709 ps
CPU time 18.46 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 205228 kb
Host smart-01453f26-6ca4-42b3-8050-3819c4838a3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=728204664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.728204664
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.303124214
Short name T1516
Test name
Test status
Simulation time 13336627736 ps
CPU time 17.82 seconds
Started May 26 01:32:07 PM PDT 24
Finished May 26 01:32:26 PM PDT 24
Peak memory 205288 kb
Host smart-9cc9f60c-d842-44d5-a6e0-7d6c99cd1a84
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=303124214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.303124214
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2204742188
Short name T896
Test name
Test status
Simulation time 10056181365 ps
CPU time 14.34 seconds
Started May 26 01:32:05 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 205260 kb
Host smart-1e7ca45f-afff-4271-b5c1-8ffb0fe20644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22047
42188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2204742188
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2977950785
Short name T965
Test name
Test status
Simulation time 10177309127 ps
CPU time 13.96 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 205332 kb
Host smart-d9b64117-7cb6-4332-819c-061b9993fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29779
50785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2977950785
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3022725486
Short name T1017
Test name
Test status
Simulation time 10063022116 ps
CPU time 14.9 seconds
Started May 26 01:32:07 PM PDT 24
Finished May 26 01:32:23 PM PDT 24
Peak memory 205232 kb
Host smart-224208c9-de7d-463a-9e09-b792a583d6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30227
25486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3022725486
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.1653212225
Short name T1078
Test name
Test status
Simulation time 10106723787 ps
CPU time 13.57 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 205320 kb
Host smart-1a5e7d02-05a3-4e74-ba91-7fd9ce82572b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16532
12225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.1653212225
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.12984131
Short name T676
Test name
Test status
Simulation time 10802760002 ps
CPU time 18.08 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:23 PM PDT 24
Peak memory 205252 kb
Host smart-762cc21a-e8e5-4abf-964d-725e889d3f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12984
131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.12984131
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1502931852
Short name T1815
Test name
Test status
Simulation time 10298851793 ps
CPU time 17.69 seconds
Started May 26 01:32:05 PM PDT 24
Finished May 26 01:32:24 PM PDT 24
Peak memory 205276 kb
Host smart-22704b5f-f33c-4297-a7ee-3394e281325a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15029
31852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1502931852
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.649938158
Short name T505
Test name
Test status
Simulation time 10091503681 ps
CPU time 13.83 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:35 PM PDT 24
Peak memory 205292 kb
Host smart-b5a2afc1-9043-4e95-96e5-82f6b362a882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64993
8158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.649938158
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2563610849
Short name T1700
Test name
Test status
Simulation time 10067280448 ps
CPU time 14.77 seconds
Started May 26 01:32:23 PM PDT 24
Finished May 26 01:32:38 PM PDT 24
Peak memory 205160 kb
Host smart-5fb80d85-8248-4a91-8cfa-46b100b8a49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25636
10849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2563610849
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1322640435
Short name T337
Test name
Test status
Simulation time 10122408464 ps
CPU time 16.08 seconds
Started May 26 01:32:07 PM PDT 24
Finished May 26 01:32:24 PM PDT 24
Peak memory 205324 kb
Host smart-798b69fe-223d-4ef4-ac07-a9255fe4685c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13226
40435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1322640435
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.519583291
Short name T1225
Test name
Test status
Simulation time 10113928493 ps
CPU time 13.63 seconds
Started May 26 01:32:04 PM PDT 24
Finished May 26 01:32:19 PM PDT 24
Peak memory 205336 kb
Host smart-72bdaf91-6ffb-43de-a118-a9b7dba6204c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51958
3291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.519583291
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1311050039
Short name T527
Test name
Test status
Simulation time 13227641005 ps
CPU time 17.76 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:25 PM PDT 24
Peak memory 205260 kb
Host smart-bdeaa11e-4158-4c98-b495-54e385119c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13110
50039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1311050039
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.160893054
Short name T504
Test name
Test status
Simulation time 10129146463 ps
CPU time 14.95 seconds
Started May 26 01:32:02 PM PDT 24
Finished May 26 01:32:18 PM PDT 24
Peak memory 205236 kb
Host smart-140fb6a4-53d7-471d-b31f-b391b96b642d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16089
3054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.160893054
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3478830613
Short name T761
Test name
Test status
Simulation time 10046192827 ps
CPU time 15.14 seconds
Started May 26 01:32:03 PM PDT 24
Finished May 26 01:32:19 PM PDT 24
Peak memory 205312 kb
Host smart-359c6398-d975-4414-a69d-a40d3daa8ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34788
30613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3478830613
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3401241173
Short name T755
Test name
Test status
Simulation time 10103007705 ps
CPU time 13.35 seconds
Started May 26 01:32:12 PM PDT 24
Finished May 26 01:32:27 PM PDT 24
Peak memory 205204 kb
Host smart-113e82a9-9cc0-4dea-aef1-32834e02970a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34012
41173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3401241173
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.4131512817
Short name T1103
Test name
Test status
Simulation time 10097220408 ps
CPU time 16.16 seconds
Started May 26 01:32:11 PM PDT 24
Finished May 26 01:32:28 PM PDT 24
Peak memory 205336 kb
Host smart-a62c1895-9842-48e2-8c08-9ba10f4da2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
12817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.4131512817
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.322162167
Short name T702
Test name
Test status
Simulation time 10064130952 ps
CPU time 16.24 seconds
Started May 26 01:32:18 PM PDT 24
Finished May 26 01:32:34 PM PDT 24
Peak memory 205272 kb
Host smart-901318cc-b538-4298-95d4-cd5324e206f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
2167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.322162167
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.653257587
Short name T1376
Test name
Test status
Simulation time 10095894269 ps
CPU time 14.82 seconds
Started May 26 01:32:11 PM PDT 24
Finished May 26 01:32:28 PM PDT 24
Peak memory 205328 kb
Host smart-38652d44-cba0-47ea-bcee-be82bba28da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65325
7587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.653257587
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3059279520
Short name T1196
Test name
Test status
Simulation time 10076606947 ps
CPU time 15.44 seconds
Started May 26 01:32:22 PM PDT 24
Finished May 26 01:32:38 PM PDT 24
Peak memory 205300 kb
Host smart-473ad925-a2d5-4646-af60-f0e84ce21bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30592
79520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3059279520
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.1752890172
Short name T1538
Test name
Test status
Simulation time 10132095907 ps
CPU time 14.82 seconds
Started May 26 01:32:13 PM PDT 24
Finished May 26 01:32:29 PM PDT 24
Peak memory 205224 kb
Host smart-b80a2ee7-45a3-4659-ad95-faa7b6e780a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
90172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.1752890172
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1368523114
Short name T1695
Test name
Test status
Simulation time 10059415236 ps
CPU time 14.19 seconds
Started May 26 01:32:15 PM PDT 24
Finished May 26 01:32:30 PM PDT 24
Peak memory 205200 kb
Host smart-dde601f9-cc0c-457a-8fa7-4b298fcbbe44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13685
23114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1368523114
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4081119327
Short name T1859
Test name
Test status
Simulation time 10042191597 ps
CPU time 13.75 seconds
Started May 26 01:32:22 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 205260 kb
Host smart-21c4e0b9-ced7-437a-bc9f-17633d42dbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
19327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4081119327
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1438421356
Short name T175
Test name
Test status
Simulation time 22404440256 ps
CPU time 39.87 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:55 PM PDT 24
Peak memory 205320 kb
Host smart-f50cffa7-9d2b-4034-a7d4-87f8d02fe65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14384
21356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1438421356
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3882547343
Short name T560
Test name
Test status
Simulation time 10066300991 ps
CPU time 14.58 seconds
Started May 26 01:32:15 PM PDT 24
Finished May 26 01:32:30 PM PDT 24
Peak memory 205272 kb
Host smart-a4eebed6-0779-4c9a-b7c9-ee533a7d1943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38825
47343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3882547343
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1149024665
Short name T1867
Test name
Test status
Simulation time 10137486776 ps
CPU time 18.11 seconds
Started May 26 01:32:17 PM PDT 24
Finished May 26 01:32:36 PM PDT 24
Peak memory 205220 kb
Host smart-4aca2735-71c6-43a8-aac9-e5980dd6fb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11490
24665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1149024665
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.56136141
Short name T1581
Test name
Test status
Simulation time 10093647378 ps
CPU time 14.18 seconds
Started May 26 01:32:13 PM PDT 24
Finished May 26 01:32:28 PM PDT 24
Peak memory 205232 kb
Host smart-86ae8c0a-1851-448d-8e1b-210716c95c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56136
141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.56136141
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3578480124
Short name T556
Test name
Test status
Simulation time 10038227178 ps
CPU time 12.52 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:28 PM PDT 24
Peak memory 205232 kb
Host smart-90e847d2-b3ba-4f17-9c44-63ed209ebd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35784
80124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3578480124
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1424170357
Short name T152
Test name
Test status
Simulation time 10060714637 ps
CPU time 13.47 seconds
Started May 26 01:32:16 PM PDT 24
Finished May 26 01:32:30 PM PDT 24
Peak memory 205300 kb
Host smart-d964b422-e678-4c20-aa99-1e0168c8d6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241
70357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1424170357
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1712486668
Short name T1217
Test name
Test status
Simulation time 10083383394 ps
CPU time 16.36 seconds
Started May 26 01:32:13 PM PDT 24
Finished May 26 01:32:30 PM PDT 24
Peak memory 205232 kb
Host smart-3649886e-6faf-40b2-b41d-ac889e754255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
86668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1712486668
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.146085032
Short name T957
Test name
Test status
Simulation time 10125291294 ps
CPU time 12.87 seconds
Started May 26 01:32:06 PM PDT 24
Finished May 26 01:32:20 PM PDT 24
Peak memory 205256 kb
Host smart-a169c7e4-43b4-4f95-ad90-6f5cb14456a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
5032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.146085032
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.65308219
Short name T342
Test name
Test status
Simulation time 10073206797 ps
CPU time 14.39 seconds
Started May 26 01:32:14 PM PDT 24
Finished May 26 01:32:29 PM PDT 24
Peak memory 205228 kb
Host smart-df5be45c-1183-4d6c-9b03-fbffcbee6ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65308
219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.65308219
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.4197271368
Short name T862
Test name
Test status
Simulation time 10075251150 ps
CPU time 13.19 seconds
Started May 26 01:32:17 PM PDT 24
Finished May 26 01:32:30 PM PDT 24
Peak memory 205240 kb
Host smart-c389ccfd-766b-41b9-95ac-41918b8e18f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41972
71368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.4197271368
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.625731229
Short name T1095
Test name
Test status
Simulation time 10074596623 ps
CPU time 13.8 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:18 PM PDT 24
Peak memory 205292 kb
Host smart-590befce-b5f7-4242-98ea-704ca4f0c8ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=625731229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.625731229
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.1394765542
Short name T938
Test name
Test status
Simulation time 10106217578 ps
CPU time 15.24 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:11 PM PDT 24
Peak memory 205288 kb
Host smart-2a06540a-f51a-4978-b2f7-7e4098071fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13947
65542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.1394765542
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3357499133
Short name T202
Test name
Test status
Simulation time 13574000844 ps
CPU time 16.5 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:46 PM PDT 24
Peak memory 205244 kb
Host smart-db67be8b-c609-42cb-b73c-dd6c55335c93
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3357499133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3357499133
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1420510971
Short name T769
Test name
Test status
Simulation time 13282930780 ps
CPU time 19.35 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:50 PM PDT 24
Peak memory 205244 kb
Host smart-009c358a-cbfa-416c-856b-acb08b02bc45
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1420510971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1420510971
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.3227742517
Short name T1051
Test name
Test status
Simulation time 13277529203 ps
CPU time 17.52 seconds
Started May 26 01:32:28 PM PDT 24
Finished May 26 01:32:46 PM PDT 24
Peak memory 205248 kb
Host smart-2e9a2252-d34a-4b1a-bfb2-0fa3ece63960
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3227742517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.3227742517
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2378747845
Short name T1728
Test name
Test status
Simulation time 10052330282 ps
CPU time 13.84 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:45 PM PDT 24
Peak memory 205256 kb
Host smart-acf49e4a-8f87-460c-8a68-cd5d2e947794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
47845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2378747845
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2160240480
Short name T1483
Test name
Test status
Simulation time 10143068785 ps
CPU time 13.52 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:44 PM PDT 24
Peak memory 205248 kb
Host smart-8d865a51-cb28-4790-b1a8-5a2bf8ca3628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
40480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2160240480
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.4086472450
Short name T897
Test name
Test status
Simulation time 10080604830 ps
CPU time 14.48 seconds
Started May 26 01:32:38 PM PDT 24
Finished May 26 01:32:53 PM PDT 24
Peak memory 205252 kb
Host smart-18d8df40-f9be-4595-af2d-f021e32b03e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40864
72450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.4086472450
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3274978665
Short name T1411
Test name
Test status
Simulation time 10045727249 ps
CPU time 15.27 seconds
Started May 26 01:32:29 PM PDT 24
Finished May 26 01:32:45 PM PDT 24
Peak memory 205240 kb
Host smart-19ac8ff6-5bc9-4414-8b87-5d47784fef4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32749
78665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3274978665
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3144038584
Short name T742
Test name
Test status
Simulation time 10737009751 ps
CPU time 15.79 seconds
Started May 26 01:32:33 PM PDT 24
Finished May 26 01:32:49 PM PDT 24
Peak memory 205256 kb
Host smart-af43c522-7a32-4b4a-8203-33bed54671ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31440
38584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3144038584
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.934840886
Short name T1351
Test name
Test status
Simulation time 10163565342 ps
CPU time 15.79 seconds
Started May 26 01:32:27 PM PDT 24
Finished May 26 01:32:44 PM PDT 24
Peak memory 205328 kb
Host smart-ebc8df02-e458-4569-a5db-627a46005aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93484
0886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.934840886
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3172887789
Short name T635
Test name
Test status
Simulation time 10109853079 ps
CPU time 16.29 seconds
Started May 26 01:32:55 PM PDT 24
Finished May 26 01:33:12 PM PDT 24
Peak memory 205304 kb
Host smart-d51b7553-4626-46c5-adb2-814aa150d08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31728
87789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3172887789
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.623595485
Short name T502
Test name
Test status
Simulation time 10135424831 ps
CPU time 18.48 seconds
Started May 26 01:32:30 PM PDT 24
Finished May 26 01:32:49 PM PDT 24
Peak memory 205260 kb
Host smart-9f9d894c-fad0-45f4-a472-bc072afe055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62359
5485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.623595485
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2434775509
Short name T825
Test name
Test status
Simulation time 10063519833 ps
CPU time 14.23 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:50 PM PDT 24
Peak memory 205304 kb
Host smart-23056856-8e92-4a65-affe-e701a9e8f048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24347
75509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2434775509
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1329281570
Short name T992
Test name
Test status
Simulation time 13185544892 ps
CPU time 20.03 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:56 PM PDT 24
Peak memory 205300 kb
Host smart-db546bb6-5b89-46eb-957f-e0c952981703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13292
81570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1329281570
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3111938896
Short name T508
Test name
Test status
Simulation time 10119475164 ps
CPU time 18.01 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:55 PM PDT 24
Peak memory 205468 kb
Host smart-1bad64b8-b7f5-435b-802d-b769a99dd772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31119
38896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3111938896
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2086207623
Short name T454
Test name
Test status
Simulation time 10044282699 ps
CPU time 13.93 seconds
Started May 26 01:32:36 PM PDT 24
Finished May 26 01:32:51 PM PDT 24
Peak memory 205276 kb
Host smart-c27b4a19-3047-40dc-95cc-a14480a0c7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20862
07623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2086207623
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1805500004
Short name T1436
Test name
Test status
Simulation time 10122064213 ps
CPU time 16.89 seconds
Started May 26 01:32:38 PM PDT 24
Finished May 26 01:32:55 PM PDT 24
Peak memory 205232 kb
Host smart-4f3a7634-2516-4f57-a6ce-5d829b14f406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18055
00004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1805500004
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.249228948
Short name T1495
Test name
Test status
Simulation time 10058091917 ps
CPU time 14.99 seconds
Started May 26 01:32:37 PM PDT 24
Finished May 26 01:32:52 PM PDT 24
Peak memory 205336 kb
Host smart-9b22e722-af6b-4d83-89dd-bd6eb772eef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24922
8948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.249228948
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.830944834
Short name T388
Test name
Test status
Simulation time 10084529411 ps
CPU time 15.83 seconds
Started May 26 01:32:56 PM PDT 24
Finished May 26 01:33:13 PM PDT 24
Peak memory 205232 kb
Host smart-96e2508a-5bca-4cbf-a606-0d89f599bfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83094
4834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.830944834
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.4097807518
Short name T1048
Test name
Test status
Simulation time 10088826852 ps
CPU time 16.71 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:11 PM PDT 24
Peak memory 205452 kb
Host smart-4ee6b85e-4712-4e45-bdbf-d24a3d85ff7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40978
07518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.4097807518
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1747207529
Short name T867
Test name
Test status
Simulation time 10061138293 ps
CPU time 14.16 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 205192 kb
Host smart-2e1ece40-1949-4621-af20-727312ffcf0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
07529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1747207529
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3032697636
Short name T1446
Test name
Test status
Simulation time 10030398259 ps
CPU time 14.3 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 205292 kb
Host smart-3f7caee8-b6f9-48fa-9153-019ebf41263b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
97636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3032697636
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3905487822
Short name T1680
Test name
Test status
Simulation time 24629061135 ps
CPU time 48.26 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 205256 kb
Host smart-2542f9ff-8205-473e-a9b3-98cabc9e0b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39054
87822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3905487822
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1763901603
Short name T1754
Test name
Test status
Simulation time 10047142821 ps
CPU time 12.64 seconds
Started May 26 01:32:57 PM PDT 24
Finished May 26 01:33:10 PM PDT 24
Peak memory 205236 kb
Host smart-b0b3d19e-a0c7-4128-b640-7d6e4456b2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17639
01603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1763901603
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2345024735
Short name T1240
Test name
Test status
Simulation time 10099974569 ps
CPU time 13.59 seconds
Started May 26 01:32:47 PM PDT 24
Finished May 26 01:33:01 PM PDT 24
Peak memory 205288 kb
Host smart-d7712939-1cc2-4ce7-8059-6d3024f1b94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23450
24735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2345024735
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.968480642
Short name T340
Test name
Test status
Simulation time 10066906640 ps
CPU time 14.09 seconds
Started May 26 01:32:46 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 205264 kb
Host smart-01133eb9-7e11-424b-9a4c-494218a9095d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96848
0642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.968480642
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2453523971
Short name T488
Test name
Test status
Simulation time 10050997418 ps
CPU time 16.07 seconds
Started May 26 01:32:51 PM PDT 24
Finished May 26 01:33:08 PM PDT 24
Peak memory 205252 kb
Host smart-e9d89097-ed6a-4060-8019-e8bc7e3c7de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24535
23971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2453523971
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.295953388
Short name T1060
Test name
Test status
Simulation time 10068599181 ps
CPU time 14.41 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:09 PM PDT 24
Peak memory 205224 kb
Host smart-c9dfb8ae-d2dd-4967-8fde-dda54d92a173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
3388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.295953388
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1295248156
Short name T551
Test name
Test status
Simulation time 10102102960 ps
CPU time 15.43 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 205272 kb
Host smart-b9d525e9-a8a5-4195-9177-860c1e737616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12952
48156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1295248156
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.3743184397
Short name T781
Test name
Test status
Simulation time 10144817636 ps
CPU time 13.3 seconds
Started May 26 01:32:21 PM PDT 24
Finished May 26 01:32:35 PM PDT 24
Peak memory 205228 kb
Host smart-b474afbc-1fbc-4990-af2d-27704f63e33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37431
84397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.3743184397
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.433721891
Short name T821
Test name
Test status
Simulation time 10051500881 ps
CPU time 14.81 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:33:00 PM PDT 24
Peak memory 205308 kb
Host smart-43d585ca-d0bd-4ced-95d5-205430f70609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43372
1891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.433721891
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.592976764
Short name T1722
Test name
Test status
Simulation time 10114579764 ps
CPU time 16.57 seconds
Started May 26 01:32:45 PM PDT 24
Finished May 26 01:33:02 PM PDT 24
Peak memory 205304 kb
Host smart-f900955e-6ac9-4259-af29-12d6fd3babbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59297
6764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.592976764
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.1793413389
Short name T882
Test name
Test status
Simulation time 10164298295 ps
CPU time 14.67 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:36 PM PDT 24
Peak memory 205328 kb
Host smart-935191f2-f1f1-4f8d-baf6-e57734b701f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1793413389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.1793413389
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.2755480314
Short name T817
Test name
Test status
Simulation time 10111522209 ps
CPU time 13.45 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:24 PM PDT 24
Peak memory 205312 kb
Host smart-cc15226b-736a-476d-8a65-ff59f82cc6ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2755480314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.2755480314
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.3437980717
Short name T980
Test name
Test status
Simulation time 10154304253 ps
CPU time 15.37 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 205168 kb
Host smart-82a4de25-a67d-4dbc-bfac-26a9ab980b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
80717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.3437980717
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3960115899
Short name T1207
Test name
Test status
Simulation time 14019498281 ps
CPU time 20.15 seconds
Started May 26 01:32:54 PM PDT 24
Finished May 26 01:33:15 PM PDT 24
Peak memory 205328 kb
Host smart-f3dcfa63-c5c4-4efe-bc26-428d4e36d00b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3960115899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.3960115899
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.394881501
Short name T1478
Test name
Test status
Simulation time 13347955565 ps
CPU time 19.62 seconds
Started May 26 01:32:57 PM PDT 24
Finished May 26 01:33:18 PM PDT 24
Peak memory 205280 kb
Host smart-3f3e8269-55df-4630-a95c-ee147731cc23
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=394881501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.394881501
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2985856325
Short name T1787
Test name
Test status
Simulation time 13236516286 ps
CPU time 17.67 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:22 PM PDT 24
Peak memory 205292 kb
Host smart-65971b1d-7114-4a95-a403-925c7a13b5e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2985856325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.2985856325
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.387053676
Short name T604
Test name
Test status
Simulation time 10044495488 ps
CPU time 12.86 seconds
Started May 26 01:33:01 PM PDT 24
Finished May 26 01:33:14 PM PDT 24
Peak memory 205288 kb
Host smart-bac8fd30-b3f1-42bf-9dab-d039795b4584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38705
3676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.387053676
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1995505061
Short name T1637
Test name
Test status
Simulation time 11160681201 ps
CPU time 16.42 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:19 PM PDT 24
Peak memory 205316 kb
Host smart-c29eff1a-ba5e-4c81-8dc2-6c7e449097df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955
05061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1995505061
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1711658775
Short name T542
Test name
Test status
Simulation time 10038010148 ps
CPU time 17.29 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:21 PM PDT 24
Peak memory 205220 kb
Host smart-aef2f192-0840-4d56-be10-62a4c1d56831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17116
58775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1711658775
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3388779134
Short name T1440
Test name
Test status
Simulation time 10800716826 ps
CPU time 15.44 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:20 PM PDT 24
Peak memory 205348 kb
Host smart-493d3819-6e27-4112-b6da-09c608f74b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33887
79134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3388779134
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1808561626
Short name T1671
Test name
Test status
Simulation time 10290971277 ps
CPU time 18.15 seconds
Started May 26 01:33:01 PM PDT 24
Finished May 26 01:33:20 PM PDT 24
Peak memory 205328 kb
Host smart-61f90fd3-bfad-4844-b6f6-e5c488bf0dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18085
61626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1808561626
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2723341292
Short name T783
Test name
Test status
Simulation time 10052055901 ps
CPU time 14.98 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 205276 kb
Host smart-44e02895-934e-48f1-89dc-2091319b7952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
41292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2723341292
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.82715013
Short name T798
Test name
Test status
Simulation time 10056210896 ps
CPU time 14.26 seconds
Started May 26 01:33:15 PM PDT 24
Finished May 26 01:33:30 PM PDT 24
Peak memory 205292 kb
Host smart-2ec0cafd-3276-4f72-a417-01b2f6536b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82715
013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.82715013
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3213927865
Short name T532
Test name
Test status
Simulation time 10079400047 ps
CPU time 14.01 seconds
Started May 26 01:33:03 PM PDT 24
Finished May 26 01:33:18 PM PDT 24
Peak memory 205240 kb
Host smart-33c3e971-5e01-4e93-a42f-43dc7001e4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32139
27865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3213927865
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1515058250
Short name T430
Test name
Test status
Simulation time 10132904690 ps
CPU time 15.23 seconds
Started May 26 01:33:01 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 205240 kb
Host smart-d7e9763a-3516-4d2b-ab9c-827028cffa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15150
58250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1515058250
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.379666379
Short name T134
Test name
Test status
Simulation time 13228800564 ps
CPU time 19.44 seconds
Started May 26 01:33:00 PM PDT 24
Finished May 26 01:33:20 PM PDT 24
Peak memory 205216 kb
Host smart-7a6ab67e-06c4-4589-ad05-651d6a904b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37966
6379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.379666379
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.894300449
Short name T1771
Test name
Test status
Simulation time 10088189692 ps
CPU time 13.37 seconds
Started May 26 01:33:04 PM PDT 24
Finished May 26 01:33:18 PM PDT 24
Peak memory 205268 kb
Host smart-5b029a19-1566-4594-9a81-2c5c41a017e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89430
0449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.894300449
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.946303709
Short name T1168
Test name
Test status
Simulation time 10040108234 ps
CPU time 13.44 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:24 PM PDT 24
Peak memory 205320 kb
Host smart-2f84fb74-2027-43ec-8bc9-d3b2966efbf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94630
3709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.946303709
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.848683726
Short name T1040
Test name
Test status
Simulation time 10103598669 ps
CPU time 13.46 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 205300 kb
Host smart-15f21a3d-947c-4a38-bc96-f79635bb9d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84868
3726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.848683726
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1770662515
Short name T890
Test name
Test status
Simulation time 10122333976 ps
CPU time 15.13 seconds
Started May 26 01:33:01 PM PDT 24
Finished May 26 01:33:17 PM PDT 24
Peak memory 205248 kb
Host smart-e0b9dda2-e16c-412f-88af-5d317b239503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17706
62515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1770662515
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.977453356
Short name T1643
Test name
Test status
Simulation time 10070053807 ps
CPU time 14.21 seconds
Started May 26 01:33:01 PM PDT 24
Finished May 26 01:33:15 PM PDT 24
Peak memory 205176 kb
Host smart-3b83d002-7b32-4ca7-8a32-3ba42fb0d552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97745
3356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.977453356
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3366277543
Short name T1807
Test name
Test status
Simulation time 10058565036 ps
CPU time 14.58 seconds
Started May 26 01:33:12 PM PDT 24
Finished May 26 01:33:28 PM PDT 24
Peak memory 205240 kb
Host smart-9f1b62c6-fade-4ac9-a106-597e5b09dfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33662
77543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3366277543
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1282672104
Short name T1223
Test name
Test status
Simulation time 10086680528 ps
CPU time 14.37 seconds
Started May 26 01:33:12 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 205240 kb
Host smart-cab3e3c8-71ad-4a50-8700-afd88f6c60c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12826
72104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1282672104
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.2745386745
Short name T763
Test name
Test status
Simulation time 10050363830 ps
CPU time 14.93 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 205228 kb
Host smart-daf88ea1-f0b0-4d1a-9e7b-73af9adbdfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
86745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.2745386745
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.4101540532
Short name T707
Test name
Test status
Simulation time 10037068000 ps
CPU time 15.76 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:28 PM PDT 24
Peak memory 205220 kb
Host smart-81b263e3-c648-4b0c-9daf-0392d420ec29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41015
40532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.4101540532
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3282232814
Short name T1222
Test name
Test status
Simulation time 18126775994 ps
CPU time 31.05 seconds
Started May 26 01:33:02 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 205252 kb
Host smart-8c256ebd-f93b-416a-8854-16c9b41bf38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32822
32814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3282232814
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3468265333
Short name T326
Test name
Test status
Simulation time 10129060621 ps
CPU time 13.93 seconds
Started May 26 01:33:13 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 205240 kb
Host smart-21168e5b-8f0f-4849-8e56-7d066b84059b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34682
65333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3468265333
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3783702868
Short name T1261
Test name
Test status
Simulation time 10076083344 ps
CPU time 13.13 seconds
Started May 26 01:33:12 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 205260 kb
Host smart-2d392af9-f9d5-46fa-b4c5-254ca0f2a530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37837
02868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3783702868
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.728168153
Short name T1403
Test name
Test status
Simulation time 10067386990 ps
CPU time 14.21 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 205288 kb
Host smart-3e805efa-8439-4cf7-8e72-3e1abd702bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72816
8153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.728168153
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.619351904
Short name T393
Test name
Test status
Simulation time 10047065744 ps
CPU time 14.81 seconds
Started May 26 01:33:17 PM PDT 24
Finished May 26 01:33:33 PM PDT 24
Peak memory 205316 kb
Host smart-12370d09-6c47-4a2c-8453-218691b8bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61935
1904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.619351904
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1905264314
Short name T722
Test name
Test status
Simulation time 10129546951 ps
CPU time 16.71 seconds
Started May 26 01:33:15 PM PDT 24
Finished May 26 01:33:32 PM PDT 24
Peak memory 205316 kb
Host smart-46e9181f-59a2-49c6-b5b3-3e4fb3f3f6e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19052
64314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1905264314
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.259796945
Short name T1855
Test name
Test status
Simulation time 10102587852 ps
CPU time 15.38 seconds
Started May 26 01:33:10 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 205224 kb
Host smart-59036fe9-0197-4ca1-85bf-2d2ddcd04fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25979
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.259796945
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3476372009
Short name T1463
Test name
Test status
Simulation time 10124860171 ps
CPU time 14 seconds
Started May 26 01:32:51 PM PDT 24
Finished May 26 01:33:06 PM PDT 24
Peak memory 205276 kb
Host smart-5ad3a7cd-db92-4a1a-8965-d742055d7248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34763
72009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3476372009
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.692815597
Short name T1901
Test name
Test status
Simulation time 10083487853 ps
CPU time 13.32 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:26 PM PDT 24
Peak memory 205328 kb
Host smart-08b59656-be5e-4982-acef-bd756fa7c20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69281
5597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.692815597
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2772190487
Short name T1601
Test name
Test status
Simulation time 10091996622 ps
CPU time 14.75 seconds
Started May 26 01:33:11 PM PDT 24
Finished May 26 01:33:27 PM PDT 24
Peak memory 205204 kb
Host smart-a9ad23c9-9c64-4473-8a39-57657e81ca31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27721
90487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2772190487
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.2193511253
Short name T1305
Test name
Test status
Simulation time 10134493740 ps
CPU time 14.71 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205292 kb
Host smart-bb649497-bd71-4498-9ae6-79764de28829
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2193511253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.2193511253
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.3644101210
Short name T1038
Test name
Test status
Simulation time 10048888611 ps
CPU time 13.92 seconds
Started May 26 01:33:46 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205228 kb
Host smart-81a68ad6-d66a-4d7b-8fe6-fce81692512f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3644101210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.3644101210
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.712783374
Short name T1928
Test name
Test status
Simulation time 10128700399 ps
CPU time 13.46 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:00 PM PDT 24
Peak memory 205264 kb
Host smart-9eb50506-7b3c-48b8-8bfe-e215988b86fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71278
3374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.712783374
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1935958575
Short name T1002
Test name
Test status
Simulation time 14028884829 ps
CPU time 18.72 seconds
Started May 26 01:33:22 PM PDT 24
Finished May 26 01:33:41 PM PDT 24
Peak memory 205260 kb
Host smart-db3c1f2c-acf4-4fcf-8124-7215b8d46613
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1935958575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1935958575
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1191814755
Short name T381
Test name
Test status
Simulation time 13272530964 ps
CPU time 16.91 seconds
Started May 26 01:33:20 PM PDT 24
Finished May 26 01:33:38 PM PDT 24
Peak memory 205332 kb
Host smart-34deded3-f1bb-4027-af7e-5268d8185639
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1191814755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1191814755
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3811485703
Short name T590
Test name
Test status
Simulation time 13352521241 ps
CPU time 17.85 seconds
Started May 26 01:33:18 PM PDT 24
Finished May 26 01:33:37 PM PDT 24
Peak memory 205232 kb
Host smart-5faefff3-709a-4cb0-9217-e45233e27e12
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3811485703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3811485703
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1496799887
Short name T535
Test name
Test status
Simulation time 10051537918 ps
CPU time 15.04 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:35 PM PDT 24
Peak memory 205264 kb
Host smart-a479a4b2-04af-4c5c-85c6-484c0d10757b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14967
99887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1496799887
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.602139971
Short name T1332
Test name
Test status
Simulation time 10247182736 ps
CPU time 16.07 seconds
Started May 26 01:33:21 PM PDT 24
Finished May 26 01:33:38 PM PDT 24
Peak memory 205336 kb
Host smart-51ded6be-9f5d-46aa-946e-c7f7d78d220d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60213
9971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.602139971
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.629802468
Short name T1694
Test name
Test status
Simulation time 10055792608 ps
CPU time 13.14 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:43 PM PDT 24
Peak memory 205244 kb
Host smart-d5bb0621-f64b-4dc6-8112-4e6fddcb0068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62980
2468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.629802468
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3710103774
Short name T472
Test name
Test status
Simulation time 10068185363 ps
CPU time 15.58 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:36 PM PDT 24
Peak memory 205308 kb
Host smart-a31d0e20-70b1-41d2-97cd-9199fc80eccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37101
03774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3710103774
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3747784197
Short name T800
Test name
Test status
Simulation time 10798124651 ps
CPU time 14.7 seconds
Started May 26 01:33:21 PM PDT 24
Finished May 26 01:33:36 PM PDT 24
Peak memory 205240 kb
Host smart-2994f031-4d87-4e0d-a70a-701c81d0d9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
84197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3747784197
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.752500674
Short name T1251
Test name
Test status
Simulation time 10223160756 ps
CPU time 16.59 seconds
Started May 26 01:33:21 PM PDT 24
Finished May 26 01:33:38 PM PDT 24
Peak memory 205304 kb
Host smart-7e3b77d0-87ff-4c26-9cc1-c6eee7cd307c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75250
0674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.752500674
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3202762138
Short name T1328
Test name
Test status
Simulation time 10127417434 ps
CPU time 15.46 seconds
Started May 26 01:33:43 PM PDT 24
Finished May 26 01:34:00 PM PDT 24
Peak memory 205236 kb
Host smart-09b9391a-1a63-442a-9b51-33330da2221d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32027
62138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3202762138
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2176035862
Short name T1683
Test name
Test status
Simulation time 10058028626 ps
CPU time 15.69 seconds
Started May 26 01:33:43 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 205184 kb
Host smart-a222967e-176b-4d38-b2e9-d91ac16c3f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21760
35862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2176035862
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2949160151
Short name T318
Test name
Test status
Simulation time 10107422418 ps
CPU time 14.77 seconds
Started May 26 01:33:18 PM PDT 24
Finished May 26 01:33:34 PM PDT 24
Peak memory 205240 kb
Host smart-2fb364e1-c874-40ef-986c-cc9ad0287ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
60151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2949160151
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.4261236299
Short name T1069
Test name
Test status
Simulation time 10104938948 ps
CPU time 14.69 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:44 PM PDT 24
Peak memory 205224 kb
Host smart-ce860250-500b-45fa-bd15-b949e15c14d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42612
36299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.4261236299
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2649364398
Short name T1497
Test name
Test status
Simulation time 13258262566 ps
CPU time 20 seconds
Started May 26 01:33:26 PM PDT 24
Finished May 26 01:33:47 PM PDT 24
Peak memory 205180 kb
Host smart-05ab70ed-b8ca-43ee-8df9-9225e8785132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26493
64398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2649364398
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.458051163
Short name T1146
Test name
Test status
Simulation time 10119552103 ps
CPU time 14.05 seconds
Started May 26 01:33:29 PM PDT 24
Finished May 26 01:33:44 PM PDT 24
Peak memory 205332 kb
Host smart-02274c5a-ccc4-42af-8cb3-65447c4a4c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45805
1163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.458051163
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3091004764
Short name T1909
Test name
Test status
Simulation time 10045167746 ps
CPU time 15.33 seconds
Started May 26 01:33:30 PM PDT 24
Finished May 26 01:33:46 PM PDT 24
Peak memory 205240 kb
Host smart-df4930a6-cd02-446b-9c09-d80c1c442daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30910
04764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3091004764
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.99842992
Short name T333
Test name
Test status
Simulation time 10094998271 ps
CPU time 13.57 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:43 PM PDT 24
Peak memory 205284 kb
Host smart-033ecd18-c472-483e-9570-6ea668f5388b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99842
992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.99842992
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3861254976
Short name T400
Test name
Test status
Simulation time 10060460073 ps
CPU time 16.27 seconds
Started May 26 01:33:26 PM PDT 24
Finished May 26 01:33:44 PM PDT 24
Peak memory 205488 kb
Host smart-c832b9fc-7d8e-405a-8e28-f3cd63ac79e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38612
54976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3861254976
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.2513435886
Short name T513
Test name
Test status
Simulation time 10041506472 ps
CPU time 13.44 seconds
Started May 26 01:33:43 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 205264 kb
Host smart-4eacecbc-2371-4bc2-86c0-317fac1230dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25134
35886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.2513435886
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3166292034
Short name T811
Test name
Test status
Simulation time 10042649745 ps
CPU time 14.64 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:33:59 PM PDT 24
Peak memory 205312 kb
Host smart-b7311faf-bd6c-403c-88c3-226c19589730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
92034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3166292034
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1405323434
Short name T780
Test name
Test status
Simulation time 10035286541 ps
CPU time 14.2 seconds
Started May 26 01:33:43 PM PDT 24
Finished May 26 01:33:58 PM PDT 24
Peak memory 205304 kb
Host smart-3ff1fac7-1804-47b8-a83d-7d06b200a3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14053
23434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1405323434
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.4107937692
Short name T1285
Test name
Test status
Simulation time 20112098534 ps
CPU time 35.68 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:34:04 PM PDT 24
Peak memory 205340 kb
Host smart-e28ab356-0404-4094-9abf-a587719178ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
37692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.4107937692
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2032042471
Short name T941
Test name
Test status
Simulation time 10092047003 ps
CPU time 15.23 seconds
Started May 26 01:33:27 PM PDT 24
Finished May 26 01:33:43 PM PDT 24
Peak memory 205176 kb
Host smart-c1e47334-f905-4d06-a38f-df755ab18d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20320
42471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2032042471
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3711582920
Short name T1430
Test name
Test status
Simulation time 10086614712 ps
CPU time 17.52 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:47 PM PDT 24
Peak memory 205288 kb
Host smart-551d5614-6097-423c-ba3d-f395fa74aa0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
82920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3711582920
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.834440144
Short name T1011
Test name
Test status
Simulation time 10118017945 ps
CPU time 14.29 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:44 PM PDT 24
Peak memory 205284 kb
Host smart-e61cd8b3-ca14-4af1-8875-12c739cbe99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83444
0144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.834440144
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4070717400
Short name T949
Test name
Test status
Simulation time 10097160543 ps
CPU time 14.32 seconds
Started May 26 01:33:32 PM PDT 24
Finished May 26 01:33:47 PM PDT 24
Peak memory 205280 kb
Host smart-dd636135-e240-4c8c-84cd-48fc6e0c8232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40707
17400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4070717400
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1612550570
Short name T1917
Test name
Test status
Simulation time 10079922219 ps
CPU time 13.95 seconds
Started May 26 01:33:34 PM PDT 24
Finished May 26 01:33:48 PM PDT 24
Peak memory 205316 kb
Host smart-048d8112-3a2d-42df-b812-86038ce7ddb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16125
50570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1612550570
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1933848413
Short name T80
Test name
Test status
Simulation time 10113867351 ps
CPU time 13.98 seconds
Started May 26 01:33:42 PM PDT 24
Finished May 26 01:33:57 PM PDT 24
Peak memory 205200 kb
Host smart-774ed5a8-db52-4e0a-b79f-c57c9ebdcb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
48413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1933848413
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.3827810664
Short name T656
Test name
Test status
Simulation time 10163731718 ps
CPU time 15.88 seconds
Started May 26 01:33:19 PM PDT 24
Finished May 26 01:33:36 PM PDT 24
Peak memory 205288 kb
Host smart-dfc3a604-38e2-4e66-abcb-4a1ace6a2f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38278
10664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3827810664
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2873001962
Short name T1016
Test name
Test status
Simulation time 10106634308 ps
CPU time 15.95 seconds
Started May 26 01:33:34 PM PDT 24
Finished May 26 01:33:50 PM PDT 24
Peak memory 205268 kb
Host smart-b89761c3-88e5-4fd3-8f4b-6f34d0077fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28730
01962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2873001962
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.4022510990
Short name T460
Test name
Test status
Simulation time 10073847647 ps
CPU time 15.97 seconds
Started May 26 01:33:28 PM PDT 24
Finished May 26 01:33:45 PM PDT 24
Peak memory 205332 kb
Host smart-051e4e64-7bfa-4220-8754-f7e079b8f023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40225
10990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.4022510990
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.295190333
Short name T64
Test name
Test status
Simulation time 10147192376 ps
CPU time 14.62 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:19 PM PDT 24
Peak memory 205284 kb
Host smart-9898529c-82cd-4d49-b044-a0538dcbca18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=295190333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.295190333
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2791220589
Short name T554
Test name
Test status
Simulation time 10056473877 ps
CPU time 16.03 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:11 PM PDT 24
Peak memory 205308 kb
Host smart-2b28b7ba-f869-4803-a741-87746a9caa07
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2791220589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2791220589
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.3872418563
Short name T617
Test name
Test status
Simulation time 10136092996 ps
CPU time 14.26 seconds
Started May 26 01:33:56 PM PDT 24
Finished May 26 01:34:11 PM PDT 24
Peak memory 205256 kb
Host smart-1df12fb9-0b7d-48f1-9781-a481c9238704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
18563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.3872418563
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.760738659
Short name T1336
Test name
Test status
Simulation time 14155406159 ps
CPU time 16.65 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:34:02 PM PDT 24
Peak memory 205300 kb
Host smart-0ca411f5-97cc-4bf8-be53-a9e7a24327cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=760738659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.760738659
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2299325354
Short name T55
Test name
Test status
Simulation time 13231813194 ps
CPU time 16.42 seconds
Started May 26 01:33:44 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205316 kb
Host smart-473447da-3e56-477a-90c2-f8799599bb8a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2299325354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2299325354
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.4022588796
Short name T1102
Test name
Test status
Simulation time 13290639147 ps
CPU time 17.24 seconds
Started May 26 01:33:43 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205316 kb
Host smart-7db55e54-04a7-4571-8cc6-89f0351555b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4022588796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.4022588796
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1539102355
Short name T320
Test name
Test status
Simulation time 10052751988 ps
CPU time 13.51 seconds
Started May 26 01:33:48 PM PDT 24
Finished May 26 01:34:02 PM PDT 24
Peak memory 205212 kb
Host smart-addcae5e-2ea0-4b24-a34b-ecfadefc45da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15391
02355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1539102355
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1490265421
Short name T1498
Test name
Test status
Simulation time 11099353869 ps
CPU time 16.01 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:02 PM PDT 24
Peak memory 205368 kb
Host smart-6ee0daaf-97fd-4bea-8ca4-db2b6ae35887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14902
65421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1490265421
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1413145269
Short name T1136
Test name
Test status
Simulation time 10061292698 ps
CPU time 15.44 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205260 kb
Host smart-dcb1099a-3b8a-40d7-af1b-a870efec545d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
45269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1413145269
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.841084281
Short name T933
Test name
Test status
Simulation time 10050753153 ps
CPU time 13.03 seconds
Started May 26 01:33:47 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205320 kb
Host smart-76928084-b321-4b06-a41b-e3cf323aa971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84108
4281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.841084281
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1026433260
Short name T865
Test name
Test status
Simulation time 10852415147 ps
CPU time 16.43 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:03 PM PDT 24
Peak memory 205284 kb
Host smart-11b93ad6-7dc6-467d-b154-18b64fd2516f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
33260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1026433260
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2208281602
Short name T86
Test name
Test status
Simulation time 10107450092 ps
CPU time 15.92 seconds
Started May 26 01:33:51 PM PDT 24
Finished May 26 01:34:08 PM PDT 24
Peak memory 205268 kb
Host smart-64f42024-b502-45e3-91fa-2dd5d2591076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22082
81602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2208281602
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2814843444
Short name T1371
Test name
Test status
Simulation time 10093150880 ps
CPU time 14.75 seconds
Started May 26 01:33:55 PM PDT 24
Finished May 26 01:34:10 PM PDT 24
Peak memory 205260 kb
Host smart-1e22c433-601f-4391-ba60-a522b9b4d704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28148
43444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2814843444
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3976787376
Short name T1444
Test name
Test status
Simulation time 10043553823 ps
CPU time 13.65 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:34:08 PM PDT 24
Peak memory 205272 kb
Host smart-5c5e31fd-6b61-4906-b459-a5fedad80528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
87376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3976787376
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3738845279
Short name T1145
Test name
Test status
Simulation time 10116193337 ps
CPU time 15.68 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:02 PM PDT 24
Peak memory 205296 kb
Host smart-d3416282-821b-4b47-902b-9a7554c6ca10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37388
45279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3738845279
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1834784673
Short name T1727
Test name
Test status
Simulation time 10103696237 ps
CPU time 15.91 seconds
Started May 26 01:33:47 PM PDT 24
Finished May 26 01:34:04 PM PDT 24
Peak memory 205260 kb
Host smart-58b5b095-b769-4021-99a0-3e63dcae7e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18347
84673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1834784673
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1999563585
Short name T1691
Test name
Test status
Simulation time 13233655493 ps
CPU time 16.55 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:03 PM PDT 24
Peak memory 205276 kb
Host smart-49ba22ae-cf04-4436-85f1-5a9d3029c995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
63585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1999563585
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1489722833
Short name T823
Test name
Test status
Simulation time 10102486091 ps
CPU time 14.82 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:01 PM PDT 24
Peak memory 205308 kb
Host smart-2a665c25-2bd5-4316-9a9e-2fe52aacacef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14897
22833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1489722833
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1454960800
Short name T603
Test name
Test status
Simulation time 10050856185 ps
CPU time 13.37 seconds
Started May 26 01:33:45 PM PDT 24
Finished May 26 01:34:00 PM PDT 24
Peak memory 205236 kb
Host smart-76cc6e81-4080-4995-a5e0-931f84335022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14549
60800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1454960800
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1070216375
Short name T112
Test name
Test status
Simulation time 10117769740 ps
CPU time 17.09 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:12 PM PDT 24
Peak memory 205228 kb
Host smart-dd10e5e5-e5fd-47c2-969f-5b7ecdffca64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
16375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1070216375
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1388166627
Short name T1622
Test name
Test status
Simulation time 10102723204 ps
CPU time 14.82 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:10 PM PDT 24
Peak memory 205272 kb
Host smart-3e294e53-dffc-4cac-8b0e-81fefbe406a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13881
66627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1388166627
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.43851234
Short name T741
Test name
Test status
Simulation time 10059349585 ps
CPU time 17.06 seconds
Started May 26 01:33:56 PM PDT 24
Finished May 26 01:34:14 PM PDT 24
Peak memory 205316 kb
Host smart-f76775c6-3257-4e54-994f-23725ad73025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43851
234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.43851234
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.62310948
Short name T581
Test name
Test status
Simulation time 10094511995 ps
CPU time 14.57 seconds
Started May 26 01:33:52 PM PDT 24
Finished May 26 01:34:07 PM PDT 24
Peak memory 205280 kb
Host smart-bae10d07-0a6e-4ebc-b644-35ea640e11f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62310
948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.62310948
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1518079496
Short name T151
Test name
Test status
Simulation time 10053994999 ps
CPU time 16.26 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:11 PM PDT 24
Peak memory 205244 kb
Host smart-c5a9f22d-aa29-4c9f-8730-9cdb15057a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15180
79496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1518079496
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.1498538780
Short name T1492
Test name
Test status
Simulation time 10056678472 ps
CPU time 15.77 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:34:10 PM PDT 24
Peak memory 205272 kb
Host smart-098a09a0-01d7-4122-a110-f915e7251700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14985
38780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.1498538780
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4294613474
Short name T876
Test name
Test status
Simulation time 10051495607 ps
CPU time 14.37 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:34:08 PM PDT 24
Peak memory 205316 kb
Host smart-0aadf863-2a08-4ad2-9ac0-4c79dc995ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
13474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4294613474
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1685753196
Short name T1091
Test name
Test status
Simulation time 10049693080 ps
CPU time 14.48 seconds
Started May 26 01:34:19 PM PDT 24
Finished May 26 01:34:33 PM PDT 24
Peak memory 205264 kb
Host smart-3b88add9-fd58-4ce6-9923-5e41cf122618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16857
53196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1685753196
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3845601940
Short name T1014
Test name
Test status
Simulation time 17499530753 ps
CPU time 32.63 seconds
Started May 26 01:33:52 PM PDT 24
Finished May 26 01:34:25 PM PDT 24
Peak memory 205356 kb
Host smart-32d053a3-05ec-413a-b4a1-070cb2556612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38456
01940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3845601940
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3911591039
Short name T236
Test name
Test status
Simulation time 10083819324 ps
CPU time 13.21 seconds
Started May 26 01:33:53 PM PDT 24
Finished May 26 01:34:07 PM PDT 24
Peak memory 205184 kb
Host smart-c172b4d4-9aa2-4a15-ab9a-220a4077e43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39115
91039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3911591039
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3884008428
Short name T946
Test name
Test status
Simulation time 10144420587 ps
CPU time 15.46 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:10 PM PDT 24
Peak memory 205232 kb
Host smart-35026098-6568-42ac-abb3-9cd3b33d660f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38840
08428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3884008428
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.752478776
Short name T278
Test name
Test status
Simulation time 10061801440 ps
CPU time 14.53 seconds
Started May 26 01:33:56 PM PDT 24
Finished May 26 01:34:11 PM PDT 24
Peak memory 205252 kb
Host smart-b94815c1-ae30-416f-a67e-c38d2e8b6d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75247
8776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.752478776
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2316761692
Short name T1053
Test name
Test status
Simulation time 10069161296 ps
CPU time 15.06 seconds
Started May 26 01:33:52 PM PDT 24
Finished May 26 01:34:08 PM PDT 24
Peak memory 205236 kb
Host smart-7942f12d-2e6d-4adb-b3b7-3feac8c54566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
61692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2316761692
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2282598149
Short name T1295
Test name
Test status
Simulation time 10058404746 ps
CPU time 14.42 seconds
Started May 26 01:33:52 PM PDT 24
Finished May 26 01:34:07 PM PDT 24
Peak memory 205292 kb
Host smart-3ccb43bc-787e-4a13-a14a-7690417bd011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
98149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2282598149
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1435554637
Short name T66
Test name
Test status
Simulation time 10150741827 ps
CPU time 14.15 seconds
Started May 26 01:33:48 PM PDT 24
Finished May 26 01:34:03 PM PDT 24
Peak memory 205492 kb
Host smart-220abd2d-b3c9-4874-a63b-936fdb2c34c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14355
54637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1435554637
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.4068355214
Short name T1101
Test name
Test status
Simulation time 10085905880 ps
CPU time 15.42 seconds
Started May 26 01:33:56 PM PDT 24
Finished May 26 01:34:12 PM PDT 24
Peak memory 205348 kb
Host smart-63d65f35-34e4-42b4-a09f-737dfef7ce6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
55214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.4068355214
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.1087016681
Short name T993
Test name
Test status
Simulation time 10055225582 ps
CPU time 15.9 seconds
Started May 26 01:33:54 PM PDT 24
Finished May 26 01:34:11 PM PDT 24
Peak memory 205228 kb
Host smart-fb73c258-3e18-445b-ba50-4d31e696d2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10870
16681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.1087016681
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.47417163
Short name T469
Test name
Test status
Simulation time 10140377242 ps
CPU time 13.84 seconds
Started May 26 01:34:03 PM PDT 24
Finished May 26 01:34:19 PM PDT 24
Peak memory 205440 kb
Host smart-45672911-6139-4b44-a19a-7d29ba88d596
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=47417163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.47417163
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2890853087
Short name T544
Test name
Test status
Simulation time 10077372747 ps
CPU time 17.66 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205288 kb
Host smart-abae5a70-9247-49d8-8e29-c3b29740b3c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2890853087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2890853087
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.1433090223
Short name T1124
Test name
Test status
Simulation time 10145709457 ps
CPU time 13 seconds
Started May 26 01:34:10 PM PDT 24
Finished May 26 01:34:23 PM PDT 24
Peak memory 205312 kb
Host smart-5fbe2906-08d3-4541-b3cc-9adfcd44603f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
90223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.1433090223
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2832118286
Short name T1115
Test name
Test status
Simulation time 13891388482 ps
CPU time 18.6 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:22 PM PDT 24
Peak memory 205272 kb
Host smart-f30e25a7-4ba7-4304-a274-064f355547fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2832118286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2832118286
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.662974480
Short name T1428
Test name
Test status
Simulation time 13271048906 ps
CPU time 16.7 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205256 kb
Host smart-b6a22631-a3d1-4569-a559-428ffd7e7151
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=662974480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.662974480
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1835111762
Short name T1819
Test name
Test status
Simulation time 13237849341 ps
CPU time 18.1 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205228 kb
Host smart-9d41d31c-c1d5-4c82-a7ce-300b93750670
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1835111762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1835111762
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1225179412
Short name T1524
Test name
Test status
Simulation time 10076179761 ps
CPU time 13.74 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:18 PM PDT 24
Peak memory 205184 kb
Host smart-e7a9c93d-336d-472a-bf3b-eecd595bb1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
79412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1225179412
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3861847200
Short name T1093
Test name
Test status
Simulation time 10308985249 ps
CPU time 15.82 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:18 PM PDT 24
Peak memory 205316 kb
Host smart-8159022a-4e8b-4c87-92e1-3b0db4df67c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38618
47200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3861847200
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2447531100
Short name T1211
Test name
Test status
Simulation time 10044875796 ps
CPU time 16.43 seconds
Started May 26 01:34:05 PM PDT 24
Finished May 26 01:34:23 PM PDT 24
Peak memory 205200 kb
Host smart-13ee159b-9dfe-436d-817a-7d0395429664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24475
31100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2447531100
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.523533423
Short name T1287
Test name
Test status
Simulation time 10049522415 ps
CPU time 13.74 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205348 kb
Host smart-eed914a1-9c27-40de-839a-d8ad09d909e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52353
3423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.523533423
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3646677618
Short name T703
Test name
Test status
Simulation time 10844080792 ps
CPU time 18.33 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:22 PM PDT 24
Peak memory 205340 kb
Host smart-b64a4f6c-cc3e-4f32-9b89-b602bd947ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36466
77618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3646677618
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1748118177
Short name T1559
Test name
Test status
Simulation time 10372140683 ps
CPU time 16.44 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205296 kb
Host smart-6bc8b6e9-5324-4b0e-9d79-c0b21e4477b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17481
18177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1748118177
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2396150626
Short name T1324
Test name
Test status
Simulation time 10109348226 ps
CPU time 14.58 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205296 kb
Host smart-5c4a545e-1e04-4c26-b7a9-48d9f52ffe3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23961
50626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2396150626
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1190092169
Short name T68
Test name
Test status
Simulation time 10039955481 ps
CPU time 13.22 seconds
Started May 26 01:34:03 PM PDT 24
Finished May 26 01:34:19 PM PDT 24
Peak memory 205248 kb
Host smart-97e1e52f-997a-4563-98ab-0583bead336b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11900
92169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1190092169
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1533021439
Short name T132
Test name
Test status
Simulation time 10083974823 ps
CPU time 14.68 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205296 kb
Host smart-84ce1652-1159-4a43-8b20-0fa53bf473ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15330
21439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1533021439
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1215295204
Short name T612
Test name
Test status
Simulation time 10088886967 ps
CPU time 15.08 seconds
Started May 26 01:34:00 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205232 kb
Host smart-57622531-e732-45d7-b9b2-9521a9711392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12152
95204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1215295204
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1975246338
Short name T1291
Test name
Test status
Simulation time 13166874401 ps
CPU time 20.76 seconds
Started May 26 01:34:00 PM PDT 24
Finished May 26 01:34:22 PM PDT 24
Peak memory 205180 kb
Host smart-e4a0c50f-bbff-455d-be57-1cf5cf7392c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19752
46338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1975246338
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1359030034
Short name T1008
Test name
Test status
Simulation time 10118828763 ps
CPU time 14.02 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205308 kb
Host smart-f25cfa86-094f-4bc9-9e36-fbbb29dcd9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13590
30034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1359030034
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.251768537
Short name T356
Test name
Test status
Simulation time 10059695113 ps
CPU time 12.93 seconds
Started May 26 01:34:10 PM PDT 24
Finished May 26 01:34:23 PM PDT 24
Peak memory 205376 kb
Host smart-c7960a0e-7e11-41d5-97ed-219c590d9b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176
8537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.251768537
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.137584812
Short name T109
Test name
Test status
Simulation time 10100840151 ps
CPU time 14.84 seconds
Started May 26 01:34:03 PM PDT 24
Finished May 26 01:34:20 PM PDT 24
Peak memory 205240 kb
Host smart-dc06cd8d-a4de-4491-8359-ece36965a477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13758
4812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.137584812
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.346267895
Short name T82
Test name
Test status
Simulation time 10083161399 ps
CPU time 15.47 seconds
Started May 26 01:34:03 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205192 kb
Host smart-464f02d1-caf9-4a02-a0ff-5f1c3e20dab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
7895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.346267895
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.153754021
Short name T1000
Test name
Test status
Simulation time 10061907438 ps
CPU time 14.47 seconds
Started May 26 01:34:10 PM PDT 24
Finished May 26 01:34:26 PM PDT 24
Peak memory 205152 kb
Host smart-60e89a62-a5a1-4415-a8b8-a45334523ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15375
4021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.153754021
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.4167197058
Short name T804
Test name
Test status
Simulation time 10070665028 ps
CPU time 16.16 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:20 PM PDT 24
Peak memory 205296 kb
Host smart-51a0024c-ae88-4b30-a0a1-0c7f4565ce2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41671
97058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.4167197058
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1084220987
Short name T1817
Test name
Test status
Simulation time 10080881955 ps
CPU time 13.69 seconds
Started May 26 01:34:01 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205320 kb
Host smart-0da34b6a-1d35-4702-880a-326abf21ec88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10842
20987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1084220987
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.1915760616
Short name T873
Test name
Test status
Simulation time 10062608564 ps
CPU time 13.55 seconds
Started May 26 01:34:00 PM PDT 24
Finished May 26 01:34:16 PM PDT 24
Peak memory 205224 kb
Host smart-ecce80c9-d8d0-477c-9687-e2b8f28ab679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19157
60616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.1915760616
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3989260441
Short name T1777
Test name
Test status
Simulation time 10047273689 ps
CPU time 15.38 seconds
Started May 26 01:34:06 PM PDT 24
Finished May 26 01:34:23 PM PDT 24
Peak memory 205268 kb
Host smart-330ed4d5-1b2d-4fcf-bfd6-ac3ed5b9a814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
60441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3989260441
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3035699770
Short name T1645
Test name
Test status
Simulation time 10043565366 ps
CPU time 14.36 seconds
Started May 26 01:34:00 PM PDT 24
Finished May 26 01:34:16 PM PDT 24
Peak memory 205316 kb
Host smart-58586400-3d66-45b6-bb4d-25e245c8ae37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30356
99770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3035699770
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.401976212
Short name T246
Test name
Test status
Simulation time 21163325739 ps
CPU time 41.62 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205372 kb
Host smart-9ba7b8c3-9f2d-4be1-9887-7c6dcfc76374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
6212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.401976212
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2224666764
Short name T73
Test name
Test status
Simulation time 10042046079 ps
CPU time 14.2 seconds
Started May 26 01:34:05 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205248 kb
Host smart-86fd9695-1293-4877-bddd-c5794e00363b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246
66764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2224666764
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.256615090
Short name T1080
Test name
Test status
Simulation time 10090353075 ps
CPU time 14.18 seconds
Started May 26 01:34:05 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205272 kb
Host smart-8f46ca46-4404-4e78-9d3e-de66f45b991c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25661
5090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.256615090
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.3188505919
Short name T363
Test name
Test status
Simulation time 10093407817 ps
CPU time 15.4 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:19 PM PDT 24
Peak memory 205268 kb
Host smart-398a6226-858a-4ec0-a276-384f5073b7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31885
05919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.3188505919
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.428608073
Short name T1001
Test name
Test status
Simulation time 10075125747 ps
CPU time 14.12 seconds
Started May 26 01:34:04 PM PDT 24
Finished May 26 01:34:20 PM PDT 24
Peak memory 205296 kb
Host smart-cbd6779f-a000-44c3-ab59-a8d9d4be79cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860
8073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.428608073
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3395391280
Short name T1248
Test name
Test status
Simulation time 10062984557 ps
CPU time 13 seconds
Started May 26 01:34:10 PM PDT 24
Finished May 26 01:34:24 PM PDT 24
Peak memory 205324 kb
Host smart-091dd8ed-da79-4166-9968-93fd15f0a5b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33953
91280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3395391280
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2932446790
Short name T1450
Test name
Test status
Simulation time 10051329347 ps
CPU time 15.04 seconds
Started May 26 01:34:05 PM PDT 24
Finished May 26 01:34:21 PM PDT 24
Peak memory 205196 kb
Host smart-4f270897-0f9e-4155-b840-5a946daa1920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
46790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2932446790
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4053058585
Short name T958
Test name
Test status
Simulation time 10159926625 ps
CPU time 15.03 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:19 PM PDT 24
Peak memory 205244 kb
Host smart-94869312-8bcb-400f-8a3f-49f3b1c9667c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
58585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4053058585
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.4026495797
Short name T960
Test name
Test status
Simulation time 10064371911 ps
CPU time 13.15 seconds
Started May 26 01:34:02 PM PDT 24
Finished May 26 01:34:17 PM PDT 24
Peak memory 205288 kb
Host smart-b35e8460-921e-4a89-a703-717b1deaa3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40264
95797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.4026495797
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2648564335
Short name T1372
Test name
Test status
Simulation time 10062578752 ps
CPU time 12.52 seconds
Started May 26 01:34:10 PM PDT 24
Finished May 26 01:34:24 PM PDT 24
Peak memory 204944 kb
Host smart-d290ab02-dc5e-480f-9b43-0eceb748c251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26485
64335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2648564335
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.406616330
Short name T638
Test name
Test status
Simulation time 10219519145 ps
CPU time 14.4 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:37 PM PDT 24
Peak memory 205268 kb
Host smart-52e1a261-0c4f-4179-9ee9-9ac53f8f3af8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=406616330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.406616330
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.1637941248
Short name T754
Test name
Test status
Simulation time 10054310032 ps
CPU time 13.39 seconds
Started May 26 01:34:28 PM PDT 24
Finished May 26 01:34:43 PM PDT 24
Peak memory 205248 kb
Host smart-77dce2c4-fcab-45d2-8c9a-3bd0f981f74e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1637941248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.1637941248
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.3903735926
Short name T1872
Test name
Test status
Simulation time 10103063342 ps
CPU time 15.59 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205264 kb
Host smart-7db97d92-21b9-4f82-b17b-dd1806bf284f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39037
35926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.3903735926
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.755182022
Short name T1381
Test name
Test status
Simulation time 13497157216 ps
CPU time 18.26 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:32 PM PDT 24
Peak memory 205300 kb
Host smart-202c4a3f-612f-4f42-a1e3-e4ebd09a5cd6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=755182022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.755182022
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.454447452
Short name T1910
Test name
Test status
Simulation time 13295393417 ps
CPU time 19.45 seconds
Started May 26 01:34:12 PM PDT 24
Finished May 26 01:34:32 PM PDT 24
Peak memory 205304 kb
Host smart-d5aa21c4-3b9b-4aba-b739-0a159892d8b0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=454447452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.454447452
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3952281806
Short name T1414
Test name
Test status
Simulation time 13265735524 ps
CPU time 16.81 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:33 PM PDT 24
Peak memory 205308 kb
Host smart-748913b6-133c-4d2b-86b4-62799ba99fa0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3952281806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.3952281806
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.6148391
Short name T1904
Test name
Test status
Simulation time 10057881978 ps
CPU time 16.74 seconds
Started May 26 01:34:11 PM PDT 24
Finished May 26 01:34:29 PM PDT 24
Peak memory 205296 kb
Host smart-3c9bd4a0-daaf-423e-8730-73548b732ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61483
91 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.6148391
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.696978229
Short name T768
Test name
Test status
Simulation time 11038621459 ps
CPU time 15.85 seconds
Started May 26 01:34:11 PM PDT 24
Finished May 26 01:34:28 PM PDT 24
Peak memory 205296 kb
Host smart-5292377a-8afc-4a05-826e-ef960568e9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69697
8229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.696978229
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.4277850818
Short name T1066
Test name
Test status
Simulation time 10044865964 ps
CPU time 14.31 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205260 kb
Host smart-52bd0a7d-f49c-4186-8825-f6ec5fb74d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
50818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.4277850818
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1300651980
Short name T1256
Test name
Test status
Simulation time 10079189721 ps
CPU time 16.59 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:32 PM PDT 24
Peak memory 204812 kb
Host smart-e2d65133-6b94-48c3-9d2f-d5817802aaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13006
51980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1300651980
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1047551455
Short name T1598
Test name
Test status
Simulation time 10058129119 ps
CPU time 15.81 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205232 kb
Host smart-1c621c8c-40bf-40a3-9613-7a76e28dc6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10475
51455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1047551455
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3217082958
Short name T510
Test name
Test status
Simulation time 10101532443 ps
CPU time 14.19 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205252 kb
Host smart-8e5b1145-8ce0-4fa4-89bb-1b4b07c2f03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32170
82958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3217082958
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2426620565
Short name T951
Test name
Test status
Simulation time 10041677151 ps
CPU time 14.35 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:28 PM PDT 24
Peak memory 205296 kb
Host smart-14018dc2-4945-4290-8d1f-e5c613f42bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24266
20565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2426620565
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2097826122
Short name T1461
Test name
Test status
Simulation time 10099600939 ps
CPU time 15.18 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205272 kb
Host smart-58c6cacb-518b-46d6-9857-3e78366d7bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
26122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2097826122
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.799747490
Short name T32
Test name
Test status
Simulation time 10132047048 ps
CPU time 16.28 seconds
Started May 26 01:34:10 PM PDT 24
Finished May 26 01:34:27 PM PDT 24
Peak memory 205188 kb
Host smart-96da8089-3d38-4bcc-af11-f2bac43cd38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79974
7490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.799747490
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.4168783661
Short name T879
Test name
Test status
Simulation time 13198819446 ps
CPU time 17.06 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205332 kb
Host smart-dd83e128-22d6-44c0-a498-159bf0f99fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41687
83661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.4168783661
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1673424701
Short name T314
Test name
Test status
Simulation time 10091726925 ps
CPU time 14.98 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:29 PM PDT 24
Peak memory 205192 kb
Host smart-5477cb2d-4c35-4f1e-8fa9-953901daf910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
24701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1673424701
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3500039516
Short name T889
Test name
Test status
Simulation time 10059943603 ps
CPU time 16.95 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205288 kb
Host smart-e17ded33-651f-4c7c-a9e8-528bf05eedd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35000
39516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3500039516
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3858467646
Short name T1706
Test name
Test status
Simulation time 10123341165 ps
CPU time 14.74 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205232 kb
Host smart-ac8612a2-abeb-45fd-96ec-8cc74f58d015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38584
67646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3858467646
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4243451610
Short name T1368
Test name
Test status
Simulation time 10072245277 ps
CPU time 14.57 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:29 PM PDT 24
Peak memory 205232 kb
Host smart-2ec30489-8923-4f06-ba86-c51f15dba6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42434
51610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4243451610
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2760055792
Short name T447
Test name
Test status
Simulation time 10092535959 ps
CPU time 14.49 seconds
Started May 26 01:34:11 PM PDT 24
Finished May 26 01:34:26 PM PDT 24
Peak memory 205256 kb
Host smart-b0787194-34e2-457e-86a2-f3c272ed455e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600
55792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2760055792
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.687773593
Short name T1885
Test name
Test status
Simulation time 10090736329 ps
CPU time 16.41 seconds
Started May 26 01:34:11 PM PDT 24
Finished May 26 01:34:28 PM PDT 24
Peak memory 205304 kb
Host smart-9e78dd31-35f0-49a8-bce2-43b307e4d539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68777
3593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.687773593
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.2023746176
Short name T640
Test name
Test status
Simulation time 10057311370 ps
CPU time 16.01 seconds
Started May 26 01:34:17 PM PDT 24
Finished May 26 01:34:33 PM PDT 24
Peak memory 205288 kb
Host smart-d2e2f86e-1c17-4a1e-9be9-aa437d8dc3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20237
46176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.2023746176
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.961499575
Short name T1119
Test name
Test status
Simulation time 10064121155 ps
CPU time 16.36 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205272 kb
Host smart-0665eb1f-09a9-4efe-9356-7c395670ffb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96149
9575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.961499575
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3192369427
Short name T849
Test name
Test status
Simulation time 10088262829 ps
CPU time 16.35 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205232 kb
Host smart-c1765daf-ac71-4cb0-a24a-b5e02e21bb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31923
69427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3192369427
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.4121074628
Short name T775
Test name
Test status
Simulation time 29399689474 ps
CPU time 55.97 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 204712 kb
Host smart-4dcf267d-bdbd-4a49-8805-e617433d552c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41210
74628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.4121074628
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3353776227
Short name T497
Test name
Test status
Simulation time 10093576810 ps
CPU time 15.27 seconds
Started May 26 01:34:12 PM PDT 24
Finished May 26 01:34:28 PM PDT 24
Peak memory 205224 kb
Host smart-68ee8e3f-a940-4d5c-b013-1c803710e85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33537
76227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3353776227
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3449409855
Short name T875
Test name
Test status
Simulation time 10184114095 ps
CPU time 15.1 seconds
Started May 26 01:34:12 PM PDT 24
Finished May 26 01:34:28 PM PDT 24
Peak memory 205484 kb
Host smart-346a737a-2819-4435-93b1-57c51a011d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34494
09855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3449409855
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.1335152251
Short name T360
Test name
Test status
Simulation time 10092535744 ps
CPU time 16.19 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205264 kb
Host smart-8f1b91ef-27c3-4002-8bd8-7dd73f8e08b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
52251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.1335152251
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.1622302625
Short name T1309
Test name
Test status
Simulation time 10040809561 ps
CPU time 16.17 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205280 kb
Host smart-27340c8f-54e8-41fc-b983-b5b9bfc3c9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16223
02625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.1622302625
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2544981961
Short name T1025
Test name
Test status
Simulation time 10075288661 ps
CPU time 13.02 seconds
Started May 26 01:34:17 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205292 kb
Host smart-aa4ea4e3-cae2-4509-ba4d-26ca1a7e5887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25449
81961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2544981961
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.2077242397
Short name T822
Test name
Test status
Simulation time 10061649842 ps
CPU time 15.78 seconds
Started May 26 01:34:15 PM PDT 24
Finished May 26 01:34:31 PM PDT 24
Peak memory 205236 kb
Host smart-044603c7-57e1-4007-bc57-b5f445a04105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
42397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.2077242397
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.930119182
Short name T1456
Test name
Test status
Simulation time 10100250009 ps
CPU time 15.11 seconds
Started May 26 01:34:14 PM PDT 24
Finished May 26 01:34:30 PM PDT 24
Peak memory 205304 kb
Host smart-b50e2a9a-a88b-4df5-9456-332062303f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93011
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.930119182
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1267053529
Short name T1094
Test name
Test status
Simulation time 10073285549 ps
CPU time 14.88 seconds
Started May 26 01:34:13 PM PDT 24
Finished May 26 01:34:29 PM PDT 24
Peak memory 205240 kb
Host smart-dcdaae27-a913-4e4e-8e2d-34c169fc1b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
53529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1267053529
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.4143673966
Short name T1112
Test name
Test status
Simulation time 10068994641 ps
CPU time 15.45 seconds
Started May 26 01:34:12 PM PDT 24
Finished May 26 01:34:29 PM PDT 24
Peak memory 205292 kb
Host smart-27ab065e-7264-4c10-a6ab-8790716b5d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41436
73966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.4143673966
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2433059508
Short name T1894
Test name
Test status
Simulation time 10194532837 ps
CPU time 16.35 seconds
Started May 26 01:27:39 PM PDT 24
Finished May 26 01:27:57 PM PDT 24
Peak memory 205248 kb
Host smart-ed2ce299-502c-4139-83a7-6cfeb9bbeeda
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2433059508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2433059508
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.553799238
Short name T750
Test name
Test status
Simulation time 10056109431 ps
CPU time 17.01 seconds
Started May 26 01:27:40 PM PDT 24
Finished May 26 01:27:58 PM PDT 24
Peak memory 205300 kb
Host smart-a0072338-743e-438d-89ca-919ad944a5c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=553799238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.553799238
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.320338285
Short name T1541
Test name
Test status
Simulation time 10089161329 ps
CPU time 15.36 seconds
Started May 26 01:27:37 PM PDT 24
Finished May 26 01:27:53 PM PDT 24
Peak memory 205260 kb
Host smart-e2845733-2758-4bc7-8396-9cf4c3418c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32033
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.320338285
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3118218142
Short name T1793
Test name
Test status
Simulation time 13861368736 ps
CPU time 19.16 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:27:32 PM PDT 24
Peak memory 205332 kb
Host smart-ca9681d0-0033-4532-be65-d62fa722db16
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3118218142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3118218142
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1424252943
Short name T4
Test name
Test status
Simulation time 13370058115 ps
CPU time 21.14 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:35 PM PDT 24
Peak memory 205332 kb
Host smart-bb558ce1-4a5b-480d-8d6b-a587fa58dbbf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1424252943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1424252943
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.2290005074
Short name T476
Test name
Test status
Simulation time 13203052187 ps
CPU time 16.93 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:31 PM PDT 24
Peak memory 205380 kb
Host smart-3ae27a08-d913-493e-86ea-97d2de4d5a52
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2290005074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.2290005074
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.603292662
Short name T467
Test name
Test status
Simulation time 10099042577 ps
CPU time 13.95 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:29 PM PDT 24
Peak memory 205184 kb
Host smart-5abae45a-b27f-48f5-86cb-3a492199b8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60329
2662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.603292662
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1098488568
Short name T76
Test name
Test status
Simulation time 10054455139 ps
CPU time 16.06 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:31 PM PDT 24
Peak memory 205328 kb
Host smart-384108f2-f63a-4bc5-b5e7-0fb61d7800c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10984
88568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1098488568
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3110846764
Short name T477
Test name
Test status
Simulation time 10686972058 ps
CPU time 17.14 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:32 PM PDT 24
Peak memory 205300 kb
Host smart-75fb74a7-daad-430c-b3fc-519d7554b44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
46764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3110846764
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.686574617
Short name T1778
Test name
Test status
Simulation time 10042345107 ps
CPU time 14.38 seconds
Started May 26 01:27:20 PM PDT 24
Finished May 26 01:27:35 PM PDT 24
Peak memory 205260 kb
Host smart-3c82ca10-c946-4d5f-aa9c-1cfb2bbdc8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68657
4617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.686574617
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1387279309
Short name T1027
Test name
Test status
Simulation time 10064023894 ps
CPU time 12.48 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:27:25 PM PDT 24
Peak memory 205252 kb
Host smart-89406c89-88be-40dc-816d-154887475328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13872
79309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1387279309
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3693289013
Short name T1877
Test name
Test status
Simulation time 10806356949 ps
CPU time 15.18 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:30 PM PDT 24
Peak memory 205288 kb
Host smart-782583e0-670f-4f38-8281-7f0f9f61ff1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36932
89013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3693289013
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3025021350
Short name T1174
Test name
Test status
Simulation time 10297676595 ps
CPU time 16.87 seconds
Started May 26 01:27:12 PM PDT 24
Finished May 26 01:27:30 PM PDT 24
Peak memory 205276 kb
Host smart-3ccd96da-88b2-4b37-bfd4-712a1978b83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
21350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3025021350
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3047126563
Short name T1132
Test name
Test status
Simulation time 10125091431 ps
CPU time 13.91 seconds
Started May 26 01:27:37 PM PDT 24
Finished May 26 01:27:52 PM PDT 24
Peak memory 205328 kb
Host smart-b2d487ab-5fba-4890-a709-d63db8ad81bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30471
26563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3047126563
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3727231965
Short name T1187
Test name
Test status
Simulation time 10044738708 ps
CPU time 15.94 seconds
Started May 26 01:27:31 PM PDT 24
Finished May 26 01:27:48 PM PDT 24
Peak memory 205188 kb
Host smart-324a046f-7bd3-4eec-b0eb-e049f6beb28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37272
31965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3727231965
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.598525233
Short name T1380
Test name
Test status
Simulation time 10112297098 ps
CPU time 13.71 seconds
Started May 26 01:27:14 PM PDT 24
Finished May 26 01:27:29 PM PDT 24
Peak memory 205228 kb
Host smart-48866512-6857-4ceb-9c5e-deec3ddd9aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59852
5233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.598525233
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1771206305
Short name T1628
Test name
Test status
Simulation time 10061559396 ps
CPU time 13.83 seconds
Started May 26 01:27:13 PM PDT 24
Finished May 26 01:27:28 PM PDT 24
Peak memory 205280 kb
Host smart-58e21a58-0a82-44c1-b357-717c7c5d52a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17712
06305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1771206305
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1841597483
Short name T404
Test name
Test status
Simulation time 13223284827 ps
CPU time 18.05 seconds
Started May 26 01:27:19 PM PDT 24
Finished May 26 01:27:38 PM PDT 24
Peak memory 205280 kb
Host smart-6917ffd0-f8ae-420e-a5c8-7a8f09cc20a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18415
97483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1841597483
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2508539285
Short name T1184
Test name
Test status
Simulation time 10086626197 ps
CPU time 13.21 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:38 PM PDT 24
Peak memory 205236 kb
Host smart-27888953-206c-4f18-bd5e-8351cd0e42b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25085
39285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2508539285
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2253115146
Short name T855
Test name
Test status
Simulation time 10040247115 ps
CPU time 14.3 seconds
Started May 26 01:27:25 PM PDT 24
Finished May 26 01:27:40 PM PDT 24
Peak memory 205324 kb
Host smart-300e78b5-468b-40a0-b4b0-f60e0176fa18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531
15146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2253115146
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1664440942
Short name T83
Test name
Test status
Simulation time 10093920216 ps
CPU time 13.26 seconds
Started May 26 01:27:20 PM PDT 24
Finished May 26 01:27:34 PM PDT 24
Peak memory 205336 kb
Host smart-c316cd9f-0b33-4b74-be59-b7daed1b998a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16644
40942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1664440942
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.4217464311
Short name T1317
Test name
Test status
Simulation time 10106555571 ps
CPU time 13.72 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:39 PM PDT 24
Peak memory 205348 kb
Host smart-d406b175-6fca-4fce-8017-8e054f897a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42174
64311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4217464311
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1958229658
Short name T1147
Test name
Test status
Simulation time 10077277320 ps
CPU time 13.87 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:39 PM PDT 24
Peak memory 205228 kb
Host smart-da69d2ec-f2f2-439e-a72d-f463d4c277b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19582
29658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1958229658
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3607094943
Short name T1847
Test name
Test status
Simulation time 10095202007 ps
CPU time 14.69 seconds
Started May 26 01:27:28 PM PDT 24
Finished May 26 01:27:43 PM PDT 24
Peak memory 205272 kb
Host smart-bc125f3e-da7c-4020-ae0c-6f1e7b4ab3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36070
94943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3607094943
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.3127858854
Short name T1275
Test name
Test status
Simulation time 10088336458 ps
CPU time 13.78 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:44 PM PDT 24
Peak memory 205204 kb
Host smart-bacc198d-9ef3-4ec0-b94f-4c97f62db5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31278
58854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.3127858854
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1803304211
Short name T1734
Test name
Test status
Simulation time 10062430548 ps
CPU time 16.95 seconds
Started May 26 01:27:31 PM PDT 24
Finished May 26 01:27:49 PM PDT 24
Peak memory 205204 kb
Host smart-d869fb5b-62c5-463e-bc8b-97a9b69ca451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18033
04211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1803304211
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3477550166
Short name T559
Test name
Test status
Simulation time 10057010040 ps
CPU time 15.27 seconds
Started May 26 01:27:30 PM PDT 24
Finished May 26 01:27:46 PM PDT 24
Peak memory 205300 kb
Host smart-905c8a15-f995-471c-bfde-fa1b72c73dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34775
50166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3477550166
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1888870616
Short name T793
Test name
Test status
Simulation time 25860301223 ps
CPU time 47.77 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:28:12 PM PDT 24
Peak memory 205360 kb
Host smart-03553a35-6e12-4b72-b846-376a01e60f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18888
70616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1888870616
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2977238133
Short name T310
Test name
Test status
Simulation time 10075064698 ps
CPU time 13.86 seconds
Started May 26 01:27:24 PM PDT 24
Finished May 26 01:27:39 PM PDT 24
Peak memory 205280 kb
Host smart-e4139641-e276-4e1f-9e87-a99d0ab275f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29772
38133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2977238133
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2236693159
Short name T735
Test name
Test status
Simulation time 10137970559 ps
CPU time 14.46 seconds
Started May 26 01:27:26 PM PDT 24
Finished May 26 01:27:41 PM PDT 24
Peak memory 205344 kb
Host smart-80fb7614-6b8a-43cf-b210-c6c33257123f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
93159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2236693159
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1377018988
Short name T605
Test name
Test status
Simulation time 10063538751 ps
CPU time 13.12 seconds
Started May 26 01:27:21 PM PDT 24
Finished May 26 01:27:35 PM PDT 24
Peak memory 205256 kb
Host smart-f6c165a6-1041-4886-875c-f62411a91a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
18988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1377018988
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1670877850
Short name T1757
Test name
Test status
Simulation time 10061299314 ps
CPU time 15.3 seconds
Started May 26 01:27:33 PM PDT 24
Finished May 26 01:27:49 PM PDT 24
Peak memory 205220 kb
Host smart-c3938e90-e96d-4744-95f8-a09701dc16b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16708
77850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1670877850
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.2641037875
Short name T216
Test name
Test status
Simulation time 891595023 ps
CPU time 1.62 seconds
Started May 26 01:27:40 PM PDT 24
Finished May 26 01:27:43 PM PDT 24
Peak memory 221400 kb
Host smart-306046be-8d7a-4cd8-9aba-6762fc198b00
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2641037875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.2641037875
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1026231459
Short name T1739
Test name
Test status
Simulation time 10128946245 ps
CPU time 14.1 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:44 PM PDT 24
Peak memory 205260 kb
Host smart-bcc3303c-5de2-4215-8c0c-f10b6ddc5470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10262
31459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1026231459
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.2327232617
Short name T1521
Test name
Test status
Simulation time 10059597466 ps
CPU time 16.18 seconds
Started May 26 01:27:29 PM PDT 24
Finished May 26 01:27:47 PM PDT 24
Peak memory 205264 kb
Host smart-e2e7e807-b72c-4f81-b6a6-92a336cc802b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
32617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2327232617
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.665553216
Short name T1668
Test name
Test status
Simulation time 10126697667 ps
CPU time 13.56 seconds
Started May 26 01:27:10 PM PDT 24
Finished May 26 01:27:24 PM PDT 24
Peak memory 205224 kb
Host smart-dda4be5a-9649-4cf3-bce4-573998ba81c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66555
3216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.665553216
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.145588915
Short name T1135
Test name
Test status
Simulation time 10064292171 ps
CPU time 13.72 seconds
Started May 26 01:27:30 PM PDT 24
Finished May 26 01:27:45 PM PDT 24
Peak memory 205332 kb
Host smart-44ed250d-4724-4d23-8a09-0d1180e2f5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14558
8915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.145588915
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2147956650
Short name T1162
Test name
Test status
Simulation time 10069783706 ps
CPU time 14.06 seconds
Started May 26 01:27:28 PM PDT 24
Finished May 26 01:27:43 PM PDT 24
Peak memory 205260 kb
Host smart-6fabcb19-8e63-4a3d-9d42-3be366aaf2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21479
56650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2147956650
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.493034859
Short name T1233
Test name
Test status
Simulation time 10136010881 ps
CPU time 13.37 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205312 kb
Host smart-e59dcfe8-aedf-430f-affa-e14c95e67548
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=493034859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.493034859
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.1501155712
Short name T1383
Test name
Test status
Simulation time 10067342447 ps
CPU time 13.53 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:45 PM PDT 24
Peak memory 205296 kb
Host smart-76e22b4f-9cae-4b20-8fa2-447a148d2fde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1501155712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.1501155712
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.1844629052
Short name T1049
Test name
Test status
Simulation time 10191452184 ps
CPU time 13.48 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205260 kb
Host smart-6834fb11-b4bb-4138-8939-ac3077158b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
29052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.1844629052
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.735842053
Short name T1751
Test name
Test status
Simulation time 13508160601 ps
CPU time 20.36 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:50 PM PDT 24
Peak memory 205252 kb
Host smart-288fd0d2-e3fd-48c9-b6e2-30e234b84ecb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=735842053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.735842053
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2858166639
Short name T1356
Test name
Test status
Simulation time 13281286453 ps
CPU time 17.44 seconds
Started May 26 01:34:24 PM PDT 24
Finished May 26 01:34:42 PM PDT 24
Peak memory 205256 kb
Host smart-2baf82ab-bb3f-46fa-afd6-05a4760a2afa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2858166639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2858166639
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.994411416
Short name T1678
Test name
Test status
Simulation time 13272789540 ps
CPU time 18.59 seconds
Started May 26 01:34:21 PM PDT 24
Finished May 26 01:34:40 PM PDT 24
Peak memory 205368 kb
Host smart-8aca9a3e-c283-4ae2-8ded-ff25a00a2b91
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=994411416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.994411416
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.795134428
Short name T733
Test name
Test status
Simulation time 10075211624 ps
CPU time 14.16 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:36 PM PDT 24
Peak memory 205176 kb
Host smart-f73540eb-d630-4e8e-b2c0-d50944172e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79513
4428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.795134428
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3940154358
Short name T1496
Test name
Test status
Simulation time 10958702565 ps
CPU time 17.77 seconds
Started May 26 01:34:21 PM PDT 24
Finished May 26 01:34:39 PM PDT 24
Peak memory 205344 kb
Host smart-a464da45-e765-403f-9a72-2d4b124db7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39401
54358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3940154358
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2614293257
Short name T1194
Test name
Test status
Simulation time 10042128552 ps
CPU time 14.75 seconds
Started May 26 01:34:24 PM PDT 24
Finished May 26 01:34:40 PM PDT 24
Peak memory 205312 kb
Host smart-923fae8e-fea2-4dfe-ae9c-8a9f44802f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26142
93257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2614293257
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.307751180
Short name T1550
Test name
Test status
Simulation time 10073885539 ps
CPU time 15.03 seconds
Started May 26 01:34:20 PM PDT 24
Finished May 26 01:34:36 PM PDT 24
Peak memory 205368 kb
Host smart-474c7be5-6ab1-433f-9beb-7f5b0c883982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
1180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.307751180
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3029080038
Short name T646
Test name
Test status
Simulation time 10759580822 ps
CPU time 16.23 seconds
Started May 26 01:34:21 PM PDT 24
Finished May 26 01:34:38 PM PDT 24
Peak memory 205508 kb
Host smart-686049e8-461e-404c-b395-65b5d1ab54a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30290
80038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3029080038
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.4113949886
Short name T1361
Test name
Test status
Simulation time 10070266245 ps
CPU time 14.27 seconds
Started May 26 01:34:28 PM PDT 24
Finished May 26 01:34:43 PM PDT 24
Peak memory 205204 kb
Host smart-ea66dc2d-7f25-4fb7-85f6-24fce407eaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41139
49886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.4113949886
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3991023824
Short name T1084
Test name
Test status
Simulation time 10116425841 ps
CPU time 13.87 seconds
Started May 26 01:34:33 PM PDT 24
Finished May 26 01:34:47 PM PDT 24
Peak memory 205244 kb
Host smart-4424b3f2-45ce-4961-b31c-cfd816b88125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39910
23824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3991023824
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3274048185
Short name T1377
Test name
Test status
Simulation time 10069859384 ps
CPU time 13.15 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:44 PM PDT 24
Peak memory 205280 kb
Host smart-746bc2f4-5fb3-4a47-8772-fb73c062bfbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740
48185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3274048185
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3740233436
Short name T1278
Test name
Test status
Simulation time 10153502256 ps
CPU time 12.6 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:43 PM PDT 24
Peak memory 205236 kb
Host smart-224d873e-aba1-47e4-b239-a09f0c92a8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37402
33436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3740233436
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.4125016965
Short name T1082
Test name
Test status
Simulation time 10088435832 ps
CPU time 14.03 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:36 PM PDT 24
Peak memory 205256 kb
Host smart-41699c5a-4fff-4725-bfdd-eda22a787cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41250
16965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.4125016965
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1823404755
Short name T563
Test name
Test status
Simulation time 13234283822 ps
CPU time 15.71 seconds
Started May 26 01:34:26 PM PDT 24
Finished May 26 01:34:42 PM PDT 24
Peak memory 205200 kb
Host smart-2ff45b34-6a13-43af-997b-03edaddd6c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18234
04755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1823404755
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3381528844
Short name T1034
Test name
Test status
Simulation time 10101263403 ps
CPU time 14.12 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:37 PM PDT 24
Peak memory 205320 kb
Host smart-a48d8939-fbc1-4ff6-86a2-376bb169a8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33815
28844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3381528844
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3208953003
Short name T1801
Test name
Test status
Simulation time 10067162653 ps
CPU time 14 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:37 PM PDT 24
Peak memory 205308 kb
Host smart-caaba51a-3664-4f66-9d09-b5360da45592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32089
53003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3208953003
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2392169539
Short name T124
Test name
Test status
Simulation time 10127537281 ps
CPU time 13.36 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:36 PM PDT 24
Peak memory 205256 kb
Host smart-93d5b339-5eba-4aa9-92a5-6fcf6118050a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23921
69539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2392169539
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3234236065
Short name T1035
Test name
Test status
Simulation time 10110107521 ps
CPU time 16.59 seconds
Started May 26 01:34:25 PM PDT 24
Finished May 26 01:34:42 PM PDT 24
Peak memory 205156 kb
Host smart-167200ed-0a32-4ee1-a30f-7a4fdd93b3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32342
36065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3234236065
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.667062564
Short name T1164
Test name
Test status
Simulation time 10096134110 ps
CPU time 17.24 seconds
Started May 26 01:34:26 PM PDT 24
Finished May 26 01:34:44 PM PDT 24
Peak memory 205348 kb
Host smart-747a9545-5077-4295-8f34-9a552f507abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66706
2564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.667062564
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.691793535
Short name T327
Test name
Test status
Simulation time 10088773193 ps
CPU time 16.28 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:39 PM PDT 24
Peak memory 205216 kb
Host smart-7d927aa7-242e-4c75-b35c-d495164b542d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69179
3535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.691793535
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.92196870
Short name T167
Test name
Test status
Simulation time 10066321693 ps
CPU time 14.11 seconds
Started May 26 01:34:36 PM PDT 24
Finished May 26 01:34:50 PM PDT 24
Peak memory 205288 kb
Host smart-57df6958-cb36-4acc-8908-933a2de2a103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92196
870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.92196870
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.2520315541
Short name T531
Test name
Test status
Simulation time 10078133520 ps
CPU time 12.88 seconds
Started May 26 01:34:23 PM PDT 24
Finished May 26 01:34:36 PM PDT 24
Peak memory 205280 kb
Host smart-7033cf50-c624-4dee-b61e-8a77fa3bd3f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25203
15541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.2520315541
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.979028013
Short name T1761
Test name
Test status
Simulation time 10051817985 ps
CPU time 14.46 seconds
Started May 26 01:34:23 PM PDT 24
Finished May 26 01:34:38 PM PDT 24
Peak memory 205292 kb
Host smart-b237bf9e-5aad-4471-b52a-f6c37d769053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97902
8013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.979028013
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3181288008
Short name T1277
Test name
Test status
Simulation time 10040105213 ps
CPU time 14.16 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205288 kb
Host smart-f1cc6ee8-55d3-44d7-a340-d302ea9d410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31812
88008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3181288008
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.2796369784
Short name T1288
Test name
Test status
Simulation time 25701499808 ps
CPU time 53.78 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:35:16 PM PDT 24
Peak memory 205288 kb
Host smart-f997a56e-9e81-4d68-a95c-797d9cd54e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27963
69784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.2796369784
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1110791012
Short name T569
Test name
Test status
Simulation time 10084382900 ps
CPU time 15.34 seconds
Started May 26 01:34:24 PM PDT 24
Finished May 26 01:34:40 PM PDT 24
Peak memory 205264 kb
Host smart-c8896c35-052a-485d-aeae-6dbf54b6090d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11107
91012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1110791012
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.169052685
Short name T1360
Test name
Test status
Simulation time 10131968210 ps
CPU time 14.06 seconds
Started May 26 01:34:23 PM PDT 24
Finished May 26 01:34:38 PM PDT 24
Peak memory 205280 kb
Host smart-cfe903c0-f659-477a-997e-f71767508fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16905
2685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.169052685
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.2796937220
Short name T655
Test name
Test status
Simulation time 10089912395 ps
CPU time 13.92 seconds
Started May 26 01:34:21 PM PDT 24
Finished May 26 01:34:35 PM PDT 24
Peak memory 205268 kb
Host smart-2c3dbcca-27ce-4707-aa89-81609c7d9587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
37220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.2796937220
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1570661964
Short name T464
Test name
Test status
Simulation time 10042928331 ps
CPU time 15.66 seconds
Started May 26 01:34:22 PM PDT 24
Finished May 26 01:34:38 PM PDT 24
Peak memory 205280 kb
Host smart-60bd5de3-1c05-49a2-bee2-fa3e9d0faeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15706
61964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1570661964
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.151747425
Short name T88
Test name
Test status
Simulation time 10050820855 ps
CPU time 13.84 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:45 PM PDT 24
Peak memory 205212 kb
Host smart-7c470281-9d17-415c-841b-84d78e06533b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15174
7425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.151747425
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3679456313
Short name T517
Test name
Test status
Simulation time 10132997256 ps
CPU time 12.41 seconds
Started May 26 01:34:26 PM PDT 24
Finished May 26 01:34:39 PM PDT 24
Peak memory 205328 kb
Host smart-eb8a59b9-1260-42eb-8320-ccfdce5077d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794
56313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3679456313
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.4258417262
Short name T1353
Test name
Test status
Simulation time 10116743789 ps
CPU time 12.97 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:43 PM PDT 24
Peak memory 205232 kb
Host smart-5807340e-9dcb-47fb-83f8-d3a44aad9670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
17262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4258417262
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2277140650
Short name T1237
Test name
Test status
Simulation time 10055183118 ps
CPU time 14.81 seconds
Started May 26 01:34:26 PM PDT 24
Finished May 26 01:34:41 PM PDT 24
Peak memory 205360 kb
Host smart-8e029bc9-d61c-4b69-9171-77c8d6d3c990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22771
40650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2277140650
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1839386528
Short name T1395
Test name
Test status
Simulation time 10098269442 ps
CPU time 17.24 seconds
Started May 26 01:34:23 PM PDT 24
Finished May 26 01:34:41 PM PDT 24
Peak memory 205228 kb
Host smart-67db5cbf-b5ad-41b1-ab5b-9351b7d2d481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18393
86528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1839386528
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.345120865
Short name T1603
Test name
Test status
Simulation time 10139468401 ps
CPU time 15.4 seconds
Started May 26 01:34:44 PM PDT 24
Finished May 26 01:35:00 PM PDT 24
Peak memory 205244 kb
Host smart-a2e6d358-3bed-4e88-ac69-901aa9562978
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=345120865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.345120865
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.2798557727
Short name T659
Test name
Test status
Simulation time 10061653360 ps
CPU time 16.11 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:58 PM PDT 24
Peak memory 205296 kb
Host smart-fcb1f760-9118-460d-8921-cb64cb2f7780
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2798557727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.2798557727
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3530009347
Short name T863
Test name
Test status
Simulation time 10170433490 ps
CPU time 14.43 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205248 kb
Host smart-78ff868c-3971-4dc0-aa56-68482d99c0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
09347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3530009347
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3112520859
Short name T1206
Test name
Test status
Simulation time 13398961699 ps
CPU time 17.26 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:49 PM PDT 24
Peak memory 205328 kb
Host smart-5ff9cc8e-1d27-491a-a9aa-086ffa7baf95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3112520859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3112520859
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1755545057
Short name T13
Test name
Test status
Simulation time 13212412234 ps
CPU time 19.93 seconds
Started May 26 01:34:33 PM PDT 24
Finished May 26 01:34:53 PM PDT 24
Peak memory 205240 kb
Host smart-57d99f1c-6c60-4a34-8cf0-b1b3974c773f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1755545057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1755545057
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2700785163
Short name T1219
Test name
Test status
Simulation time 13317334696 ps
CPU time 17.48 seconds
Started May 26 01:34:28 PM PDT 24
Finished May 26 01:34:47 PM PDT 24
Peak memory 205256 kb
Host smart-e769b7b6-2bd6-46f1-923a-2b016e559a2e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2700785163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2700785163
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.164358675
Short name T1608
Test name
Test status
Simulation time 10056046154 ps
CPU time 13.19 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:45 PM PDT 24
Peak memory 205236 kb
Host smart-51826c89-d5e5-438e-bf50-1f6143413207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16435
8675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.164358675
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.285920504
Short name T771
Test name
Test status
Simulation time 10957466059 ps
CPU time 15.57 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:45 PM PDT 24
Peak memory 205264 kb
Host smart-5a10b98b-d08b-459d-a581-5a1c6933e8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28592
0504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.285920504
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1291811354
Short name T369
Test name
Test status
Simulation time 10038584665 ps
CPU time 15.57 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:48 PM PDT 24
Peak memory 205196 kb
Host smart-bfe00b85-8f00-4b74-a386-72cb02aa44cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12918
11354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1291811354
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2907860627
Short name T1844
Test name
Test status
Simulation time 10056157002 ps
CPU time 15.92 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:47 PM PDT 24
Peak memory 205368 kb
Host smart-60a48d4b-4dfd-4aed-b674-fa091d470628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078
60627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2907860627
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1531324036
Short name T130
Test name
Test status
Simulation time 10843072307 ps
CPU time 15.72 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205228 kb
Host smart-a03cf37a-9fb2-491f-a7f8-61be16e8ab95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15313
24036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1531324036
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.2880789570
Short name T848
Test name
Test status
Simulation time 10108290109 ps
CPU time 14.74 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205236 kb
Host smart-ba13e89a-12ba-47e3-baba-2f4bc06be37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28807
89570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.2880789570
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.21393133
Short name T1890
Test name
Test status
Simulation time 10114183994 ps
CPU time 13.81 seconds
Started May 26 01:34:44 PM PDT 24
Finished May 26 01:34:58 PM PDT 24
Peak memory 205196 kb
Host smart-dbcbda57-4176-4cc0-9fb7-7bc1b7234343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393
133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.21393133
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2634999920
Short name T1756
Test name
Test status
Simulation time 10046492925 ps
CPU time 14.07 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205236 kb
Host smart-8acb21e2-e16b-47e5-b71a-43cbbdecb561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26349
99920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2634999920
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1888220939
Short name T1455
Test name
Test status
Simulation time 10102938767 ps
CPU time 15.81 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:47 PM PDT 24
Peak memory 205304 kb
Host smart-246d9eb7-8faf-424a-805e-7cc247b2a6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18882
20939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1888220939
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3029100910
Short name T931
Test name
Test status
Simulation time 10108759883 ps
CPU time 13.83 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:44 PM PDT 24
Peak memory 205328 kb
Host smart-e25ed07b-a793-4dc4-b7c1-164248120c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30291
00910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3029100910
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1044528557
Short name T777
Test name
Test status
Simulation time 13192111811 ps
CPU time 16.92 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:48 PM PDT 24
Peak memory 205272 kb
Host smart-61c97c50-ac47-4483-b131-33edfdce6548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10445
28557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1044528557
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3925311936
Short name T1836
Test name
Test status
Simulation time 10103237534 ps
CPU time 15.17 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205260 kb
Host smart-86901b26-02dc-4b5e-abc0-f2a1ebc9a54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39253
11936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3925311936
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.4120703135
Short name T1626
Test name
Test status
Simulation time 10062292074 ps
CPU time 14.1 seconds
Started May 26 01:34:30 PM PDT 24
Finished May 26 01:34:45 PM PDT 24
Peak memory 205488 kb
Host smart-a81f4c80-a488-4629-a6a4-034c9f8b649f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
03135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.4120703135
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1676010204
Short name T680
Test name
Test status
Simulation time 10071744657 ps
CPU time 13.83 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:46 PM PDT 24
Peak memory 205248 kb
Host smart-f5680826-8c87-40cd-ba27-aa38918410e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16760
10204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1676010204
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.4045503012
Short name T1335
Test name
Test status
Simulation time 10144302120 ps
CPU time 15.99 seconds
Started May 26 01:34:29 PM PDT 24
Finished May 26 01:34:47 PM PDT 24
Peak memory 205284 kb
Host smart-88081a2d-c603-4d37-b7d3-92f8a32345f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40455
03012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.4045503012
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2826997506
Short name T470
Test name
Test status
Simulation time 10045692581 ps
CPU time 17.28 seconds
Started May 26 01:34:31 PM PDT 24
Finished May 26 01:34:49 PM PDT 24
Peak memory 205272 kb
Host smart-6f56804f-3f02-47ba-b710-c8e9393242f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28269
97506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2826997506
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.226465136
Short name T991
Test name
Test status
Simulation time 10092454901 ps
CPU time 14.34 seconds
Started May 26 01:34:37 PM PDT 24
Finished May 26 01:34:52 PM PDT 24
Peak memory 205292 kb
Host smart-a8844950-deab-46ea-b162-9783a8692db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22646
5136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.226465136
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.4140209284
Short name T1636
Test name
Test status
Simulation time 10136623410 ps
CPU time 15.47 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205460 kb
Host smart-dbe151be-9af9-4f2a-8772-3f38ce150b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
09284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.4140209284
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.250189033
Short name T23
Test name
Test status
Simulation time 10062076996 ps
CPU time 13.46 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205256 kb
Host smart-213619e9-1b6e-42b3-9d14-6477dbd54c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25018
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.250189033
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2350038996
Short name T1633
Test name
Test status
Simulation time 10056127393 ps
CPU time 14.41 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:54 PM PDT 24
Peak memory 205152 kb
Host smart-8bbda1da-51c5-4e95-9513-49faf53850e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23500
38996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2350038996
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1454470018
Short name T1830
Test name
Test status
Simulation time 10074114556 ps
CPU time 14.83 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205280 kb
Host smart-d310428b-5b08-449a-8a91-d29ab8f22861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14544
70018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1454470018
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.1641596975
Short name T1526
Test name
Test status
Simulation time 10088228352 ps
CPU time 15.83 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205284 kb
Host smart-06d02d7d-396a-401f-b5c8-46a9f5804fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16415
96975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.1641596975
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3190110706
Short name T686
Test name
Test status
Simulation time 10063434379 ps
CPU time 15.03 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205280 kb
Host smart-bc6424ba-e528-477e-aa7a-a2488a1b667b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31901
10706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3190110706
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2136632723
Short name T139
Test name
Test status
Simulation time 10094336333 ps
CPU time 16.3 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:54 PM PDT 24
Peak memory 205296 kb
Host smart-02791dcd-176d-4d73-a15f-6a9a8697a88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21366
32723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2136632723
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1378595866
Short name T1466
Test name
Test status
Simulation time 10080376760 ps
CPU time 14.04 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205252 kb
Host smart-a6a781ae-47bc-4798-80ad-d92326227b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13785
95866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1378595866
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.3167867471
Short name T1875
Test name
Test status
Simulation time 10131337249 ps
CPU time 13.43 seconds
Started May 26 01:34:28 PM PDT 24
Finished May 26 01:34:43 PM PDT 24
Peak memory 205328 kb
Host smart-2ac4734f-249f-4373-8f2a-e1128409db8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
67471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3167867471
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.4003512778
Short name T1599
Test name
Test status
Simulation time 10074382864 ps
CPU time 15.29 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205244 kb
Host smart-b4110021-acf4-4b7a-b14b-acf8af832da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40035
12778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.4003512778
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1975525606
Short name T1689
Test name
Test status
Simulation time 10086714214 ps
CPU time 16.66 seconds
Started May 26 01:34:37 PM PDT 24
Finished May 26 01:34:54 PM PDT 24
Peak memory 205204 kb
Host smart-1eb4bf33-4ce3-4e0d-a28d-d5b27d68e235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
25606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1975525606
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.3442969295
Short name T619
Test name
Test status
Simulation time 10133685499 ps
CPU time 14.63 seconds
Started May 26 01:34:48 PM PDT 24
Finished May 26 01:35:03 PM PDT 24
Peak memory 205284 kb
Host smart-ed52c2b3-9346-40c3-856c-e106b4ebfb13
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3442969295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.3442969295
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.2736140282
Short name T903
Test name
Test status
Simulation time 10052906241 ps
CPU time 17.15 seconds
Started May 26 01:34:49 PM PDT 24
Finished May 26 01:35:06 PM PDT 24
Peak memory 205260 kb
Host smart-a2fac189-8bad-4181-be9c-3462dc7e24ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2736140282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.2736140282
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.1060424646
Short name T1518
Test name
Test status
Simulation time 10086983594 ps
CPU time 14.06 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 205276 kb
Host smart-15dbe5c0-59b0-49eb-9992-20600f822cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10604
24646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.1060424646
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1687081564
Short name T623
Test name
Test status
Simulation time 13371711608 ps
CPU time 17.79 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205244 kb
Host smart-6f395074-56f8-4009-9476-6981269d2ac2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1687081564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1687081564
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3301345844
Short name T1850
Test name
Test status
Simulation time 13367621246 ps
CPU time 16.68 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205256 kb
Host smart-da72368b-76bf-461a-8be0-2763780bb5cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3301345844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3301345844
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1809370465
Short name T1555
Test name
Test status
Simulation time 13192879048 ps
CPU time 17.03 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:58 PM PDT 24
Peak memory 205272 kb
Host smart-7399d680-fe07-4357-9ab3-19961aa03467
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1809370465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1809370465
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3960327517
Short name T1407
Test name
Test status
Simulation time 10060846965 ps
CPU time 16.55 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205220 kb
Host smart-d49fbad3-dacb-44fd-a047-a180411157e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39603
27517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3960327517
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3189079269
Short name T163
Test name
Test status
Simulation time 11041484560 ps
CPU time 16.76 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205348 kb
Host smart-f0b51594-3361-4473-aa53-727f9ff4fdd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890
79269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3189079269
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1031457508
Short name T53
Test name
Test status
Simulation time 10063976414 ps
CPU time 14.06 seconds
Started May 26 01:34:43 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205184 kb
Host smart-037d19a1-ad29-4fea-a3b1-7f7635b184ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10314
57508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1031457508
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2645478304
Short name T1350
Test name
Test status
Simulation time 10069715941 ps
CPU time 13.12 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205284 kb
Host smart-fe1fb075-44a2-40eb-a508-c0bd4ffe8de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454
78304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2645478304
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.4159077263
Short name T573
Test name
Test status
Simulation time 10741861454 ps
CPU time 16.09 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205332 kb
Host smart-8e19372b-cecf-4cb6-a68c-ee76a8f69efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41590
77263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.4159077263
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1109923649
Short name T1255
Test name
Test status
Simulation time 10187275979 ps
CPU time 15.29 seconds
Started May 26 01:34:42 PM PDT 24
Finished May 26 01:34:58 PM PDT 24
Peak memory 205452 kb
Host smart-b25e97ac-6b97-426a-bf12-872caa6fda9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11099
23649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1109923649
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3912275561
Short name T1499
Test name
Test status
Simulation time 10109049668 ps
CPU time 15.17 seconds
Started May 26 01:34:49 PM PDT 24
Finished May 26 01:35:05 PM PDT 24
Peak memory 205224 kb
Host smart-82cf9e1a-35d6-4278-9541-a8e3f68269db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39122
75561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3912275561
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2242383751
Short name T564
Test name
Test status
Simulation time 10053984195 ps
CPU time 13.75 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:00 PM PDT 24
Peak memory 205284 kb
Host smart-a0bae634-6332-452d-b7c7-2f41b0719375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
83751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2242383751
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.1807756847
Short name T1111
Test name
Test status
Simulation time 10170717772 ps
CPU time 16.89 seconds
Started May 26 01:34:44 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 205220 kb
Host smart-010ffbae-44cc-4e2b-9f1b-db5929fb1384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18077
56847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.1807756847
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2226121521
Short name T1820
Test name
Test status
Simulation time 10078090916 ps
CPU time 13.21 seconds
Started May 26 01:34:37 PM PDT 24
Finished May 26 01:34:51 PM PDT 24
Peak memory 205256 kb
Host smart-9a43396e-a9ea-4fd0-99f8-dff3cd751e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22261
21521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2226121521
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3951476256
Short name T866
Test name
Test status
Simulation time 13186578521 ps
CPU time 16.83 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205300 kb
Host smart-91844d63-9770-468d-b320-10816653f075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39514
76256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3951476256
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.451111252
Short name T1616
Test name
Test status
Simulation time 10152060917 ps
CPU time 15.53 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205200 kb
Host smart-26c3d159-223b-4957-8b0f-fa0d134ff7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45111
1252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.451111252
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2692273003
Short name T370
Test name
Test status
Simulation time 10043231114 ps
CPU time 14.02 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:53 PM PDT 24
Peak memory 205344 kb
Host smart-94e134db-9ff6-4f0e-897e-80e87ffe92c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26922
73003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2692273003
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.852952863
Short name T114
Test name
Test status
Simulation time 10151904708 ps
CPU time 14.74 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205316 kb
Host smart-ebf73735-168d-4a3e-bade-1579d87741f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85295
2863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.852952863
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3607524238
Short name T1824
Test name
Test status
Simulation time 10143124532 ps
CPU time 14.84 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205236 kb
Host smart-bea3566d-3b6b-4fe2-9dec-0b50799569a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075
24238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3607524238
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1177979134
Short name T1615
Test name
Test status
Simulation time 10100931098 ps
CPU time 13.88 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205184 kb
Host smart-c9ff0fcb-a06c-415a-8f60-a5984d74560b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11779
79134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1177979134
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2847796144
Short name T624
Test name
Test status
Simulation time 10181322321 ps
CPU time 13.88 seconds
Started May 26 01:34:37 PM PDT 24
Finished May 26 01:34:52 PM PDT 24
Peak memory 205304 kb
Host smart-25c5bb7a-171b-45e0-abcf-2e7c7daf078a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477
96144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2847796144
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.1953999808
Short name T1832
Test name
Test status
Simulation time 10085589235 ps
CPU time 16.3 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:03 PM PDT 24
Peak memory 205304 kb
Host smart-1223dac0-32ec-47e3-95aa-bb840f260340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19539
99808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.1953999808
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2306061744
Short name T692
Test name
Test status
Simulation time 10057242776 ps
CPU time 14.57 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:56 PM PDT 24
Peak memory 205272 kb
Host smart-797da118-a30d-4c29-b965-14437bc230e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23060
61744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2306061744
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.357167196
Short name T1914
Test name
Test status
Simulation time 10058786126 ps
CPU time 13.47 seconds
Started May 26 01:34:45 PM PDT 24
Finished May 26 01:34:59 PM PDT 24
Peak memory 205216 kb
Host smart-3b70a6fd-7b36-4c31-b458-1c8eb7ca7452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35716
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.357167196
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2767438848
Short name T1028
Test name
Test status
Simulation time 29521416135 ps
CPU time 55.61 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 205320 kb
Host smart-e4046a32-7993-402f-852b-c2c142214026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27674
38848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2767438848
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.307216571
Short name T948
Test name
Test status
Simulation time 10049358864 ps
CPU time 13.33 seconds
Started May 26 01:34:40 PM PDT 24
Finished May 26 01:34:54 PM PDT 24
Peak memory 205236 kb
Host smart-490f99f1-c079-4834-b3b4-d55f88d7fc8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721
6571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.307216571
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3710017171
Short name T1392
Test name
Test status
Simulation time 10065400336 ps
CPU time 14.57 seconds
Started May 26 01:34:38 PM PDT 24
Finished May 26 01:34:53 PM PDT 24
Peak memory 205292 kb
Host smart-1adc9a68-5a05-44f6-88b5-640ad924f852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
17171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3710017171
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.2206214486
Short name T1141
Test name
Test status
Simulation time 10085311023 ps
CPU time 14.36 seconds
Started May 26 01:34:41 PM PDT 24
Finished May 26 01:34:57 PM PDT 24
Peak memory 205340 kb
Host smart-94823f2a-98cb-4173-b1fc-cdb594b44622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22062
14486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.2206214486
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3501666564
Short name T572
Test name
Test status
Simulation time 10045569343 ps
CPU time 15.51 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205232 kb
Host smart-b7c177dc-4a6b-4c00-854c-bef267b5aaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
66564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3501666564
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3791640943
Short name T720
Test name
Test status
Simulation time 10072943961 ps
CPU time 13.93 seconds
Started May 26 01:34:47 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 205260 kb
Host smart-8baaefc7-9f7a-4f5f-87e3-a48497be1370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916
40943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3791640943
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3670333650
Short name T1246
Test name
Test status
Simulation time 10119330789 ps
CPU time 16.82 seconds
Started May 26 01:34:42 PM PDT 24
Finished May 26 01:34:59 PM PDT 24
Peak memory 205440 kb
Host smart-634bed2b-4f3d-4a93-81c8-c0916a8322e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36703
33650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3670333650
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3463386139
Short name T1036
Test name
Test status
Simulation time 10134899610 ps
CPU time 15.16 seconds
Started May 26 01:34:39 PM PDT 24
Finished May 26 01:34:55 PM PDT 24
Peak memory 205460 kb
Host smart-f07262a0-848c-42c2-9af2-cff0ba4d3d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34633
86139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3463386139
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2691865843
Short name T1743
Test name
Test status
Simulation time 10060152749 ps
CPU time 13.35 seconds
Started May 26 01:34:37 PM PDT 24
Finished May 26 01:34:51 PM PDT 24
Peak memory 205308 kb
Host smart-8d2ba435-ee7f-47c2-b61b-a0d99f62ec45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26918
65843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2691865843
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.1697333270
Short name T1525
Test name
Test status
Simulation time 10193987316 ps
CPU time 16.66 seconds
Started May 26 01:35:01 PM PDT 24
Finished May 26 01:35:18 PM PDT 24
Peak memory 205300 kb
Host smart-56b691df-f4ff-4edf-8a0d-8a145cc4b815
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1697333270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.1697333270
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3666305980
Short name T665
Test name
Test status
Simulation time 10101131841 ps
CPU time 14.08 seconds
Started May 26 01:34:57 PM PDT 24
Finished May 26 01:35:12 PM PDT 24
Peak memory 205332 kb
Host smart-9be9f5c4-cd70-493f-8e46-ea2251de0c6e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3666305980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3666305980
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.4001678815
Short name T481
Test name
Test status
Simulation time 10143984375 ps
CPU time 15.92 seconds
Started May 26 01:34:58 PM PDT 24
Finished May 26 01:35:15 PM PDT 24
Peak memory 205256 kb
Host smart-ef8e9d02-ed58-42af-a024-ba0a61d91aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40016
78815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.4001678815
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.335563158
Short name T424
Test name
Test status
Simulation time 13833241621 ps
CPU time 17.69 seconds
Started May 26 01:34:47 PM PDT 24
Finished May 26 01:35:05 PM PDT 24
Peak memory 205356 kb
Host smart-afade79a-40d1-4a19-8af3-308903deb040
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=335563158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.335563158
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1629440978
Short name T1358
Test name
Test status
Simulation time 13282009694 ps
CPU time 17.77 seconds
Started May 26 01:34:49 PM PDT 24
Finished May 26 01:35:07 PM PDT 24
Peak memory 205312 kb
Host smart-672765cc-72a0-403e-9d84-004c68571b80
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1629440978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1629440978
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.79634647
Short name T429
Test name
Test status
Simulation time 13237360331 ps
CPU time 17.18 seconds
Started May 26 01:34:48 PM PDT 24
Finished May 26 01:35:06 PM PDT 24
Peak memory 205292 kb
Host smart-c15da708-ddd4-4799-bfd1-5a2d1d11d46f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=79634647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.79634647
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3725540367
Short name T1458
Test name
Test status
Simulation time 10055047136 ps
CPU time 15 seconds
Started May 26 01:34:50 PM PDT 24
Finished May 26 01:35:05 PM PDT 24
Peak memory 205184 kb
Host smart-9a37a45c-b26f-4294-98bd-cbeac7cb6385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
40367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3725540367
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.226728291
Short name T600
Test name
Test status
Simulation time 10473903437 ps
CPU time 14.62 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 205296 kb
Host smart-0f38bc25-ebb2-4a17-ad0c-6f7a94e4d696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22672
8291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.226728291
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2794883452
Short name T657
Test name
Test status
Simulation time 10057429808 ps
CPU time 17.04 seconds
Started May 26 01:34:48 PM PDT 24
Finished May 26 01:35:06 PM PDT 24
Peak memory 205152 kb
Host smart-84ede5c1-57ee-407f-8adf-aaf8f72eee3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27948
83452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2794883452
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3368907278
Short name T1658
Test name
Test status
Simulation time 10071620556 ps
CPU time 13.33 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 205272 kb
Host smart-d76256e6-ecdc-4553-a86c-f3b256cdf9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33689
07278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3368907278
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.1145557931
Short name T1548
Test name
Test status
Simulation time 10154253849 ps
CPU time 15.14 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:01 PM PDT 24
Peak memory 205288 kb
Host smart-4865ebfe-24f1-4f6a-87fd-d0aba0633614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11455
57931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1145557931
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3040937165
Short name T1566
Test name
Test status
Simulation time 10091794605 ps
CPU time 15.09 seconds
Started May 26 01:34:57 PM PDT 24
Finished May 26 01:35:13 PM PDT 24
Peak memory 205256 kb
Host smart-29ecb4c9-9317-408c-a781-9e57db3d07d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30409
37165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3040937165
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.693458356
Short name T630
Test name
Test status
Simulation time 10086384034 ps
CPU time 16.56 seconds
Started May 26 01:34:54 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 205212 kb
Host smart-e0bfe06b-403a-4f81-924f-99041e8b6184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69345
8356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.693458356
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.78375610
Short name T710
Test name
Test status
Simulation time 10156606527 ps
CPU time 13.9 seconds
Started May 26 01:34:47 PM PDT 24
Finished May 26 01:35:02 PM PDT 24
Peak memory 205268 kb
Host smart-0fe33176-8740-4927-a8ba-62c3e78247a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78375
610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.78375610
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.8310452
Short name T1866
Test name
Test status
Simulation time 10056041630 ps
CPU time 15.55 seconds
Started May 26 01:34:47 PM PDT 24
Finished May 26 01:35:03 PM PDT 24
Peak memory 205276 kb
Host smart-20719562-71ff-4414-a2cd-5d427a0eb19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83104
52 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.8310452
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2959731530
Short name T1340
Test name
Test status
Simulation time 13227235023 ps
CPU time 18.23 seconds
Started May 26 01:34:46 PM PDT 24
Finished May 26 01:35:05 PM PDT 24
Peak memory 205256 kb
Host smart-1ef8c476-e133-4057-9a60-7988d3a8a627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29597
31530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2959731530
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2738232503
Short name T1131
Test name
Test status
Simulation time 10161634078 ps
CPU time 14.73 seconds
Started May 26 01:34:49 PM PDT 24
Finished May 26 01:35:05 PM PDT 24
Peak memory 205280 kb
Host smart-65af0b0a-cbb8-457d-bfa0-2b37172f9a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27382
32503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2738232503
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2668672146
Short name T1882
Test name
Test status
Simulation time 10053511359 ps
CPU time 14.29 seconds
Started May 26 01:34:47 PM PDT 24
Finished May 26 01:35:02 PM PDT 24
Peak memory 205292 kb
Host smart-d440455a-f422-496e-bf8c-26cfa19445a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26686
72146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2668672146
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.736127112
Short name T129
Test name
Test status
Simulation time 10073283938 ps
CPU time 13.97 seconds
Started May 26 01:34:53 PM PDT 24
Finished May 26 01:35:07 PM PDT 24
Peak memory 205232 kb
Host smart-1cb7d8a2-77fa-4598-959b-80f302fc9459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73612
7112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.736127112
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.4064469004
Short name T653
Test name
Test status
Simulation time 10097743500 ps
CPU time 17.67 seconds
Started May 26 01:34:57 PM PDT 24
Finished May 26 01:35:16 PM PDT 24
Peak memory 205488 kb
Host smart-1f45b559-e992-4bba-a56a-531a0171453e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40644
69004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.4064469004
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.537462658
Short name T444
Test name
Test status
Simulation time 10064678230 ps
CPU time 16.78 seconds
Started May 26 01:35:00 PM PDT 24
Finished May 26 01:35:18 PM PDT 24
Peak memory 205328 kb
Host smart-643c019e-66ee-4af5-b663-15a95cb7f53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53746
2658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.537462658
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1658187324
Short name T372
Test name
Test status
Simulation time 10049056120 ps
CPU time 14.84 seconds
Started May 26 01:34:54 PM PDT 24
Finished May 26 01:35:10 PM PDT 24
Peak memory 205332 kb
Host smart-cbd322e0-4d40-4155-ba4d-369afa0a0115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
87324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1658187324
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4133019328
Short name T1577
Test name
Test status
Simulation time 10089334748 ps
CPU time 15.63 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:12 PM PDT 24
Peak memory 205272 kb
Host smart-08f1198b-f22d-42c5-91aa-9a724e794733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41330
19328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4133019328
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.36860162
Short name T1503
Test name
Test status
Simulation time 10057882911 ps
CPU time 15.32 seconds
Started May 26 01:35:01 PM PDT 24
Finished May 26 01:35:17 PM PDT 24
Peak memory 205320 kb
Host smart-554ce911-7fb8-43ce-af09-351916699362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36860
162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.36860162
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3846618077
Short name T695
Test name
Test status
Simulation time 10045141543 ps
CPU time 13.63 seconds
Started May 26 01:34:54 PM PDT 24
Finished May 26 01:35:08 PM PDT 24
Peak memory 205180 kb
Host smart-35ab4a46-a0c1-4ad9-9864-1ac751c8a565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38466
18077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3846618077
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.1729363203
Short name T1902
Test name
Test status
Simulation time 10042519558 ps
CPU time 13.56 seconds
Started May 26 01:34:56 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 205228 kb
Host smart-be79a9b8-6602-4c53-8493-15a30fff8428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17293
63203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.1729363203
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.460230859
Short name T1214
Test name
Test status
Simulation time 22711684195 ps
CPU time 48.5 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205292 kb
Host smart-ee676411-0d49-495b-b6ae-e38f9cad4ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46023
0859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.460230859
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1742284925
Short name T868
Test name
Test status
Simulation time 10062024534 ps
CPU time 13.84 seconds
Started May 26 01:34:56 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 205200 kb
Host smart-e5dbca60-c2d2-4851-b786-8af58701f05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17422
84925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1742284925
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2989878701
Short name T1789
Test name
Test status
Simulation time 10096817754 ps
CPU time 14.08 seconds
Started May 26 01:34:57 PM PDT 24
Finished May 26 01:35:12 PM PDT 24
Peak memory 205296 kb
Host smart-834b7512-a18c-45b6-a2bb-02413df2ac3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29898
78701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2989878701
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.1147620931
Short name T224
Test name
Test status
Simulation time 10088819693 ps
CPU time 13.32 seconds
Started May 26 01:34:56 PM PDT 24
Finished May 26 01:35:10 PM PDT 24
Peak memory 205244 kb
Host smart-ad15c40a-b325-420c-9c1f-2abcab394466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11476
20931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.1147620931
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.28834985
Short name T1210
Test name
Test status
Simulation time 10095181970 ps
CPU time 15.09 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 205240 kb
Host smart-01b91522-6cb2-4534-baad-de2a94d3c4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28834
985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.28834985
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1221143548
Short name T1883
Test name
Test status
Simulation time 10046964236 ps
CPU time 14.98 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 205308 kb
Host smart-1ca4982b-dd8a-475c-b1fc-069e4a71f908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12211
43548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1221143548
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3337531182
Short name T914
Test name
Test status
Simulation time 10047723622 ps
CPU time 15.58 seconds
Started May 26 01:34:54 PM PDT 24
Finished May 26 01:35:10 PM PDT 24
Peak memory 205296 kb
Host smart-4b9cb5e3-2653-4bbd-93a9-fb20e24e7feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375
31182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3337531182
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.74980971
Short name T146
Test name
Test status
Simulation time 10126783317 ps
CPU time 14.26 seconds
Started May 26 01:34:49 PM PDT 24
Finished May 26 01:35:03 PM PDT 24
Peak memory 205280 kb
Host smart-1a1341e8-63e0-4ed7-bb11-e99f2279f183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74980
971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.74980971
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2085870857
Short name T1470
Test name
Test status
Simulation time 10073887563 ps
CPU time 15.04 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:11 PM PDT 24
Peak memory 205300 kb
Host smart-8afe9821-8dcf-4831-b6f7-65ef0872ee3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
70857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2085870857
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1505947944
Short name T1282
Test name
Test status
Simulation time 10052918982 ps
CPU time 15.37 seconds
Started May 26 01:34:53 PM PDT 24
Finished May 26 01:35:09 PM PDT 24
Peak memory 205316 kb
Host smart-88b1b7d0-93f8-411d-bbf6-c5e636b0be03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
47944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1505947944
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.1488958859
Short name T1579
Test name
Test status
Simulation time 10148055367 ps
CPU time 14.07 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205208 kb
Host smart-83037989-c5d8-441c-97c1-6a0eaf203d07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1488958859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.1488958859
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.695524809
Short name T249
Test name
Test status
Simulation time 10063088412 ps
CPU time 15.91 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:21 PM PDT 24
Peak memory 205136 kb
Host smart-3355bfb1-25e7-47f7-a1d3-df73750181ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=695524809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.695524809
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.3348955811
Short name T352
Test name
Test status
Simulation time 10092912284 ps
CPU time 14.63 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:21 PM PDT 24
Peak memory 205256 kb
Host smart-83792e4f-dbd9-4413-843b-c919cf03c479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
55811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.3348955811
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1188981463
Short name T1416
Test name
Test status
Simulation time 13511639791 ps
CPU time 16.6 seconds
Started May 26 01:34:57 PM PDT 24
Finished May 26 01:35:15 PM PDT 24
Peak memory 205272 kb
Host smart-2a3797cd-0b28-4109-8875-536e62fe7166
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1188981463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.1188981463
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3886401664
Short name T675
Test name
Test status
Simulation time 13250342293 ps
CPU time 17.23 seconds
Started May 26 01:34:56 PM PDT 24
Finished May 26 01:35:15 PM PDT 24
Peak memory 205304 kb
Host smart-b4cd8668-c751-4474-8afc-5167700b95e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3886401664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3886401664
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2701936353
Short name T611
Test name
Test status
Simulation time 10056102341 ps
CPU time 14.76 seconds
Started May 26 01:34:56 PM PDT 24
Finished May 26 01:35:12 PM PDT 24
Peak memory 205228 kb
Host smart-657c304c-ab88-4f63-902d-4d37c893d6ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019
36353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2701936353
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1638007655
Short name T181
Test name
Test status
Simulation time 10288629423 ps
CPU time 14.23 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205308 kb
Host smart-6e924042-5466-4726-ab60-9c66a69cf6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
07655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1638007655
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.4126287017
Short name T647
Test name
Test status
Simulation time 10059963121 ps
CPU time 13.08 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205260 kb
Host smart-712040f8-5e65-41d4-9f00-13f61f403398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41262
87017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.4126287017
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2208501451
Short name T1879
Test name
Test status
Simulation time 10066500484 ps
CPU time 12.8 seconds
Started May 26 01:35:06 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205292 kb
Host smart-4690a979-560b-4bb7-9030-c8fe5c8f2316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22085
01451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2208501451
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2397299710
Short name T790
Test name
Test status
Simulation time 10750380879 ps
CPU time 15.4 seconds
Started May 26 01:35:02 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205240 kb
Host smart-20fa2001-b93f-4176-827a-0760b168c787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23972
99710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2397299710
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2848504821
Short name T553
Test name
Test status
Simulation time 10216111055 ps
CPU time 14.82 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205248 kb
Host smart-0c66e866-5481-4651-8b5e-a4252bd6356e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
04821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2848504821
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.884872381
Short name T683
Test name
Test status
Simulation time 10144200837 ps
CPU time 15.13 seconds
Started May 26 01:35:04 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205460 kb
Host smart-80c6ea7c-6578-4e16-af0c-f6f49797df7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88487
2381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.884872381
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.330400138
Short name T1253
Test name
Test status
Simulation time 10069185160 ps
CPU time 13.31 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:18 PM PDT 24
Peak memory 205264 kb
Host smart-b58e0dd2-7895-49c4-a7dc-406dfb31ff8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.330400138
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.4130344787
Short name T1717
Test name
Test status
Simulation time 10128045550 ps
CPU time 16.24 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:23 PM PDT 24
Peak memory 205304 kb
Host smart-b30d15c0-55f6-43bb-a73c-bd23f7900164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41303
44787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4130344787
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.500691654
Short name T859
Test name
Test status
Simulation time 10101638502 ps
CPU time 13.43 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205276 kb
Host smart-01b840d1-1009-4997-a1d4-7f1d6a36783d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50069
1654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.500691654
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.2174348953
Short name T1454
Test name
Test status
Simulation time 13217491522 ps
CPU time 17.79 seconds
Started May 26 01:35:02 PM PDT 24
Finished May 26 01:35:21 PM PDT 24
Peak memory 205232 kb
Host smart-3056db7f-c4d8-4a55-b8ef-eb218672676f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
48953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2174348953
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2092015302
Short name T602
Test name
Test status
Simulation time 10092337771 ps
CPU time 14.45 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205304 kb
Host smart-4bad481a-9077-403c-b701-b0f15eaa129b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
15302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2092015302
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.605617643
Short name T1915
Test name
Test status
Simulation time 10070083348 ps
CPU time 15.43 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205264 kb
Host smart-60c4fe01-c27e-43bd-9873-b1864d64b19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60561
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.605617643
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1069396206
Short name T102
Test name
Test status
Simulation time 10135338015 ps
CPU time 14.59 seconds
Started May 26 01:35:02 PM PDT 24
Finished May 26 01:35:17 PM PDT 24
Peak memory 205280 kb
Host smart-49e035ed-614b-4ab8-95a2-0b22552bba43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10693
96206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1069396206
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2302680879
Short name T1072
Test name
Test status
Simulation time 10113439022 ps
CPU time 16.02 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:22 PM PDT 24
Peak memory 205300 kb
Host smart-e06a38f4-13a6-4bde-a22b-ec4996628d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23026
80879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2302680879
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3915944965
Short name T1325
Test name
Test status
Simulation time 10077816643 ps
CPU time 14.45 seconds
Started May 26 01:35:06 PM PDT 24
Finished May 26 01:35:21 PM PDT 24
Peak memory 205324 kb
Host smart-4efa2c7f-712d-4ee4-859a-4bc869e7a2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39159
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3915944965
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1224288781
Short name T591
Test name
Test status
Simulation time 10116613646 ps
CPU time 14.96 seconds
Started May 26 01:35:04 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205332 kb
Host smart-bce3fb9a-00f0-4e9f-96db-01939bef68f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12242
88781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1224288781
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.2465215610
Short name T1339
Test name
Test status
Simulation time 10065988000 ps
CPU time 14.56 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205340 kb
Host smart-ab91c8ae-b205-49f9-b2c5-1708098658df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652
15610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.2465215610
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.4026179985
Short name T247
Test name
Test status
Simulation time 10083727506 ps
CPU time 13.11 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:17 PM PDT 24
Peak memory 205304 kb
Host smart-fca9fa29-0dd7-4f93-9b8e-e017e24ac08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40261
79985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.4026179985
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2246414187
Short name T1635
Test name
Test status
Simulation time 10039251577 ps
CPU time 15.77 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:22 PM PDT 24
Peak memory 205200 kb
Host smart-a86f50c6-f403-4f34-8c77-e1434f6b29eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22464
14187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2246414187
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2732839088
Short name T260
Test name
Test status
Simulation time 23516759499 ps
CPU time 42.85 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:47 PM PDT 24
Peak memory 205364 kb
Host smart-b31041af-4643-45c2-ae0f-b6d8da665818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27328
39088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2732839088
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.4007711944
Short name T1139
Test name
Test status
Simulation time 10069895980 ps
CPU time 14.38 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:21 PM PDT 24
Peak memory 205304 kb
Host smart-327b5f27-3f4f-4737-a308-da63706d67ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
11944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.4007711944
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1131660234
Short name T1459
Test name
Test status
Simulation time 10083856509 ps
CPU time 14.01 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205244 kb
Host smart-cd93b2b7-be26-400c-a442-31246069ed6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11316
60234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1131660234
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1349265600
Short name T824
Test name
Test status
Simulation time 10084293646 ps
CPU time 15.74 seconds
Started May 26 01:35:06 PM PDT 24
Finished May 26 01:35:22 PM PDT 24
Peak memory 205312 kb
Host smart-22a879f8-8be0-45d8-98da-d10a70b9c2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13492
65600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1349265600
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1026030265
Short name T57
Test name
Test status
Simulation time 10041224243 ps
CPU time 18.66 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:23 PM PDT 24
Peak memory 205256 kb
Host smart-d67038aa-70e7-47c9-b5b2-537277a6f20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260
30265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1026030265
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3817805894
Short name T155
Test name
Test status
Simulation time 10072158293 ps
CPU time 14.79 seconds
Started May 26 01:35:04 PM PDT 24
Finished May 26 01:35:19 PM PDT 24
Peak memory 205452 kb
Host smart-2e418fd0-f285-4b6e-bf99-f9f02c3655ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38178
05894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3817805894
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3893000814
Short name T1851
Test name
Test status
Simulation time 10059326675 ps
CPU time 13.92 seconds
Started May 26 01:35:03 PM PDT 24
Finished May 26 01:35:18 PM PDT 24
Peak memory 205224 kb
Host smart-60820202-2c0a-4f92-a802-0a4aac268371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38930
00814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3893000814
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2408315745
Short name T716
Test name
Test status
Simulation time 10121017092 ps
CPU time 16.03 seconds
Started May 26 01:34:55 PM PDT 24
Finished May 26 01:35:13 PM PDT 24
Peak memory 205188 kb
Host smart-ad563fec-bab7-49e3-87e7-cd4c5fe20abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
15745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2408315745
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3038424469
Short name T1037
Test name
Test status
Simulation time 10101769334 ps
CPU time 15.08 seconds
Started May 26 01:35:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205012 kb
Host smart-103acde9-c668-4e97-9d38-9215cfc99fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30384
24469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3038424469
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.3133975661
Short name T987
Test name
Test status
Simulation time 10089246525 ps
CPU time 12.8 seconds
Started May 26 01:35:06 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 205348 kb
Host smart-86267f34-7119-47c0-86c8-bc00bc91a04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31339
75661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.3133975661
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.2870925331
Short name T730
Test name
Test status
Simulation time 10133099582 ps
CPU time 13.63 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 205296 kb
Host smart-f53461a3-80ed-4cb2-88db-9dafd2fdb2e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2870925331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.2870925331
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.89995180
Short name T1688
Test name
Test status
Simulation time 10051507579 ps
CPU time 15.94 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:38 PM PDT 24
Peak memory 205272 kb
Host smart-28e85d05-d51c-44f0-8e97-53284afbf9ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=89995180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.89995180
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.1917190266
Short name T932
Test name
Test status
Simulation time 10080658241 ps
CPU time 14.61 seconds
Started May 26 01:35:11 PM PDT 24
Finished May 26 01:35:27 PM PDT 24
Peak memory 205148 kb
Host smart-10b6f97d-be71-4716-a2a5-9a8d25f84a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171
90266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.1917190266
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.322484344
Short name T664
Test name
Test status
Simulation time 13513181055 ps
CPU time 21.31 seconds
Started May 26 01:35:11 PM PDT 24
Finished May 26 01:35:34 PM PDT 24
Peak memory 205260 kb
Host smart-660ef36e-ae5c-497a-a978-41d95b87a51c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=322484344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.322484344
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1036503567
Short name T1056
Test name
Test status
Simulation time 13262366655 ps
CPU time 18.35 seconds
Started May 26 01:35:11 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205304 kb
Host smart-218bb117-9dec-4f38-bc87-21077f0f8da5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1036503567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1036503567
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2409351949
Short name T482
Test name
Test status
Simulation time 13243124765 ps
CPU time 18.32 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:32 PM PDT 24
Peak memory 205304 kb
Host smart-262ccfe0-4d1e-4667-94a4-b1815fa8a4f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2409351949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2409351949
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1954118858
Short name T1462
Test name
Test status
Simulation time 10058698399 ps
CPU time 15.14 seconds
Started May 26 01:35:12 PM PDT 24
Finished May 26 01:35:28 PM PDT 24
Peak memory 205280 kb
Host smart-4dfbeb66-c338-4bf9-b733-5b1a3ab08485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19541
18858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1954118858
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2074046150
Short name T1479
Test name
Test status
Simulation time 10038976087 ps
CPU time 13.74 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:28 PM PDT 24
Peak memory 205304 kb
Host smart-877ded54-af9e-4175-bb39-b3b9d2003930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20740
46150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2074046150
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.222001775
Short name T1619
Test name
Test status
Simulation time 10745434773 ps
CPU time 14.62 seconds
Started May 26 01:35:16 PM PDT 24
Finished May 26 01:35:31 PM PDT 24
Peak memory 205272 kb
Host smart-cec932c2-a771-4012-9205-0824b2ba32d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22200
1775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.222001775
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.4004938783
Short name T682
Test name
Test status
Simulation time 10049920525 ps
CPU time 13.41 seconds
Started May 26 01:35:12 PM PDT 24
Finished May 26 01:35:26 PM PDT 24
Peak memory 205228 kb
Host smart-af9fe4e3-5733-4237-9eaf-f77065ddf582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40049
38783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.4004938783
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2714680024
Short name T1321
Test name
Test status
Simulation time 10058181173 ps
CPU time 14.14 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205224 kb
Host smart-ca70d027-7e61-4d61-93f4-973392245d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27146
80024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2714680024
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1345838613
Short name T1086
Test name
Test status
Simulation time 10112387019 ps
CPU time 15.02 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205256 kb
Host smart-ac6544f9-68da-497d-9104-9c21b6bbc4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13458
38613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1345838613
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2610205645
Short name T71
Test name
Test status
Simulation time 10111351165 ps
CPU time 15.5 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:29 PM PDT 24
Peak memory 205308 kb
Host smart-cb609f54-c7fd-45ad-aefe-08bf4f1d9561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26102
05645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2610205645
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.733699943
Short name T1750
Test name
Test status
Simulation time 10037126967 ps
CPU time 16.54 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205336 kb
Host smart-a0a3a530-d07d-43d7-aee4-c64648529c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73369
9943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.733699943
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3411612804
Short name T671
Test name
Test status
Simulation time 10103029538 ps
CPU time 14.14 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:29 PM PDT 24
Peak memory 205228 kb
Host smart-96386a91-c844-4760-9ded-235279422a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34116
12804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3411612804
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.46123755
Short name T835
Test name
Test status
Simulation time 10096981690 ps
CPU time 14.9 seconds
Started May 26 01:35:17 PM PDT 24
Finished May 26 01:35:32 PM PDT 24
Peak memory 205252 kb
Host smart-287fe46a-81e1-49d0-9603-1d236ccbb1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46123
755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.46123755
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.286466160
Short name T567
Test name
Test status
Simulation time 13194533408 ps
CPU time 17.17 seconds
Started May 26 01:35:14 PM PDT 24
Finished May 26 01:35:32 PM PDT 24
Peak memory 205228 kb
Host smart-8a3ef3e0-2d9a-4a86-9a31-0fa518efcd57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
6160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.286466160
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4038503288
Short name T1303
Test name
Test status
Simulation time 10083835039 ps
CPU time 14.25 seconds
Started May 26 01:35:17 PM PDT 24
Finished May 26 01:35:31 PM PDT 24
Peak memory 205288 kb
Host smart-65d33a1c-8adb-4586-86f3-81fe4c442ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40385
03288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4038503288
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1218508748
Short name T668
Test name
Test status
Simulation time 10076499764 ps
CPU time 13.39 seconds
Started May 26 01:35:16 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205256 kb
Host smart-d8ecfbad-54e8-405d-bd88-99c981f0fa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185
08748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1218508748
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.261812744
Short name T1385
Test name
Test status
Simulation time 10117036158 ps
CPU time 14.02 seconds
Started May 26 01:35:16 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205080 kb
Host smart-6e70177e-a373-40ab-bf08-96e7396a6a83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26181
2744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.261812744
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1081072326
Short name T1160
Test name
Test status
Simulation time 10139080364 ps
CPU time 15.1 seconds
Started May 26 01:35:11 PM PDT 24
Finished May 26 01:35:27 PM PDT 24
Peak memory 205300 kb
Host smart-391f19b4-6f04-4ea9-89fd-adebc121ee2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
72326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1081072326
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2276933883
Short name T375
Test name
Test status
Simulation time 10084252874 ps
CPU time 14.66 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:31 PM PDT 24
Peak memory 205204 kb
Host smart-c7a7b487-daf4-45bf-a49d-89aa2f9f9ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22769
33883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2276933883
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3431181353
Short name T1735
Test name
Test status
Simulation time 10060015879 ps
CPU time 14.77 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:28 PM PDT 24
Peak memory 205488 kb
Host smart-b1117692-520c-4d68-b994-dab9d3ff6542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34311
81353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3431181353
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.853343338
Short name T1710
Test name
Test status
Simulation time 10060542345 ps
CPU time 13.91 seconds
Started May 26 01:35:14 PM PDT 24
Finished May 26 01:35:28 PM PDT 24
Peak memory 205268 kb
Host smart-c66d1f4e-9637-4394-b664-de2497299371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85334
3338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.853343338
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.203984711
Short name T1081
Test name
Test status
Simulation time 10055829015 ps
CPU time 15.26 seconds
Started May 26 01:35:11 PM PDT 24
Finished May 26 01:35:28 PM PDT 24
Peak memory 205272 kb
Host smart-c3ab0c4a-1473-488f-95bc-23279a63d26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20398
4711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.203984711
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.4099748774
Short name T1715
Test name
Test status
Simulation time 10062970666 ps
CPU time 14.51 seconds
Started May 26 01:35:14 PM PDT 24
Finished May 26 01:35:29 PM PDT 24
Peak memory 205236 kb
Host smart-d51a9f22-07e4-4b14-9dbc-b80958fd56bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40997
48774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.4099748774
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1590487488
Short name T1097
Test name
Test status
Simulation time 10034980644 ps
CPU time 17.77 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:34 PM PDT 24
Peak memory 205304 kb
Host smart-e58eac0f-c609-4247-a6fe-ddc4064cf248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15904
87488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1590487488
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3325626022
Short name T90
Test name
Test status
Simulation time 32181707545 ps
CPU time 65.49 seconds
Started May 26 01:35:16 PM PDT 24
Finished May 26 01:36:22 PM PDT 24
Peak memory 205068 kb
Host smart-363fc2a6-80ac-45cd-997c-e11c2df3f3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33256
26022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3325626022
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2832168857
Short name T1401
Test name
Test status
Simulation time 10079344181 ps
CPU time 14.3 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205196 kb
Host smart-5d1ce61d-2ea8-44dd-b232-a3dc1bd91d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28321
68857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2832168857
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1314640911
Short name T1406
Test name
Test status
Simulation time 10071998018 ps
CPU time 13.55 seconds
Started May 26 01:35:16 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205228 kb
Host smart-f2df9a4a-8ff3-4694-9368-e5471a1af555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146
40911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1314640911
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1645097898
Short name T968
Test name
Test status
Simulation time 10094928331 ps
CPU time 15.08 seconds
Started May 26 01:35:16 PM PDT 24
Finished May 26 01:35:32 PM PDT 24
Peak memory 205260 kb
Host smart-bdc347cc-f107-4377-b57c-3e98e4240e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16450
97898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1645097898
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.4130950883
Short name T1582
Test name
Test status
Simulation time 10056337583 ps
CPU time 12.99 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:27 PM PDT 24
Peak memory 205284 kb
Host smart-a818c081-8f70-42a5-b322-83db1e0d5f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41309
50883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.4130950883
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.80509590
Short name T140
Test name
Test status
Simulation time 10068097351 ps
CPU time 14.09 seconds
Started May 26 01:35:14 PM PDT 24
Finished May 26 01:35:29 PM PDT 24
Peak memory 205264 kb
Host smart-f2545c46-539d-4797-b808-0ab7682a9860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80509
590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.80509590
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3177286236
Short name T689
Test name
Test status
Simulation time 10056563279 ps
CPU time 14.05 seconds
Started May 26 01:35:11 PM PDT 24
Finished May 26 01:35:26 PM PDT 24
Peak memory 205256 kb
Host smart-f12d2361-403e-4f1d-b3a8-518363d09451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31772
86236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3177286236
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1818742828
Short name T1669
Test name
Test status
Simulation time 10160185117 ps
CPU time 14.55 seconds
Started May 26 01:35:14 PM PDT 24
Finished May 26 01:35:29 PM PDT 24
Peak memory 205312 kb
Host smart-26fb0cff-73b4-46a3-9995-97fbcd32973b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18187
42828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1818742828
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1378515114
Short name T465
Test name
Test status
Simulation time 10085947112 ps
CPU time 14.46 seconds
Started May 26 01:35:15 PM PDT 24
Finished May 26 01:35:30 PM PDT 24
Peak memory 205340 kb
Host smart-6e5b9e39-6c7b-4c36-81cf-42f4dfa111e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13785
15114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1378515114
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3892661731
Short name T622
Test name
Test status
Simulation time 10070012559 ps
CPU time 13.45 seconds
Started May 26 01:35:13 PM PDT 24
Finished May 26 01:35:26 PM PDT 24
Peak memory 205236 kb
Host smart-80a56177-17df-467a-a90d-ecbee6b1ca23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38926
61731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3892661731
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.601912571
Short name T1337
Test name
Test status
Simulation time 10144721502 ps
CPU time 15.29 seconds
Started May 26 01:35:31 PM PDT 24
Finished May 26 01:35:47 PM PDT 24
Peak memory 205496 kb
Host smart-2a1e5cd2-1ce0-4838-90e2-098e057261ac
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=601912571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.601912571
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.684809384
Short name T1089
Test name
Test status
Simulation time 10121783748 ps
CPU time 13.66 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205284 kb
Host smart-67b2df0b-4415-4ba5-b241-dc396cc50eab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=684809384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.684809384
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.3494941002
Short name T463
Test name
Test status
Simulation time 10118270691 ps
CPU time 13.33 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:43 PM PDT 24
Peak memory 205300 kb
Host smart-cda89a14-623d-4703-82b7-e38c1e18263c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34949
41002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.3494941002
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1312952737
Short name T1310
Test name
Test status
Simulation time 14329555365 ps
CPU time 19.86 seconds
Started May 26 01:35:20 PM PDT 24
Finished May 26 01:35:41 PM PDT 24
Peak memory 205364 kb
Host smart-7d55ff60-fe2f-45ec-9067-fd23ee0b24d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1312952737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1312952737
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3362536734
Short name T1893
Test name
Test status
Simulation time 13237167274 ps
CPU time 18.01 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:41 PM PDT 24
Peak memory 205316 kb
Host smart-e0ec524a-16ac-433c-acfe-eec14a86b6dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3362536734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3362536734
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2587077764
Short name T1674
Test name
Test status
Simulation time 13261623932 ps
CPU time 18.51 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:41 PM PDT 24
Peak memory 205312 kb
Host smart-aa2cc95c-a6d8-4595-bf87-381f7e5d7f56
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2587077764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2587077764
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3766059651
Short name T1186
Test name
Test status
Simulation time 10049908615 ps
CPU time 14.74 seconds
Started May 26 01:35:19 PM PDT 24
Finished May 26 01:35:35 PM PDT 24
Peak memory 205276 kb
Host smart-97686966-c7c6-4951-84db-ff597433e418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
59651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3766059651
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3387653559
Short name T1092
Test name
Test status
Simulation time 10066344859 ps
CPU time 13.6 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 205248 kb
Host smart-22b095bc-c874-4cd6-a87e-ed8f79645632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33876
53559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3387653559
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3407543872
Short name T1870
Test name
Test status
Simulation time 11258606101 ps
CPU time 15.17 seconds
Started May 26 01:35:26 PM PDT 24
Finished May 26 01:35:42 PM PDT 24
Peak memory 205336 kb
Host smart-abbfbee3-ead9-4711-aaca-f64772419407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075
43872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3407543872
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1277984863
Short name T489
Test name
Test status
Simulation time 10039710363 ps
CPU time 13.85 seconds
Started May 26 01:35:23 PM PDT 24
Finished May 26 01:35:38 PM PDT 24
Peak memory 205320 kb
Host smart-e76030e4-da1e-4e86-9825-f42f28b28308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12779
84863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1277984863
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2814432781
Short name T1676
Test name
Test status
Simulation time 10069238927 ps
CPU time 14.13 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:37 PM PDT 24
Peak memory 205356 kb
Host smart-30721437-c1d8-4846-b048-64d9a8ed6a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28144
32781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2814432781
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3174012324
Short name T495
Test name
Test status
Simulation time 10773251108 ps
CPU time 17.2 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:39 PM PDT 24
Peak memory 205268 kb
Host smart-150bfc46-c8d7-43fa-aa30-57bc1b458ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31740
12324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3174012324
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.695820199
Short name T854
Test name
Test status
Simulation time 10122693512 ps
CPU time 14.39 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:37 PM PDT 24
Peak memory 204984 kb
Host smart-fd40ac4c-36c9-457d-baf1-5799204d5640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69582
0199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.695820199
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1442401820
Short name T1065
Test name
Test status
Simulation time 10153952639 ps
CPU time 14.28 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:44 PM PDT 24
Peak memory 205216 kb
Host smart-b3aaa36f-fcfd-405d-a15f-2643b8587f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
01820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1442401820
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3412503674
Short name T496
Test name
Test status
Simulation time 10086993859 ps
CPU time 13.38 seconds
Started May 26 01:35:26 PM PDT 24
Finished May 26 01:35:40 PM PDT 24
Peak memory 205312 kb
Host smart-90689ef0-e649-4bdb-b45b-8e92e0549980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
03674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3412503674
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1984081170
Short name T1834
Test name
Test status
Simulation time 10180725505 ps
CPU time 15.32 seconds
Started May 26 01:35:20 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 205184 kb
Host smart-2e3e8ac3-6c08-4ec1-86d4-0a11562baa5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19840
81170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1984081170
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.56460069
Short name T830
Test name
Test status
Simulation time 10127392924 ps
CPU time 13.99 seconds
Started May 26 01:35:20 PM PDT 24
Finished May 26 01:35:35 PM PDT 24
Peak memory 205224 kb
Host smart-ec4bf687-85e6-43eb-916c-3865024e73c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56460
069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.56460069
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2895055480
Short name T1605
Test name
Test status
Simulation time 13176469495 ps
CPU time 16.43 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:39 PM PDT 24
Peak memory 204972 kb
Host smart-852061ca-fa78-4da1-8c6d-6738fe1042d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28950
55480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2895055480
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.4036002485
Short name T1188
Test name
Test status
Simulation time 10092320650 ps
CPU time 14.03 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:37 PM PDT 24
Peak memory 205308 kb
Host smart-d2c2bc11-5c4a-451a-8feb-34d8cd0acb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40360
02485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.4036002485
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3652894088
Short name T1254
Test name
Test status
Simulation time 10107423235 ps
CPU time 18.07 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:41 PM PDT 24
Peak memory 205260 kb
Host smart-6febd884-7287-4f8a-87fe-4c558fcfbe75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528
94088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3652894088
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.829633425
Short name T939
Test name
Test status
Simulation time 10095247842 ps
CPU time 16.22 seconds
Started May 26 01:35:23 PM PDT 24
Finished May 26 01:35:40 PM PDT 24
Peak memory 205304 kb
Host smart-c3cb0f07-7644-4187-afae-989d7eadef10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82963
3425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.829633425
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1817562623
Short name T1794
Test name
Test status
Simulation time 10136726106 ps
CPU time 18.34 seconds
Started May 26 01:35:20 PM PDT 24
Finished May 26 01:35:39 PM PDT 24
Peak memory 205288 kb
Host smart-c8b66bcf-baf9-4b19-8023-0d0057bfe14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
62623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1817562623
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3644956692
Short name T737
Test name
Test status
Simulation time 10067548283 ps
CPU time 13.85 seconds
Started May 26 01:35:20 PM PDT 24
Finished May 26 01:35:34 PM PDT 24
Peak memory 205324 kb
Host smart-b2e8024e-fc0f-4692-bbf7-e55b3354344b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
56692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3644956692
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3166961653
Short name T1512
Test name
Test status
Simulation time 10108517661 ps
CPU time 14.92 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:38 PM PDT 24
Peak memory 205276 kb
Host smart-6bd184e1-5569-48c1-9d27-bf86f1f00b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
61653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3166961653
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.2888371460
Short name T1176
Test name
Test status
Simulation time 10117196725 ps
CPU time 17.04 seconds
Started May 26 01:35:26 PM PDT 24
Finished May 26 01:35:44 PM PDT 24
Peak memory 205272 kb
Host smart-d5e5212f-78b4-4a0c-aaa3-e542ceeac248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28883
71460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.2888371460
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1643698686
Short name T203
Test name
Test status
Simulation time 10064428746 ps
CPU time 13.95 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 205144 kb
Host smart-b34fde24-f5a9-40d9-8a50-feee6172f272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16436
98686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1643698686
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3763488407
Short name T1632
Test name
Test status
Simulation time 10047171493 ps
CPU time 13.52 seconds
Started May 26 01:35:26 PM PDT 24
Finished May 26 01:35:40 PM PDT 24
Peak memory 205288 kb
Host smart-7ff2aed7-3123-4116-96aa-a06364ffc5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37634
88407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3763488407
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3606895361
Short name T50
Test name
Test status
Simulation time 15799164123 ps
CPU time 29.62 seconds
Started May 26 01:35:25 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205356 kb
Host smart-65dbbe17-2630-43ef-a242-41c3e61ec01d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36068
95361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3606895361
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.239332426
Short name T1887
Test name
Test status
Simulation time 10077176672 ps
CPU time 15.31 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:38 PM PDT 24
Peak memory 205132 kb
Host smart-55535fd1-de4d-464e-b6dd-20e8b35af10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23933
2426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.239332426
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1612780928
Short name T1015
Test name
Test status
Simulation time 10132952729 ps
CPU time 14.27 seconds
Started May 26 01:35:22 PM PDT 24
Finished May 26 01:35:37 PM PDT 24
Peak memory 205284 kb
Host smart-afd7f9dd-406e-4551-b346-00df87b2f6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16127
80928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1612780928
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.68849406
Short name T746
Test name
Test status
Simulation time 10064494042 ps
CPU time 14.24 seconds
Started May 26 01:35:24 PM PDT 24
Finished May 26 01:35:39 PM PDT 24
Peak memory 205208 kb
Host smart-3a78208f-3308-48a0-ac3c-713c3495876f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68849
406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.68849406
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1314127492
Short name T1215
Test name
Test status
Simulation time 10040086120 ps
CPU time 16.16 seconds
Started May 26 01:35:23 PM PDT 24
Finished May 26 01:35:40 PM PDT 24
Peak memory 205328 kb
Host smart-eb85ee24-497d-4b03-9a39-4659d0419eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13141
27492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1314127492
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1307140486
Short name T787
Test name
Test status
Simulation time 10075234652 ps
CPU time 14.26 seconds
Started May 26 01:35:26 PM PDT 24
Finished May 26 01:35:41 PM PDT 24
Peak memory 205300 kb
Host smart-70af0eb4-1067-4dd3-9018-65cd95ee88fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13071
40486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1307140486
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2041971717
Short name T1634
Test name
Test status
Simulation time 10090129687 ps
CPU time 13.89 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:36 PM PDT 24
Peak memory 205244 kb
Host smart-0c74ce3d-43d2-42a6-ae06-2c0393e59fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
71717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2041971717
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.533839449
Short name T782
Test name
Test status
Simulation time 10088146151 ps
CPU time 13.05 seconds
Started May 26 01:35:24 PM PDT 24
Finished May 26 01:35:38 PM PDT 24
Peak memory 205276 kb
Host smart-ef169074-ebe1-429b-9a20-25d208efb711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53383
9449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.533839449
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3046882315
Short name T1781
Test name
Test status
Simulation time 10065004969 ps
CPU time 12.97 seconds
Started May 26 01:35:21 PM PDT 24
Finished May 26 01:35:35 PM PDT 24
Peak memory 205276 kb
Host smart-d37c2a56-5f1c-4266-be60-70fc6217ee15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30468
82315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3046882315
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.3730822502
Short name T784
Test name
Test status
Simulation time 10140931114 ps
CPU time 13.35 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:53 PM PDT 24
Peak memory 205276 kb
Host smart-410d0d67-c52d-4700-86f0-0efe29392a18
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3730822502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.3730822502
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2049652835
Short name T1659
Test name
Test status
Simulation time 10099667522 ps
CPU time 14.43 seconds
Started May 26 01:35:41 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205220 kb
Host smart-1bfcd3a4-434e-4808-ac36-b23a9dd8d975
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2049652835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2049652835
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.3423653665
Short name T913
Test name
Test status
Simulation time 10127439471 ps
CPU time 13.85 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:52 PM PDT 24
Peak memory 205148 kb
Host smart-0e0061bb-03f7-42ac-a341-48e0900cfebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34236
53665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.3423653665
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4049316159
Short name T1731
Test name
Test status
Simulation time 13998766823 ps
CPU time 21.29 seconds
Started May 26 01:35:34 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205328 kb
Host smart-51aa8e3a-0188-4580-8c22-5e6dab3b3ae4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4049316159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.4049316159
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1951007543
Short name T1179
Test name
Test status
Simulation time 13269328208 ps
CPU time 18.03 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:48 PM PDT 24
Peak memory 205276 kb
Host smart-8d94ee17-5dbf-4326-8246-7caae2b9994e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1951007543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1951007543
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1153190894
Short name T1760
Test name
Test status
Simulation time 13280711367 ps
CPU time 18.65 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:50 PM PDT 24
Peak memory 205308 kb
Host smart-ce2a5b4a-366a-4df3-92de-f39abfe430ee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1153190894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1153190894
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3700825801
Short name T385
Test name
Test status
Simulation time 10063294137 ps
CPU time 13.85 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205228 kb
Host smart-c32bb9fc-9c35-45e7-96ff-8b82c45b897b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37008
25801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3700825801
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.214759759
Short name T197
Test name
Test status
Simulation time 11065648114 ps
CPU time 17.89 seconds
Started May 26 01:35:31 PM PDT 24
Finished May 26 01:35:50 PM PDT 24
Peak memory 205316 kb
Host smart-7b48edf5-bae6-4e3f-a7dc-de0979eed82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
9759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.214759759
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3263930512
Short name T592
Test name
Test status
Simulation time 10065360608 ps
CPU time 16.31 seconds
Started May 26 01:35:28 PM PDT 24
Finished May 26 01:35:44 PM PDT 24
Peak memory 205304 kb
Host smart-b838c88b-8111-4829-939b-64f77e3ac8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32639
30512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3263930512
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2542246826
Short name T415
Test name
Test status
Simulation time 10089018204 ps
CPU time 14.14 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:44 PM PDT 24
Peak memory 205284 kb
Host smart-c1f480db-3492-4dc6-acbe-f061375535c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25422
46826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2542246826
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2356062479
Short name T956
Test name
Test status
Simulation time 10830645928 ps
CPU time 16.59 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:48 PM PDT 24
Peak memory 205236 kb
Host smart-9a207ee3-ede2-4173-b0f0-d153f23b57f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23560
62479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2356062479
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3030999852
Short name T1448
Test name
Test status
Simulation time 10189974694 ps
CPU time 15.83 seconds
Started May 26 01:35:28 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205292 kb
Host smart-3fc69471-5ad0-4ca8-9410-8f6bbefef39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30309
99852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3030999852
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.239760744
Short name T773
Test name
Test status
Simulation time 10107994761 ps
CPU time 13.35 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205224 kb
Host smart-ef5a9c12-d1bd-45e2-9fd4-7b2ea0e8710a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23976
0744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.239760744
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2281973429
Short name T929
Test name
Test status
Simulation time 10077917657 ps
CPU time 17.68 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205264 kb
Host smart-69b3eaf7-e145-43f0-a68a-fbf14126eabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22819
73429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2281973429
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3761630884
Short name T803
Test name
Test status
Simulation time 10141376292 ps
CPU time 14.97 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205312 kb
Host smart-beff1173-45eb-46bf-8b66-d0577c864c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37616
30884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3761630884
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2720564142
Short name T1212
Test name
Test status
Simulation time 10063732459 ps
CPU time 13.46 seconds
Started May 26 01:35:28 PM PDT 24
Finished May 26 01:35:43 PM PDT 24
Peak memory 205308 kb
Host smart-68eae0e6-b342-44e5-b0da-4c5852ced1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27205
64142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2720564142
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2106789514
Short name T411
Test name
Test status
Simulation time 13246391438 ps
CPU time 16.88 seconds
Started May 26 01:35:27 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205300 kb
Host smart-27bd9a46-0fbf-47b3-8125-f075d7a61a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21067
89514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2106789514
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2119730867
Short name T1586
Test name
Test status
Simulation time 10098070601 ps
CPU time 15.68 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:46 PM PDT 24
Peak memory 205268 kb
Host smart-c2581885-8c13-4bde-8d9c-ff9cee8ffe86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21197
30867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2119730867
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.360515045
Short name T818
Test name
Test status
Simulation time 10052309552 ps
CPU time 16.46 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:48 PM PDT 24
Peak memory 205260 kb
Host smart-67cc926d-036a-4bd2-a300-76310f7069b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36051
5045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.360515045
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2999797030
Short name T952
Test name
Test status
Simulation time 10145209430 ps
CPU time 14.89 seconds
Started May 26 01:35:28 PM PDT 24
Finished May 26 01:35:43 PM PDT 24
Peak memory 205252 kb
Host smart-3b37baaf-c53f-47a7-a67b-59729819ad3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29997
97030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2999797030
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3668316462
Short name T901
Test name
Test status
Simulation time 10075152042 ps
CPU time 13.95 seconds
Started May 26 01:35:31 PM PDT 24
Finished May 26 01:35:46 PM PDT 24
Peak memory 205252 kb
Host smart-df63b183-1f76-47b0-bfec-49cac694de8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36683
16462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3668316462
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3398908578
Short name T84
Test name
Test status
Simulation time 10076088989 ps
CPU time 15.12 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205308 kb
Host smart-3b2c63e4-2e05-4ffb-8713-07c245d394fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33989
08578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3398908578
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.3520790161
Short name T354
Test name
Test status
Simulation time 10090245580 ps
CPU time 14.22 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:53 PM PDT 24
Peak memory 205184 kb
Host smart-5866d87e-d85b-427e-b339-41eb77f3da9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35207
90161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.3520790161
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3463785690
Short name T1375
Test name
Test status
Simulation time 10051965305 ps
CPU time 13.36 seconds
Started May 26 01:35:39 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205216 kb
Host smart-b0c2e837-dafa-491d-b586-36a64ea0a02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34637
85690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3463785690
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1145659492
Short name T43
Test name
Test status
Simulation time 10072897102 ps
CPU time 17.02 seconds
Started May 26 01:35:42 PM PDT 24
Finished May 26 01:35:59 PM PDT 24
Peak memory 205428 kb
Host smart-9993b610-10e1-45d5-9edd-e1db1999a092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11456
59492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1145659492
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2512648328
Short name T279
Test name
Test status
Simulation time 23305041642 ps
CPU time 46.26 seconds
Started May 26 01:35:28 PM PDT 24
Finished May 26 01:36:15 PM PDT 24
Peak memory 205344 kb
Host smart-13e6d2de-2079-4512-970f-f9088d942d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25126
48328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2512648328
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3598772517
Short name T475
Test name
Test status
Simulation time 10079811470 ps
CPU time 13.28 seconds
Started May 26 01:35:31 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205328 kb
Host smart-072a5337-dc87-4e5d-8dd1-306e988d009f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35987
72517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3598772517
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3806776969
Short name T648
Test name
Test status
Simulation time 10117048202 ps
CPU time 14.9 seconds
Started May 26 01:35:33 PM PDT 24
Finished May 26 01:35:48 PM PDT 24
Peak memory 205344 kb
Host smart-bdac60a1-c566-47da-a803-9206bccb8c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38067
76969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3806776969
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.1989632989
Short name T42
Test name
Test status
Simulation time 10085583964 ps
CPU time 14.89 seconds
Started May 26 01:35:29 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205308 kb
Host smart-730380c5-66e1-4366-98e4-455cd35dcfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19896
32989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.1989632989
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1914272282
Short name T1493
Test name
Test status
Simulation time 10049611329 ps
CPU time 13.76 seconds
Started May 26 01:35:31 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205244 kb
Host smart-6a32029d-c548-4f6e-84ef-2ef48a59514f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19142
72282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1914272282
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3361248826
Short name T596
Test name
Test status
Simulation time 10119131373 ps
CPU time 14.04 seconds
Started May 26 01:35:39 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205452 kb
Host smart-fb6554c7-fe11-4985-ba28-aefc076cfda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33612
48826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3361248826
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1787886991
Short name T519
Test name
Test status
Simulation time 10055560190 ps
CPU time 16.75 seconds
Started May 26 01:35:31 PM PDT 24
Finished May 26 01:35:48 PM PDT 24
Peak memory 205224 kb
Host smart-f175ce82-1f10-4487-bcb1-ff4607275e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878
86991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1787886991
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1821991607
Short name T1507
Test name
Test status
Simulation time 10092024189 ps
CPU time 14.4 seconds
Started May 26 01:35:30 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205256 kb
Host smart-177fffba-7316-4aa2-b618-36a708569b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18219
91607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1821991607
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1153301999
Short name T371
Test name
Test status
Simulation time 10161533449 ps
CPU time 14.53 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205312 kb
Host smart-bcc35278-7dcb-4997-81e3-a5e85103924e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11533
01999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1153301999
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3809937233
Short name T358
Test name
Test status
Simulation time 10087924031 ps
CPU time 15.67 seconds
Started May 26 01:35:28 PM PDT 24
Finished May 26 01:35:45 PM PDT 24
Peak memory 205352 kb
Host smart-085c3761-31cf-474f-ba0f-a9ab46be245c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38099
37233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3809937233
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.1760021332
Short name T1443
Test name
Test status
Simulation time 10183986655 ps
CPU time 16.7 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:58 PM PDT 24
Peak memory 205308 kb
Host smart-46648157-1a3b-46cc-b920-65f1c08078b2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1760021332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.1760021332
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.1116544279
Short name T1055
Test name
Test status
Simulation time 10085750906 ps
CPU time 15.26 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:57 PM PDT 24
Peak memory 205280 kb
Host smart-b3c17a7d-5aa8-440e-a031-9c6e4cb40d5f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1116544279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.1116544279
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.1788321055
Short name T1333
Test name
Test status
Simulation time 10065843671 ps
CPU time 15.39 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205460 kb
Host smart-6c55fd7b-3287-4748-a721-24ed9aa9483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17883
21055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.1788321055
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2951052814
Short name T828
Test name
Test status
Simulation time 13947863362 ps
CPU time 19.21 seconds
Started May 26 01:35:37 PM PDT 24
Finished May 26 01:35:57 PM PDT 24
Peak memory 205312 kb
Host smart-64f4f355-3b13-4ebf-b6b9-d8c650bd25e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2951052814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2951052814
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3551426607
Short name T1749
Test name
Test status
Simulation time 13222209534 ps
CPU time 18.12 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:57 PM PDT 24
Peak memory 205248 kb
Host smart-6945af4d-8077-4a07-827e-2d63edb0b3e0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3551426607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3551426607
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.4259877577
Short name T1736
Test name
Test status
Simulation time 13242238665 ps
CPU time 20.09 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:36:00 PM PDT 24
Peak memory 205272 kb
Host smart-dccee993-617e-4e09-b2bb-ac9b4ef179c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4259877577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.4259877577
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1347582727
Short name T1484
Test name
Test status
Simulation time 10114574766 ps
CPU time 14.2 seconds
Started May 26 01:35:37 PM PDT 24
Finished May 26 01:35:52 PM PDT 24
Peak memory 205272 kb
Host smart-16b95d16-bde9-4295-9089-e5d68da1908c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13475
82727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1347582727
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1507013002
Short name T1821
Test name
Test status
Simulation time 10096008002 ps
CPU time 13.66 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205300 kb
Host smart-039fd58d-7672-4ccf-abbe-4b1ec0585011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15070
13002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1507013002
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1081416170
Short name T176
Test name
Test status
Simulation time 10864861127 ps
CPU time 16.4 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205284 kb
Host smart-6719e147-8bd7-47cd-a7db-1673427a51c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10814
16170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1081416170
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1492007796
Short name T1755
Test name
Test status
Simulation time 10042377592 ps
CPU time 13.4 seconds
Started May 26 01:35:42 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205280 kb
Host smart-aa93c0e9-a98a-40cf-8e07-845e257f4e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14920
07796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1492007796
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1208622304
Short name T1107
Test name
Test status
Simulation time 10053392680 ps
CPU time 13.8 seconds
Started May 26 01:35:39 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205316 kb
Host smart-d1639ee2-5a84-4e7c-83f8-3f6bccf89178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12086
22304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1208622304
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.214052226
Short name T1556
Test name
Test status
Simulation time 10580286820 ps
CPU time 14.74 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205220 kb
Host smart-6c8ba0d7-171f-41d8-85e0-831b6c473f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405
2226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.214052226
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.4248773365
Short name T1126
Test name
Test status
Simulation time 10192805336 ps
CPU time 17.14 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:59 PM PDT 24
Peak memory 205312 kb
Host smart-b0aec23a-b8de-4e21-892d-4e1c2dff6e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
73365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.4248773365
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1838280112
Short name T772
Test name
Test status
Simulation time 10128265367 ps
CPU time 14.55 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205300 kb
Host smart-ba79e89f-77bc-4266-834f-52b9d8a6fa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18382
80112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1838280112
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1464417582
Short name T670
Test name
Test status
Simulation time 10050929893 ps
CPU time 13.88 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205304 kb
Host smart-48012e26-a1a1-4752-bea9-b1e167595eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14644
17582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1464417582
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.4176565337
Short name T1024
Test name
Test status
Simulation time 10175402380 ps
CPU time 13.07 seconds
Started May 26 01:35:42 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205312 kb
Host smart-0706d480-27bc-4337-8f87-a8950b5171c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41765
65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4176565337
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2522095980
Short name T778
Test name
Test status
Simulation time 10087705947 ps
CPU time 16.56 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205228 kb
Host smart-24d3d3b1-6d50-425a-82c0-81bdb2065bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25220
95980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2522095980
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2151899956
Short name T698
Test name
Test status
Simulation time 13187872783 ps
CPU time 16.06 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:57 PM PDT 24
Peak memory 205256 kb
Host smart-1920d383-867b-400e-888b-ac8b1ee7260d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21518
99956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2151899956
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3898124107
Short name T1216
Test name
Test status
Simulation time 10096852374 ps
CPU time 14.41 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205292 kb
Host smart-26d3ab7a-a517-4271-ab09-1cf05a027db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38981
24107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3898124107
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1446766643
Short name T539
Test name
Test status
Simulation time 10054162864 ps
CPU time 13.51 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205276 kb
Host smart-0dd0d51a-e8a8-4363-8a49-ba0dae414e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14467
66643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1446766643
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3890685087
Short name T123
Test name
Test status
Simulation time 10119431024 ps
CPU time 14.19 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205196 kb
Host smart-b853a5d6-6875-4333-8a88-fca865db8351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
85087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3890685087
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.1420352596
Short name T22
Test name
Test status
Simulation time 10089021684 ps
CPU time 15.12 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205184 kb
Host smart-c66cccc5-1d12-4eb6-b36c-84f627180140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14203
52596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.1420352596
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.870299696
Short name T336
Test name
Test status
Simulation time 10089224875 ps
CPU time 13.35 seconds
Started May 26 01:35:41 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205200 kb
Host smart-ceabbf03-ebae-4caa-965f-efe34e7d6d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87029
9696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.870299696
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2533078078
Short name T1631
Test name
Test status
Simulation time 10091218891 ps
CPU time 17.71 seconds
Started May 26 01:35:41 PM PDT 24
Finished May 26 01:35:59 PM PDT 24
Peak memory 205300 kb
Host smart-1d370986-9c83-4e5d-82c9-47cf77b558cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25330
78078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2533078078
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2230415657
Short name T198
Test name
Test status
Simulation time 10073097963 ps
CPU time 13.85 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:53 PM PDT 24
Peak memory 205212 kb
Host smart-dc5a3d5a-5f5c-49d5-87cd-ca7097102812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304
15657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2230415657
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.486163193
Short name T1841
Test name
Test status
Simulation time 10115410636 ps
CPU time 13.5 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205196 kb
Host smart-18b31302-d57b-45ef-a8e7-f9babf3748be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48616
3193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.486163193
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1547744438
Short name T807
Test name
Test status
Simulation time 10045488569 ps
CPU time 14.43 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205252 kb
Host smart-adc166f8-6bb3-43ff-8b07-91254717535c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
44438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1547744438
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.988909252
Short name T924
Test name
Test status
Simulation time 10036060411 ps
CPU time 17.02 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205280 kb
Host smart-89e661bd-938b-43b2-97e4-d0aae61554ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98890
9252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.988909252
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3555048912
Short name T256
Test name
Test status
Simulation time 17457949050 ps
CPU time 32.07 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:36:13 PM PDT 24
Peak memory 205344 kb
Host smart-acbcbb02-d63c-4481-9c11-776c3fd0be5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
48912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3555048912
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2422998858
Short name T1099
Test name
Test status
Simulation time 10090492421 ps
CPU time 14.58 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205248 kb
Host smart-3393c217-c044-4634-8d65-ea3f6421b831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24229
98858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2422998858
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.45776253
Short name T315
Test name
Test status
Simulation time 10150527346 ps
CPU time 16.46 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205252 kb
Host smart-c94ded09-8eeb-45a3-afc1-401929719be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45776
253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.45776253
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.3321427959
Short name T1534
Test name
Test status
Simulation time 10080232359 ps
CPU time 13.42 seconds
Started May 26 01:35:37 PM PDT 24
Finished May 26 01:35:50 PM PDT 24
Peak memory 205268 kb
Host smart-ba2c542a-38db-4864-81fb-d7cd7b11adfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33214
27959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.3321427959
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.306623256
Short name T422
Test name
Test status
Simulation time 10050481930 ps
CPU time 15.08 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205236 kb
Host smart-719fe252-441d-431f-8306-132d3bf0ecb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30662
3256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.306623256
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1205621855
Short name T29
Test name
Test status
Simulation time 10116687968 ps
CPU time 13.9 seconds
Started May 26 01:35:41 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205276 kb
Host smart-eb383ebb-7692-4516-91aa-3d9eee7e9cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12056
21855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1205621855
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.994185328
Short name T1133
Test name
Test status
Simulation time 10059156635 ps
CPU time 15.54 seconds
Started May 26 01:35:38 PM PDT 24
Finished May 26 01:35:55 PM PDT 24
Peak memory 205256 kb
Host smart-e5874ac5-6db4-464c-9761-0a32f68c960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99418
5328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.994185328
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.131932237
Short name T153
Test name
Test status
Simulation time 10135538412 ps
CPU time 13.03 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:54 PM PDT 24
Peak memory 205340 kb
Host smart-55a4b5c4-0ef3-4bd9-aed2-8a97df172505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13193
2237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.131932237
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.253745389
Short name T837
Test name
Test status
Simulation time 10067275388 ps
CPU time 15.27 seconds
Started May 26 01:35:40 PM PDT 24
Finished May 26 01:35:57 PM PDT 24
Peak memory 205228 kb
Host smart-ed356c43-b8b2-49b3-9d3e-32faff40187e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25374
5389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.253745389
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.666800436
Short name T1427
Test name
Test status
Simulation time 10086450765 ps
CPU time 13.46 seconds
Started May 26 01:35:42 PM PDT 24
Finished May 26 01:35:56 PM PDT 24
Peak memory 205480 kb
Host smart-85980375-077c-4e6d-b887-ab36dcd8c908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66680
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.666800436
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.3280433443
Short name T1892
Test name
Test status
Simulation time 10157745005 ps
CPU time 16.81 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:12 PM PDT 24
Peak memory 205236 kb
Host smart-85b3c717-a1ec-4d35-94df-ac997a23397b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3280433443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.3280433443
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.4215615179
Short name T717
Test name
Test status
Simulation time 10066533167 ps
CPU time 15.86 seconds
Started May 26 01:35:52 PM PDT 24
Finished May 26 01:36:09 PM PDT 24
Peak memory 205280 kb
Host smart-cf28fad9-5e85-41a4-b62f-6830abebf6d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4215615179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.4215615179
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.2470687584
Short name T1266
Test name
Test status
Simulation time 10126159571 ps
CPU time 15.43 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:11 PM PDT 24
Peak memory 205216 kb
Host smart-13252b5a-1a43-4e58-aecb-838295fda3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706
87584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.2470687584
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1242620223
Short name T576
Test name
Test status
Simulation time 13752057652 ps
CPU time 17.24 seconds
Started May 26 01:35:46 PM PDT 24
Finished May 26 01:36:04 PM PDT 24
Peak memory 205300 kb
Host smart-0a2a5b84-2d9c-4a82-aec5-3a52091145c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1242620223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1242620223
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3341767318
Short name T1032
Test name
Test status
Simulation time 13269352896 ps
CPU time 20.9 seconds
Started May 26 01:35:45 PM PDT 24
Finished May 26 01:36:06 PM PDT 24
Peak memory 205368 kb
Host smart-bf300314-aa15-4a9a-8f76-856012552836
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3341767318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3341767318
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2536788864
Short name T1858
Test name
Test status
Simulation time 13425675073 ps
CPU time 20.36 seconds
Started May 26 01:35:48 PM PDT 24
Finished May 26 01:36:09 PM PDT 24
Peak memory 205228 kb
Host smart-b590b9e7-c53f-4b1d-92a3-250d164fc1bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2536788864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2536788864
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.17097878
Short name T1711
Test name
Test status
Simulation time 10060360142 ps
CPU time 13.53 seconds
Started May 26 01:35:45 PM PDT 24
Finished May 26 01:35:59 PM PDT 24
Peak memory 205260 kb
Host smart-6c5d9cf1-dc8a-4cac-a704-a0c971ab02d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17097
878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.17097878
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3879651248
Short name T218
Test name
Test status
Simulation time 11196041616 ps
CPU time 15.73 seconds
Started May 26 01:35:48 PM PDT 24
Finished May 26 01:36:05 PM PDT 24
Peak memory 205172 kb
Host smart-886c4131-3ca1-436d-9213-379c56ef5afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38796
51248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3879651248
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3170247117
Short name T1800
Test name
Test status
Simulation time 10098635994 ps
CPU time 14.19 seconds
Started May 26 01:35:50 PM PDT 24
Finished May 26 01:36:05 PM PDT 24
Peak memory 205260 kb
Host smart-0d0d445f-c545-4fb5-bdec-8832bfceed5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31702
47117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3170247117
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2820833411
Short name T899
Test name
Test status
Simulation time 10068116499 ps
CPU time 15.51 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:03 PM PDT 24
Peak memory 205288 kb
Host smart-f5e3b494-3fc4-49fc-b811-5e7d09ed2bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28208
33411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2820833411
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3803944091
Short name T1183
Test name
Test status
Simulation time 10875720463 ps
CPU time 14.03 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:02 PM PDT 24
Peak memory 205240 kb
Host smart-a3a2317c-a712-490f-9956-c6959d9dad0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38039
44091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3803944091
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1379604020
Short name T383
Test name
Test status
Simulation time 10156759202 ps
CPU time 15.77 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:03 PM PDT 24
Peak memory 205272 kb
Host smart-b6f325a2-ed9a-404b-ace9-30e558e93c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13796
04020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1379604020
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2165868092
Short name T1043
Test name
Test status
Simulation time 10153173425 ps
CPU time 13.62 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:08 PM PDT 24
Peak memory 205248 kb
Host smart-4d4a8455-a97e-421d-8eaa-6f43315e1f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21658
68092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2165868092
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3084958260
Short name T912
Test name
Test status
Simulation time 10053759503 ps
CPU time 14.34 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:09 PM PDT 24
Peak memory 205324 kb
Host smart-57927c9b-25e2-4fab-88b0-4029eeb25aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30849
58260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3084958260
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4096884907
Short name T1373
Test name
Test status
Simulation time 10132519964 ps
CPU time 14.76 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:03 PM PDT 24
Peak memory 205268 kb
Host smart-36f157ce-58a2-4366-bb0e-65d5bc1ea9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968
84907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4096884907
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2984187624
Short name T380
Test name
Test status
Simulation time 10104143417 ps
CPU time 19.04 seconds
Started May 26 01:35:46 PM PDT 24
Finished May 26 01:36:06 PM PDT 24
Peak memory 205256 kb
Host smart-d45643ce-42a6-4bcf-a7f6-56b3a8c74587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29841
87624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2984187624
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2412184265
Short name T711
Test name
Test status
Simulation time 13227558849 ps
CPU time 19.03 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:07 PM PDT 24
Peak memory 205256 kb
Host smart-cb30283f-a5e6-49ad-a7f9-c41e8818d5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121
84265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2412184265
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2035971100
Short name T1087
Test name
Test status
Simulation time 10098859290 ps
CPU time 15.59 seconds
Started May 26 01:35:48 PM PDT 24
Finished May 26 01:36:04 PM PDT 24
Peak memory 205212 kb
Host smart-98890e23-315d-4f54-b416-96ad18aef602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359
71100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2035971100
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3567133179
Short name T453
Test name
Test status
Simulation time 10066182683 ps
CPU time 17.13 seconds
Started May 26 01:35:45 PM PDT 24
Finished May 26 01:36:02 PM PDT 24
Peak memory 205180 kb
Host smart-40b56686-e480-44c4-a148-cb964db1d13d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35671
33179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3567133179
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2892590132
Short name T110
Test name
Test status
Simulation time 10130930130 ps
CPU time 17.69 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:05 PM PDT 24
Peak memory 205328 kb
Host smart-4132fac3-9453-44f8-a76c-7730827be3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28925
90132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2892590132
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3186820745
Short name T1625
Test name
Test status
Simulation time 10090760594 ps
CPU time 14.36 seconds
Started May 26 01:35:50 PM PDT 24
Finished May 26 01:36:05 PM PDT 24
Peak memory 205260 kb
Host smart-0e29ae92-6917-4935-aa7a-868060c14717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868
20745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3186820745
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3675517112
Short name T1150
Test name
Test status
Simulation time 10089566391 ps
CPU time 13.69 seconds
Started May 26 01:35:47 PM PDT 24
Finished May 26 01:36:01 PM PDT 24
Peak memory 205240 kb
Host smart-a90cb308-9a5f-4820-ba50-6ab1624de7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36755
17112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3675517112
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2498187971
Short name T1169
Test name
Test status
Simulation time 10061300987 ps
CPU time 14.08 seconds
Started May 26 01:35:48 PM PDT 24
Finished May 26 01:36:03 PM PDT 24
Peak memory 205324 kb
Host smart-6be4be1b-d056-469b-967a-9940e68f1f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24981
87971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2498187971
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2340933957
Short name T187
Test name
Test status
Simulation time 10058492300 ps
CPU time 14.59 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:09 PM PDT 24
Peak memory 205336 kb
Host smart-22589083-7ccf-4913-ba7e-4bce2aec1b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
33957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2340933957
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.2614047003
Short name T442
Test name
Test status
Simulation time 10063797047 ps
CPU time 13.93 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:10 PM PDT 24
Peak memory 205288 kb
Host smart-c3239a1b-6bf0-45c2-b74b-e1cd9be8e976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26140
47003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.2614047003
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2741702141
Short name T1907
Test name
Test status
Simulation time 10072133222 ps
CPU time 14.28 seconds
Started May 26 01:35:55 PM PDT 24
Finished May 26 01:36:11 PM PDT 24
Peak memory 205468 kb
Host smart-63cfbe2f-0428-472c-873d-6c7bda223ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27417
02141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2741702141
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4280866527
Short name T1884
Test name
Test status
Simulation time 10042530943 ps
CPU time 13.23 seconds
Started May 26 01:35:56 PM PDT 24
Finished May 26 01:36:10 PM PDT 24
Peak memory 205308 kb
Host smart-436da73e-17a0-4b8e-9567-a9f5ce5ff161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
66527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4280866527
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3544911005
Short name T1753
Test name
Test status
Simulation time 19708724917 ps
CPU time 39.52 seconds
Started May 26 01:35:48 PM PDT 24
Finished May 26 01:36:28 PM PDT 24
Peak memory 205248 kb
Host smart-f4775a6f-2143-4189-85de-96bcd20e263d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35449
11005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3544911005
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.2051912740
Short name T405
Test name
Test status
Simulation time 10103398098 ps
CPU time 14.51 seconds
Started May 26 01:35:48 PM PDT 24
Finished May 26 01:36:03 PM PDT 24
Peak memory 205284 kb
Host smart-77429394-5ca3-471b-8f79-f6a91a054e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
12740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2051912740
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3671942295
Short name T844
Test name
Test status
Simulation time 10124135021 ps
CPU time 13.61 seconds
Started May 26 01:35:46 PM PDT 24
Finished May 26 01:36:01 PM PDT 24
Peak memory 205228 kb
Host smart-32e6c0c8-e507-4b1c-8eb4-0b094561358a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36719
42295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3671942295
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2122896349
Short name T574
Test name
Test status
Simulation time 10056505957 ps
CPU time 13.76 seconds
Started May 26 01:35:46 PM PDT 24
Finished May 26 01:36:00 PM PDT 24
Peak memory 205308 kb
Host smart-b7a06ccf-be6d-43c6-96a9-c0afbab25ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21228
96349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2122896349
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.87844736
Short name T942
Test name
Test status
Simulation time 10057634382 ps
CPU time 18.6 seconds
Started May 26 01:35:55 PM PDT 24
Finished May 26 01:36:15 PM PDT 24
Peak memory 205240 kb
Host smart-ce239c00-3f4f-4530-9eb9-75ae5e576815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87844
736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.87844736
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.4034928316
Short name T359
Test name
Test status
Simulation time 10054429591 ps
CPU time 14.6 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:08 PM PDT 24
Peak memory 205308 kb
Host smart-e5dbfd91-218c-4ddd-a85a-6cc9ffa38277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40349
28316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.4034928316
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2819784652
Short name T59
Test name
Test status
Simulation time 10102240196 ps
CPU time 13.57 seconds
Started May 26 01:35:55 PM PDT 24
Finished May 26 01:36:10 PM PDT 24
Peak memory 205152 kb
Host smart-c1f316a5-2a74-4bcf-8476-40479e5fca6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28197
84652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2819784652
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1149950128
Short name T1121
Test name
Test status
Simulation time 10123470988 ps
CPU time 14.97 seconds
Started May 26 01:35:46 PM PDT 24
Finished May 26 01:36:01 PM PDT 24
Peak memory 205284 kb
Host smart-cc4ea491-820a-4da7-a792-e4e7d1b87d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11499
50128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1149950128
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3579564868
Short name T1365
Test name
Test status
Simulation time 10103098479 ps
CPU time 13.41 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:08 PM PDT 24
Peak memory 205224 kb
Host smart-aa071b5e-5941-4d0d-9852-12e2e59b29ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
64868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3579564868
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3206467844
Short name T1423
Test name
Test status
Simulation time 10110960703 ps
CPU time 14.24 seconds
Started May 26 01:35:56 PM PDT 24
Finished May 26 01:36:12 PM PDT 24
Peak memory 205276 kb
Host smart-260c7033-61c2-4f78-afb3-f14c4847221c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
67844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3206467844
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.110536961
Short name T986
Test name
Test status
Simulation time 10165582379 ps
CPU time 13.98 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:21 PM PDT 24
Peak memory 205300 kb
Host smart-81017a3b-99bb-4f88-9da9-49d085536c51
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=110536961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.110536961
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.2941657709
Short name T1638
Test name
Test status
Simulation time 10108903989 ps
CPU time 14.66 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:22 PM PDT 24
Peak memory 205196 kb
Host smart-4d6538c8-a6b1-4621-871a-e8746ca7df7d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2941657709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.2941657709
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.2665360604
Short name T316
Test name
Test status
Simulation time 10111347223 ps
CPU time 15.18 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:25 PM PDT 24
Peak memory 205236 kb
Host smart-151642d8-d45e-4555-b05b-346cb4fd23bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26653
60604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.2665360604
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.453526943
Short name T1536
Test name
Test status
Simulation time 13732972057 ps
CPU time 18.17 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:09 PM PDT 24
Peak memory 205356 kb
Host smart-117802ae-78eb-40af-8d3e-f33b1a0ce2ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=453526943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.453526943
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2065981833
Short name T1445
Test name
Test status
Simulation time 13420134534 ps
CPU time 18.77 seconds
Started May 26 01:27:49 PM PDT 24
Finished May 26 01:28:09 PM PDT 24
Peak memory 205280 kb
Host smart-438382ce-29ce-428c-9b9b-10dcb3c7f7a8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2065981833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2065981833
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.968015559
Short name T757
Test name
Test status
Simulation time 13259036553 ps
CPU time 20.82 seconds
Started May 26 01:27:53 PM PDT 24
Finished May 26 01:28:14 PM PDT 24
Peak memory 205260 kb
Host smart-93ac9b5c-c02e-49b0-8d79-6eb04e65182e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=968015559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.968015559
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.4225743976
Short name T1522
Test name
Test status
Simulation time 10097876903 ps
CPU time 13.52 seconds
Started May 26 01:27:51 PM PDT 24
Finished May 26 01:28:05 PM PDT 24
Peak memory 205240 kb
Host smart-f605e825-df22-411c-9dea-4c30a1bc577d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42257
43976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.4225743976
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1033946904
Short name T1837
Test name
Test status
Simulation time 10116152990 ps
CPU time 15.41 seconds
Started May 26 01:27:49 PM PDT 24
Finished May 26 01:28:05 PM PDT 24
Peak memory 205280 kb
Host smart-5f26bcfe-00d7-4fa8-aa00-e1d2bbc42487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10339
46904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1033946904
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1415360211
Short name T48
Test name
Test status
Simulation time 10056148323 ps
CPU time 15.37 seconds
Started May 26 01:27:57 PM PDT 24
Finished May 26 01:28:13 PM PDT 24
Peak memory 205224 kb
Host smart-6b2ef810-4008-44e3-9da3-356d2680158c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
60211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1415360211
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.4231244755
Short name T1607
Test name
Test status
Simulation time 10055240068 ps
CPU time 13.96 seconds
Started May 26 01:27:49 PM PDT 24
Finished May 26 01:28:04 PM PDT 24
Peak memory 205360 kb
Host smart-ee0aa28b-6243-482c-b852-43c583390339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42312
44755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.4231244755
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1966026314
Short name T1171
Test name
Test status
Simulation time 10724875672 ps
CPU time 15.58 seconds
Started May 26 01:27:49 PM PDT 24
Finished May 26 01:28:06 PM PDT 24
Peak memory 205240 kb
Host smart-0ccaa2cc-2799-4ec7-9bf7-19a056bd2e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19660
26314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1966026314
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3301110812
Short name T582
Test name
Test status
Simulation time 10116529422 ps
CPU time 15.65 seconds
Started May 26 01:27:52 PM PDT 24
Finished May 26 01:28:08 PM PDT 24
Peak memory 205260 kb
Host smart-a1934a38-c97c-48cb-9787-54863ea5ad1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33011
10812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3301110812
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1272983315
Short name T1267
Test name
Test status
Simulation time 10110385517 ps
CPU time 14.8 seconds
Started May 26 01:28:05 PM PDT 24
Finished May 26 01:28:21 PM PDT 24
Peak memory 205236 kb
Host smart-8da761d1-c484-4dd4-8798-2d89307c8202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12729
83315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1272983315
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1787347346
Short name T1860
Test name
Test status
Simulation time 10057127603 ps
CPU time 17.25 seconds
Started May 26 01:28:08 PM PDT 24
Finished May 26 01:28:26 PM PDT 24
Peak memory 205320 kb
Host smart-a1322a07-a2c8-4af5-9df5-2a6c4697f2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873
47346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1787347346
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.4280187339
Short name T892
Test name
Test status
Simulation time 10076366425 ps
CPU time 13.24 seconds
Started May 26 01:27:49 PM PDT 24
Finished May 26 01:28:03 PM PDT 24
Peak memory 205148 kb
Host smart-cf9a6eed-2b3f-441a-9c0e-a13020bb6b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42801
87339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.4280187339
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2662461896
Short name T1417
Test name
Test status
Simulation time 10106254412 ps
CPU time 16.84 seconds
Started May 26 01:27:50 PM PDT 24
Finished May 26 01:28:08 PM PDT 24
Peak memory 205312 kb
Host smart-ba4937a5-7d43-4aaa-821b-cf44b0f6f204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
61896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2662461896
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.183084848
Short name T1105
Test name
Test status
Simulation time 13247152149 ps
CPU time 17.05 seconds
Started May 26 01:27:58 PM PDT 24
Finished May 26 01:28:16 PM PDT 24
Peak memory 205264 kb
Host smart-fbd2ef03-297f-4b87-a496-336e0762fd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18308
4848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.183084848
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1314094092
Short name T697
Test name
Test status
Simulation time 10096715172 ps
CPU time 15.47 seconds
Started May 26 01:27:59 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 205312 kb
Host smart-bc166b16-e218-42ca-964a-ba6d0823eb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13140
94092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1314094092
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4146173935
Short name T984
Test name
Test status
Simulation time 10054332034 ps
CPU time 14.29 seconds
Started May 26 01:28:10 PM PDT 24
Finished May 26 01:28:25 PM PDT 24
Peak memory 205248 kb
Host smart-605abe94-4485-4176-8c0e-ea9ddc3da1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41461
73935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4146173935
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.426526790
Short name T1868
Test name
Test status
Simulation time 10119904089 ps
CPU time 14.52 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:30 PM PDT 24
Peak memory 205284 kb
Host smart-551ee33a-0065-474f-aaf5-2ae937b8b83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42652
6790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.426526790
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2362776304
Short name T1041
Test name
Test status
Simulation time 10047538629 ps
CPU time 13.48 seconds
Started May 26 01:28:01 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 205304 kb
Host smart-8667e2a0-bbd7-4a0f-a6e6-40d4daed1055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23627
76304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2362776304
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2233270615
Short name T543
Test name
Test status
Simulation time 10169170040 ps
CPU time 14.63 seconds
Started May 26 01:28:00 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 205224 kb
Host smart-7ea67e31-9e18-4ec0-aad5-0e4fc19c10f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
70615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2233270615
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.3056854820
Short name T1252
Test name
Test status
Simulation time 10064410197 ps
CPU time 14.22 seconds
Started May 26 01:27:59 PM PDT 24
Finished May 26 01:28:14 PM PDT 24
Peak memory 205184 kb
Host smart-cee86714-daf4-4ed2-9b1b-874d13be7212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30568
54820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.3056854820
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.526776290
Short name T1329
Test name
Test status
Simulation time 10040595871 ps
CPU time 17.07 seconds
Started May 26 01:28:01 PM PDT 24
Finished May 26 01:28:19 PM PDT 24
Peak memory 205332 kb
Host smart-0c8d336b-074b-43ac-a05c-b5f771b8192b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52677
6290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.526776290
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2046065539
Short name T1083
Test name
Test status
Simulation time 10055398709 ps
CPU time 13.63 seconds
Started May 26 01:28:07 PM PDT 24
Finished May 26 01:28:22 PM PDT 24
Peak memory 205260 kb
Host smart-8051eb8f-e6e9-44d4-8cbb-6cef05c57a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20460
65539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2046065539
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.537494266
Short name T1720
Test name
Test status
Simulation time 10155905083 ps
CPU time 16.1 seconds
Started May 26 01:28:09 PM PDT 24
Finished May 26 01:28:26 PM PDT 24
Peak memory 205240 kb
Host smart-fafc7635-3399-4b3b-b91c-83d465f9e55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53749
4266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.537494266
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.1248092226
Short name T895
Test name
Test status
Simulation time 10135003059 ps
CPU time 14.32 seconds
Started May 26 01:28:01 PM PDT 24
Finished May 26 01:28:16 PM PDT 24
Peak memory 205296 kb
Host smart-305016e7-b190-4c91-90d4-277a89ab8e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12480
92226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.1248092226
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2795220000
Short name T546
Test name
Test status
Simulation time 10056538261 ps
CPU time 16.39 seconds
Started May 26 01:27:58 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 205264 kb
Host smart-92bb9c87-27aa-4e4c-acb5-89d9d5f82a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27952
20000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2795220000
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.607993723
Short name T217
Test name
Test status
Simulation time 736411158 ps
CPU time 1.55 seconds
Started May 26 01:28:14 PM PDT 24
Finished May 26 01:28:16 PM PDT 24
Peak memory 222512 kb
Host smart-a3f9d721-7bbc-4c1a-88ca-5025c2ea60cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=607993723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.607993723
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.647041129
Short name T142
Test name
Test status
Simulation time 10052882878 ps
CPU time 15.12 seconds
Started May 26 01:27:59 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 205340 kb
Host smart-2d7110ba-ddee-4d6a-910c-02afcc51b7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64704
1129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.647041129
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1697133342
Short name T1418
Test name
Test status
Simulation time 10077989926 ps
CPU time 13.94 seconds
Started May 26 01:28:08 PM PDT 24
Finished May 26 01:28:23 PM PDT 24
Peak memory 205240 kb
Host smart-a67a0dd1-4c7c-4c8f-9a08-9bdf563c06b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16971
33342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1697133342
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1296895633
Short name T999
Test name
Test status
Simulation time 10100013848 ps
CPU time 14.26 seconds
Started May 26 01:27:40 PM PDT 24
Finished May 26 01:27:55 PM PDT 24
Peak memory 205268 kb
Host smart-c29ba22d-a4cd-4ef1-a9fb-b02e1b0d89d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12968
95633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1296895633
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3510404619
Short name T964
Test name
Test status
Simulation time 10119725178 ps
CPU time 13.26 seconds
Started May 26 01:28:10 PM PDT 24
Finished May 26 01:28:24 PM PDT 24
Peak memory 205224 kb
Host smart-b87abb5e-a1fd-4ad4-ac0b-bc24b17512cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35104
04619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3510404619
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2137642346
Short name T1737
Test name
Test status
Simulation time 10064892044 ps
CPU time 13.73 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 205260 kb
Host smart-de661f60-ca2b-4de0-8cae-2011ddf5387b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
42346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2137642346
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.2581477610
Short name T1137
Test name
Test status
Simulation time 10137360974 ps
CPU time 15.39 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205256 kb
Host smart-cb2db099-022a-43fa-bd2d-fcade188fbfa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2581477610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.2581477610
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.3482656824
Short name T827
Test name
Test status
Simulation time 10088463668 ps
CPU time 15.43 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205260 kb
Host smart-c17796e8-a5bd-470a-8459-22d6c61b0407
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3482656824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.3482656824
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.896104273
Short name T490
Test name
Test status
Simulation time 10105521641 ps
CPU time 14.56 seconds
Started May 26 01:36:04 PM PDT 24
Finished May 26 01:36:19 PM PDT 24
Peak memory 205180 kb
Host smart-5111ff3f-9b9a-415b-8f9b-175f831c297f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89610
4273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.896104273
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1758950760
Short name T578
Test name
Test status
Simulation time 13876458672 ps
CPU time 19.95 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:15 PM PDT 24
Peak memory 205288 kb
Host smart-a4af629a-d1a9-4d32-a991-257268776879
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1758950760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1758950760
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2491072927
Short name T1542
Test name
Test status
Simulation time 13216960111 ps
CPU time 20.14 seconds
Started May 26 01:35:57 PM PDT 24
Finished May 26 01:36:18 PM PDT 24
Peak memory 205292 kb
Host smart-aebf84a0-7061-4454-977d-a052829d7f8c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2491072927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2491072927
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1119100060
Short name T1343
Test name
Test status
Simulation time 13310839476 ps
CPU time 18.71 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:15 PM PDT 24
Peak memory 205312 kb
Host smart-e9cd4a80-d99e-4af6-b8ac-ab2485918f94
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1119100060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1119100060
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4201560553
Short name T1920
Test name
Test status
Simulation time 10057265736 ps
CPU time 14.2 seconds
Started May 26 01:35:52 PM PDT 24
Finished May 26 01:36:07 PM PDT 24
Peak memory 205220 kb
Host smart-eebc87df-57c9-462e-abe6-86d1a996fd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
60553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4201560553
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3296844534
Short name T797
Test name
Test status
Simulation time 10195544033 ps
CPU time 14.19 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:08 PM PDT 24
Peak memory 205268 kb
Host smart-30ca1dbc-a6ae-4b71-bf8c-2b1b8b72a6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968
44534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3296844534
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.1446783090
Short name T953
Test name
Test status
Simulation time 10045250934 ps
CPU time 14.65 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:20 PM PDT 24
Peak memory 205300 kb
Host smart-e936ed48-fa1f-4b2d-9d2e-3349997e458b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14467
83090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.1446783090
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.4144157987
Short name T1696
Test name
Test status
Simulation time 10097333685 ps
CPU time 14.19 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:10 PM PDT 24
Peak memory 205256 kb
Host smart-6e6e051d-f284-4543-b538-54e0a5681468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41441
57987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4144157987
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3050590423
Short name T715
Test name
Test status
Simulation time 10602515900 ps
CPU time 16.53 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:12 PM PDT 24
Peak memory 205508 kb
Host smart-3c992e77-9e18-4c05-8fba-9950084ac2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30505
90423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3050590423
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2248353923
Short name T1829
Test name
Test status
Simulation time 10051680949 ps
CPU time 14.53 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:09 PM PDT 24
Peak memory 205232 kb
Host smart-a7742dd5-bfdf-4395-943a-8b66505dd872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22483
53923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2248353923
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3334154526
Short name T1192
Test name
Test status
Simulation time 10150342164 ps
CPU time 16.87 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205228 kb
Host smart-38f5da26-0354-4ee2-87b6-a86395455afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33341
54526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3334154526
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3584564393
Short name T1926
Test name
Test status
Simulation time 10087152141 ps
CPU time 17.12 seconds
Started May 26 01:36:06 PM PDT 24
Finished May 26 01:36:23 PM PDT 24
Peak memory 205288 kb
Host smart-c9f742ba-2cc8-4189-a936-f070d1f4fb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35845
64393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3584564393
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1872843382
Short name T21
Test name
Test status
Simulation time 10093690077 ps
CPU time 13.75 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:09 PM PDT 24
Peak memory 205280 kb
Host smart-e8c23115-e8f7-43bd-9e15-34815fd7d5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
43382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1872843382
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2445741748
Short name T1408
Test name
Test status
Simulation time 10089645676 ps
CPU time 14.84 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:11 PM PDT 24
Peak memory 205312 kb
Host smart-af21d128-9fd5-44ea-8de0-ae6afd42e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24457
41748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2445741748
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3512816770
Short name T758
Test name
Test status
Simulation time 13235276344 ps
CPU time 16.83 seconds
Started May 26 01:35:57 PM PDT 24
Finished May 26 01:36:14 PM PDT 24
Peak memory 205264 kb
Host smart-9bbe5a75-8894-4ea7-af66-a4180c76b55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35128
16770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3512816770
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.4246488719
Short name T478
Test name
Test status
Simulation time 10089831569 ps
CPU time 14.48 seconds
Started May 26 01:35:55 PM PDT 24
Finished May 26 01:36:11 PM PDT 24
Peak memory 205444 kb
Host smart-e056fd41-11f6-4d0c-9e42-3a9db1363fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42464
88719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.4246488719
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1735655367
Short name T725
Test name
Test status
Simulation time 10065342809 ps
CPU time 13.14 seconds
Started May 26 01:35:53 PM PDT 24
Finished May 26 01:36:07 PM PDT 24
Peak memory 205336 kb
Host smart-de95df45-8fdd-4af0-8bac-a1f0b2619040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17356
55367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1735655367
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2784661719
Short name T1202
Test name
Test status
Simulation time 10114924774 ps
CPU time 14.82 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205196 kb
Host smart-561c0878-57e0-4fd5-a60d-3bae59eae97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
61719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2784661719
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3167895220
Short name T414
Test name
Test status
Simulation time 10101666028 ps
CPU time 14.45 seconds
Started May 26 01:36:02 PM PDT 24
Finished May 26 01:36:17 PM PDT 24
Peak memory 205224 kb
Host smart-b3f78d1f-859c-46be-858f-4a357c7c026f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31678
95220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3167895220
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2411570796
Short name T1803
Test name
Test status
Simulation time 10043661094 ps
CPU time 13.56 seconds
Started May 26 01:36:07 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205292 kb
Host smart-8bdc8c33-6961-41b2-895b-578aa5c16a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
70796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2411570796
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1634917644
Short name T1389
Test name
Test status
Simulation time 10062723507 ps
CPU time 13.37 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:18 PM PDT 24
Peak memory 205276 kb
Host smart-5febae9d-4a34-4a4c-85c8-2969a325d606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16349
17644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1634917644
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.127730644
Short name T182
Test name
Test status
Simulation time 10054357394 ps
CPU time 13.9 seconds
Started May 26 01:36:06 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205272 kb
Host smart-a6e37e97-f309-47ae-8448-e56d7182253a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12773
0644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.127730644
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.3352175635
Short name T1482
Test name
Test status
Simulation time 10055903280 ps
CPU time 13.76 seconds
Started May 26 01:36:07 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205236 kb
Host smart-2999dc55-be17-47cb-b419-d38000a218b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
75635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.3352175635
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2852388100
Short name T1232
Test name
Test status
Simulation time 10122285263 ps
CPU time 13.54 seconds
Started May 26 01:36:04 PM PDT 24
Finished May 26 01:36:18 PM PDT 24
Peak memory 205296 kb
Host smart-f82df205-88f9-4d05-a454-9f1c05a6790e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28523
88100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2852388100
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.4093783295
Short name T51
Test name
Test status
Simulation time 24748530034 ps
CPU time 46.02 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205252 kb
Host smart-5d144220-302d-4ab2-8d00-44da7bf43a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40937
83295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.4093783295
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.4127740865
Short name T1585
Test name
Test status
Simulation time 10054310838 ps
CPU time 15.41 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:19 PM PDT 24
Peak memory 205276 kb
Host smart-a50afa30-30fe-46b6-ab39-f264ecb6c29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41277
40865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.4127740865
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.559530201
Short name T1709
Test name
Test status
Simulation time 10130744458 ps
CPU time 13.78 seconds
Started May 26 01:36:14 PM PDT 24
Finished May 26 01:36:28 PM PDT 24
Peak memory 205300 kb
Host smart-990506bb-10ec-4b2c-9f35-0085b1cd996a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55953
0201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.559530201
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.3300554547
Short name T479
Test name
Test status
Simulation time 10064626137 ps
CPU time 15.12 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:19 PM PDT 24
Peak memory 205212 kb
Host smart-fc9f4a9f-3005-455e-bfab-ec61486f751d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
54547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.3300554547
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.964541463
Short name T450
Test name
Test status
Simulation time 10039828199 ps
CPU time 14.13 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:20 PM PDT 24
Peak memory 205180 kb
Host smart-3c50464d-b04e-4540-908b-36add609f7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96454
1463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.964541463
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.506016492
Short name T148
Test name
Test status
Simulation time 10064929305 ps
CPU time 15.68 seconds
Started May 26 01:36:02 PM PDT 24
Finished May 26 01:36:19 PM PDT 24
Peak memory 205236 kb
Host smart-422a8218-7509-4d99-a734-059967d3806f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50601
6492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.506016492
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3854112950
Short name T1460
Test name
Test status
Simulation time 10061941015 ps
CPU time 16.77 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:22 PM PDT 24
Peak memory 205236 kb
Host smart-86d4df7b-a8b0-4780-bc2a-180e249c236c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38541
12950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3854112950
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.367524848
Short name T1934
Test name
Test status
Simulation time 10162222334 ps
CPU time 14.41 seconds
Started May 26 01:35:54 PM PDT 24
Finished May 26 01:36:10 PM PDT 24
Peak memory 205344 kb
Host smart-94285222-3df4-44c0-bfde-6ffb829753f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36752
4848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.367524848
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3651240488
Short name T971
Test name
Test status
Simulation time 10115666428 ps
CPU time 13.44 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:17 PM PDT 24
Peak memory 205316 kb
Host smart-94b26781-da0d-418d-8b19-134a9f0e3cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36512
40488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3651240488
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3190428856
Short name T1166
Test name
Test status
Simulation time 10071547773 ps
CPU time 15.09 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:21 PM PDT 24
Peak memory 205284 kb
Host smart-1f6c5213-5582-4613-9980-8482392ba1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
28856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3190428856
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.678723958
Short name T1838
Test name
Test status
Simulation time 10134741724 ps
CPU time 13.7 seconds
Started May 26 01:36:19 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205144 kb
Host smart-4304b411-14c6-4955-a2ee-d707c9e23abb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=678723958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.678723958
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.1683010386
Short name T658
Test name
Test status
Simulation time 10060169958 ps
CPU time 16.34 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:34 PM PDT 24
Peak memory 205224 kb
Host smart-7048d380-9858-4931-b07a-ae616ff2653f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1683010386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.1683010386
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.3776965526
Short name T341
Test name
Test status
Simulation time 10174443091 ps
CPU time 14.4 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:36:31 PM PDT 24
Peak memory 205204 kb
Host smart-1f3a5a77-9067-422c-9299-030a17b56acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37769
65526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.3776965526
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.161605804
Short name T1447
Test name
Test status
Simulation time 13924073107 ps
CPU time 18.09 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:22 PM PDT 24
Peak memory 205348 kb
Host smart-ae6d2aba-1244-41af-a404-194a3a5b393d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=161605804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.161605804
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1869300260
Short name T1846
Test name
Test status
Simulation time 13191600401 ps
CPU time 16.79 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:23 PM PDT 24
Peak memory 205204 kb
Host smart-8791b54d-c4b9-4d10-9748-1a0de618e8af
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1869300260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1869300260
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.913556299
Short name T459
Test name
Test status
Simulation time 13346897540 ps
CPU time 17.97 seconds
Started May 26 01:36:04 PM PDT 24
Finished May 26 01:36:23 PM PDT 24
Peak memory 205308 kb
Host smart-41d90461-875c-4401-be85-9c0d25f4b36d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=913556299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.913556299
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1692917023
Short name T443
Test name
Test status
Simulation time 10045281985 ps
CPU time 12.96 seconds
Started May 26 01:36:07 PM PDT 24
Finished May 26 01:36:20 PM PDT 24
Peak memory 205236 kb
Host smart-891a8d62-8c09-4e57-aba2-2f72b12e27bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929
17023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1692917023
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.64309789
Short name T171
Test name
Test status
Simulation time 11167192455 ps
CPU time 14.6 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:20 PM PDT 24
Peak memory 205324 kb
Host smart-6b9d221c-93dc-4f45-96fc-9ac5ae8cd0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64309
789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.64309789
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3300750332
Short name T595
Test name
Test status
Simulation time 10048351780 ps
CPU time 17.15 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:36:34 PM PDT 24
Peak memory 205252 kb
Host smart-66088ecd-50ba-419c-89f5-35d3769d7fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007
50332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3300750332
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3897481947
Short name T1279
Test name
Test status
Simulation time 10049400466 ps
CPU time 17.54 seconds
Started May 26 01:36:05 PM PDT 24
Finished May 26 01:36:23 PM PDT 24
Peak memory 205528 kb
Host smart-f46d473f-56ab-40d6-af78-8d0929743e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38974
81947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3897481947
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.350975517
Short name T571
Test name
Test status
Simulation time 10924609405 ps
CPU time 15.06 seconds
Started May 26 01:36:03 PM PDT 24
Finished May 26 01:36:19 PM PDT 24
Peak memory 205208 kb
Host smart-11797653-3dd7-444f-a5dc-239788a1a75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35097
5517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.350975517
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1387153586
Short name T1514
Test name
Test status
Simulation time 10110395353 ps
CPU time 14.25 seconds
Started May 26 01:36:21 PM PDT 24
Finished May 26 01:36:36 PM PDT 24
Peak memory 205256 kb
Host smart-cd7bf766-f207-4586-bda6-fe15cf04f749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13871
53586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1387153586
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2756807742
Short name T1022
Test name
Test status
Simulation time 10122705347 ps
CPU time 14.1 seconds
Started May 26 01:36:18 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205224 kb
Host smart-3628a2ab-19d0-4fc6-a128-49603fbf453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
07742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2756807742
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2248795921
Short name T1193
Test name
Test status
Simulation time 10047758872 ps
CPU time 14.87 seconds
Started May 26 01:36:20 PM PDT 24
Finished May 26 01:36:36 PM PDT 24
Peak memory 205256 kb
Host smart-07e610a4-d99c-40b9-8c85-16a493a92206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
95921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2248795921
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3510551068
Short name T1613
Test name
Test status
Simulation time 10115660613 ps
CPU time 17.84 seconds
Started May 26 01:36:18 PM PDT 24
Finished May 26 01:36:36 PM PDT 24
Peak memory 205344 kb
Host smart-786b0ce9-1657-4e15-b8e8-3780c8d8bf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35105
51068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3510551068
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3453086848
Short name T1143
Test name
Test status
Simulation time 10069605896 ps
CPU time 14.43 seconds
Started May 26 01:36:19 PM PDT 24
Finished May 26 01:36:34 PM PDT 24
Peak memory 205228 kb
Host smart-53db5e36-7bbe-4996-896b-c35ba06d6599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34530
86848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3453086848
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2080164817
Short name T1178
Test name
Test status
Simulation time 13209915054 ps
CPU time 18.63 seconds
Started May 26 01:36:20 PM PDT 24
Finished May 26 01:36:39 PM PDT 24
Peak memory 205296 kb
Host smart-346ebdf6-32a1-4446-8b7d-da93727489dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20801
64817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2080164817
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.671857385
Short name T1302
Test name
Test status
Simulation time 10097310231 ps
CPU time 13.56 seconds
Started May 26 01:36:21 PM PDT 24
Finished May 26 01:36:36 PM PDT 24
Peak memory 205324 kb
Host smart-90a82c54-8f0c-4ccf-97ef-820edb82ea3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67185
7385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.671857385
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3760359962
Short name T1642
Test name
Test status
Simulation time 10061034402 ps
CPU time 14.28 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205352 kb
Host smart-ada6d1e6-63e4-49c3-86fc-1b8d12220bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37603
59962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3760359962
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2931245753
Short name T121
Test name
Test status
Simulation time 10123029206 ps
CPU time 14.97 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205324 kb
Host smart-4631caa4-3e64-4631-80ba-d028a1e10090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
45753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2931245753
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3031875391
Short name T1510
Test name
Test status
Simulation time 10122080351 ps
CPU time 13.28 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:36:31 PM PDT 24
Peak memory 205276 kb
Host smart-caab4ad4-0761-4986-80b3-97c957c13253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
75391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3031875391
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2449053509
Short name T1030
Test name
Test status
Simulation time 10048136489 ps
CPU time 14.18 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205296 kb
Host smart-c00b4910-cea0-4e0b-8f38-76e52aab1cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24490
53509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2449053509
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1210689047
Short name T410
Test name
Test status
Simulation time 10095790239 ps
CPU time 14.73 seconds
Started May 26 01:36:20 PM PDT 24
Finished May 26 01:36:35 PM PDT 24
Peak memory 205284 kb
Host smart-48ed4459-33e3-44d9-a19b-f16b7cff1473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12106
89047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1210689047
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3454600546
Short name T168
Test name
Test status
Simulation time 10082909853 ps
CPU time 14.53 seconds
Started May 26 01:36:20 PM PDT 24
Finished May 26 01:36:35 PM PDT 24
Peak memory 205300 kb
Host smart-da140940-addc-4293-9193-31083d24c1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34546
00546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3454600546
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.3501506634
Short name T484
Test name
Test status
Simulation time 10096773868 ps
CPU time 16.14 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:34 PM PDT 24
Peak memory 205192 kb
Host smart-d1eae1fc-ab09-4227-ba3a-b7f1ce688e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
06634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.3501506634
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3890249360
Short name T18
Test name
Test status
Simulation time 10059392199 ps
CPU time 14.85 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205228 kb
Host smart-b3c6214c-ba1a-44a9-a577-da5d3b389e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
49360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3890249360
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2938161362
Short name T801
Test name
Test status
Simulation time 10053894922 ps
CPU time 16.83 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:35 PM PDT 24
Peak memory 205208 kb
Host smart-753a5f10-ee15-45d8-a602-816425de5fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
61362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2938161362
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.80924968
Short name T1554
Test name
Test status
Simulation time 31682697783 ps
CPU time 63.42 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:37:21 PM PDT 24
Peak memory 205368 kb
Host smart-2abe8374-50cd-4117-b43b-4a3b1a3dbdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80924
968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.80924968
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3654292741
Short name T981
Test name
Test status
Simulation time 10084094475 ps
CPU time 15.57 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205276 kb
Host smart-82453f7a-42ea-441f-8494-d1f2e00494ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
92741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3654292741
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1460662249
Short name T1809
Test name
Test status
Simulation time 10132701238 ps
CPU time 14.79 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:36:32 PM PDT 24
Peak memory 205308 kb
Host smart-4c3690ff-7eff-4f61-9320-5ebadcb622ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14606
62249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1460662249
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3087653678
Short name T1308
Test name
Test status
Simulation time 10076690236 ps
CPU time 13.41 seconds
Started May 26 01:36:18 PM PDT 24
Finished May 26 01:36:32 PM PDT 24
Peak memory 205264 kb
Host smart-a015cd87-9c20-4278-a555-493d94f82e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
53678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3087653678
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.4094169633
Short name T529
Test name
Test status
Simulation time 10102960070 ps
CPU time 16.02 seconds
Started May 26 01:36:20 PM PDT 24
Finished May 26 01:36:37 PM PDT 24
Peak memory 205264 kb
Host smart-b05a35d8-d971-4aef-8330-a55e8f27f14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40941
69633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.4094169633
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1470904342
Short name T1685
Test name
Test status
Simulation time 10059614655 ps
CPU time 13.56 seconds
Started May 26 01:36:19 PM PDT 24
Finished May 26 01:36:33 PM PDT 24
Peak memory 205268 kb
Host smart-92fb7fd0-5b6e-495e-8dd2-2501d94b9dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14709
04342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1470904342
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2814801066
Short name T487
Test name
Test status
Simulation time 10045975286 ps
CPU time 14.48 seconds
Started May 26 01:36:19 PM PDT 24
Finished May 26 01:36:34 PM PDT 24
Peak memory 205192 kb
Host smart-5584257e-5765-402f-8616-9bc748d46812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28148
01066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2814801066
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.1140861584
Short name T161
Test name
Test status
Simulation time 10099166775 ps
CPU time 14.43 seconds
Started May 26 01:36:02 PM PDT 24
Finished May 26 01:36:18 PM PDT 24
Peak memory 205280 kb
Host smart-bc00dc9a-f239-43eb-a5cb-c01542238f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11408
61584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.1140861584
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3155135547
Short name T1535
Test name
Test status
Simulation time 10061597144 ps
CPU time 14.17 seconds
Started May 26 01:36:21 PM PDT 24
Finished May 26 01:36:37 PM PDT 24
Peak memory 205300 kb
Host smart-e4b5c133-1b53-45b7-858b-9cbf856b0fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31551
35547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3155135547
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.4046080120
Short name T713
Test name
Test status
Simulation time 10060729190 ps
CPU time 15.24 seconds
Started May 26 01:36:16 PM PDT 24
Finished May 26 01:36:32 PM PDT 24
Peak memory 205316 kb
Host smart-b052f9e1-0d3f-46be-ad16-972a75100198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460
80120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.4046080120
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.2594199261
Short name T1527
Test name
Test status
Simulation time 10141837188 ps
CPU time 18.15 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:48 PM PDT 24
Peak memory 205248 kb
Host smart-12811231-1326-4a72-98b3-616ab157c071
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2594199261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.2594199261
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.69741930
Short name T808
Test name
Test status
Simulation time 10048453340 ps
CPU time 14.77 seconds
Started May 26 01:36:33 PM PDT 24
Finished May 26 01:36:49 PM PDT 24
Peak memory 205308 kb
Host smart-2903b229-67be-46d8-944d-cb1e422f2cc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=69741930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.69741930
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.2870828931
Short name T378
Test name
Test status
Simulation time 10134554210 ps
CPU time 13.85 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205280 kb
Host smart-fa1f1f2a-c9f9-4a36-88e1-f3f79413e4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28708
28931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.2870828931
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.531100801
Short name T1729
Test name
Test status
Simulation time 14173192657 ps
CPU time 18.97 seconds
Started May 26 01:36:18 PM PDT 24
Finished May 26 01:36:38 PM PDT 24
Peak memory 205236 kb
Host smart-c9cf0dc2-28e9-4ecc-a834-6ccead0ddf9e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=531100801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.531100801
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.621415375
Short name T677
Test name
Test status
Simulation time 13309598055 ps
CPU time 20.39 seconds
Started May 26 01:36:17 PM PDT 24
Finished May 26 01:36:39 PM PDT 24
Peak memory 205280 kb
Host smart-4678c96e-25c1-4da8-a142-6cf4bbc08ef8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=621415375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.621415375
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2345434144
Short name T1873
Test name
Test status
Simulation time 13214750573 ps
CPU time 16.65 seconds
Started May 26 01:36:18 PM PDT 24
Finished May 26 01:36:36 PM PDT 24
Peak memory 205256 kb
Host smart-15f1437d-7d4b-49d9-a06d-59550aa9a6e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2345434144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2345434144
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2930816617
Short name T518
Test name
Test status
Simulation time 10051336937 ps
CPU time 16.61 seconds
Started May 26 01:36:21 PM PDT 24
Finished May 26 01:36:38 PM PDT 24
Peak memory 205316 kb
Host smart-6de50b80-633c-4c18-a56e-07c24de88635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29308
16617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2930816617
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.351288063
Short name T853
Test name
Test status
Simulation time 10072707127 ps
CPU time 15.71 seconds
Started May 26 01:36:19 PM PDT 24
Finished May 26 01:36:35 PM PDT 24
Peak memory 205200 kb
Host smart-70ea920b-7edc-4e6f-8c5d-8eebf6d58307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35128
8063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.351288063
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2950998627
Short name T1281
Test name
Test status
Simulation time 11032119205 ps
CPU time 15.87 seconds
Started May 26 01:36:19 PM PDT 24
Finished May 26 01:36:35 PM PDT 24
Peak memory 205336 kb
Host smart-f8c0f824-1859-43ed-b602-5d9eda48b92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29509
98627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2950998627
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1240981090
Short name T1076
Test name
Test status
Simulation time 10044541023 ps
CPU time 14.15 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205308 kb
Host smart-f4b2fe89-a13f-43ff-b7d1-b66323a92ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12409
81090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1240981090
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3534409322
Short name T1630
Test name
Test status
Simulation time 10054874351 ps
CPU time 13.54 seconds
Started May 26 01:36:25 PM PDT 24
Finished May 26 01:36:39 PM PDT 24
Peak memory 205224 kb
Host smart-f05b02e4-f6a8-47be-ad7e-6767c1d94268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35344
09322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3534409322
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.784332624
Short name T33
Test name
Test status
Simulation time 10861666504 ps
CPU time 16.55 seconds
Started May 26 01:36:24 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205296 kb
Host smart-641d42b3-1208-4940-b68c-ba2707cb4d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78433
2624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.784332624
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.2541533818
Short name T1765
Test name
Test status
Simulation time 10203666025 ps
CPU time 15.79 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205212 kb
Host smart-5e275918-4055-4e27-a356-8fb463902ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25415
33818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.2541533818
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1455741747
Short name T1790
Test name
Test status
Simulation time 10115815483 ps
CPU time 14.65 seconds
Started May 26 01:36:25 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205216 kb
Host smart-24f21f7b-9505-4c08-8b2c-b091c96cc185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14557
41747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1455741747
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1728054790
Short name T28
Test name
Test status
Simulation time 10076481877 ps
CPU time 15.05 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205276 kb
Host smart-0833e5c0-f40a-4574-aebb-3350bce93d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17280
54790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1728054790
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3710880904
Short name T1167
Test name
Test status
Simulation time 10121538990 ps
CPU time 12.99 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205204 kb
Host smart-17131563-e7b4-4110-b9d6-1b833714202f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37108
80904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3710880904
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.729706603
Short name T1570
Test name
Test status
Simulation time 10076113549 ps
CPU time 14.49 seconds
Started May 26 01:36:25 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205304 kb
Host smart-da7cfad7-13f4-43e9-b846-ac3c0744dc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72970
6603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.729706603
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1995869776
Short name T343
Test name
Test status
Simulation time 13228439942 ps
CPU time 16.15 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:45 PM PDT 24
Peak memory 205276 kb
Host smart-790277de-de97-4c59-b00d-f15049c82b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19958
69776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1995869776
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3103519229
Short name T1738
Test name
Test status
Simulation time 10106372000 ps
CPU time 13.6 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205320 kb
Host smart-f354d768-f6a4-479b-9021-e31a10d672d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31035
19229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3103519229
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1372882957
Short name T432
Test name
Test status
Simulation time 10049749776 ps
CPU time 15.74 seconds
Started May 26 01:36:25 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205236 kb
Host smart-c3cd6fe5-bfe7-4271-b4bf-0a55ed84034d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13728
82957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1372882957
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.693589434
Short name T105
Test name
Test status
Simulation time 10181431598 ps
CPU time 13.78 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205260 kb
Host smart-f5cad76f-e239-4c71-b43c-afa923de8314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69358
9434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.693589434
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2751813705
Short name T1567
Test name
Test status
Simulation time 10091620139 ps
CPU time 14.49 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205224 kb
Host smart-f4dffc9e-be6d-4fe0-b419-67a2ef9a6c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27518
13705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2751813705
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1368364152
Short name T886
Test name
Test status
Simulation time 10120841390 ps
CPU time 13.92 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205276 kb
Host smart-daeffb9e-edff-4d74-b7ba-8776a5d52b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13683
64152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1368364152
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1708968205
Short name T391
Test name
Test status
Simulation time 10073983473 ps
CPU time 13.88 seconds
Started May 26 01:36:30 PM PDT 24
Finished May 26 01:36:45 PM PDT 24
Peak memory 205328 kb
Host smart-84d2b2a0-663a-4fa4-8d13-db2b64273054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17089
68205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1708968205
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3929181899
Short name T190
Test name
Test status
Simulation time 10081565803 ps
CPU time 13.65 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205268 kb
Host smart-95287961-dabb-471d-a687-0713db5acb55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
81899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3929181899
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.1147713433
Short name T1772
Test name
Test status
Simulation time 10088395374 ps
CPU time 16.81 seconds
Started May 26 01:36:24 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205276 kb
Host smart-f05b7a04-7d17-40da-a5a5-bffaf4d30421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
13433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.1147713433
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3265712003
Short name T1106
Test name
Test status
Simulation time 10053753550 ps
CPU time 14.32 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205268 kb
Host smart-4a7b97e2-07fa-43b2-9043-2a94787d1c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32657
12003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3265712003
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2288883739
Short name T1748
Test name
Test status
Simulation time 10044220771 ps
CPU time 13.68 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205276 kb
Host smart-89adc640-6a58-4712-8aa7-86b3c25bd860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888
83739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2288883739
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.170471509
Short name T1562
Test name
Test status
Simulation time 22704457171 ps
CPU time 40.26 seconds
Started May 26 01:36:25 PM PDT 24
Finished May 26 01:37:05 PM PDT 24
Peak memory 205516 kb
Host smart-ffb48f0a-72cb-4155-9ee5-9bcb7847507f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17047
1509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.170471509
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.897200340
Short name T1520
Test name
Test status
Simulation time 10081732214 ps
CPU time 14.37 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:44 PM PDT 24
Peak memory 205256 kb
Host smart-a3e1ea81-c3e9-45ba-93bf-d4bafed2bdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89720
0340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.897200340
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2602928700
Short name T963
Test name
Test status
Simulation time 10104036023 ps
CPU time 13.06 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:41 PM PDT 24
Peak memory 205332 kb
Host smart-8aeb2e7f-e68f-446a-a22d-e5543a08a68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26029
28700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2602928700
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.1371082167
Short name T321
Test name
Test status
Simulation time 10100561770 ps
CPU time 13.59 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205244 kb
Host smart-7a6e7e0d-88ee-412a-a2ea-4d3488112c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13710
82167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.1371082167
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.2856811615
Short name T561
Test name
Test status
Simulation time 10041660767 ps
CPU time 14.37 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205260 kb
Host smart-3040f3d7-5419-4724-9cea-44a293c87d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28568
11615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.2856811615
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1935920438
Short name T843
Test name
Test status
Simulation time 10112452493 ps
CPU time 15.33 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:44 PM PDT 24
Peak memory 205296 kb
Host smart-6e5b05b9-f74b-49d6-acaf-b10f49ae8152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19359
20438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1935920438
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2703550282
Short name T696
Test name
Test status
Simulation time 10078891912 ps
CPU time 16.27 seconds
Started May 26 01:36:25 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205260 kb
Host smart-18f4a82e-e18f-4d02-b2fa-dc0691bb0b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27035
50282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2703550282
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3337668199
Short name T922
Test name
Test status
Simulation time 10108538502 ps
CPU time 14.78 seconds
Started May 26 01:36:18 PM PDT 24
Finished May 26 01:36:34 PM PDT 24
Peak memory 205188 kb
Host smart-4994aa6b-d51e-4b34-9a33-7da008530b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33376
68199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3337668199
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1796357443
Short name T1644
Test name
Test status
Simulation time 10059293487 ps
CPU time 15.32 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:53 PM PDT 24
Peak memory 205236 kb
Host smart-f2480ccd-79d4-462c-b737-6b8fabb16b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
57443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1796357443
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2942415641
Short name T1258
Test name
Test status
Simulation time 10052093281 ps
CPU time 15.03 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:45 PM PDT 24
Peak memory 205260 kb
Host smart-0ebe2037-d5ae-416e-9b2b-f5bbee5c28fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29424
15641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2942415641
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.2950534211
Short name T1257
Test name
Test status
Simulation time 10142176541 ps
CPU time 14.91 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205220 kb
Host smart-d6325af8-1c3d-4542-8fa6-348acf8edc95
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2950534211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.2950534211
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.716918382
Short name T1590
Test name
Test status
Simulation time 10062424646 ps
CPU time 14.43 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:49 PM PDT 24
Peak memory 205316 kb
Host smart-69094036-dc39-4498-8fde-4e9197153ff6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=716918382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.716918382
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.2502537166
Short name T1889
Test name
Test status
Simulation time 10104282601 ps
CPU time 14.14 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:53 PM PDT 24
Peak memory 205220 kb
Host smart-14144109-cd82-468e-9435-7aa8de3d96e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
37166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.2502537166
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2202042301
Short name T1311
Test name
Test status
Simulation time 13285910332 ps
CPU time 17.6 seconds
Started May 26 01:36:29 PM PDT 24
Finished May 26 01:36:48 PM PDT 24
Peak memory 205356 kb
Host smart-0f8d4851-1ad7-4a82-95e3-443467eec161
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2202042301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2202042301
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.924381897
Short name T1378
Test name
Test status
Simulation time 10057307723 ps
CPU time 14.67 seconds
Started May 26 01:36:30 PM PDT 24
Finished May 26 01:36:46 PM PDT 24
Peak memory 205304 kb
Host smart-eaf19346-bd47-4bf1-a6fa-ff2c5e96adf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92438
1897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.924381897
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1420038011
Short name T164
Test name
Test status
Simulation time 10897379908 ps
CPU time 17.46 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:47 PM PDT 24
Peak memory 205308 kb
Host smart-12fe8142-d96b-40b9-838e-9592b94b2cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14200
38011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1420038011
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1073255011
Short name T1662
Test name
Test status
Simulation time 10059635369 ps
CPU time 17.52 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:56 PM PDT 24
Peak memory 205224 kb
Host smart-88aabc64-6c58-4fae-9c0a-c1be89b83818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10732
55011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1073255011
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2775407157
Short name T652
Test name
Test status
Simulation time 10092783543 ps
CPU time 13.96 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205224 kb
Host smart-08d9d9a8-ddd9-47fc-a112-33cbe6659d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27754
07157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2775407157
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.778256713
Short name T328
Test name
Test status
Simulation time 10600728972 ps
CPU time 14.35 seconds
Started May 26 01:36:26 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205244 kb
Host smart-785983dc-ab64-45bf-b874-d6173fa36509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77825
6713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.778256713
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.375132644
Short name T1366
Test name
Test status
Simulation time 10064883696 ps
CPU time 16.08 seconds
Started May 26 01:36:30 PM PDT 24
Finished May 26 01:36:47 PM PDT 24
Peak memory 205268 kb
Host smart-32d9e97c-8a9a-4e34-876e-f130fd80cfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37513
2644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.375132644
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.1659965359
Short name T1175
Test name
Test status
Simulation time 10103324829 ps
CPU time 14.14 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205232 kb
Host smart-16b3d7e0-2e55-4d69-9426-c92eaa011547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16599
65359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.1659965359
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2098469062
Short name T627
Test name
Test status
Simulation time 10043307015 ps
CPU time 15.17 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205292 kb
Host smart-425a59cf-9199-49fc-ad86-557fef4b5960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20984
69062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2098469062
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.215012346
Short name T838
Test name
Test status
Simulation time 10118542080 ps
CPU time 13.35 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:42 PM PDT 24
Peak memory 205272 kb
Host smart-f888d192-5fd6-48ea-bdcc-39f3d256677c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21501
2346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.215012346
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.385852079
Short name T1647
Test name
Test status
Simulation time 10093443414 ps
CPU time 16.89 seconds
Started May 26 01:36:29 PM PDT 24
Finished May 26 01:36:47 PM PDT 24
Peak memory 205108 kb
Host smart-4623f73c-48c2-433b-992b-fa748c797078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.385852079
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3998479644
Short name T1284
Test name
Test status
Simulation time 13163960465 ps
CPU time 20.2 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205200 kb
Host smart-3b63d91f-8bbb-4249-9ca0-b8ab14d5b907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
79644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3998479644
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.621563396
Short name T643
Test name
Test status
Simulation time 10108815503 ps
CPU time 13.24 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 204484 kb
Host smart-bd272186-f747-4a3f-9e21-67b5a9232fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62156
3396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.621563396
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.4170159847
Short name T1039
Test name
Test status
Simulation time 10043669311 ps
CPU time 13.2 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 204476 kb
Host smart-a0308c3e-4414-4d2a-8c69-5a2e5a4660d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701
59847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.4170159847
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1882535126
Short name T116
Test name
Test status
Simulation time 10160528787 ps
CPU time 13.61 seconds
Started May 26 01:36:31 PM PDT 24
Finished May 26 01:36:45 PM PDT 24
Peak memory 205240 kb
Host smart-25b5823d-9a07-4889-b6f7-f8465058c5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825
35126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1882535126
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.4075166409
Short name T1276
Test name
Test status
Simulation time 10130919352 ps
CPU time 13.95 seconds
Started May 26 01:36:27 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205296 kb
Host smart-dc3f3bbf-dabe-4e66-bb60-94001e8f3a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
66409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.4075166409
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3282072468
Short name T1104
Test name
Test status
Simulation time 10074314875 ps
CPU time 13.97 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:44 PM PDT 24
Peak memory 205288 kb
Host smart-910836f1-9076-4696-a4db-dcf146985f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
72468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3282072468
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2082237387
Short name T920
Test name
Test status
Simulation time 10087745791 ps
CPU time 14.89 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:53 PM PDT 24
Peak memory 205232 kb
Host smart-a9802862-60f0-426b-abc1-bd259b76cfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
37387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2082237387
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.637462721
Short name T184
Test name
Test status
Simulation time 10078695936 ps
CPU time 14.08 seconds
Started May 26 01:36:31 PM PDT 24
Finished May 26 01:36:46 PM PDT 24
Peak memory 205272 kb
Host smart-86cc48f1-aa91-42e8-8392-9d956316c94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63746
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.637462721
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.1787560729
Short name T552
Test name
Test status
Simulation time 10082328335 ps
CPU time 16.77 seconds
Started May 26 01:36:38 PM PDT 24
Finished May 26 01:36:56 PM PDT 24
Peak memory 205204 kb
Host smart-8a140011-8335-4792-b283-adc65578b83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
60729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.1787560729
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.514172206
Short name T466
Test name
Test status
Simulation time 10045058136 ps
CPU time 13.61 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205232 kb
Host smart-d3f90300-8e38-4090-8ce6-80578cf0f8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51417
2206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.514172206
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.418096390
Short name T1620
Test name
Test status
Simulation time 10053008368 ps
CPU time 16.05 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:54 PM PDT 24
Peak memory 205256 kb
Host smart-a6cde0d2-cbfa-40f0-bf78-77d5bc13a135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
6390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.418096390
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.1967848215
Short name T1609
Test name
Test status
Simulation time 17250022679 ps
CPU time 33.16 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:37:11 PM PDT 24
Peak memory 205292 kb
Host smart-eb0d966e-74fd-4341-8a88-14fb62a7c83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19678
48215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.1967848215
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1309163044
Short name T1153
Test name
Test status
Simulation time 10084834797 ps
CPU time 13.97 seconds
Started May 26 01:36:28 PM PDT 24
Finished May 26 01:36:43 PM PDT 24
Peak memory 205228 kb
Host smart-ff9f686f-6a0a-4b82-8643-beb0b58eba47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13091
63044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1309163044
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3780393932
Short name T514
Test name
Test status
Simulation time 10073631705 ps
CPU time 13.08 seconds
Started May 26 01:36:23 PM PDT 24
Finished May 26 01:36:36 PM PDT 24
Peak memory 205224 kb
Host smart-7ba9b4f9-a470-40ab-a458-e96fbfeabe50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37803
93932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3780393932
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.3575950675
Short name T1629
Test name
Test status
Simulation time 10074503309 ps
CPU time 14.34 seconds
Started May 26 01:36:29 PM PDT 24
Finished May 26 01:36:44 PM PDT 24
Peak memory 205256 kb
Host smart-b2ea4ed3-6f7d-454e-9ac3-d02258997245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
50675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.3575950675
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2183203699
Short name T1398
Test name
Test status
Simulation time 10050587317 ps
CPU time 13.12 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205260 kb
Host smart-9222b227-db39-4521-a2e0-a00deab14efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21832
03699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2183203699
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2474808453
Short name T1545
Test name
Test status
Simulation time 10040726900 ps
CPU time 14.57 seconds
Started May 26 01:36:31 PM PDT 24
Finished May 26 01:36:46 PM PDT 24
Peak memory 205264 kb
Host smart-e03bff6c-8d60-49f1-b116-99996625a7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24748
08453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2474808453
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2884136575
Short name T1429
Test name
Test status
Simulation time 10055465913 ps
CPU time 15.61 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:54 PM PDT 24
Peak memory 205224 kb
Host smart-2d8806c3-0ccd-4dcf-9ece-63ce63ae5080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28841
36575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2884136575
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.742291235
Short name T1120
Test name
Test status
Simulation time 10117245983 ps
CPU time 16.46 seconds
Started May 26 01:36:30 PM PDT 24
Finished May 26 01:36:47 PM PDT 24
Peak memory 205364 kb
Host smart-3634206e-fd98-4311-b43e-404e0d293115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74229
1235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.742291235
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.685686490
Short name T323
Test name
Test status
Simulation time 10086763862 ps
CPU time 14 seconds
Started May 26 01:36:29 PM PDT 24
Finished May 26 01:36:44 PM PDT 24
Peak memory 205164 kb
Host smart-e3ad63e8-7b93-4ac0-ac71-f25c1b4818d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68568
6490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.685686490
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3774438613
Short name T1330
Test name
Test status
Simulation time 10072393120 ps
CPU time 16.55 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:55 PM PDT 24
Peak memory 205204 kb
Host smart-f1cf2eb7-0311-4ffa-ae3a-b4848224efb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744
38613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3774438613
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.1742886640
Short name T1005
Test name
Test status
Simulation time 10165450098 ps
CPU time 14.16 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205296 kb
Host smart-3f16dbcb-cc1a-46f7-9e38-7a93952b6a1a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1742886640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.1742886640
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.4159342481
Short name T1473
Test name
Test status
Simulation time 10068642014 ps
CPU time 14.62 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205272 kb
Host smart-4b110eb2-1bf6-47ec-85ca-97833f09e178
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4159342481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.4159342481
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.2662014283
Short name T860
Test name
Test status
Simulation time 10177608778 ps
CPU time 16.35 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:53 PM PDT 24
Peak memory 205436 kb
Host smart-dd63a383-23d8-4639-af10-4eaa9b538491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26620
14283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.2662014283
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3642855077
Short name T988
Test name
Test status
Simulation time 14003495550 ps
CPU time 18.75 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:54 PM PDT 24
Peak memory 205308 kb
Host smart-57b02c51-9684-4bfd-ad5f-42a470f6d329
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3642855077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3642855077
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.340482485
Short name T1759
Test name
Test status
Simulation time 13287934204 ps
CPU time 17.81 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205284 kb
Host smart-8d20a83f-da29-47de-97dc-be8747b4da8b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=340482485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.340482485
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1436041511
Short name T1438
Test name
Test status
Simulation time 13288172041 ps
CPU time 17.31 seconds
Started May 26 01:36:33 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205352 kb
Host smart-e11157ef-726b-4a00-a938-aaf77b288088
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1436041511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1436041511
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2034902607
Short name T721
Test name
Test status
Simulation time 10071906068 ps
CPU time 15.13 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205164 kb
Host smart-8b59fe99-8ac8-44e4-aad5-eb493eb9b6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20349
02607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2034902607
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1102841671
Short name T1415
Test name
Test status
Simulation time 11008084569 ps
CPU time 14.94 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:53 PM PDT 24
Peak memory 205388 kb
Host smart-04fd8a3d-412f-48a8-af56-7c7155857dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
41671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1102841671
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1256005195
Short name T1762
Test name
Test status
Simulation time 10052046261 ps
CPU time 13.29 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:49 PM PDT 24
Peak memory 205332 kb
Host smart-d62aaafb-e39a-4e7c-b267-d8d422516a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12560
05195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1256005195
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.4371703
Short name T1657
Test name
Test status
Simulation time 10112014783 ps
CPU time 17.07 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:56 PM PDT 24
Peak memory 205272 kb
Host smart-2ab29189-50fc-4471-9fd7-e4fed8e4869c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43717
03 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.4371703
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.653801665
Short name T565
Test name
Test status
Simulation time 10778015794 ps
CPU time 14.97 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:53 PM PDT 24
Peak memory 205240 kb
Host smart-87f74197-2837-4906-8d9a-aa2ed728c093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65380
1665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.653801665
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2867450448
Short name T1935
Test name
Test status
Simulation time 10253917212 ps
CPU time 18.14 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:55 PM PDT 24
Peak memory 205176 kb
Host smart-55b39984-b910-44bc-a340-7bae0780b7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28674
50448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2867450448
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1326519191
Short name T387
Test name
Test status
Simulation time 10041385226 ps
CPU time 13.83 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205276 kb
Host smart-0e988578-d56b-4742-8997-7db84718e4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13265
19191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1326519191
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.3001644965
Short name T687
Test name
Test status
Simulation time 10147897055 ps
CPU time 18.31 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:57 PM PDT 24
Peak memory 205456 kb
Host smart-59838965-1b85-4c44-82f6-f1cbab4d229c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30016
44965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.3001644965
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1441260308
Short name T416
Test name
Test status
Simulation time 10100228943 ps
CPU time 14.2 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205248 kb
Host smart-f0bcddca-9364-4941-9217-84e4414757b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
60308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1441260308
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.623818460
Short name T641
Test name
Test status
Simulation time 13179720236 ps
CPU time 19.37 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:55 PM PDT 24
Peak memory 205308 kb
Host smart-6f131180-3ce7-49bb-9b4d-dc4c604db40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62381
8460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.623818460
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3280713604
Short name T1170
Test name
Test status
Simulation time 10096298195 ps
CPU time 13.84 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205204 kb
Host smart-7065f03c-50d5-439c-b647-43ddda85e902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32807
13604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3280713604
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3894707953
Short name T1268
Test name
Test status
Simulation time 10058162926 ps
CPU time 15.59 seconds
Started May 26 01:36:33 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205300 kb
Host smart-a9853c44-4882-48c5-9b84-1c4390886f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38947
07953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3894707953
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2691980777
Short name T1457
Test name
Test status
Simulation time 10146314669 ps
CPU time 15.97 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205272 kb
Host smart-6a97600f-b574-461c-acdc-d75111330fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26919
80777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2691980777
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3421253676
Short name T1606
Test name
Test status
Simulation time 10090345706 ps
CPU time 15.37 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205276 kb
Host smart-fdf96974-bc39-415c-97ae-b67e681c5189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34212
53676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3421253676
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2762620180
Short name T382
Test name
Test status
Simulation time 10087644961 ps
CPU time 18.2 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:56 PM PDT 24
Peak memory 205464 kb
Host smart-edf7c9ff-1e24-4edd-b091-8175544fa845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27626
20180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2762620180
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.890380654
Short name T486
Test name
Test status
Simulation time 10052849973 ps
CPU time 14.97 seconds
Started May 26 01:36:35 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205256 kb
Host smart-d1b45ef6-71bb-41a6-8430-f60589726de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89038
0654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.890380654
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.171084743
Short name T1433
Test name
Test status
Simulation time 10109731384 ps
CPU time 14.02 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205196 kb
Host smart-f8fef3ca-f178-4ba6-9e1d-f105aa98bbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17108
4743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.171084743
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.748690787
Short name T503
Test name
Test status
Simulation time 10092523405 ps
CPU time 13.52 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205300 kb
Host smart-071283cb-615d-400b-871e-5411da5870d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74869
0787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.748690787
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.13758466
Short name T864
Test name
Test status
Simulation time 10062058739 ps
CPU time 14.8 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205236 kb
Host smart-9e1219ca-6d92-4b6f-978b-17448f10d950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13758
466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.13758466
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3814436548
Short name T1062
Test name
Test status
Simulation time 10051565789 ps
CPU time 14.1 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205304 kb
Host smart-f67cef2a-890c-43e6-abc9-afc8f50d4509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
36548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3814436548
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.80445799
Short name T1587
Test name
Test status
Simulation time 28926336475 ps
CPU time 51.71 seconds
Started May 26 01:36:33 PM PDT 24
Finished May 26 01:37:25 PM PDT 24
Peak memory 205236 kb
Host smart-f62495ac-3d68-4088-ad8d-79baea02e15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80445
799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.80445799
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.105492377
Short name T26
Test name
Test status
Simulation time 10092275570 ps
CPU time 15.16 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:50 PM PDT 24
Peak memory 205252 kb
Host smart-e794f0e8-2258-4a40-bf36-a745a6e6e45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10549
2377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.105492377
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2502147522
Short name T1677
Test name
Test status
Simulation time 10106835903 ps
CPU time 13.87 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205268 kb
Host smart-2567f40d-255c-4062-b718-95570f46bde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25021
47522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2502147522
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.905316245
Short name T311
Test name
Test status
Simulation time 10078324872 ps
CPU time 13.93 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205336 kb
Host smart-08b9ff4d-2779-4a93-9483-d7dc8bc3bf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90531
6245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.905316245
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3791468721
Short name T366
Test name
Test status
Simulation time 10036157360 ps
CPU time 13.45 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205236 kb
Host smart-68989fd7-4cca-436b-9d9f-ec4167bd5c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37914
68721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3791468721
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2478337710
Short name T1543
Test name
Test status
Simulation time 10093816397 ps
CPU time 16.53 seconds
Started May 26 01:36:33 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205252 kb
Host smart-048156db-b0a5-48e3-807b-40b1984e4499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24783
37710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2478337710
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2945727711
Short name T934
Test name
Test status
Simulation time 10050398739 ps
CPU time 14.23 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205212 kb
Host smart-5374e400-5865-48bd-ba7d-8275c6745118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29457
27711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2945727711
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.128462511
Short name T1903
Test name
Test status
Simulation time 10123710528 ps
CPU time 15.89 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205336 kb
Host smart-40658f1a-7278-48b6-80f8-2338fbe38012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12846
2511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.128462511
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.67982946
Short name T346
Test name
Test status
Simulation time 10052212944 ps
CPU time 15.13 seconds
Started May 26 01:36:34 PM PDT 24
Finished May 26 01:36:51 PM PDT 24
Peak memory 205280 kb
Host smart-454efb9c-af6a-4592-a92f-7604e986930b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67982
946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.67982946
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.19911019
Short name T523
Test name
Test status
Simulation time 10079889747 ps
CPU time 13.87 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:52 PM PDT 24
Peak memory 205308 kb
Host smart-98b85bc2-24c7-42fc-9763-dbb4d29928cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19911
019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.19911019
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.788474063
Short name T1681
Test name
Test status
Simulation time 10150205327 ps
CPU time 15.3 seconds
Started May 26 01:36:50 PM PDT 24
Finished May 26 01:37:06 PM PDT 24
Peak memory 205284 kb
Host smart-1aacace7-c0d2-4ddf-ac4d-5b76b73f0de9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=788474063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.788474063
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.1400566376
Short name T690
Test name
Test status
Simulation time 10087951253 ps
CPU time 13.86 seconds
Started May 26 01:36:53 PM PDT 24
Finished May 26 01:37:08 PM PDT 24
Peak memory 205252 kb
Host smart-d9351f65-082e-4cd6-9e12-f0930ef5e174
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1400566376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.1400566376
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3146135973
Short name T248
Test name
Test status
Simulation time 10174190491 ps
CPU time 15.36 seconds
Started May 26 01:36:53 PM PDT 24
Finished May 26 01:37:09 PM PDT 24
Peak memory 205360 kb
Host smart-27086b6d-d7a1-44a6-809c-2a21292f960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31461
35973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3146135973
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1370862002
Short name T1289
Test name
Test status
Simulation time 13389299750 ps
CPU time 17.77 seconds
Started May 26 01:36:36 PM PDT 24
Finished May 26 01:36:55 PM PDT 24
Peak memory 205296 kb
Host smart-05221a62-aa40-416d-b61b-9d09c14cefcb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1370862002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1370862002
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.46056667
Short name T1726
Test name
Test status
Simulation time 13339260026 ps
CPU time 18.62 seconds
Started May 26 01:36:44 PM PDT 24
Finished May 26 01:37:04 PM PDT 24
Peak memory 205316 kb
Host smart-c3b59fc7-85f0-482b-9c3a-26d5ca16a957
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=46056667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.46056667
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.834725629
Short name T6
Test name
Test status
Simulation time 13201208427 ps
CPU time 19.19 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:37:02 PM PDT 24
Peak memory 205368 kb
Host smart-178af140-fc61-4d66-a977-cac6bd28f703
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=834725629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.834725629
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3987086009
Short name T1594
Test name
Test status
Simulation time 10058727021 ps
CPU time 16.05 seconds
Started May 26 01:36:41 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205264 kb
Host smart-b8c33ff2-7f02-479d-a5db-48ed387ac00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
86009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3987086009
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3293931655
Short name T1293
Test name
Test status
Simulation time 10045562873 ps
CPU time 14.51 seconds
Started May 26 01:36:46 PM PDT 24
Finished May 26 01:37:02 PM PDT 24
Peak memory 205168 kb
Host smart-3536db6f-fb26-4a68-a70e-308c27f6bbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32939
31655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3293931655
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1712303990
Short name T1320
Test name
Test status
Simulation time 10810142972 ps
CPU time 14.63 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:36:59 PM PDT 24
Peak memory 205236 kb
Host smart-f4bbf6e7-78f1-4991-a183-eee0bd427a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17123
03990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1712303990
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.4106802842
Short name T1839
Test name
Test status
Simulation time 10032433072 ps
CPU time 15.5 seconds
Started May 26 01:36:41 PM PDT 24
Finished May 26 01:36:57 PM PDT 24
Peak memory 205216 kb
Host smart-e7b4f905-749c-47a8-9f5a-9be346f1788b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41068
02842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.4106802842
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3725864478
Short name T493
Test name
Test status
Simulation time 10056397831 ps
CPU time 13.38 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205364 kb
Host smart-7df8da74-6527-4504-9c02-0a1963cdfa77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
64478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3725864478
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.416137476
Short name T1142
Test name
Test status
Simulation time 10810133549 ps
CPU time 15.15 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205280 kb
Host smart-a71bcbdf-fe78-4c67-a121-f09e07b47d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41613
7476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.416137476
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3726091342
Short name T420
Test name
Test status
Simulation time 10163330872 ps
CPU time 15.36 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:36:59 PM PDT 24
Peak memory 205256 kb
Host smart-57ded6a0-c515-41f6-bf85-3f72602a750a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
91342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3726091342
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3605538359
Short name T926
Test name
Test status
Simulation time 10171659839 ps
CPU time 13.19 seconds
Started May 26 01:36:48 PM PDT 24
Finished May 26 01:37:02 PM PDT 24
Peak memory 205260 kb
Host smart-0b0c118b-4017-4c21-a4fd-8fb24cfcf9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36055
38359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3605538359
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.444098667
Short name T1530
Test name
Test status
Simulation time 10043943680 ps
CPU time 14.05 seconds
Started May 26 01:36:45 PM PDT 24
Finished May 26 01:37:00 PM PDT 24
Peak memory 204024 kb
Host smart-3288ad83-d1b8-4cfa-b030-2c74e7a74542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44409
8667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.444098667
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2553517767
Short name T639
Test name
Test status
Simulation time 10109269245 ps
CPU time 14.39 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205200 kb
Host smart-51b79d95-3d22-43e9-a2ed-0662b6f66c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25535
17767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2553517767
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2653213243
Short name T367
Test name
Test status
Simulation time 10136443220 ps
CPU time 17.6 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:37:02 PM PDT 24
Peak memory 205212 kb
Host smart-ce565a61-5d99-4079-b37c-4277d6be2855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26532
13243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2653213243
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.629452515
Short name T833
Test name
Test status
Simulation time 13255097204 ps
CPU time 21.26 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:37:06 PM PDT 24
Peak memory 205300 kb
Host smart-b52902cd-0bb4-42c1-a62d-818aa7c2adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62945
2515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.629452515
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3900921761
Short name T322
Test name
Test status
Simulation time 10096084577 ps
CPU time 17 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:37:02 PM PDT 24
Peak memory 205272 kb
Host smart-339eb14f-4482-4258-b63f-b82744e68ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
21761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3900921761
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.780171873
Short name T869
Test name
Test status
Simulation time 10104801884 ps
CPU time 15.05 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205292 kb
Host smart-9bc88781-97d1-4cf2-8abc-541e6f3a0d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78017
1873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.780171873
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.866843182
Short name T93
Test name
Test status
Simulation time 10096349742 ps
CPU time 14.5 seconds
Started May 26 01:36:44 PM PDT 24
Finished May 26 01:37:00 PM PDT 24
Peak memory 205268 kb
Host smart-e3b024d0-cc9b-4763-8c4d-583ea54e819f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86684
3182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.866843182
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1538488137
Short name T1718
Test name
Test status
Simulation time 10124478410 ps
CPU time 14.48 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:36:59 PM PDT 24
Peak memory 205288 kb
Host smart-34fcb2e2-d8e6-4281-b9cc-bfbceef88424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
88137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1538488137
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2978255546
Short name T788
Test name
Test status
Simulation time 10057214150 ps
CPU time 17.47 seconds
Started May 26 01:36:46 PM PDT 24
Finished May 26 01:37:05 PM PDT 24
Peak memory 205212 kb
Host smart-0cc6a530-22f6-40fa-97bb-9df052361fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782
55546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2978255546
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1696759657
Short name T1331
Test name
Test status
Simulation time 10082107088 ps
CPU time 14.12 seconds
Started May 26 01:36:45 PM PDT 24
Finished May 26 01:37:00 PM PDT 24
Peak memory 205248 kb
Host smart-58364a49-e68a-4761-b202-59a4369d43d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16967
59657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1696759657
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3469651193
Short name T180
Test name
Test status
Simulation time 10074731158 ps
CPU time 15.74 seconds
Started May 26 01:36:42 PM PDT 24
Finished May 26 01:36:59 PM PDT 24
Peak memory 205284 kb
Host smart-48dddc52-f813-49f7-8fce-46dcc933178d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34696
51193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3469651193
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.481026536
Short name T1301
Test name
Test status
Simulation time 10097025044 ps
CPU time 15.44 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:37:00 PM PDT 24
Peak memory 205224 kb
Host smart-401dd030-e89f-42c9-984a-c6d0f251180e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48102
6536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.481026536
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2199290148
Short name T1420
Test name
Test status
Simulation time 10039855838 ps
CPU time 12.7 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:36:57 PM PDT 24
Peak memory 205188 kb
Host smart-8f53a0d9-a9d7-4c10-af8c-ac86edcc5f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21992
90148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2199290148
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2802472126
Short name T1595
Test name
Test status
Simulation time 10073967478 ps
CPU time 12.94 seconds
Started May 26 01:36:50 PM PDT 24
Finished May 26 01:37:04 PM PDT 24
Peak memory 205268 kb
Host smart-92b7e74a-abbc-4555-821b-2255acbb690d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28024
72126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2802472126
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1601710335
Short name T973
Test name
Test status
Simulation time 22213716015 ps
CPU time 47.31 seconds
Started May 26 01:36:44 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205320 kb
Host smart-92ab1b5a-df50-4c2c-8b3b-97a5fa082f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16017
10335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1601710335
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3194495941
Short name T1808
Test name
Test status
Simulation time 10071345087 ps
CPU time 16.18 seconds
Started May 26 01:36:41 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205284 kb
Host smart-7062d386-2b72-456d-9cde-1e5a70fbc14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31944
95941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3194495941
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3273553981
Short name T749
Test name
Test status
Simulation time 10059443239 ps
CPU time 15.88 seconds
Started May 26 01:36:45 PM PDT 24
Finished May 26 01:37:02 PM PDT 24
Peak memory 204124 kb
Host smart-b6d012c4-9482-46d0-9582-1f7826fc1a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32735
53981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3273553981
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.596108323
Short name T1869
Test name
Test status
Simulation time 10099504581 ps
CPU time 13.39 seconds
Started May 26 01:36:44 PM PDT 24
Finished May 26 01:36:58 PM PDT 24
Peak memory 205276 kb
Host smart-4ed951fa-752e-42f4-9f9c-f6589518317b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59610
8323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.596108323
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2842393049
Short name T598
Test name
Test status
Simulation time 10046781175 ps
CPU time 15.91 seconds
Started May 26 01:36:46 PM PDT 24
Finished May 26 01:37:03 PM PDT 24
Peak memory 205172 kb
Host smart-4a66f214-c2dc-4262-b04f-7a1bc59996f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28423
93049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2842393049
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1634958778
Short name T154
Test name
Test status
Simulation time 10083970604 ps
CPU time 14.14 seconds
Started May 26 01:36:44 PM PDT 24
Finished May 26 01:36:59 PM PDT 24
Peak memory 205324 kb
Host smart-4a2f4db5-d2eb-4fd8-8b3a-b14be80135cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16349
58778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1634958778
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.968149401
Short name T1786
Test name
Test status
Simulation time 10098714040 ps
CPU time 15.63 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:37:00 PM PDT 24
Peak memory 205336 kb
Host smart-bac1a6e8-8cb5-4463-b27f-eecd451b447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96814
9401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.968149401
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2730030251
Short name T1769
Test name
Test status
Simulation time 10124641661 ps
CPU time 15.92 seconds
Started May 26 01:36:37 PM PDT 24
Finished May 26 01:36:54 PM PDT 24
Peak memory 205492 kb
Host smart-8ac50e06-bd40-44dd-bb4b-cf7fa3c0af2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27300
30251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2730030251
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3245088715
Short name T485
Test name
Test status
Simulation time 10103438336 ps
CPU time 13.5 seconds
Started May 26 01:36:43 PM PDT 24
Finished May 26 01:36:57 PM PDT 24
Peak memory 205216 kb
Host smart-6c7604c2-a4ff-4dba-9336-0ab809782afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32450
88715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3245088715
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1400688965
Short name T1591
Test name
Test status
Simulation time 10057993312 ps
CPU time 14.19 seconds
Started May 26 01:36:50 PM PDT 24
Finished May 26 01:37:05 PM PDT 24
Peak memory 205260 kb
Host smart-1766b0d1-9cbb-44e9-9dad-8451b5684345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14006
88965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1400688965
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.218444138
Short name T1704
Test name
Test status
Simulation time 10147558426 ps
CPU time 14.03 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:16 PM PDT 24
Peak memory 205284 kb
Host smart-54bd615b-832a-42a7-ba50-33e1fb2f554a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=218444138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.218444138
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.68592896
Short name T1693
Test name
Test status
Simulation time 10076170268 ps
CPU time 13.54 seconds
Started May 26 01:36:59 PM PDT 24
Finished May 26 01:37:13 PM PDT 24
Peak memory 205244 kb
Host smart-2393c21a-eac2-448c-9276-edc5b94facd0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=68592896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.68592896
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.826177409
Short name T850
Test name
Test status
Simulation time 10095734269 ps
CPU time 14.74 seconds
Started May 26 01:37:07 PM PDT 24
Finished May 26 01:37:22 PM PDT 24
Peak memory 205056 kb
Host smart-79e624f4-60b6-412a-a560-16e97c2ed471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82617
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.826177409
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3133337663
Short name T524
Test name
Test status
Simulation time 14299861461 ps
CPU time 17.14 seconds
Started May 26 01:36:57 PM PDT 24
Finished May 26 01:37:15 PM PDT 24
Peak memory 205280 kb
Host smart-08579329-db9b-446a-a50f-d6b95297907e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3133337663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3133337663
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.31772836
Short name T1200
Test name
Test status
Simulation time 13261281651 ps
CPU time 17.53 seconds
Started May 26 01:36:50 PM PDT 24
Finished May 26 01:37:08 PM PDT 24
Peak memory 205284 kb
Host smart-70111212-ca77-4fb8-9c2a-b0f8568bdd7c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=31772836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.31772836
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2591552899
Short name T397
Test name
Test status
Simulation time 13353604280 ps
CPU time 19.44 seconds
Started May 26 01:36:57 PM PDT 24
Finished May 26 01:37:17 PM PDT 24
Peak memory 205316 kb
Host smart-1ac6df71-6df6-47d4-bb3d-882a13de5905
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2591552899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2591552899
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.72676875
Short name T927
Test name
Test status
Simulation time 10053664065 ps
CPU time 14.62 seconds
Started May 26 01:36:50 PM PDT 24
Finished May 26 01:37:06 PM PDT 24
Peak memory 205256 kb
Host smart-4ee8bcae-49a5-43f5-be60-aff89435a889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72676
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.72676875
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2374341243
Short name T37
Test name
Test status
Simulation time 10833849202 ps
CPU time 16.39 seconds
Started May 26 01:36:53 PM PDT 24
Finished May 26 01:37:10 PM PDT 24
Peak memory 205276 kb
Host smart-6ac537f2-71b4-4ee8-9eaf-742ed1356753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
41243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2374341243
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.402232153
Short name T52
Test name
Test status
Simulation time 10046359061 ps
CPU time 13.54 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:07 PM PDT 24
Peak memory 205272 kb
Host smart-8fdf00e5-822e-4101-bc5c-da6c511f10f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40223
2153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.402232153
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.4248293350
Short name T1936
Test name
Test status
Simulation time 10079309183 ps
CPU time 14.01 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:07 PM PDT 24
Peak memory 205308 kb
Host smart-7923b124-6ab1-4080-bb60-9742e0ea8036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42482
93350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.4248293350
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.909789999
Short name T545
Test name
Test status
Simulation time 10221588669 ps
CPU time 14.74 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:08 PM PDT 24
Peak memory 205288 kb
Host smart-07ffa157-b8a3-4e0f-856e-bda829345003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90978
9999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.909789999
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1539415706
Short name T1805
Test name
Test status
Simulation time 10103798334 ps
CPU time 13.97 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:15 PM PDT 24
Peak memory 205308 kb
Host smart-5122e96f-47fb-467d-a955-ed839a289093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15394
15706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1539415706
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.4123074587
Short name T1047
Test name
Test status
Simulation time 10068852876 ps
CPU time 14.22 seconds
Started May 26 01:37:03 PM PDT 24
Finished May 26 01:37:17 PM PDT 24
Peak memory 205264 kb
Host smart-b70a69c2-07b5-47e1-9d4b-c49018b64ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41230
74587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4123074587
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.956546553
Short name T1506
Test name
Test status
Simulation time 10070706628 ps
CPU time 13.77 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:07 PM PDT 24
Peak memory 205268 kb
Host smart-2c8449e3-c1bc-4a33-b15a-9abc20b278e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95654
6553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.956546553
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1089026895
Short name T403
Test name
Test status
Simulation time 10088128956 ps
CPU time 14.81 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:08 PM PDT 24
Peak memory 205220 kb
Host smart-58ba6d60-d3e8-4bf5-a77e-45d84a66d7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10890
26895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1089026895
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3355021360
Short name T1226
Test name
Test status
Simulation time 13290449827 ps
CPU time 17.44 seconds
Started May 26 01:36:57 PM PDT 24
Finished May 26 01:37:15 PM PDT 24
Peak memory 205260 kb
Host smart-63397c78-bd6f-4d4b-80e7-b15190e8ec4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33550
21360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3355021360
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1114031083
Short name T672
Test name
Test status
Simulation time 10095869095 ps
CPU time 13.54 seconds
Started May 26 01:36:51 PM PDT 24
Finished May 26 01:37:05 PM PDT 24
Peak memory 205480 kb
Host smart-099eab20-4c23-49f9-8c8a-78d5d5264ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11140
31083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1114031083
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2038707395
Short name T701
Test name
Test status
Simulation time 10057888265 ps
CPU time 15.7 seconds
Started May 26 01:36:54 PM PDT 24
Finished May 26 01:37:11 PM PDT 24
Peak memory 205268 kb
Host smart-2e3bf8f3-fe49-4515-bcc2-ccd12d8bc8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
07395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2038707395
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2872239899
Short name T1298
Test name
Test status
Simulation time 10085078909 ps
CPU time 13.64 seconds
Started May 26 01:36:57 PM PDT 24
Finished May 26 01:37:11 PM PDT 24
Peak memory 205256 kb
Host smart-18c9f5af-aeb6-4924-bc3b-bad363308afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28722
39899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2872239899
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3664220104
Short name T785
Test name
Test status
Simulation time 10089121870 ps
CPU time 15.56 seconds
Started May 26 01:36:53 PM PDT 24
Finished May 26 01:37:10 PM PDT 24
Peak memory 205292 kb
Host smart-14e31839-0dcd-440e-8a95-39548f3b9a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
20104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3664220104
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1902118529
Short name T923
Test name
Test status
Simulation time 10097876486 ps
CPU time 14.43 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:08 PM PDT 24
Peak memory 205452 kb
Host smart-5e9199b7-eed4-4a9a-a3ab-33a4896d4863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021
18529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1902118529
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1542098565
Short name T1432
Test name
Test status
Simulation time 10073479910 ps
CPU time 15.85 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:09 PM PDT 24
Peak memory 205488 kb
Host smart-1643db76-c6d9-498d-a356-877ec2eae863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15420
98565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1542098565
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2079135950
Short name T173
Test name
Test status
Simulation time 10126064748 ps
CPU time 14.76 seconds
Started May 26 01:36:59 PM PDT 24
Finished May 26 01:37:14 PM PDT 24
Peak memory 205304 kb
Host smart-3cb90e19-557f-4656-b5ea-b7bee7bdf547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20791
35950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2079135950
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.2911040231
Short name T1766
Test name
Test status
Simulation time 10076878639 ps
CPU time 16.34 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:17 PM PDT 24
Peak memory 205280 kb
Host smart-4b351476-4def-4b58-9877-89ba68106bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29110
40231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.2911040231
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.414092874
Short name T610
Test name
Test status
Simulation time 10083024060 ps
CPU time 15.1 seconds
Started May 26 01:36:59 PM PDT 24
Finished May 26 01:37:15 PM PDT 24
Peak memory 205360 kb
Host smart-eb905fec-8b67-430e-b0f5-7a2559cb742d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
2874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.414092874
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2817858656
Short name T1652
Test name
Test status
Simulation time 10040419890 ps
CPU time 14.63 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:17 PM PDT 24
Peak memory 205240 kb
Host smart-e6e349dd-572f-4e2b-a0f5-b56176fd8599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28178
58656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2817858656
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3916799129
Short name T255
Test name
Test status
Simulation time 17398880322 ps
CPU time 29.78 seconds
Started May 26 01:36:51 PM PDT 24
Finished May 26 01:37:22 PM PDT 24
Peak memory 205340 kb
Host smart-5f66f70e-f543-45b6-97e2-86e99ff9d53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39167
99129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3916799129
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2465668995
Short name T1441
Test name
Test status
Simulation time 10072416271 ps
CPU time 15.24 seconds
Started May 26 01:36:53 PM PDT 24
Finished May 26 01:37:09 PM PDT 24
Peak memory 205356 kb
Host smart-56abc332-6926-4bd9-bb5d-2ea22f68bab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24656
68995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2465668995
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.2450592978
Short name T368
Test name
Test status
Simulation time 10129316287 ps
CPU time 17.43 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:10 PM PDT 24
Peak memory 205208 kb
Host smart-7cf8a48a-d1a4-46cf-b89f-fb6ade87da11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24505
92978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2450592978
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.2058826023
Short name T1449
Test name
Test status
Simulation time 10052821041 ps
CPU time 14.16 seconds
Started May 26 01:36:51 PM PDT 24
Finished May 26 01:37:06 PM PDT 24
Peak memory 205248 kb
Host smart-6e00ad9f-1927-4699-b3a1-49876ab5a66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20588
26023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.2058826023
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2486110542
Short name T1404
Test name
Test status
Simulation time 10036669652 ps
CPU time 13.64 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:16 PM PDT 24
Peak memory 205276 kb
Host smart-8854eb1c-5692-4842-9645-4e87f93e0bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24861
10542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2486110542
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1214863221
Short name T908
Test name
Test status
Simulation time 10048889433 ps
CPU time 13.55 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:16 PM PDT 24
Peak memory 205276 kb
Host smart-957c61eb-4a1f-41d6-9d78-9462fe74ea18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148
63221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1214863221
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3494162469
Short name T819
Test name
Test status
Simulation time 10085678765 ps
CPU time 15.95 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:17 PM PDT 24
Peak memory 205220 kb
Host smart-ee4c9e99-b63b-45e3-a8ba-743a68b793c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34941
62469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3494162469
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1513323424
Short name T147
Test name
Test status
Simulation time 10124562900 ps
CPU time 14.58 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:08 PM PDT 24
Peak memory 205188 kb
Host smart-960e9c2c-7293-4ed1-a244-4c80f71b8f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15133
23424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1513323424
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2377039606
Short name T709
Test name
Test status
Simulation time 10067343188 ps
CPU time 16.98 seconds
Started May 26 01:36:59 PM PDT 24
Finished May 26 01:37:16 PM PDT 24
Peak memory 205240 kb
Host smart-9a716806-c95c-4d41-9a44-4f5abdede2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23770
39606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2377039606
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1006859355
Short name T1888
Test name
Test status
Simulation time 10086921265 ps
CPU time 13.81 seconds
Started May 26 01:36:52 PM PDT 24
Finished May 26 01:37:07 PM PDT 24
Peak memory 205308 kb
Host smart-b2fde0e0-1fc5-42a1-8639-4aa9c86a5e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10068
59355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1006859355
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3684609265
Short name T732
Test name
Test status
Simulation time 10177054927 ps
CPU time 17.69 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:37 PM PDT 24
Peak memory 205276 kb
Host smart-1bdb91f6-f0b0-4036-ab27-9900830da143
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3684609265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3684609265
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.59399384
Short name T351
Test name
Test status
Simulation time 10047552242 ps
CPU time 14.46 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 204524 kb
Host smart-f9415eca-d8c4-44b4-a9f3-e76ae7665d5a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=59399384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.59399384
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.37432611
Short name T399
Test name
Test status
Simulation time 10124233873 ps
CPU time 13.06 seconds
Started May 26 01:37:22 PM PDT 24
Finished May 26 01:37:36 PM PDT 24
Peak memory 205308 kb
Host smart-6e343cd8-8edd-4384-803c-b195472f21ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37432
611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.37432611
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2437225604
Short name T355
Test name
Test status
Simulation time 13708390258 ps
CPU time 17.28 seconds
Started May 26 01:37:07 PM PDT 24
Finished May 26 01:37:25 PM PDT 24
Peak memory 204956 kb
Host smart-73170f83-993c-4767-bac4-da9d629f3f10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2437225604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2437225604
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.105928737
Short name T427
Test name
Test status
Simulation time 13264140089 ps
CPU time 17.35 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:18 PM PDT 24
Peak memory 205316 kb
Host smart-ee0029f1-6f64-4966-ba8f-f0af1b2000c6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=105928737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.105928737
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3573963732
Short name T1814
Test name
Test status
Simulation time 13351305172 ps
CPU time 17.28 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:18 PM PDT 24
Peak memory 205308 kb
Host smart-37dfad4e-86cc-4c5e-8e43-7546a3379da7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3573963732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3573963732
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2689241678
Short name T438
Test name
Test status
Simulation time 10071275268 ps
CPU time 16.92 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:19 PM PDT 24
Peak memory 205172 kb
Host smart-6939b2e3-d86b-4dc6-b97d-ebbe529c1965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26892
41678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2689241678
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1181057661
Short name T985
Test name
Test status
Simulation time 10670218324 ps
CPU time 17.32 seconds
Started May 26 01:37:02 PM PDT 24
Finished May 26 01:37:20 PM PDT 24
Peak memory 205348 kb
Host smart-2b85d5cd-3e6b-406e-b6d5-10c8834224f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11810
57661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1181057661
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3143476774
Short name T729
Test name
Test status
Simulation time 10082774427 ps
CPU time 14.56 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:17 PM PDT 24
Peak memory 205232 kb
Host smart-ff7d5bc6-e483-439f-9691-36f44f0899af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31434
76774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3143476774
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.965932377
Short name T1623
Test name
Test status
Simulation time 10041855313 ps
CPU time 17.15 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:18 PM PDT 24
Peak memory 205260 kb
Host smart-1bae23f5-db9c-42dd-aa92-8d4c3115bb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96593
2377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.965932377
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.704382299
Short name T409
Test name
Test status
Simulation time 10241004924 ps
CPU time 15.5 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:18 PM PDT 24
Peak memory 205232 kb
Host smart-51d09845-24f2-4576-837c-59d7060d613c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70438
2299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.704382299
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1230243272
Short name T1191
Test name
Test status
Simulation time 10177629396 ps
CPU time 16.23 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:25 PM PDT 24
Peak memory 205296 kb
Host smart-0dda9d1b-08d8-4c26-aa2d-4822632f7d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12302
43272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1230243272
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3089582760
Short name T1891
Test name
Test status
Simulation time 10038758654 ps
CPU time 13.66 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:22 PM PDT 24
Peak memory 205192 kb
Host smart-e4a1bf05-c4de-4305-b254-e502d3bef27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30895
82760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3089582760
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.721399081
Short name T1627
Test name
Test status
Simulation time 10104804789 ps
CPU time 15.36 seconds
Started May 26 01:37:06 PM PDT 24
Finished May 26 01:37:22 PM PDT 24
Peak memory 205320 kb
Host smart-77382369-6b30-416b-b781-b1fade2ad9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72139
9081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.721399081
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3449234176
Short name T1897
Test name
Test status
Simulation time 10123702071 ps
CPU time 13.7 seconds
Started May 26 01:37:00 PM PDT 24
Finished May 26 01:37:14 PM PDT 24
Peak memory 205228 kb
Host smart-d67c2853-8afc-4f7d-8475-f18321d49c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34492
34176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3449234176
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2160089623
Short name T1156
Test name
Test status
Simulation time 13163592140 ps
CPU time 16.45 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:18 PM PDT 24
Peak memory 205204 kb
Host smart-8c8d057c-127c-4c10-94ed-4bd5dcbe3bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21600
89623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2160089623
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.214573766
Short name T339
Test name
Test status
Simulation time 10118848389 ps
CPU time 13.95 seconds
Started May 26 01:37:04 PM PDT 24
Finished May 26 01:37:19 PM PDT 24
Peak memory 205260 kb
Host smart-2113a88b-0865-4f71-a2f7-b7761d867374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
3766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.214573766
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.163437298
Short name T1263
Test name
Test status
Simulation time 10046453786 ps
CPU time 17.13 seconds
Started May 26 01:36:58 PM PDT 24
Finished May 26 01:37:16 PM PDT 24
Peak memory 205260 kb
Host smart-67e824a7-9e5a-41e3-a64d-52d764c096b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16343
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.163437298
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1433126987
Short name T125
Test name
Test status
Simulation time 10187763513 ps
CPU time 14.49 seconds
Started May 26 01:36:59 PM PDT 24
Finished May 26 01:37:14 PM PDT 24
Peak memory 205268 kb
Host smart-a2e8aeda-e80f-41e1-8db9-b8b0574188b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
26987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1433126987
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1082551448
Short name T548
Test name
Test status
Simulation time 10095400026 ps
CPU time 15.19 seconds
Started May 26 01:37:05 PM PDT 24
Finished May 26 01:37:21 PM PDT 24
Peak memory 205212 kb
Host smart-0ac1eb43-e45d-45d9-93dd-d9f59f13c6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10825
51448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1082551448
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.3729153224
Short name T1165
Test name
Test status
Simulation time 10079442793 ps
CPU time 14.46 seconds
Started May 26 01:37:06 PM PDT 24
Finished May 26 01:37:21 PM PDT 24
Peak memory 205352 kb
Host smart-4050c3d3-5aef-49af-a452-d9e587905ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
53224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.3729153224
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3511577990
Short name T1402
Test name
Test status
Simulation time 10084589583 ps
CPU time 14.64 seconds
Started May 26 01:37:01 PM PDT 24
Finished May 26 01:37:16 PM PDT 24
Peak memory 205332 kb
Host smart-397a582b-81af-4bdf-ae69-cebbcb0047c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35115
77990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3511577990
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2997594790
Short name T193
Test name
Test status
Simulation time 10100116179 ps
CPU time 16.53 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:25 PM PDT 24
Peak memory 205320 kb
Host smart-5f8cd608-08da-4d35-b683-ddda1947e4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
94790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2997594790
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.2313141895
Short name T1553
Test name
Test status
Simulation time 10090209026 ps
CPU time 16.22 seconds
Started May 26 01:37:06 PM PDT 24
Finished May 26 01:37:23 PM PDT 24
Peak memory 205300 kb
Host smart-66a7fddf-19b3-416b-b69f-7018c79738c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23131
41895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.2313141895
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3191027238
Short name T745
Test name
Test status
Simulation time 10041259926 ps
CPU time 16.46 seconds
Started May 26 01:37:07 PM PDT 24
Finished May 26 01:37:25 PM PDT 24
Peak memory 205260 kb
Host smart-9a575cb6-0709-4300-8678-369d03fe2cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31910
27238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3191027238
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.496371401
Short name T1702
Test name
Test status
Simulation time 10034116959 ps
CPU time 16.16 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:25 PM PDT 24
Peak memory 205280 kb
Host smart-173732a0-e50f-4759-9364-7759fb67c838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49637
1401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.496371401
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3799373258
Short name T1833
Test name
Test status
Simulation time 25817905276 ps
CPU time 49.66 seconds
Started May 26 01:37:04 PM PDT 24
Finished May 26 01:37:55 PM PDT 24
Peak memory 205284 kb
Host smart-e59a6cb0-c328-4b4b-97a5-5a9b6ebcd62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37993
73258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3799373258
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3738355570
Short name T1602
Test name
Test status
Simulation time 10088405658 ps
CPU time 13.91 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:23 PM PDT 24
Peak memory 205276 kb
Host smart-84e2c1df-8f5f-45e1-a3fe-4db658e8f772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37383
55570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3738355570
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3804476307
Short name T1140
Test name
Test status
Simulation time 10067367052 ps
CPU time 12.91 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:21 PM PDT 24
Peak memory 205236 kb
Host smart-1f064871-f0b6-4480-ad75-094812577a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38044
76307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3804476307
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.2677489792
Short name T550
Test name
Test status
Simulation time 10056591581 ps
CPU time 14.15 seconds
Started May 26 01:37:07 PM PDT 24
Finished May 26 01:37:22 PM PDT 24
Peak memory 205264 kb
Host smart-d52f8f3b-b3a5-400c-a78a-500d66c6bbab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26774
89792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.2677489792
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3731423192
Short name T738
Test name
Test status
Simulation time 10060148549 ps
CPU time 13.83 seconds
Started May 26 01:37:06 PM PDT 24
Finished May 26 01:37:21 PM PDT 24
Peak memory 205316 kb
Host smart-ea064e39-baef-4d11-9fb9-824c374cd05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37314
23192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3731423192
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3223582516
Short name T816
Test name
Test status
Simulation time 10091497154 ps
CPU time 13.35 seconds
Started May 26 01:37:09 PM PDT 24
Finished May 26 01:37:23 PM PDT 24
Peak memory 205236 kb
Host smart-5fd332c4-f41f-404a-999f-5ac5387f0a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32235
82516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3223582516
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.977960192
Short name T1584
Test name
Test status
Simulation time 10106931606 ps
CPU time 17.1 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:26 PM PDT 24
Peak memory 205360 kb
Host smart-9c9694c9-c066-443c-808b-3804baf9adb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97796
0192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.977960192
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1748477496
Short name T874
Test name
Test status
Simulation time 10106897968 ps
CPU time 13.92 seconds
Started May 26 01:36:59 PM PDT 24
Finished May 26 01:37:14 PM PDT 24
Peak memory 205496 kb
Host smart-f8bb6ce6-7ec7-4e69-8e85-90dbc363f197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17484
77496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1748477496
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2236575029
Short name T317
Test name
Test status
Simulation time 10090422685 ps
CPU time 17.08 seconds
Started May 26 01:37:11 PM PDT 24
Finished May 26 01:37:29 PM PDT 24
Peak memory 205312 kb
Host smart-b3b20e0f-c394-4578-a0ea-01fdf4d66cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
75029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2236575029
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3782035492
Short name T601
Test name
Test status
Simulation time 10090545933 ps
CPU time 13.69 seconds
Started May 26 01:37:08 PM PDT 24
Finished May 26 01:37:22 PM PDT 24
Peak memory 205296 kb
Host smart-8ef746a6-0a56-4ae8-ae07-421b1a4b30ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37820
35492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3782035492
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3625290972
Short name T1405
Test name
Test status
Simulation time 10151948351 ps
CPU time 14.82 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:41 PM PDT 24
Peak memory 205280 kb
Host smart-86547476-0a71-42b1-ae5c-57c860ca9bf3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3625290972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3625290972
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.962907530
Short name T329
Test name
Test status
Simulation time 10064376073 ps
CPU time 14.23 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205272 kb
Host smart-98a340b4-887c-4b3c-a343-4be846e6e304
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=962907530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.962907530
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.4205508703
Short name T1290
Test name
Test status
Simulation time 10069346513 ps
CPU time 14.43 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205244 kb
Host smart-ed8d4f69-1edf-4896-995d-cf09ec8ab0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
08703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.4205508703
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1094747566
Short name T904
Test name
Test status
Simulation time 13329450616 ps
CPU time 19.87 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:39 PM PDT 24
Peak memory 205328 kb
Host smart-27d9e50c-a675-47f2-9475-7b628d40091a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1094747566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1094747566
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1697221360
Short name T1238
Test name
Test status
Simulation time 13292437228 ps
CPU time 17.83 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:37 PM PDT 24
Peak memory 205176 kb
Host smart-42d85388-eb07-4143-85ba-8aaecde2d03e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1697221360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1697221360
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.4043132586
Short name T10
Test name
Test status
Simulation time 13254203919 ps
CPU time 19.15 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:36 PM PDT 24
Peak memory 205312 kb
Host smart-a42f5c78-e955-4ae8-b0f7-865c19996ed3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4043132586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.4043132586
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1283774434
Short name T667
Test name
Test status
Simulation time 10075152697 ps
CPU time 16.4 seconds
Started May 26 01:37:22 PM PDT 24
Finished May 26 01:37:39 PM PDT 24
Peak memory 205256 kb
Host smart-f5a184b2-5e74-45c8-b18b-f44df45ac2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12837
74434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1283774434
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3730415006
Short name T1318
Test name
Test status
Simulation time 10578352598 ps
CPU time 16.66 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:35 PM PDT 24
Peak memory 205316 kb
Host smart-654b3f7c-71ad-47c3-b7b4-ee3e1ffdce18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37304
15006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3730415006
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1227995163
Short name T809
Test name
Test status
Simulation time 10055741963 ps
CPU time 13.43 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 205108 kb
Host smart-93e8c984-1c3e-46a4-b1d8-016dc0654ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12279
95163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1227995163
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.1771230476
Short name T365
Test name
Test status
Simulation time 10044112871 ps
CPU time 13.3 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205316 kb
Host smart-598f6744-5bf3-4a1d-a29f-7904ba3496e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17712
30476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1771230476
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1269934767
Short name T1828
Test name
Test status
Simulation time 10701207190 ps
CPU time 16.47 seconds
Started May 26 01:37:19 PM PDT 24
Finished May 26 01:37:36 PM PDT 24
Peak memory 205284 kb
Host smart-696a03e3-952c-451a-8b59-424484ceb11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699
34767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1269934767
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3590486266
Short name T253
Test name
Test status
Simulation time 10209357598 ps
CPU time 16.61 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:34 PM PDT 24
Peak memory 205276 kb
Host smart-eacfa58d-d429-4ea5-80c9-41f088215831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904
86266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3590486266
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1151073726
Short name T898
Test name
Test status
Simulation time 10144112279 ps
CPU time 15.58 seconds
Started May 26 01:37:16 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205236 kb
Host smart-49af6acc-76d8-4438-b2d6-4104395909cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11510
73726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1151073726
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.562976838
Short name T1916
Test name
Test status
Simulation time 10060570137 ps
CPU time 13.78 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 205220 kb
Host smart-ba95473b-1c93-4ca5-bd54-5e3990a46c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56297
6838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.562976838
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2826676326
Short name T541
Test name
Test status
Simulation time 10141150177 ps
CPU time 17.04 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:36 PM PDT 24
Peak memory 205320 kb
Host smart-0787cfeb-c844-4c10-9978-293fea28edd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
76326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2826676326
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.128703851
Short name T349
Test name
Test status
Simulation time 10062167145 ps
CPU time 14.71 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:34 PM PDT 24
Peak memory 205284 kb
Host smart-7dd7d173-b2f3-4064-b810-aa4c786422e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12870
3851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.128703851
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3188401584
Short name T344
Test name
Test status
Simulation time 13202112529 ps
CPU time 19.53 seconds
Started May 26 01:37:16 PM PDT 24
Finished May 26 01:37:37 PM PDT 24
Peak memory 205168 kb
Host smart-b7b526eb-6791-4d23-bd7b-a0677c61e516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
01584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3188401584
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3630416948
Short name T1338
Test name
Test status
Simulation time 10097791038 ps
CPU time 13.33 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:31 PM PDT 24
Peak memory 205284 kb
Host smart-4c5c0b8b-e165-42c7-b06a-e405a34bf660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
16948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3630416948
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1250095279
Short name T498
Test name
Test status
Simulation time 10044605802 ps
CPU time 14.78 seconds
Started May 26 01:37:23 PM PDT 24
Finished May 26 01:37:38 PM PDT 24
Peak memory 205288 kb
Host smart-24e5a68c-ceeb-4295-b731-4c1ab6eb4f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12500
95279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1250095279
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3304283523
Short name T1604
Test name
Test status
Simulation time 10119857423 ps
CPU time 13.93 seconds
Started May 26 01:37:16 PM PDT 24
Finished May 26 01:37:30 PM PDT 24
Peak memory 205252 kb
Host smart-c15c4121-a52a-4560-8029-09f3cba47df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33042
83523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3304283523
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1070134024
Short name T883
Test name
Test status
Simulation time 10107302617 ps
CPU time 13.77 seconds
Started May 26 01:37:22 PM PDT 24
Finished May 26 01:37:36 PM PDT 24
Peak memory 205244 kb
Host smart-579aefa9-c235-4338-9d94-ed7656d64318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
34024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1070134024
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.643527939
Short name T839
Test name
Test status
Simulation time 10078700289 ps
CPU time 13.21 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205308 kb
Host smart-c1afb8ab-921b-405b-a31d-5b7b23591eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64352
7939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.643527939
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2508428662
Short name T1922
Test name
Test status
Simulation time 10059525734 ps
CPU time 16.44 seconds
Started May 26 01:37:16 PM PDT 24
Finished May 26 01:37:34 PM PDT 24
Peak memory 205304 kb
Host smart-588a7816-b961-4804-a2ba-6901c3adf1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
28662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2508428662
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3475635770
Short name T1672
Test name
Test status
Simulation time 10079764536 ps
CPU time 14.21 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205284 kb
Host smart-039043cb-88b8-44a8-a026-833e1750844e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
35770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3475635770
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.1547771749
Short name T1899
Test name
Test status
Simulation time 10067664341 ps
CPU time 12.87 seconds
Started May 26 01:37:20 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 205224 kb
Host smart-e08a668f-2e9f-414b-801d-44fb23203378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15477
71749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.1547771749
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.300692190
Short name T458
Test name
Test status
Simulation time 10037541676 ps
CPU time 13.44 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 204616 kb
Host smart-76aa5140-6406-49e2-bab6-8dbc2af066b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30069
2190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.300692190
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.4021209516
Short name T1477
Test name
Test status
Simulation time 10032430127 ps
CPU time 16.01 seconds
Started May 26 01:37:21 PM PDT 24
Finished May 26 01:37:38 PM PDT 24
Peak memory 205204 kb
Host smart-4b595c8e-f8f6-49fc-8654-d9508be725d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40212
09516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.4021209516
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2504080836
Short name T257
Test name
Test status
Simulation time 32544460885 ps
CPU time 68.25 seconds
Started May 26 01:37:22 PM PDT 24
Finished May 26 01:38:31 PM PDT 24
Peak memory 205336 kb
Host smart-c57cf4af-4fef-4a14-b15c-2f1e3789141d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040
80836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2504080836
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.950917500
Short name T1682
Test name
Test status
Simulation time 10056592365 ps
CPU time 15.34 seconds
Started May 26 01:37:16 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205312 kb
Host smart-873fd19a-08c7-4da3-af6d-494bcd59cea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95091
7500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.950917500
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.136540539
Short name T961
Test name
Test status
Simulation time 10094148233 ps
CPU time 14.9 seconds
Started May 26 01:37:15 PM PDT 24
Finished May 26 01:37:31 PM PDT 24
Peak memory 205308 kb
Host smart-b0339861-d148-42bb-b1a3-4b27ea614074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13654
0539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.136540539
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3032630449
Short name T547
Test name
Test status
Simulation time 10053498880 ps
CPU time 16.44 seconds
Started May 26 01:37:20 PM PDT 24
Finished May 26 01:37:37 PM PDT 24
Peak memory 205208 kb
Host smart-85e5e91b-9c96-4de0-85f1-c3d892eef949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
30449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3032630449
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.112531545
Short name T621
Test name
Test status
Simulation time 10068669073 ps
CPU time 13.44 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:31 PM PDT 24
Peak memory 205288 kb
Host smart-61db78d9-9cae-41c5-9faa-9fc399bfe529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
1545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.112531545
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.2665933358
Short name T138
Test name
Test status
Simulation time 10052611774 ps
CPU time 14.01 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 205180 kb
Host smart-f244c54d-c78e-4228-bf37-df4eff68a00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26659
33358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.2665933358
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2943961972
Short name T1244
Test name
Test status
Simulation time 10063425003 ps
CPU time 17.15 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:36 PM PDT 24
Peak memory 205244 kb
Host smart-361ce128-9c50-4442-ab13-2839ff1c7e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
61972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2943961972
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2128107806
Short name T1701
Test name
Test status
Simulation time 10123882740 ps
CPU time 17.37 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:37 PM PDT 24
Peak memory 205304 kb
Host smart-504028be-6634-4c72-8e32-ad3e8aa9b2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
07806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2128107806
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3994180040
Short name T940
Test name
Test status
Simulation time 10068232078 ps
CPU time 12.85 seconds
Started May 26 01:37:18 PM PDT 24
Finished May 26 01:37:32 PM PDT 24
Peak memory 205292 kb
Host smart-b2a4b324-8774-4851-aa72-91262bae515b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39941
80040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3994180040
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.266884964
Short name T374
Test name
Test status
Simulation time 10058464318 ps
CPU time 14.36 seconds
Started May 26 01:37:17 PM PDT 24
Finished May 26 01:37:33 PM PDT 24
Peak memory 205308 kb
Host smart-645bd7d0-d956-48c1-b4e9-7f7644484f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26688
4964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.266884964
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.1971050470
Short name T1090
Test name
Test status
Simulation time 10157280549 ps
CPU time 14.7 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205248 kb
Host smart-738ea08f-9f8a-4b79-81f0-8a25876ed417
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1971050470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.1971050470
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.2304667393
Short name T724
Test name
Test status
Simulation time 10065314219 ps
CPU time 13.1 seconds
Started May 26 01:37:30 PM PDT 24
Finished May 26 01:37:44 PM PDT 24
Peak memory 205256 kb
Host smart-6a757aa4-c968-4c7d-937d-bb4b469d6ee7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2304667393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.2304667393
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.1214647944
Short name T858
Test name
Test status
Simulation time 10136162374 ps
CPU time 15.55 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:45 PM PDT 24
Peak memory 205248 kb
Host smart-63bb8244-a189-48cd-95eb-b203971dcbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
47944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.1214647944
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3953104162
Short name T1474
Test name
Test status
Simulation time 14289018585 ps
CPU time 20.77 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:47 PM PDT 24
Peak memory 205280 kb
Host smart-faa2585e-b29a-4ac5-b6d8-009cdff9a3ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3953104162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.3953104162
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3072707770
Short name T1653
Test name
Test status
Simulation time 13357655566 ps
CPU time 18.01 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:47 PM PDT 24
Peak memory 205288 kb
Host smart-6eb3a52d-e8dd-46f6-8b19-0c8d5ae6f6da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3072707770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3072707770
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2964605396
Short name T685
Test name
Test status
Simulation time 13318673113 ps
CPU time 18.83 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:46 PM PDT 24
Peak memory 205256 kb
Host smart-df5563df-c5fc-4fa4-b2e8-149901bf8b21
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2964605396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2964605396
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.681243219
Short name T606
Test name
Test status
Simulation time 10058995221 ps
CPU time 13.94 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205304 kb
Host smart-38832746-a0fc-438c-a3b0-997223ac5c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68124
3219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.681243219
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3675060553
Short name T834
Test name
Test status
Simulation time 10488662310 ps
CPU time 13.8 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205240 kb
Host smart-923ca266-10bd-4582-acbf-a829c0198242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36750
60553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3675060553
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.100696824
Short name T522
Test name
Test status
Simulation time 10085479722 ps
CPU time 15.1 seconds
Started May 26 01:37:24 PM PDT 24
Finished May 26 01:37:40 PM PDT 24
Peak memory 205248 kb
Host smart-8d925502-3aaf-43f9-ba1a-d931390adeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10069
6824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.100696824
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.126908898
Short name T1409
Test name
Test status
Simulation time 10059684191 ps
CPU time 17.12 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:45 PM PDT 24
Peak memory 205376 kb
Host smart-dbc89c4d-14da-4558-82ff-223e5b38c246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
8898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.126908898
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1643504116
Short name T1569
Test name
Test status
Simulation time 10764399953 ps
CPU time 14.26 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205228 kb
Host smart-33c9dca0-1f7f-42db-91ab-ea900b34d14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16435
04116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1643504116
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3744807323
Short name T1050
Test name
Test status
Simulation time 10295142149 ps
CPU time 17.01 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205292 kb
Host smart-1bd3f5e8-cab9-4551-9910-6d0af2ec6182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37448
07323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3744807323
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3554520810
Short name T223
Test name
Test status
Simulation time 10149307303 ps
CPU time 15.52 seconds
Started May 26 01:37:32 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205292 kb
Host smart-c66364bd-75d9-4823-bb51-7fdbd6c0d28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
20810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3554520810
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3516321641
Short name T661
Test name
Test status
Simulation time 10106435025 ps
CPU time 17.5 seconds
Started May 26 01:37:29 PM PDT 24
Finished May 26 01:37:47 PM PDT 24
Peak memory 205312 kb
Host smart-3a9d7626-6b4e-4e3f-bd7b-feb4bcf45b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35163
21641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3516321641
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3733428222
Short name T856
Test name
Test status
Simulation time 10064509920 ps
CPU time 13.98 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:41 PM PDT 24
Peak memory 205264 kb
Host smart-b5313a15-613a-44df-b9a7-d5f47fe57c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37334
28222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3733428222
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4267771915
Short name T909
Test name
Test status
Simulation time 10082321255 ps
CPU time 14.67 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205248 kb
Host smart-01a1a7dd-4f29-43de-923d-4607b182d28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42677
71915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4267771915
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1338879211
Short name T995
Test name
Test status
Simulation time 13151289139 ps
CPU time 16.33 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205220 kb
Host smart-6a1f58c9-6da5-44f4-9636-153a301deed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
79211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1338879211
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.876589410
Short name T449
Test name
Test status
Simulation time 10091145327 ps
CPU time 14.64 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:44 PM PDT 24
Peak memory 205292 kb
Host smart-d2b0fd24-8373-41a9-992f-a9deb4328b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87658
9410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.876589410
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2451532111
Short name T575
Test name
Test status
Simulation time 10072001491 ps
CPU time 13.4 seconds
Started May 26 01:37:30 PM PDT 24
Finished May 26 01:37:44 PM PDT 24
Peak memory 205288 kb
Host smart-26a480ef-65af-4d35-8c83-94b590869251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24515
32111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2451532111
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2040254640
Short name T1675
Test name
Test status
Simulation time 10099665286 ps
CPU time 14.87 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205312 kb
Host smart-574ee6c3-2943-462c-ab45-2017f55c2e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
54640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2040254640
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1587524829
Short name T483
Test name
Test status
Simulation time 10100800766 ps
CPU time 16.01 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:45 PM PDT 24
Peak memory 205216 kb
Host smart-244c60a5-4fe9-42a4-b100-0eba45c7425f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15875
24829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1587524829
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2682729718
Short name T1021
Test name
Test status
Simulation time 10054032013 ps
CPU time 14.02 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205316 kb
Host smart-5e4b46c9-a5a7-42b7-9fff-bd21d4126286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26827
29718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2682729718
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2497066120
Short name T446
Test name
Test status
Simulation time 10101447473 ps
CPU time 14.46 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205296 kb
Host smart-305cf602-6998-437a-a616-ab30beb6b561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24970
66120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2497066120
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1064604396
Short name T183
Test name
Test status
Simulation time 10081808477 ps
CPU time 15.13 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205204 kb
Host smart-3a68f924-ee09-46f6-939a-745a9cb3a0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10646
04396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1064604396
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.1547234619
Short name T1531
Test name
Test status
Simulation time 10065013779 ps
CPU time 13.57 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:40 PM PDT 24
Peak memory 205260 kb
Host smart-a6c9c316-bf0a-4c52-aa2c-753ef1280ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15472
34619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.1547234619
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.429768281
Short name T1871
Test name
Test status
Simulation time 10092065477 ps
CPU time 15.13 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205260 kb
Host smart-c1b470fa-2d4f-4171-af8d-d8b7dedbb2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42976
8281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.429768281
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4256371303
Short name T24
Test name
Test status
Simulation time 10056582887 ps
CPU time 15.47 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:45 PM PDT 24
Peak memory 205316 kb
Host smart-ec4bf0b1-63e2-43de-8cb0-8f90604223b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42563
71303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4256371303
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.52009428
Short name T1490
Test name
Test status
Simulation time 19665269194 ps
CPU time 38.39 seconds
Started May 26 01:37:32 PM PDT 24
Finished May 26 01:38:11 PM PDT 24
Peak memory 205324 kb
Host smart-9c75ed75-f1a0-4f0a-921c-95100e5261b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52009
428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.52009428
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.947164502
Short name T330
Test name
Test status
Simulation time 10094993703 ps
CPU time 15.13 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:41 PM PDT 24
Peak memory 205292 kb
Host smart-7f6fdadc-99d1-429c-a4cc-fc8bb8a53b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94716
4502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.947164502
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3372767534
Short name T133
Test name
Test status
Simulation time 10091659040 ps
CPU time 15.01 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205272 kb
Host smart-13d02863-7121-4966-a992-6bc0e88dc076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
67534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3372767534
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.3636575796
Short name T893
Test name
Test status
Simulation time 10103263358 ps
CPU time 14.14 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:44 PM PDT 24
Peak memory 205348 kb
Host smart-ff539313-ea24-4ebb-8251-d3abb8bf767b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36365
75796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.3636575796
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2840310621
Short name T1533
Test name
Test status
Simulation time 10039456406 ps
CPU time 13.34 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:40 PM PDT 24
Peak memory 205196 kb
Host smart-a2281d7e-f214-49bb-82e4-138b079c399a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403
10621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2840310621
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1355200044
Short name T156
Test name
Test status
Simulation time 10055472043 ps
CPU time 13.54 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:40 PM PDT 24
Peak memory 205252 kb
Host smart-f733076b-c9e2-47f0-aeff-7a54465c43eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
00044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1355200044
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.575697114
Short name T1319
Test name
Test status
Simulation time 10051608173 ps
CPU time 14.52 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205260 kb
Host smart-27fe732b-e771-4bca-bc0b-d0426af02dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57569
7114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.575697114
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2839022621
Short name T1661
Test name
Test status
Simulation time 10149307063 ps
CPU time 14.66 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205328 kb
Host smart-9f407a4a-7b43-44c6-811f-c3dd7ca3dac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
22621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2839022621
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3969062002
Short name T1046
Test name
Test status
Simulation time 10085561995 ps
CPU time 13.15 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205256 kb
Host smart-8d80fdad-44b8-4e0b-96b6-c1df3cb0154c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
62002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3969062002
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1812129997
Short name T1810
Test name
Test status
Simulation time 10063160712 ps
CPU time 14.92 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205296 kb
Host smart-02bc997e-95c4-4770-b2c0-65e8de6efee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18121
29997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1812129997
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.1100935143
Short name T1898
Test name
Test status
Simulation time 10221007674 ps
CPU time 15.56 seconds
Started May 26 01:28:32 PM PDT 24
Finished May 26 01:28:49 PM PDT 24
Peak memory 205264 kb
Host smart-6772b70c-debf-4e43-8b78-4cec35f2600b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1100935143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.1100935143
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.1707047297
Short name T1205
Test name
Test status
Simulation time 10055247988 ps
CPU time 16.16 seconds
Started May 26 01:28:32 PM PDT 24
Finished May 26 01:28:49 PM PDT 24
Peak memory 205252 kb
Host smart-3103a278-3b1c-4da0-84d1-0d3aa17d0db6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1707047297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.1707047297
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.4154407483
Short name T1439
Test name
Test status
Simulation time 10157404515 ps
CPU time 14.53 seconds
Started May 26 01:28:32 PM PDT 24
Finished May 26 01:28:48 PM PDT 24
Peak memory 205240 kb
Host smart-c2796396-dd0b-4752-a6e8-0e640babda38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41544
07483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.4154407483
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.4103490998
Short name T1068
Test name
Test status
Simulation time 14039729412 ps
CPU time 17.31 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:25 PM PDT 24
Peak memory 205316 kb
Host smart-214d756f-d539-4003-9dca-a04339f4cd61
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4103490998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.4103490998
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1966992130
Short name T1804
Test name
Test status
Simulation time 13290131369 ps
CPU time 16.69 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:24 PM PDT 24
Peak memory 205300 kb
Host smart-d481866e-e8cd-4042-a376-25d482df33f6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1966992130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1966992130
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3080529130
Short name T1852
Test name
Test status
Simulation time 13268758637 ps
CPU time 20.09 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:38 PM PDT 24
Peak memory 205228 kb
Host smart-00892d24-c21b-49a3-955d-0a855364fee9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3080529130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3080529130
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3758955279
Short name T1664
Test name
Test status
Simulation time 10062978093 ps
CPU time 13.9 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:29 PM PDT 24
Peak memory 205284 kb
Host smart-ff2da451-db1c-4cef-8861-26a7d784058b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37589
55279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3758955279
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3354238708
Short name T1239
Test name
Test status
Simulation time 10077150328 ps
CPU time 14.16 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:33 PM PDT 24
Peak memory 205252 kb
Host smart-810ae1d5-28bf-4bfd-8ff2-f334cd2dc5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33542
38708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3354238708
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2227083149
Short name T419
Test name
Test status
Simulation time 10210561917 ps
CPU time 15.19 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:31 PM PDT 24
Peak memory 205176 kb
Host smart-fca47467-0388-486b-8b6e-0c23d809b2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
83149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2227083149
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3352393070
Short name T394
Test name
Test status
Simulation time 10032825571 ps
CPU time 14.39 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:33 PM PDT 24
Peak memory 205256 kb
Host smart-71061374-0c13-4d7d-a228-87b4349176a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33523
93070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3352393070
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.4104663453
Short name T452
Test name
Test status
Simulation time 10114230423 ps
CPU time 14.02 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:32 PM PDT 24
Peak memory 205308 kb
Host smart-2ddf69f5-991d-471d-a0cc-5c5f147608d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046
63453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.4104663453
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.1850546449
Short name T1655
Test name
Test status
Simulation time 10785598500 ps
CPU time 16.03 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:34 PM PDT 24
Peak memory 205296 kb
Host smart-2f3404fe-52e5-4241-b0f1-0ab4bcf58c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
46449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1850546449
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1558705590
Short name T324
Test name
Test status
Simulation time 10202460206 ps
CPU time 16.31 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:34 PM PDT 24
Peak memory 205312 kb
Host smart-38d98244-c473-4980-87fd-ba6c4ac7ea98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15587
05590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1558705590
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3160823368
Short name T996
Test name
Test status
Simulation time 10178684747 ps
CPU time 14.61 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:48 PM PDT 24
Peak memory 205276 kb
Host smart-a40c87f5-d9f4-495b-a35f-b930faa8995a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
23368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3160823368
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.507383201
Short name T928
Test name
Test status
Simulation time 10048451661 ps
CPU time 14.95 seconds
Started May 26 01:28:33 PM PDT 24
Finished May 26 01:28:49 PM PDT 24
Peak memory 205332 kb
Host smart-f1c952a9-4d31-44b2-a8df-6376a905b764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50738
3201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.507383201
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.673696324
Short name T636
Test name
Test status
Simulation time 10069445770 ps
CPU time 16.11 seconds
Started May 26 01:28:17 PM PDT 24
Finished May 26 01:28:35 PM PDT 24
Peak memory 205328 kb
Host smart-56b0361b-9cba-41af-b5ab-650fbd6f392f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67369
6324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.673696324
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3226909650
Short name T691
Test name
Test status
Simulation time 10089898061 ps
CPU time 16.65 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:33 PM PDT 24
Peak memory 205228 kb
Host smart-50b249b9-b857-4aee-9c6a-53feee402834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32269
09650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3226909650
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3238095763
Short name T891
Test name
Test status
Simulation time 13231603064 ps
CPU time 19.36 seconds
Started May 26 01:28:15 PM PDT 24
Finished May 26 01:28:35 PM PDT 24
Peak memory 205248 kb
Host smart-7501aea3-b292-4602-8035-23e77728ec97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
95763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3238095763
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1046557581
Short name T1079
Test name
Test status
Simulation time 10125228779 ps
CPU time 14.49 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:32 PM PDT 24
Peak memory 205304 kb
Host smart-b508ce67-c4c9-4853-9bf3-b34cc234ae31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10465
57581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1046557581
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1967501681
Short name T1198
Test name
Test status
Simulation time 10058254964 ps
CPU time 15.38 seconds
Started May 26 01:28:16 PM PDT 24
Finished May 26 01:28:34 PM PDT 24
Peak memory 205324 kb
Host smart-61f965be-4907-43b9-a417-d434ccb193ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19675
01681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1967501681
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3152886893
Short name T1494
Test name
Test status
Simulation time 10118890546 ps
CPU time 13.67 seconds
Started May 26 01:28:19 PM PDT 24
Finished May 26 01:28:33 PM PDT 24
Peak memory 205340 kb
Host smart-2075bbd0-8237-44d2-a598-519e4197f982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528
86893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3152886893
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1268209839
Short name T1283
Test name
Test status
Simulation time 10090058097 ps
CPU time 17.87 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:42 PM PDT 24
Peak memory 205236 kb
Host smart-db690951-454b-4da7-a6b2-dd22f25f2d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12682
09839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1268209839
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1856768443
Short name T1243
Test name
Test status
Simulation time 10087744939 ps
CPU time 14.46 seconds
Started May 26 01:28:28 PM PDT 24
Finished May 26 01:28:43 PM PDT 24
Peak memory 205296 kb
Host smart-f608b2ba-833c-4861-9d16-ae526d757a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18567
68443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1856768443
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3466927615
Short name T507
Test name
Test status
Simulation time 10105782259 ps
CPU time 14.89 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:39 PM PDT 24
Peak memory 205180 kb
Host smart-1d86974d-3719-4e8a-8b2d-f3c5d2cb6ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34669
27615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3466927615
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1194766965
Short name T1421
Test name
Test status
Simulation time 10105377239 ps
CPU time 13.78 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:38 PM PDT 24
Peak memory 205280 kb
Host smart-11f1bcc2-c2b5-4d55-8489-9ed2692c35f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
66965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1194766965
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.199959896
Short name T799
Test name
Test status
Simulation time 10081473294 ps
CPU time 14.27 seconds
Started May 26 01:28:27 PM PDT 24
Finished May 26 01:28:42 PM PDT 24
Peak memory 204436 kb
Host smart-7ba40058-8214-49d9-8bc1-4326f530c4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19995
9896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.199959896
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1189938128
Short name T1923
Test name
Test status
Simulation time 10078141898 ps
CPU time 15.29 seconds
Started May 26 01:28:25 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 205272 kb
Host smart-638f9d0c-75b1-4570-8781-495837652742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11899
38128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1189938128
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.4039784588
Short name T1297
Test name
Test status
Simulation time 10057216136 ps
CPU time 13.74 seconds
Started May 26 01:28:32 PM PDT 24
Finished May 26 01:28:47 PM PDT 24
Peak memory 205304 kb
Host smart-beb24afa-c218-4c90-bebb-284ada874de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40397
84588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.4039784588
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.4072975654
Short name T254
Test name
Test status
Simulation time 20358526284 ps
CPU time 35.56 seconds
Started May 26 01:28:23 PM PDT 24
Finished May 26 01:28:59 PM PDT 24
Peak memory 205284 kb
Host smart-706284a2-c319-40d6-9b46-6bbcf1865f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40729
75654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.4072975654
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.3700974698
Short name T762
Test name
Test status
Simulation time 10057289652 ps
CPU time 13.36 seconds
Started May 26 01:28:22 PM PDT 24
Finished May 26 01:28:36 PM PDT 24
Peak memory 205260 kb
Host smart-03349559-13f3-4377-980d-567e4e979ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37009
74698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.3700974698
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1686575849
Short name T966
Test name
Test status
Simulation time 10156215601 ps
CPU time 15.09 seconds
Started May 26 01:28:25 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 205228 kb
Host smart-c13f484e-fa0b-4d48-aff5-6ab21084ff00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16865
75849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1686575849
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.1035985202
Short name T976
Test name
Test status
Simulation time 10058240096 ps
CPU time 14.81 seconds
Started May 26 01:28:29 PM PDT 24
Finished May 26 01:28:44 PM PDT 24
Peak memory 205240 kb
Host smart-e8be7bad-7a35-4b2e-8cfe-f01cfe18f697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10359
85202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.1035985202
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1967353337
Short name T384
Test name
Test status
Simulation time 10049269931 ps
CPU time 14.69 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:40 PM PDT 24
Peak memory 205264 kb
Host smart-9846b98d-a7f6-41ee-8244-f2aeea310693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19673
53337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1967353337
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3677507325
Short name T206
Test name
Test status
Simulation time 1026161615 ps
CPU time 1.92 seconds
Started May 26 01:28:34 PM PDT 24
Finished May 26 01:28:37 PM PDT 24
Peak memory 221416 kb
Host smart-459b3641-b36f-4bbb-81fe-f998b3c5e947
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3677507325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3677507325
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3774106782
Short name T17
Test name
Test status
Simulation time 10051441838 ps
CPU time 16.62 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 205296 kb
Host smart-fa4d2397-7328-40fb-8a57-86c2cdffe821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37741
06782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3774106782
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.552149950
Short name T806
Test name
Test status
Simulation time 10109249657 ps
CPU time 15.37 seconds
Started May 26 01:28:25 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 205260 kb
Host smart-c1c7bb98-90bc-426e-8ac8-aeef706d21a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55214
9950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.552149950
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4098028015
Short name T1387
Test name
Test status
Simulation time 10166989941 ps
CPU time 15.21 seconds
Started May 26 01:28:06 PM PDT 24
Finished May 26 01:28:22 PM PDT 24
Peak memory 205504 kb
Host smart-6675fed7-e6ce-4784-8af9-e675216a12e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
28015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4098028015
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.423351882
Short name T431
Test name
Test status
Simulation time 10062847270 ps
CPU time 15.97 seconds
Started May 26 01:28:27 PM PDT 24
Finished May 26 01:28:44 PM PDT 24
Peak memory 204388 kb
Host smart-10da95f4-0689-4134-981a-5e48f0c7caac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42335
1882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.423351882
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1030321578
Short name T861
Test name
Test status
Simulation time 10066861147 ps
CPU time 15.82 seconds
Started May 26 01:28:24 PM PDT 24
Finished May 26 01:28:41 PM PDT 24
Peak memory 205432 kb
Host smart-fb26b113-ac2d-4eab-ad11-1655be3f59d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10303
21578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1030321578
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.3080115986
Short name T437
Test name
Test status
Simulation time 10151084656 ps
CPU time 14.08 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:50 PM PDT 24
Peak memory 205248 kb
Host smart-05c8d37b-29d2-4fcb-be08-200cb01d1b16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3080115986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.3080115986
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.2786249932
Short name T1007
Test name
Test status
Simulation time 10058711462 ps
CPU time 13.95 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205232 kb
Host smart-6beb102d-c4b5-48da-b6de-d3ebf7892f23
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2786249932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.2786249932
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.3556937047
Short name T1180
Test name
Test status
Simulation time 10079048685 ps
CPU time 13.04 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205232 kb
Host smart-3771ba1f-ed7c-447c-82e1-597cf69dcc67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35569
37047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.3556937047
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.828718718
Short name T1784
Test name
Test status
Simulation time 14017885592 ps
CPU time 17.65 seconds
Started May 26 01:37:27 PM PDT 24
Finished May 26 01:37:46 PM PDT 24
Peak memory 205352 kb
Host smart-7f4f810d-5ff1-4c4f-8375-ba66e3cdb686
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=828718718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.828718718
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1014804659
Short name T221
Test name
Test status
Simulation time 13265901225 ps
CPU time 16.56 seconds
Started May 26 01:37:30 PM PDT 24
Finished May 26 01:37:47 PM PDT 24
Peak memory 205316 kb
Host smart-47edea0e-f920-4c07-a3a0-d5217a8d1d03
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1014804659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1014804659
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3625705560
Short name T456
Test name
Test status
Simulation time 13356811528 ps
CPU time 17.2 seconds
Started May 26 01:37:25 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205284 kb
Host smart-46e77f24-bf25-42c7-847c-b615e4831cf6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3625705560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3625705560
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.915121691
Short name T1905
Test name
Test status
Simulation time 10069276116 ps
CPU time 13.82 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:43 PM PDT 24
Peak memory 205224 kb
Host smart-b2bb4b2e-302b-4ee2-97f5-b3563eb702b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91512
1691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.915121691
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2008238193
Short name T955
Test name
Test status
Simulation time 10261677954 ps
CPU time 14.73 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:44 PM PDT 24
Peak memory 205364 kb
Host smart-dba88fe1-67cf-4d55-a047-e21d7062edab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082
38193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2008238193
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2882667988
Short name T1610
Test name
Test status
Simulation time 10047205550 ps
CPU time 13.34 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205284 kb
Host smart-54a4729b-569a-4b30-847d-50bcf17cff04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28826
67988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2882667988
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2719284201
Short name T841
Test name
Test status
Simulation time 10077596659 ps
CPU time 14.86 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:54 PM PDT 24
Peak memory 205388 kb
Host smart-df51e4ec-5098-4739-b654-8943699f5838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27192
84201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2719284201
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2106922565
Short name T386
Test name
Test status
Simulation time 10934160093 ps
CPU time 17 seconds
Started May 26 01:37:28 PM PDT 24
Finished May 26 01:37:46 PM PDT 24
Peak memory 205204 kb
Host smart-8d5f539d-5c0b-4968-a2ff-2843544687e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21069
22565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2106922565
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.826665405
Short name T1513
Test name
Test status
Simulation time 10095989962 ps
CPU time 13.75 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205272 kb
Host smart-a63c494c-20b2-48ac-8859-1da6d158df7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82666
5405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.826665405
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1231501332
Short name T1269
Test name
Test status
Simulation time 10055435723 ps
CPU time 13.56 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205332 kb
Host smart-db5c86f0-8560-4b20-a36f-38f7915359c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
01332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1231501332
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.3087619049
Short name T681
Test name
Test status
Simulation time 10102353664 ps
CPU time 15.96 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:55 PM PDT 24
Peak memory 205236 kb
Host smart-8ee87698-5d3a-40f5-a360-41be6d30eb80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
19049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.3087619049
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3767039343
Short name T1886
Test name
Test status
Simulation time 10141358969 ps
CPU time 14.74 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:58 PM PDT 24
Peak memory 205288 kb
Host smart-9a344a9d-61f2-4da0-91b8-91b4e2394575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37670
39343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3767039343
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2173203466
Short name T1031
Test name
Test status
Simulation time 10113544388 ps
CPU time 14.64 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205280 kb
Host smart-e279e0f6-3cb5-4a7d-b86d-8a0a0e041163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21732
03466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2173203466
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3830783628
Short name T684
Test name
Test status
Simulation time 13228128874 ps
CPU time 16.02 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205268 kb
Host smart-09eef00d-88c1-4be7-a6f9-64febedd845c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38307
83628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3830783628
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.962267665
Short name T577
Test name
Test status
Simulation time 10106761565 ps
CPU time 14.25 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205220 kb
Host smart-8f84c229-2099-4f32-b438-11b9c73a2d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96226
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.962267665
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2142731464
Short name T736
Test name
Test status
Simulation time 10078212770 ps
CPU time 17.23 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:54 PM PDT 24
Peak memory 205204 kb
Host smart-29a2cb44-b14b-42f5-8249-14bdc14bd9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21427
31464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2142731464
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1522822179
Short name T101
Test name
Test status
Simulation time 10151418695 ps
CPU time 13.65 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205304 kb
Host smart-aa8e100e-5899-4e67-b115-076d48dfea0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15228
22179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1522822179
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2345522887
Short name T650
Test name
Test status
Simulation time 10089480057 ps
CPU time 13.43 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205268 kb
Host smart-1b5f8f55-bc02-47e9-9ce4-d0226c4b14d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23455
22887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2345522887
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2605139313
Short name T1061
Test name
Test status
Simulation time 10077150706 ps
CPU time 15.46 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205324 kb
Host smart-86fa4255-7f05-4448-96ef-a88139cb7b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26051
39313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2605139313
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.4261948215
Short name T1294
Test name
Test status
Simulation time 10064319117 ps
CPU time 13.25 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205488 kb
Host smart-9322b66c-837e-41c5-aa67-eb334d04427b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42619
48215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.4261948215
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3439732076
Short name T137
Test name
Test status
Simulation time 10090851607 ps
CPU time 13.19 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:47 PM PDT 24
Peak memory 205304 kb
Host smart-a332f0a4-41a9-4eab-9d76-85c281f69626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
32076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3439732076
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.1299441997
Short name T1670
Test name
Test status
Simulation time 10070320273 ps
CPU time 14.84 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:58 PM PDT 24
Peak memory 205332 kb
Host smart-154e1443-175a-4391-baaa-9df7c6111246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
41997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.1299441997
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.4063120853
Short name T585
Test name
Test status
Simulation time 10043848645 ps
CPU time 14.56 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:53 PM PDT 24
Peak memory 205208 kb
Host smart-b240d868-2f37-4eb0-8b3e-b93e730031ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40631
20853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.4063120853
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2268369047
Short name T1508
Test name
Test status
Simulation time 10041960870 ps
CPU time 14.76 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:50 PM PDT 24
Peak memory 205244 kb
Host smart-f5928112-b524-4447-9769-238f0738b297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
69047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2268369047
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3788621479
Short name T802
Test name
Test status
Simulation time 31065585541 ps
CPU time 66.04 seconds
Started May 26 01:38:02 PM PDT 24
Finished May 26 01:39:09 PM PDT 24
Peak memory 205340 kb
Host smart-7efd456a-4fe5-4a4c-aa4e-340c079bd20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
21479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3788621479
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2844831847
Short name T902
Test name
Test status
Simulation time 10057220705 ps
CPU time 14.89 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205288 kb
Host smart-6bfe520d-8c70-4729-b271-a05ccc5c2ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28448
31847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2844831847
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1855486060
Short name T1247
Test name
Test status
Simulation time 10136519702 ps
CPU time 14.32 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:54 PM PDT 24
Peak memory 205264 kb
Host smart-2034b877-a855-46a4-9f81-5e1fcf606490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
86060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1855486060
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.3930933676
Short name T1840
Test name
Test status
Simulation time 10109596853 ps
CPU time 14.17 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205292 kb
Host smart-aae374ac-93d7-41a4-b4ac-3fe475c2e91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39309
33676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.3930933676
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2475926418
Short name T1012
Test name
Test status
Simulation time 10033564814 ps
CPU time 13.24 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205160 kb
Host smart-a5e607b6-5d62-4a7a-98c0-51780fb7fe98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24759
26418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2475926418
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.4192687922
Short name T150
Test name
Test status
Simulation time 10064280097 ps
CPU time 16.43 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:56 PM PDT 24
Peak memory 205280 kb
Host smart-b0f1209c-3b7e-4674-8b04-25fbb424950b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41926
87922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.4192687922
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3980449658
Short name T434
Test name
Test status
Simulation time 10063576155 ps
CPU time 17.9 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:56 PM PDT 24
Peak memory 205220 kb
Host smart-ec579fbd-ea52-4b89-9169-c0238df54e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804
49658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3980449658
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.3844838755
Short name T160
Test name
Test status
Simulation time 10129926834 ps
CPU time 14.09 seconds
Started May 26 01:37:26 PM PDT 24
Finished May 26 01:37:42 PM PDT 24
Peak memory 205208 kb
Host smart-f71056af-8e98-4dbe-8097-fcb129e24bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
38755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.3844838755
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.4211274521
Short name T1452
Test name
Test status
Simulation time 10047731044 ps
CPU time 13.66 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205264 kb
Host smart-93bf4845-6216-4a0e-8894-b53c68f06556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42112
74521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.4211274521
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2490920952
Short name T306
Test name
Test status
Simulation time 10064590315 ps
CPU time 15.21 seconds
Started May 26 01:37:32 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205280 kb
Host smart-4faba002-89d2-481c-9db8-4e113fb9a306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909
20952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2490920952
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.2381598727
Short name T708
Test name
Test status
Simulation time 10136404214 ps
CPU time 18.26 seconds
Started May 26 01:37:47 PM PDT 24
Finished May 26 01:38:07 PM PDT 24
Peak memory 205220 kb
Host smart-6f02025a-3428-4195-ad06-a1d55601c260
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2381598727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.2381598727
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1626226950
Short name T362
Test name
Test status
Simulation time 10066150952 ps
CPU time 14.87 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:38:00 PM PDT 24
Peak memory 205308 kb
Host smart-d569fa80-40fd-479f-8ca4-eaf9538ea575
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1626226950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1626226950
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.3889809721
Short name T1752
Test name
Test status
Simulation time 10165368539 ps
CPU time 15.27 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205280 kb
Host smart-396b7b55-bfe9-47f3-b7c3-c4c1813b8573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38898
09721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.3889809721
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3532469190
Short name T7
Test name
Test status
Simulation time 13499593256 ps
CPU time 20.86 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205456 kb
Host smart-f9499f15-4c52-47ab-bafe-31a047be1ca1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3532469190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3532469190
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3041816432
Short name T997
Test name
Test status
Simulation time 13333312796 ps
CPU time 17.71 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:57 PM PDT 24
Peak memory 205332 kb
Host smart-5a4f736e-5360-4248-b5eb-f3623c9d3faf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3041816432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3041816432
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2586784071
Short name T471
Test name
Test status
Simulation time 13236578606 ps
CPU time 17.43 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:54 PM PDT 24
Peak memory 205256 kb
Host smart-3a2796e2-0472-4868-9ba4-56827133bb40
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2586784071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2586784071
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1133029663
Short name T1724
Test name
Test status
Simulation time 10129922671 ps
CPU time 14.35 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205276 kb
Host smart-39cfeab5-4338-4fbd-9b90-8a4d5a36c076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11330
29663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1133029663
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2370923718
Short name T776
Test name
Test status
Simulation time 10092294558 ps
CPU time 14.18 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205392 kb
Host smart-bc040848-4a1d-4c19-bd96-5c7918736544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23709
23718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2370923718
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.4236682926
Short name T418
Test name
Test status
Simulation time 10044742614 ps
CPU time 14.14 seconds
Started May 26 01:37:32 PM PDT 24
Finished May 26 01:37:47 PM PDT 24
Peak memory 205308 kb
Host smart-405c7eee-878f-4fe1-ab1b-787c712d4ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42366
82926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.4236682926
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3305059390
Short name T1656
Test name
Test status
Simulation time 10059027132 ps
CPU time 14 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:48 PM PDT 24
Peak memory 205200 kb
Host smart-8bd880e7-1990-4fcb-b6d7-eddc308fc243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33050
59390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3305059390
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4164733046
Short name T1792
Test name
Test status
Simulation time 10760960781 ps
CPU time 15.69 seconds
Started May 26 01:37:39 PM PDT 24
Finished May 26 01:37:55 PM PDT 24
Peak memory 205336 kb
Host smart-867f3658-085e-4ae4-a4a5-0a51d8e135dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41647
33046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4164733046
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.4079425428
Short name T534
Test name
Test status
Simulation time 10315637491 ps
CPU time 17.45 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205252 kb
Host smart-643e1b08-47f5-4541-a940-07f3eaf926f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40794
25428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.4079425428
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.496759026
Short name T969
Test name
Test status
Simulation time 10094768516 ps
CPU time 14.51 seconds
Started May 26 01:37:47 PM PDT 24
Finished May 26 01:38:03 PM PDT 24
Peak memory 205220 kb
Host smart-1d9a1453-d6c6-4a19-8d13-a0b45b2b899e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49675
9026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.496759026
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.77217310
Short name T1505
Test name
Test status
Simulation time 10045722252 ps
CPU time 13.65 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205292 kb
Host smart-dfa1d1a9-8c89-40d6-89cd-1e25e451cc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77217
310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.77217310
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1860693274
Short name T462
Test name
Test status
Simulation time 10073388449 ps
CPU time 13.82 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:50 PM PDT 24
Peak memory 205200 kb
Host smart-d63f6c6b-0134-4fb3-856b-80caff748ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
93274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1860693274
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3817089174
Short name T588
Test name
Test status
Simulation time 10085749352 ps
CPU time 14.37 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:50 PM PDT 24
Peak memory 205452 kb
Host smart-a7fe27e8-fd2a-43b7-a7f1-1bac21d75236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38170
89174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3817089174
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.4167427094
Short name T1424
Test name
Test status
Simulation time 13157022237 ps
CPU time 17.45 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:56 PM PDT 24
Peak memory 205256 kb
Host smart-8476effa-41fc-4e0d-a52f-fb474e755e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674
27094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.4167427094
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1333924635
Short name T1806
Test name
Test status
Simulation time 10125295734 ps
CPU time 14.52 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205252 kb
Host smart-fe73924f-da5f-4148-9f98-dada1ad84a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13339
24635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1333924635
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1248672
Short name T1574
Test name
Test status
Simulation time 10120559439 ps
CPU time 14.64 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:53 PM PDT 24
Peak memory 205216 kb
Host smart-e68485d5-c0b3-4399-9081-d588a8a9c930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12486
72 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1248672
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3999668599
Short name T100
Test name
Test status
Simulation time 10120304083 ps
CPU time 15.97 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205280 kb
Host smart-532bcbf2-412d-45b3-8815-93229c5da5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39996
68599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3999668599
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3104111511
Short name T1593
Test name
Test status
Simulation time 10159336329 ps
CPU time 13.97 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205276 kb
Host smart-e2d124f4-b639-4e73-8a8c-13218ea8bb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31041
11511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3104111511
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.2534180421
Short name T1067
Test name
Test status
Simulation time 10072288060 ps
CPU time 14.63 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205280 kb
Host smart-45793206-ebe0-4220-8c90-91a26f6db60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25341
80421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2534180421
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.15774275
Short name T1825
Test name
Test status
Simulation time 10092639563 ps
CPU time 15.84 seconds
Started May 26 01:37:38 PM PDT 24
Finished May 26 01:37:55 PM PDT 24
Peak memory 205328 kb
Host smart-2ffe6d65-3a27-4022-9cfb-a94e0b6e4c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.15774275
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3736491980
Short name T1900
Test name
Test status
Simulation time 10082880249 ps
CPU time 16.13 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205316 kb
Host smart-09bf43a2-c0ec-44d7-9a15-2f7832b014f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364
91980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3736491980
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.3659992223
Short name T1151
Test name
Test status
Simulation time 10092794796 ps
CPU time 14.75 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205452 kb
Host smart-0ad1fc31-fc45-48e9-924a-7b2f474208d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36599
92223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.3659992223
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.324028821
Short name T674
Test name
Test status
Simulation time 10079086073 ps
CPU time 13.81 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:37:58 PM PDT 24
Peak memory 205332 kb
Host smart-592090e4-780a-4048-88b0-01bbf87f9280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32402
8821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.324028821
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2502292097
Short name T1397
Test name
Test status
Simulation time 30431422755 ps
CPU time 62.84 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:38:41 PM PDT 24
Peak memory 205520 kb
Host smart-e68b55ce-37b7-408d-a5c7-d81d3f35ecbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25022
92097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2502292097
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.910436668
Short name T1118
Test name
Test status
Simulation time 10087147172 ps
CPU time 15.17 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205264 kb
Host smart-9657390b-440b-4263-a0f7-6c5b0885a65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91043
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.910436668
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2519667772
Short name T1539
Test name
Test status
Simulation time 10156971097 ps
CPU time 14.67 seconds
Started May 26 01:37:35 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205236 kb
Host smart-b2aa8675-d744-442d-9ef3-ed1661519d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25196
67772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2519667772
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.4048698005
Short name T1117
Test name
Test status
Simulation time 10096749437 ps
CPU time 15.29 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:51 PM PDT 24
Peak memory 205188 kb
Host smart-565d0b4b-940e-4ad1-8ddc-76e6368f0f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
98005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.4048698005
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.378978415
Short name T1070
Test name
Test status
Simulation time 10066085739 ps
CPU time 14.19 seconds
Started May 26 01:37:34 PM PDT 24
Finished May 26 01:37:49 PM PDT 24
Peak memory 205256 kb
Host smart-bdc24e45-df79-42e0-9a6d-b3d21b265057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37897
8415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.378978415
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.504377976
Short name T540
Test name
Test status
Simulation time 10095429309 ps
CPU time 14.77 seconds
Started May 26 01:37:36 PM PDT 24
Finished May 26 01:37:53 PM PDT 24
Peak memory 205248 kb
Host smart-0031aba7-1503-4e17-b0db-64f92fa0c78d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50437
7976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.504377976
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2557256888
Short name T480
Test name
Test status
Simulation time 10092064374 ps
CPU time 13.76 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205264 kb
Host smart-ed1a9890-2fb9-476d-b8d4-ac8878f2b114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25572
56888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2557256888
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.688801679
Short name T1864
Test name
Test status
Simulation time 10187060552 ps
CPU time 16.55 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:55 PM PDT 24
Peak memory 205364 kb
Host smart-881b3565-3e05-4c53-943d-01cfc5156515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68880
1679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.688801679
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3733933172
Short name T1264
Test name
Test status
Simulation time 10123876260 ps
CPU time 13.82 seconds
Started May 26 01:37:37 PM PDT 24
Finished May 26 01:37:52 PM PDT 24
Peak memory 205312 kb
Host smart-b4f91215-db0a-4202-970b-02fcd165d8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37339
33172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3733933172
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3731588222
Short name T348
Test name
Test status
Simulation time 10053469507 ps
CPU time 14.63 seconds
Started May 26 01:37:33 PM PDT 24
Finished May 26 01:37:49 PM PDT 24
Peak memory 205304 kb
Host smart-c313b56f-7180-46a2-b54e-b80fc9a407ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37315
88222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3731588222
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.101037956
Short name T620
Test name
Test status
Simulation time 10161116129 ps
CPU time 16.72 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205192 kb
Host smart-dc012168-3953-4ba6-a612-0ee0fbf35654
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=101037956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.101037956
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.309087038
Short name T911
Test name
Test status
Simulation time 10052982185 ps
CPU time 16.74 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205172 kb
Host smart-697fc808-0ef8-4a58-bbe5-6b170ae078b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=309087038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.309087038
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.1118143410
Short name T440
Test name
Test status
Simulation time 10073587913 ps
CPU time 13.71 seconds
Started May 26 01:37:56 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205336 kb
Host smart-b24d08e0-47c3-4b90-8785-39202540ba11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11181
43410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.1118143410
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1338003863
Short name T230
Test name
Test status
Simulation time 13560568099 ps
CPU time 19.23 seconds
Started May 26 01:37:41 PM PDT 24
Finished May 26 01:38:01 PM PDT 24
Peak memory 205340 kb
Host smart-a5096614-ab2b-4c7b-92b9-30eb5132921e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1338003863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1338003863
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1479268335
Short name T1004
Test name
Test status
Simulation time 13236209335 ps
CPU time 17.16 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:38:02 PM PDT 24
Peak memory 205244 kb
Host smart-fe2c57d9-74d4-4e25-83c2-22624a7bf338
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1479268335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1479268335
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1214452353
Short name T54
Test name
Test status
Simulation time 13363894552 ps
CPU time 20.25 seconds
Started May 26 01:37:48 PM PDT 24
Finished May 26 01:38:09 PM PDT 24
Peak memory 205192 kb
Host smart-a4f7488c-a315-457c-b0da-504098d51091
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1214452353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1214452353
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3003753484
Short name T1163
Test name
Test status
Simulation time 10053286270 ps
CPU time 13.25 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:37:58 PM PDT 24
Peak memory 205256 kb
Host smart-6c6f4f73-9a05-4c71-a480-a4269275aa2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30037
53484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3003753484
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3253349353
Short name T1480
Test name
Test status
Simulation time 10071780120 ps
CPU time 14.87 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205260 kb
Host smart-43258c8c-a95c-4276-ad9e-98df3bba16ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533
49353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3253349353
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1388835882
Short name T1077
Test name
Test status
Simulation time 11277796965 ps
CPU time 15.72 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:58 PM PDT 24
Peak memory 205388 kb
Host smart-407a364f-8c71-4c9d-8401-7b1b406b4872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
35882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1388835882
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.240811504
Short name T744
Test name
Test status
Simulation time 10055094439 ps
CPU time 14.98 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205240 kb
Host smart-1b878a44-c680-441b-828d-33ea1a585286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24081
1504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.240811504
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.3837171623
Short name T1220
Test name
Test status
Simulation time 10059470968 ps
CPU time 14.86 seconds
Started May 26 01:37:45 PM PDT 24
Finished May 26 01:38:00 PM PDT 24
Peak memory 204984 kb
Host smart-1ca2e191-332a-4ed8-bfa0-900d782b22fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38371
71623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3837171623
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2541840210
Short name T1471
Test name
Test status
Simulation time 10847266344 ps
CPU time 16.69 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:38:01 PM PDT 24
Peak memory 205264 kb
Host smart-59ede467-36db-4c57-b2bc-17305622ba72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25418
40210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2541840210
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2800181310
Short name T87
Test name
Test status
Simulation time 10074429398 ps
CPU time 17.68 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:38:01 PM PDT 24
Peak memory 205464 kb
Host smart-01de6b82-61ec-4214-a679-696dec3242b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28001
81310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2800181310
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2104647905
Short name T579
Test name
Test status
Simulation time 10136459829 ps
CPU time 15.64 seconds
Started May 26 01:37:54 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205296 kb
Host smart-88158dde-10d9-4ff6-8d4c-1732485e7e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21046
47905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2104647905
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1466414161
Short name T918
Test name
Test status
Simulation time 10056042685 ps
CPU time 16.04 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:09 PM PDT 24
Peak memory 205260 kb
Host smart-125fb4c8-4230-4bb9-a22e-1588671e0b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14664
14161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1466414161
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3813114488
Short name T1201
Test name
Test status
Simulation time 10087160242 ps
CPU time 14.87 seconds
Started May 26 01:37:45 PM PDT 24
Finished May 26 01:38:00 PM PDT 24
Peak memory 205048 kb
Host smart-45fee868-3e47-4508-890c-51652313a124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38131
14488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3813114488
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.402929
Short name T1393
Test name
Test status
Simulation time 10094836889 ps
CPU time 13.07 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:37:57 PM PDT 24
Peak memory 205264 kb
Host smart-f1d40db4-bf7c-4e72-b2e6-473d0d204dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40292
9 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.402929
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2510498716
Short name T38
Test name
Test status
Simulation time 13214297256 ps
CPU time 19.71 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:38:04 PM PDT 24
Peak memory 205264 kb
Host smart-67f8527b-d1d8-4676-9d76-dd697b55bf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25104
98716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2510498716
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3328290119
Short name T1129
Test name
Test status
Simulation time 10147686199 ps
CPU time 13.05 seconds
Started May 26 01:37:48 PM PDT 24
Finished May 26 01:38:02 PM PDT 24
Peak memory 205248 kb
Host smart-27e7d45d-67ea-4514-847b-a0c37f33d77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33282
90119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3328290119
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3028702657
Short name T1687
Test name
Test status
Simulation time 10045120837 ps
CPU time 13.57 seconds
Started May 26 01:37:45 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205328 kb
Host smart-c238ca93-c0bc-41a3-9ce6-f835c319e25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287
02657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3028702657
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1159792913
Short name T455
Test name
Test status
Simulation time 10162631446 ps
CPU time 14.42 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205200 kb
Host smart-04ceccdf-500c-4c73-b4e7-e4da3b677bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11597
92913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1159792913
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.1749726256
Short name T558
Test name
Test status
Simulation time 10140795191 ps
CPU time 13.29 seconds
Started May 26 01:37:46 PM PDT 24
Finished May 26 01:38:00 PM PDT 24
Peak memory 205232 kb
Host smart-66ddba61-f5ed-4b50-ba46-af71253ed096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17497
26256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.1749726256
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2827047346
Short name T1650
Test name
Test status
Simulation time 10067437602 ps
CPU time 14.01 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205332 kb
Host smart-3682dfbd-5a11-433c-b0fd-99bea018c7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28270
47346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2827047346
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1551765507
Short name T1453
Test name
Test status
Simulation time 10090253857 ps
CPU time 14.11 seconds
Started May 26 01:37:51 PM PDT 24
Finished May 26 01:38:07 PM PDT 24
Peak memory 205240 kb
Host smart-9f03549f-6846-4378-8d5f-55ca09b86e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15517
65507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1551765507
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.1709300066
Short name T1374
Test name
Test status
Simulation time 10089008673 ps
CPU time 16.52 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205200 kb
Host smart-00fe6265-0d77-49d0-b109-8940003715b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
00066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.1709300066
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2474550863
Short name T634
Test name
Test status
Simulation time 10046188201 ps
CPU time 16.49 seconds
Started May 26 01:37:51 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205284 kb
Host smart-4ae1beae-af0c-488d-8885-7f04a6c67a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24745
50863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2474550863
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2566236736
Short name T613
Test name
Test status
Simulation time 10039662129 ps
CPU time 14.4 seconds
Started May 26 01:37:53 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205176 kb
Host smart-6cec2b91-dc66-40f0-bc0a-60dbbb6059c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25662
36736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2566236736
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3168452720
Short name T1571
Test name
Test status
Simulation time 17641221084 ps
CPU time 30.08 seconds
Started May 26 01:37:48 PM PDT 24
Finished May 26 01:38:19 PM PDT 24
Peak memory 205516 kb
Host smart-e2528701-95ab-4216-8c60-f3ca1db8bad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
52720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3168452720
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2845832283
Short name T1364
Test name
Test status
Simulation time 10120276246 ps
CPU time 15.41 seconds
Started May 26 01:37:43 PM PDT 24
Finished May 26 01:38:00 PM PDT 24
Peak memory 205216 kb
Host smart-f5b7c919-7eaf-4558-aad0-9cec7efb8476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28458
32283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2845832283
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1132204420
Short name T688
Test name
Test status
Simulation time 10142138717 ps
CPU time 15.01 seconds
Started May 26 01:37:48 PM PDT 24
Finished May 26 01:38:04 PM PDT 24
Peak memory 205220 kb
Host smart-6ba8195d-713f-462c-9da8-b6cec26be9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
04420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1132204420
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.490844870
Short name T390
Test name
Test status
Simulation time 10093518121 ps
CPU time 13.84 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:37:59 PM PDT 24
Peak memory 205208 kb
Host smart-8fcaf897-e2d6-4a96-97b5-d8896e5c40ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49084
4870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.490844870
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1749698200
Short name T1773
Test name
Test status
Simulation time 10049376174 ps
CPU time 14.37 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:57 PM PDT 24
Peak memory 205296 kb
Host smart-bc32d779-cc7b-4f6a-ac15-31af76901c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17496
98200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1749698200
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.4097692647
Short name T1862
Test name
Test status
Simulation time 10073070767 ps
CPU time 13.44 seconds
Started May 26 01:37:54 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205264 kb
Host smart-c8847a9d-3f70-44c6-9e1f-1b377ac48319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40976
92647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.4097692647
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1652902504
Short name T538
Test name
Test status
Simulation time 10058143954 ps
CPU time 16.32 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205308 kb
Host smart-e934e751-7583-473a-91c4-485d7012c281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16529
02504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1652902504
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2815687664
Short name T1831
Test name
Test status
Simulation time 10123758673 ps
CPU time 14.69 seconds
Started May 26 01:37:42 PM PDT 24
Finished May 26 01:37:58 PM PDT 24
Peak memory 205268 kb
Host smart-388c45de-28b4-4d7a-924f-da94bdcac5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
87664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2815687664
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.700829596
Short name T1811
Test name
Test status
Simulation time 10057491870 ps
CPU time 14.79 seconds
Started May 26 01:37:56 PM PDT 24
Finished May 26 01:38:12 PM PDT 24
Peak memory 205296 kb
Host smart-a4c08649-f2b2-443d-b3d1-905fb82bff26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70082
9596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.700829596
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.855046643
Short name T31
Test name
Test status
Simulation time 10089309810 ps
CPU time 16.32 seconds
Started May 26 01:37:44 PM PDT 24
Finished May 26 01:38:01 PM PDT 24
Peak memory 205272 kb
Host smart-129e620e-2762-418b-a72f-5692bfd23188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85504
6643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.855046643
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.1481415803
Short name T1767
Test name
Test status
Simulation time 10168558440 ps
CPU time 15.86 seconds
Started May 26 01:37:59 PM PDT 24
Finished May 26 01:38:16 PM PDT 24
Peak memory 205288 kb
Host smart-d4c848c3-2711-49b4-93e3-78d2140fd57e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1481415803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.1481415803
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.1693689616
Short name T700
Test name
Test status
Simulation time 10060233192 ps
CPU time 14.67 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:16 PM PDT 24
Peak memory 205276 kb
Host smart-46c8e111-464b-486f-b69f-c4b5009cd80e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1693689616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.1693689616
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.530565831
Short name T1345
Test name
Test status
Simulation time 10086826860 ps
CPU time 17.76 seconds
Started May 26 01:37:59 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205316 kb
Host smart-7a325a9a-22d1-4f08-854f-40700de13aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53056
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.530565831
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2414738331
Short name T759
Test name
Test status
Simulation time 13867527970 ps
CPU time 17.6 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:11 PM PDT 24
Peak memory 205284 kb
Host smart-3177b8c4-9994-4e90-81f6-75ce408c0b05
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2414738331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.2414738331
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.358521675
Short name T1026
Test name
Test status
Simulation time 13230307606 ps
CPU time 17.46 seconds
Started May 26 01:37:55 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205316 kb
Host smart-2dd82fed-d782-4544-a60b-13aecbfc8f59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=358521675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.358521675
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.2534490713
Short name T608
Test name
Test status
Simulation time 13332135157 ps
CPU time 17.13 seconds
Started May 26 01:37:56 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205292 kb
Host smart-7f067f9c-628e-4411-b2c6-07f84ba4e4fe
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2534490713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.2534490713
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.4240531633
Short name T353
Test name
Test status
Simulation time 10089001484 ps
CPU time 13.79 seconds
Started May 26 01:37:55 PM PDT 24
Finished May 26 01:38:10 PM PDT 24
Peak memory 205248 kb
Host smart-a65f6622-d302-4832-8624-fad509f16111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42405
31633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.4240531633
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2045909941
Short name T1708
Test name
Test status
Simulation time 10883983583 ps
CPU time 18.72 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:12 PM PDT 24
Peak memory 205208 kb
Host smart-fb2e0b3c-05b6-42c4-b826-778015e59cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20459
09941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2045909941
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1424226207
Short name T1588
Test name
Test status
Simulation time 10042274888 ps
CPU time 13.5 seconds
Started May 26 01:37:54 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205324 kb
Host smart-9d65ee41-8a22-4ee0-bbac-039cd7e9c60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14242
26207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1424226207
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3777025843
Short name T878
Test name
Test status
Simulation time 10093637240 ps
CPU time 13.32 seconds
Started May 26 01:37:54 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205320 kb
Host smart-3b8d0184-668f-4b6c-a7c0-607f04eb1241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37770
25843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3777025843
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1140469703
Short name T1758
Test name
Test status
Simulation time 10760768913 ps
CPU time 16.37 seconds
Started May 26 01:37:51 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205188 kb
Host smart-2ac18bf1-2822-4c1a-9d35-00206314b460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11404
69703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1140469703
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1449956309
Short name T1853
Test name
Test status
Simulation time 10055728187 ps
CPU time 14.03 seconds
Started May 26 01:38:02 PM PDT 24
Finished May 26 01:38:17 PM PDT 24
Peak memory 205184 kb
Host smart-28e66543-c8bf-4a33-b406-f33cf7fc9638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14499
56309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1449956309
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.3662090137
Short name T226
Test name
Test status
Simulation time 10049961453 ps
CPU time 14.16 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:16 PM PDT 24
Peak memory 205184 kb
Host smart-3a0e894f-fb3a-4d5f-95d4-d91ea0f69202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36620
90137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3662090137
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.843801686
Short name T426
Test name
Test status
Simulation time 10073649347 ps
CPU time 12.82 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:15 PM PDT 24
Peak memory 205180 kb
Host smart-5b156385-42ce-448b-8d55-adad4e5e87a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84380
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.843801686
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3409317414
Short name T1712
Test name
Test status
Simulation time 10120459521 ps
CPU time 15.26 seconds
Started May 26 01:37:51 PM PDT 24
Finished May 26 01:38:07 PM PDT 24
Peak memory 205280 kb
Host smart-e5229924-a215-40f5-96a8-01cd1c2665d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34093
17414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3409317414
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3793479511
Short name T251
Test name
Test status
Simulation time 10090891002 ps
CPU time 14.5 seconds
Started May 26 01:38:02 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205208 kb
Host smart-52a78319-086e-4575-979f-72412fca9f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
79511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3793479511
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3218952581
Short name T1532
Test name
Test status
Simulation time 13242801442 ps
CPU time 21.93 seconds
Started May 26 01:37:51 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205276 kb
Host smart-17e91faf-9a30-4ed7-aca0-0bcd6614cc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32189
52581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3218952581
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3423607214
Short name T1292
Test name
Test status
Simulation time 10095783258 ps
CPU time 16.7 seconds
Started May 26 01:38:03 PM PDT 24
Finished May 26 01:38:20 PM PDT 24
Peak memory 205228 kb
Host smart-0795c02e-a00a-4871-879f-e0160e60c7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34236
07214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3423607214
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.194210652
Short name T1791
Test name
Test status
Simulation time 10093182819 ps
CPU time 15.05 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:09 PM PDT 24
Peak memory 205340 kb
Host smart-2dbbf842-e96f-4030-9397-3b60c782fa73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19421
0652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.194210652
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2120110902
Short name T107
Test name
Test status
Simulation time 10103465486 ps
CPU time 13.69 seconds
Started May 26 01:37:53 PM PDT 24
Finished May 26 01:38:07 PM PDT 24
Peak memory 205432 kb
Host smart-55f952d4-8111-45c5-aa74-8553c941cd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21201
10902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2120110902
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1248996094
Short name T1913
Test name
Test status
Simulation time 10093502201 ps
CPU time 14.62 seconds
Started May 26 01:37:52 PM PDT 24
Finished May 26 01:38:08 PM PDT 24
Peak memory 205244 kb
Host smart-290f1c6b-d184-4b28-9012-7c65a3e5474b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12489
96094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1248996094
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.865389025
Short name T663
Test name
Test status
Simulation time 10081901661 ps
CPU time 14.76 seconds
Started May 26 01:37:51 PM PDT 24
Finished May 26 01:38:07 PM PDT 24
Peak memory 205304 kb
Host smart-4d5988cb-d0cb-4caf-a682-96d454ca77f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86538
9025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.865389025
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3805026303
Short name T813
Test name
Test status
Simulation time 10080776821 ps
CPU time 13.55 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205252 kb
Host smart-0638f97a-4e13-4b6e-b8fd-1d1cd8589d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38050
26303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3805026303
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.248726747
Short name T1703
Test name
Test status
Simulation time 10056979315 ps
CPU time 15.63 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205256 kb
Host smart-c7a3097c-2b9f-4de5-b627-fd7d1dd3dc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24872
6747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.248726747
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.1086606968
Short name T313
Test name
Test status
Simulation time 10062659513 ps
CPU time 13.35 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205180 kb
Host smart-1ea22b85-4eff-4d22-b886-8e1372f19d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
06968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.1086606968
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1151084072
Short name T1236
Test name
Test status
Simulation time 10048048986 ps
CPU time 14.14 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:15 PM PDT 24
Peak memory 205312 kb
Host smart-3c7f7c95-6bc1-485d-a0be-401adb8b86a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11510
84072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1151084072
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3844299178
Short name T1177
Test name
Test status
Simulation time 10040681332 ps
CPU time 13.77 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:16 PM PDT 24
Peak memory 205288 kb
Host smart-541fe0d3-ec3c-4085-b6ca-8f7b58bb3903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38442
99178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3844299178
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2450054965
Short name T1560
Test name
Test status
Simulation time 23021744582 ps
CPU time 42.07 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:45 PM PDT 24
Peak memory 205380 kb
Host smart-e9c57aa4-8fb6-4415-824b-7bb223c41abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500
54965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2450054965
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.560843615
Short name T594
Test name
Test status
Simulation time 10064031734 ps
CPU time 13.36 seconds
Started May 26 01:37:59 PM PDT 24
Finished May 26 01:38:13 PM PDT 24
Peak memory 205216 kb
Host smart-3dfaeece-d2e7-420f-9d16-fd0911d62975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56084
3615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.560843615
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3880029511
Short name T1799
Test name
Test status
Simulation time 10127802582 ps
CPU time 16.12 seconds
Started May 26 01:37:58 PM PDT 24
Finished May 26 01:38:15 PM PDT 24
Peak memory 205220 kb
Host smart-fd018bd3-8694-4e50-a8a4-ad27831d60fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38800
29511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3880029511
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1291758532
Short name T1110
Test name
Test status
Simulation time 10068934655 ps
CPU time 13.31 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:16 PM PDT 24
Peak memory 205292 kb
Host smart-c1921b24-6978-4c91-adb5-62e6bdb02697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12917
58532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1291758532
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1353950
Short name T1003
Test name
Test status
Simulation time 10060864518 ps
CPU time 16.64 seconds
Started May 26 01:37:58 PM PDT 24
Finished May 26 01:38:16 PM PDT 24
Peak memory 205252 kb
Host smart-7403988b-9a77-4af4-9ccd-c9221df7f1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
50 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1353950
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.4177485309
Short name T1203
Test name
Test status
Simulation time 10059129099 ps
CPU time 15.41 seconds
Started May 26 01:37:59 PM PDT 24
Finished May 26 01:38:15 PM PDT 24
Peak memory 205256 kb
Host smart-1cc99520-7874-4906-b468-05ff75479c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41774
85309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.4177485309
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1584326798
Short name T520
Test name
Test status
Simulation time 10088383051 ps
CPU time 13.3 seconds
Started May 26 01:38:09 PM PDT 24
Finished May 26 01:38:24 PM PDT 24
Peak memory 205232 kb
Host smart-e045a836-8e08-4463-9962-443eecffee68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15843
26798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1584326798
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2142242661
Short name T1390
Test name
Test status
Simulation time 10112952641 ps
CPU time 14.36 seconds
Started May 26 01:38:03 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205224 kb
Host smart-a5278bf4-2d70-4afe-8a7e-bc4eab9b8c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422
42661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2142242661
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3449593526
Short name T3
Test name
Test status
Simulation time 10062144596 ps
CPU time 13.31 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:14 PM PDT 24
Peak memory 205240 kb
Host smart-adc148e9-675e-45da-ad4d-2e471ea39ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34495
93526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3449593526
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3772733352
Short name T884
Test name
Test status
Simulation time 10104954350 ps
CPU time 15.97 seconds
Started May 26 01:38:04 PM PDT 24
Finished May 26 01:38:20 PM PDT 24
Peak memory 205240 kb
Host smart-0c704993-7823-4509-8296-2bfbf4a52df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37727
33352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3772733352
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.335834531
Short name T974
Test name
Test status
Simulation time 10136957379 ps
CPU time 16.95 seconds
Started May 26 01:38:07 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205312 kb
Host smart-46c63a53-bf7d-4df9-944d-1eb258135fc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=335834531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.335834531
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.2693386589
Short name T1209
Test name
Test status
Simulation time 10065698815 ps
CPU time 13.41 seconds
Started May 26 01:38:10 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205332 kb
Host smart-8403e3ed-0bc6-497d-ba67-7ff31928b125
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2693386589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.2693386589
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.1116716346
Short name T810
Test name
Test status
Simulation time 10127237132 ps
CPU time 14.74 seconds
Started May 26 01:38:12 PM PDT 24
Finished May 26 01:38:27 PM PDT 24
Peak memory 205272 kb
Host smart-a6b6b198-9f3e-466d-93c6-84e33fd4d15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11167
16346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.1116716346
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.4162725161
Short name T9
Test name
Test status
Simulation time 13513785557 ps
CPU time 18.06 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:20 PM PDT 24
Peak memory 205272 kb
Host smart-ab2e5273-4d4e-4b40-b98d-8fcd211590cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4162725161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.4162725161
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1399399673
Short name T406
Test name
Test status
Simulation time 13257636247 ps
CPU time 17.14 seconds
Started May 26 01:38:05 PM PDT 24
Finished May 26 01:38:23 PM PDT 24
Peak memory 205344 kb
Host smart-6dfcf6af-dbb6-438d-928a-731f0e5cc299
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1399399673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1399399673
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1715014716
Short name T1575
Test name
Test status
Simulation time 13256763221 ps
CPU time 17.11 seconds
Started May 26 01:38:00 PM PDT 24
Finished May 26 01:38:19 PM PDT 24
Peak memory 205260 kb
Host smart-7984a020-cb89-4cb8-81be-8adcddd543f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1715014716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.1715014716
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4106538863
Short name T1547
Test name
Test status
Simulation time 10065755367 ps
CPU time 16.5 seconds
Started May 26 01:38:06 PM PDT 24
Finished May 26 01:38:24 PM PDT 24
Peak memory 205296 kb
Host smart-87a36bcf-9ce0-4682-83fc-1dc5e4178a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41065
38863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4106538863
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.4174001873
Short name T170
Test name
Test status
Simulation time 10796238622 ps
CPU time 15.68 seconds
Started May 26 01:38:03 PM PDT 24
Finished May 26 01:38:20 PM PDT 24
Peak memory 205188 kb
Host smart-164977cb-20ba-455a-a3da-065dbaca5bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41740
01873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.4174001873
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_enable.1382051471
Short name T1775
Test name
Test status
Simulation time 10058141886 ps
CPU time 14.63 seconds
Started May 26 01:38:06 PM PDT 24
Finished May 26 01:38:21 PM PDT 24
Peak memory 205348 kb
Host smart-e80683e8-98a3-4706-bc82-56c3218e7b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13820
51471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1382051471
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1583187488
Short name T1394
Test name
Test status
Simulation time 10710409279 ps
CPU time 15.88 seconds
Started May 26 01:38:06 PM PDT 24
Finished May 26 01:38:22 PM PDT 24
Peak memory 205348 kb
Host smart-66957bac-018e-4834-884c-414b0e271272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15831
87488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1583187488
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2994157689
Short name T915
Test name
Test status
Simulation time 10208455350 ps
CPU time 17.82 seconds
Started May 26 01:38:02 PM PDT 24
Finished May 26 01:38:21 PM PDT 24
Peak memory 205308 kb
Host smart-23d791b5-a0e4-49e3-8501-2e2fbff73683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29941
57689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2994157689
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.754610433
Short name T1797
Test name
Test status
Simulation time 10114237222 ps
CPU time 13.83 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:23 PM PDT 24
Peak memory 205324 kb
Host smart-7f112f5b-ce64-48b6-acaf-09684c70cfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75461
0433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.754610433
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.465063448
Short name T766
Test name
Test status
Simulation time 10089832111 ps
CPU time 16.2 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:26 PM PDT 24
Peak memory 205280 kb
Host smart-1951967f-458c-4bf7-abd6-ad117aa35446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46506
3448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.465063448
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.806753657
Short name T350
Test name
Test status
Simulation time 10106262202 ps
CPU time 13.63 seconds
Started May 26 01:38:04 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205204 kb
Host smart-ef7f659c-5516-4178-ac65-b1b157c73db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80675
3657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.806753657
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2923264333
Short name T1573
Test name
Test status
Simulation time 10077719485 ps
CPU time 15.95 seconds
Started May 26 01:38:05 PM PDT 24
Finished May 26 01:38:22 PM PDT 24
Peak memory 205232 kb
Host smart-5c2557d1-3db7-4d88-a158-4d9d2aee18ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29232
64333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2923264333
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1031959532
Short name T586
Test name
Test status
Simulation time 13200623999 ps
CPU time 17.46 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:19 PM PDT 24
Peak memory 205296 kb
Host smart-99dda583-8c0d-4320-a94e-bf382ea73320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10319
59532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1031959532
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3104895010
Short name T660
Test name
Test status
Simulation time 10177176724 ps
CPU time 14.1 seconds
Started May 26 01:38:05 PM PDT 24
Finished May 26 01:38:20 PM PDT 24
Peak memory 205344 kb
Host smart-8edf02dd-98fa-438d-b583-b3a057fc636b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31048
95010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3104895010
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3278815630
Short name T1529
Test name
Test status
Simulation time 10069802679 ps
CPU time 16.77 seconds
Started May 26 01:38:02 PM PDT 24
Finished May 26 01:38:20 PM PDT 24
Peak memory 205260 kb
Host smart-7386d572-a0c1-4107-8442-3872d1a65b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32788
15630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3278815630
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3145720304
Short name T127
Test name
Test status
Simulation time 10090548127 ps
CPU time 14.57 seconds
Started May 26 01:38:02 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205488 kb
Host smart-11814daf-5fe8-47e7-9912-a852212372c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457
20304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3145720304
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3940979143
Short name T1823
Test name
Test status
Simulation time 10087811476 ps
CPU time 13.78 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:24 PM PDT 24
Peak memory 205244 kb
Host smart-3896499c-a86e-4703-a797-a474f98a5e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
79143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3940979143
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3245782071
Short name T1363
Test name
Test status
Simulation time 10068873364 ps
CPU time 14.9 seconds
Started May 26 01:38:09 PM PDT 24
Finished May 26 01:38:26 PM PDT 24
Peak memory 205200 kb
Host smart-e8589424-6c55-4dc9-b9e0-cdb411da8f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
82071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3245782071
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1921560148
Short name T805
Test name
Test status
Simulation time 10076572221 ps
CPU time 14.82 seconds
Started May 26 01:38:10 PM PDT 24
Finished May 26 01:38:26 PM PDT 24
Peak memory 205304 kb
Host smart-2e1e3f62-8407-4f48-a4f2-8ec2d36015f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
60148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1921560148
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4088840991
Short name T1861
Test name
Test status
Simulation time 10113329672 ps
CPU time 14.44 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205268 kb
Host smart-45c3e527-788b-4388-ad6d-4fd231691e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40888
40991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4088840991
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.1104126717
Short name T1231
Test name
Test status
Simulation time 10067454309 ps
CPU time 14.89 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:24 PM PDT 24
Peak memory 205280 kb
Host smart-413ff670-a729-4109-9cae-0c20ca8c2a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11041
26717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.1104126717
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.90549570
Short name T626
Test name
Test status
Simulation time 10060346069 ps
CPU time 12.82 seconds
Started May 26 01:38:11 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205276 kb
Host smart-537f5743-c7f2-4878-b9ba-2f8d4094f6b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90549
570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.90549570
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.128895141
Short name T19
Test name
Test status
Simulation time 10040425713 ps
CPU time 17.1 seconds
Started May 26 01:38:10 PM PDT 24
Finished May 26 01:38:28 PM PDT 24
Peak memory 205188 kb
Host smart-7f0f35c7-60a6-49ae-9a6c-ca4082f72eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
5141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.128895141
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2458685034
Short name T1716
Test name
Test status
Simulation time 31983315063 ps
CPU time 67.62 seconds
Started May 26 01:38:11 PM PDT 24
Finished May 26 01:39:20 PM PDT 24
Peak memory 205252 kb
Host smart-d6efca01-e493-40f3-b922-afaff85b5f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24586
85034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2458685034
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3782543064
Short name T1488
Test name
Test status
Simulation time 10072849705 ps
CPU time 14.32 seconds
Started May 26 01:38:09 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205344 kb
Host smart-7b1193bd-69da-4f78-a1fd-f23f4b217047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37825
43064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3782543064
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3940923581
Short name T747
Test name
Test status
Simulation time 10136571103 ps
CPU time 14.23 seconds
Started May 26 01:38:16 PM PDT 24
Finished May 26 01:38:31 PM PDT 24
Peak memory 205228 kb
Host smart-8d17c7b7-270a-42c1-96a1-ebad3f52f468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39409
23581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3940923581
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.2705473791
Short name T1551
Test name
Test status
Simulation time 10096949313 ps
CPU time 14.16 seconds
Started May 26 01:38:11 PM PDT 24
Finished May 26 01:38:26 PM PDT 24
Peak memory 205336 kb
Host smart-28292cc5-61f3-4486-a9ff-941dcd55f5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
73791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.2705473791
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3709313035
Short name T1181
Test name
Test status
Simulation time 10045839621 ps
CPU time 14.36 seconds
Started May 26 01:38:10 PM PDT 24
Finished May 26 01:38:26 PM PDT 24
Peak memory 205204 kb
Host smart-b787af6e-3aa6-477c-94b4-bf68967b6c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37093
13035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3709313035
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3122487498
Short name T1544
Test name
Test status
Simulation time 10055120532 ps
CPU time 14.96 seconds
Started May 26 01:38:07 PM PDT 24
Finished May 26 01:38:24 PM PDT 24
Peak memory 205256 kb
Host smart-77de130b-d464-42a1-bdb0-4839244297a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
87498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3122487498
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.4289872747
Short name T1235
Test name
Test status
Simulation time 10060039911 ps
CPU time 14.05 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:23 PM PDT 24
Peak memory 205252 kb
Host smart-8851ac33-6a94-4458-afa4-1bcb0c8788a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42898
72747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.4289872747
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.170649211
Short name T975
Test name
Test status
Simulation time 10135527760 ps
CPU time 15.82 seconds
Started May 26 01:38:01 PM PDT 24
Finished May 26 01:38:18 PM PDT 24
Peak memory 205300 kb
Host smart-3e9529ac-9038-4af7-8364-b1d76451226d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
9211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.170649211
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.4206782263
Short name T433
Test name
Test status
Simulation time 10058602069 ps
CPU time 18.21 seconds
Started May 26 01:38:09 PM PDT 24
Finished May 26 01:38:29 PM PDT 24
Peak memory 205340 kb
Host smart-81694e20-4705-4d58-80fa-29b63c26786b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
82263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.4206782263
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1027742981
Short name T376
Test name
Test status
Simulation time 10083559099 ps
CPU time 14.72 seconds
Started May 26 01:38:08 PM PDT 24
Finished May 26 01:38:24 PM PDT 24
Peak memory 205316 kb
Host smart-e8dec3e9-c0da-4eac-b9c5-6a24a1e25fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277
42981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1027742981
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3288678721
Short name T395
Test name
Test status
Simulation time 10163151342 ps
CPU time 13.21 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:32 PM PDT 24
Peak memory 205348 kb
Host smart-5b15bdd6-805a-4e18-b92c-c03649dc917a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3288678721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3288678721
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.761472545
Short name T389
Test name
Test status
Simulation time 10047183240 ps
CPU time 13.08 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205332 kb
Host smart-6b3af759-2b0f-4ad5-a5a4-b91c6a254da8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=761472545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.761472545
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.2792737941
Short name T1933
Test name
Test status
Simulation time 10121407100 ps
CPU time 14.16 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205180 kb
Host smart-10ca45f8-e30e-4364-baf8-59695eb85c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27927
37941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.2792737941
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2687694905
Short name T1148
Test name
Test status
Simulation time 14095512917 ps
CPU time 17.97 seconds
Started May 26 01:38:13 PM PDT 24
Finished May 26 01:38:32 PM PDT 24
Peak memory 205252 kb
Host smart-591e136b-ae5d-4496-92af-930d799683e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2687694905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2687694905
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.263696715
Short name T1614
Test name
Test status
Simulation time 13244533396 ps
CPU time 16.74 seconds
Started May 26 01:38:09 PM PDT 24
Finished May 26 01:38:27 PM PDT 24
Peak memory 205356 kb
Host smart-952082b9-c77c-4b39-9d79-a81a3dcc5d1b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=263696715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.263696715
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1326354590
Short name T846
Test name
Test status
Simulation time 13299332465 ps
CPU time 17.1 seconds
Started May 26 01:38:07 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205300 kb
Host smart-ab11c4e0-9f54-48e1-bf31-2b2d9bdcf5f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1326354590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1326354590
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3771092762
Short name T1528
Test name
Test status
Simulation time 10055996715 ps
CPU time 17.62 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:39 PM PDT 24
Peak memory 205252 kb
Host smart-a2426c06-e658-4998-bd3e-58460aabc22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37710
92762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3771092762
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2463890253
Short name T1611
Test name
Test status
Simulation time 10062760968 ps
CPU time 13.29 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:33 PM PDT 24
Peak memory 205340 kb
Host smart-f7d7a88a-c37c-4a5d-b3f6-7d5d40d7300d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24638
90253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2463890253
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2762971248
Short name T196
Test name
Test status
Simulation time 10657236809 ps
CPU time 14.79 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:35 PM PDT 24
Peak memory 205368 kb
Host smart-bcd47251-5a7c-4bc2-8bb4-8879acb908d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27629
71248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2762971248
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.4139182584
Short name T77
Test name
Test status
Simulation time 10038436303 ps
CPU time 17.06 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:37 PM PDT 24
Peak memory 205264 kb
Host smart-bf4d64e2-d40a-4d66-9353-65cb19a51ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41391
82584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.4139182584
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2075364507
Short name T364
Test name
Test status
Simulation time 10059612653 ps
CPU time 15.15 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205340 kb
Host smart-d5f87dc0-2a2e-4451-853c-703bda72dcf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
64507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2075364507
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3813095209
Short name T1161
Test name
Test status
Simulation time 10807299966 ps
CPU time 15.63 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205304 kb
Host smart-a6fcc81d-e0a8-42ad-924e-63b630e26d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38130
95209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3813095209
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2763658410
Short name T1719
Test name
Test status
Simulation time 10133022213 ps
CPU time 17.28 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205276 kb
Host smart-ef9701eb-3769-4934-a833-e8f0ef8c1088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
58410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2763658410
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1360940969
Short name T1182
Test name
Test status
Simulation time 10108698026 ps
CPU time 15.67 seconds
Started May 26 01:38:17 PM PDT 24
Finished May 26 01:38:33 PM PDT 24
Peak memory 205260 kb
Host smart-d923bd80-2887-4f4c-8958-aea78a54eff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13609
40969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1360940969
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3058242075
Short name T760
Test name
Test status
Simulation time 10036990189 ps
CPU time 17.33 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:38 PM PDT 24
Peak memory 205216 kb
Host smart-50e8721e-b863-4dec-b01f-d0cb3d8d12e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30582
42075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3058242075
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.4131760455
Short name T1776
Test name
Test status
Simulation time 10089937609 ps
CPU time 13.72 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205352 kb
Host smart-a732b810-5f28-4957-9ef2-6d4281cb1cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41317
60455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.4131760455
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2285031987
Short name T1564
Test name
Test status
Simulation time 10115288543 ps
CPU time 13.98 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205272 kb
Host smart-9f82d16b-1c88-468e-b68b-82cf2312f4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22850
31987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2285031987
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.1489509593
Short name T1185
Test name
Test status
Simulation time 13311031120 ps
CPU time 20.75 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:41 PM PDT 24
Peak memory 205212 kb
Host smart-df3945d5-01f0-41e8-abeb-7222fae83bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
09593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1489509593
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.50232635
Short name T1451
Test name
Test status
Simulation time 10119288529 ps
CPU time 14.54 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205284 kb
Host smart-41baecfd-074b-484d-a897-c97fea33d329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50232
635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.50232635
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3102956356
Short name T1322
Test name
Test status
Simulation time 10084605033 ps
CPU time 14.61 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:35 PM PDT 24
Peak memory 205216 kb
Host smart-2efeb30e-a285-4d0b-95ca-120f4e7eed36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31029
56356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3102956356
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3757684529
Short name T117
Test name
Test status
Simulation time 10085273089 ps
CPU time 15.52 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:38 PM PDT 24
Peak memory 205292 kb
Host smart-b4ace421-bca9-4173-8ede-2b9b9a9bdb29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37576
84529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3757684529
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1632680537
Short name T1929
Test name
Test status
Simulation time 10081004208 ps
CPU time 15.1 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205288 kb
Host smart-ac373a87-48cc-4f29-8cc4-81f6df7609c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16326
80537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1632680537
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1543634929
Short name T1580
Test name
Test status
Simulation time 10097418944 ps
CPU time 13.19 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205256 kb
Host smart-81779bfc-3d10-4c91-b583-b6cbf4df8be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
34929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1543634929
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3966638792
Short name T1044
Test name
Test status
Simulation time 10063701077 ps
CPU time 13.79 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205192 kb
Host smart-59dfb578-9706-4711-bb29-b6a693f25559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666
38792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3966638792
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1352167268
Short name T199
Test name
Test status
Simulation time 10106960484 ps
CPU time 14.8 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205292 kb
Host smart-7973f556-6a18-4c1f-88c4-59c353562b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13521
67268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1352167268
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.398185912
Short name T1413
Test name
Test status
Simulation time 10057554219 ps
CPU time 14.95 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:35 PM PDT 24
Peak memory 205308 kb
Host smart-1bcf0ff0-cd3f-4c60-bd78-62531e5d25c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818
5912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.398185912
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3946662495
Short name T748
Test name
Test status
Simulation time 10046104485 ps
CPU time 14.32 seconds
Started May 26 01:38:21 PM PDT 24
Finished May 26 01:38:37 PM PDT 24
Peak memory 205316 kb
Host smart-70d58a91-9282-4611-8504-f3d76c03c2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39466
62495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3946662495
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3345185203
Short name T521
Test name
Test status
Simulation time 10035259095 ps
CPU time 14.2 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205224 kb
Host smart-fdbb3307-2888-4dcd-899f-1f04204a4b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33451
85203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3345185203
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3389732422
Short name T259
Test name
Test status
Simulation time 31987166472 ps
CPU time 67.31 seconds
Started May 26 01:38:16 PM PDT 24
Finished May 26 01:39:24 PM PDT 24
Peak memory 205324 kb
Host smart-a752beaa-491e-46c1-a83f-54b1ce95cdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897
32422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3389732422
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3636720857
Short name T1880
Test name
Test status
Simulation time 10081865218 ps
CPU time 13.66 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205244 kb
Host smart-95d3dda8-eafe-4950-9575-44d04eff749b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36367
20857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3636720857
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3358702836
Short name T1229
Test name
Test status
Simulation time 10101578099 ps
CPU time 14.36 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205268 kb
Host smart-854d6c0f-8161-45a9-b4ce-9c13d2ef0d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33587
02836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3358702836
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.1082749958
Short name T1189
Test name
Test status
Simulation time 10104767294 ps
CPU time 16.18 seconds
Started May 26 01:38:22 PM PDT 24
Finished May 26 01:38:39 PM PDT 24
Peak memory 205268 kb
Host smart-1a16ae5d-d6cd-43b5-9383-dae5ae67a220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10827
49958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.1082749958
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1279531150
Short name T222
Test name
Test status
Simulation time 10038530128 ps
CPU time 13.37 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:35 PM PDT 24
Peak memory 205296 kb
Host smart-9aae25c1-b58e-4cb0-8d77-6722d75580ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12795
31150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1279531150
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3066116160
Short name T89
Test name
Test status
Simulation time 10050703513 ps
CPU time 16.62 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:37 PM PDT 24
Peak memory 205240 kb
Host smart-e52d0c2a-1139-4700-9621-62622d587d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30661
16160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3066116160
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2565336779
Short name T1857
Test name
Test status
Simulation time 10042866344 ps
CPU time 13.88 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205220 kb
Host smart-5ef31158-a0a8-4a9f-abe6-b6ac6d2816c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25653
36779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2565336779
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1305224302
Short name T907
Test name
Test status
Simulation time 10102215076 ps
CPU time 14.71 seconds
Started May 26 01:38:09 PM PDT 24
Finished May 26 01:38:25 PM PDT 24
Peak memory 205248 kb
Host smart-f201ebfc-3c6d-41a2-a6a7-eb5e6cedb2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13052
24302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1305224302
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1487880822
Short name T516
Test name
Test status
Simulation time 10055365382 ps
CPU time 14.14 seconds
Started May 26 01:38:21 PM PDT 24
Finished May 26 01:38:37 PM PDT 24
Peak memory 205280 kb
Host smart-065c7258-2555-44de-8a93-4820173b30ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14878
80822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1487880822
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3408426874
Short name T1260
Test name
Test status
Simulation time 10075244681 ps
CPU time 16.33 seconds
Started May 26 01:38:21 PM PDT 24
Finished May 26 01:38:39 PM PDT 24
Peak memory 205224 kb
Host smart-cdd32435-69b0-41bf-aee5-930b580baa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
26874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3408426874
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.3404981205
Short name T1019
Test name
Test status
Simulation time 10152774415 ps
CPU time 13.79 seconds
Started May 26 01:38:30 PM PDT 24
Finished May 26 01:38:45 PM PDT 24
Peak memory 205312 kb
Host smart-ac8111b4-1226-44bb-a265-e1e095d0ba5c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3404981205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.3404981205
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.3282480827
Short name T972
Test name
Test status
Simulation time 10054169585 ps
CPU time 13.61 seconds
Started May 26 01:38:35 PM PDT 24
Finished May 26 01:38:51 PM PDT 24
Peak memory 204676 kb
Host smart-8a8b101f-6d74-49de-9e3f-83e50d090a8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3282480827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.3282480827
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.1687787006
Short name T1600
Test name
Test status
Simulation time 10140156094 ps
CPU time 13.44 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205256 kb
Host smart-c625ca96-57dc-4434-b940-5d5ce9d32e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
87006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.1687787006
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4079251279
Short name T1863
Test name
Test status
Simulation time 14045979764 ps
CPU time 18.01 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:40 PM PDT 24
Peak memory 205280 kb
Host smart-b1265515-b3b4-4ea6-9aa8-525a934f95d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4079251279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.4079251279
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.554282773
Short name T1245
Test name
Test status
Simulation time 13253241002 ps
CPU time 16.9 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:39 PM PDT 24
Peak memory 205224 kb
Host smart-7ae96141-e814-46c9-a2d5-1f085600657f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=554282773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.554282773
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2055846486
Short name T500
Test name
Test status
Simulation time 13210664610 ps
CPU time 21.21 seconds
Started May 26 01:38:21 PM PDT 24
Finished May 26 01:38:44 PM PDT 24
Peak memory 205296 kb
Host smart-b30d548c-5621-41e3-96c3-c365dc258543
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2055846486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2055846486
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1835397332
Short name T794
Test name
Test status
Simulation time 10054911047 ps
CPU time 13.99 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205296 kb
Host smart-d74bd954-5a59-4d75-9fa4-5859611efc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18353
97332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1835397332
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.40389305
Short name T233
Test name
Test status
Simulation time 10070186450 ps
CPU time 14.02 seconds
Started May 26 01:38:22 PM PDT 24
Finished May 26 01:38:37 PM PDT 24
Peak memory 205240 kb
Host smart-a66f456e-e35b-455c-ae02-50c822c01239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.40389305
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.842719163
Short name T1931
Test name
Test status
Simulation time 10648560336 ps
CPU time 17.16 seconds
Started May 26 01:38:17 PM PDT 24
Finished May 26 01:38:35 PM PDT 24
Peak memory 205328 kb
Host smart-b93f4b1d-6c95-4fc3-878c-367c44090333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84271
9163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.842719163
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.756925557
Short name T774
Test name
Test status
Simulation time 10041207261 ps
CPU time 14.71 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 205312 kb
Host smart-71970713-9d89-4633-8650-78afb4dcc85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75692
5557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.756925557
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1861424836
Short name T678
Test name
Test status
Simulation time 10060434588 ps
CPU time 13.22 seconds
Started May 26 01:38:21 PM PDT 24
Finished May 26 01:38:36 PM PDT 24
Peak memory 205284 kb
Host smart-28939a85-a0eb-419e-8514-e10ad23422ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18614
24836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1861424836
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3831126783
Short name T1523
Test name
Test status
Simulation time 10852846006 ps
CPU time 16.26 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:38 PM PDT 24
Peak memory 205252 kb
Host smart-b72be039-7f61-44ba-afb7-9c28b9b71235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38311
26783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3831126783
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.774263627
Short name T791
Test name
Test status
Simulation time 10153387098 ps
CPU time 16.12 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:39 PM PDT 24
Peak memory 205324 kb
Host smart-b67f8ff4-cdd0-4b69-8bef-7dd4b52dfdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77426
3627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.774263627
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3699399718
Short name T70
Test name
Test status
Simulation time 10202097213 ps
CPU time 15.42 seconds
Started May 26 01:38:36 PM PDT 24
Finished May 26 01:38:53 PM PDT 24
Peak memory 205232 kb
Host smart-0aa3bd04-f62b-41be-8bfe-d96bd81f8a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36993
99718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3699399718
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.329718310
Short name T417
Test name
Test status
Simulation time 10076437888 ps
CPU time 12.85 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 205220 kb
Host smart-fd2495df-0450-4465-bac5-18682529cc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32971
8310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.329718310
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.929898541
Short name T451
Test name
Test status
Simulation time 10077662763 ps
CPU time 15.79 seconds
Started May 26 01:38:20 PM PDT 24
Finished May 26 01:38:37 PM PDT 24
Peak memory 205224 kb
Host smart-6d338a1c-8fc2-4ac7-bb22-bca62960eaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92989
8541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.929898541
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2656460954
Short name T728
Test name
Test status
Simulation time 10069041297 ps
CPU time 14.45 seconds
Started May 26 01:38:18 PM PDT 24
Finished May 26 01:38:33 PM PDT 24
Peak memory 205280 kb
Host smart-591a67ca-ca50-48f0-a55a-70de4b889f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26564
60954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2656460954
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2251698213
Short name T795
Test name
Test status
Simulation time 13196383987 ps
CPU time 16.66 seconds
Started May 26 01:38:22 PM PDT 24
Finished May 26 01:38:40 PM PDT 24
Peak memory 205220 kb
Host smart-f20630d3-7760-454a-b3d1-d4577f4038d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22516
98213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2251698213
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2459859748
Short name T607
Test name
Test status
Simulation time 10090014369 ps
CPU time 12.92 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:44 PM PDT 24
Peak memory 205276 kb
Host smart-2398d0ed-7665-4eae-bcdf-4bd77e057054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24598
59748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2459859748
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1506289720
Short name T614
Test name
Test status
Simulation time 10074344402 ps
CPU time 13.9 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205312 kb
Host smart-7d29a05a-2d3b-4fec-b8f2-a07f2770a24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15062
89720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1506289720
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.4110817135
Short name T104
Test name
Test status
Simulation time 10105498038 ps
CPU time 15.24 seconds
Started May 26 01:38:30 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 205268 kb
Host smart-ad508931-c29c-41b8-bd69-bb5339fc125b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41108
17135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.4110817135
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3353997554
Short name T439
Test name
Test status
Simulation time 10173712538 ps
CPU time 14.02 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 205292 kb
Host smart-db71e5cb-47af-4d3b-92a4-978dbed532c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33539
97554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3353997554
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2490979870
Short name T20
Test name
Test status
Simulation time 10101823219 ps
CPU time 13.47 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 205208 kb
Host smart-7dc65010-2c40-4043-825c-b02f60625588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24909
79870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2490979870
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2118468481
Short name T1927
Test name
Test status
Simulation time 10097241550 ps
CPU time 13.85 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 205300 kb
Host smart-0a9f6dc6-be64-4084-9c80-cbf8c82dda30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21184
68481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2118468481
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2367015732
Short name T185
Test name
Test status
Simulation time 10050747183 ps
CPU time 14.66 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205192 kb
Host smart-c55323a6-d5a3-4ce4-b1a7-5b133d853332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23670
15732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2367015732
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.2112761513
Short name T1426
Test name
Test status
Simulation time 10044590547 ps
CPU time 14.33 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205300 kb
Host smart-ed2d6240-a0f3-4ec3-a14a-4705971a6a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21127
61513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.2112761513
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3976959839
Short name T1697
Test name
Test status
Simulation time 10045956930 ps
CPU time 13.7 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 205468 kb
Host smart-0323414c-1085-4cf9-a4e8-8fa57b2ccb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39769
59839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3976959839
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.733576298
Short name T1742
Test name
Test status
Simulation time 10074878641 ps
CPU time 13.01 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:49 PM PDT 24
Peak memory 205232 kb
Host smart-f5e21eeb-b40a-4dd3-b87b-e82b53cabd8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73357
6298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.733576298
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1750241593
Short name T1843
Test name
Test status
Simulation time 32423537250 ps
CPU time 59.98 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:39:34 PM PDT 24
Peak memory 205316 kb
Host smart-0f26a765-25dd-48cf-8442-1677707c6985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
41593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1750241593
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2830657520
Short name T994
Test name
Test status
Simulation time 10092971728 ps
CPU time 13.6 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205468 kb
Host smart-fed94934-ab7b-4ea5-bc69-12d692309971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306
57520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2830657520
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1175525320
Short name T1565
Test name
Test status
Simulation time 10149370604 ps
CPU time 16.08 seconds
Started May 26 01:38:30 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 205312 kb
Host smart-c8dbb73a-3eea-4114-a267-627236bca003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11755
25320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1175525320
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.3190434184
Short name T1552
Test name
Test status
Simulation time 10090483877 ps
CPU time 12.78 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205232 kb
Host smart-1a77569b-c1da-4be1-b1c0-147bb80bc96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
34184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.3190434184
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2353080612
Short name T1741
Test name
Test status
Simulation time 10047620481 ps
CPU time 13.86 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205240 kb
Host smart-15611e57-75c9-4961-8e68-4d5afe205317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23530
80612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2353080612
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2741840669
Short name T1546
Test name
Test status
Simulation time 10049599509 ps
CPU time 13.65 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205292 kb
Host smart-f5f3834b-2287-47bf-a5f7-96fb3252cee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27418
40669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2741840669
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.301275051
Short name T814
Test name
Test status
Simulation time 10085968317 ps
CPU time 13.1 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:49 PM PDT 24
Peak memory 205232 kb
Host smart-77b1e214-d89f-4bfa-987f-f9421b8d4249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
5051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.301275051
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1007237112
Short name T845
Test name
Test status
Simulation time 10099602858 ps
CPU time 13.47 seconds
Started May 26 01:38:19 PM PDT 24
Finished May 26 01:38:34 PM PDT 24
Peak memory 205324 kb
Host smart-9aaadcb8-1196-424f-94b5-264efda3c946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10072
37112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1007237112
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2696257283
Short name T1234
Test name
Test status
Simulation time 10103184088 ps
CPU time 14.57 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:49 PM PDT 24
Peak memory 205240 kb
Host smart-20fbd5cd-1ba6-4dd8-b8b3-a9c8e6363d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26962
57283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2696257283
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3605402397
Short name T1651
Test name
Test status
Simulation time 10124135605 ps
CPU time 15.85 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205304 kb
Host smart-d8ae65ad-deb5-4d81-8474-cab9d4de2657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36054
02397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3605402397
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3635227906
Short name T832
Test name
Test status
Simulation time 10154237181 ps
CPU time 16.07 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205268 kb
Host smart-4c7ff217-41bd-4b57-a665-2e0cf1760733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3635227906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3635227906
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.1081560476
Short name T840
Test name
Test status
Simulation time 10054609173 ps
CPU time 14.22 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205256 kb
Host smart-2b47dad1-6af6-4575-affd-3f80151ea7d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1081560476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.1081560476
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.2303189712
Short name T509
Test name
Test status
Simulation time 10123184227 ps
CPU time 13.45 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205272 kb
Host smart-4b27258d-16bc-42bb-b0b9-cbd77ccc1e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23031
89712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.2303189712
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1990888605
Short name T1848
Test name
Test status
Simulation time 13720523373 ps
CPU time 17.37 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205272 kb
Host smart-581a6a50-4139-4ece-bd14-af384a9966f8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1990888605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1990888605
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.2219868790
Short name T1412
Test name
Test status
Simulation time 13273637968 ps
CPU time 16.62 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:52 PM PDT 24
Peak memory 205356 kb
Host smart-bae263bd-3c23-4cbe-8c61-ed79053c46f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2219868790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.2219868790
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2953931287
Short name T435
Test name
Test status
Simulation time 13256546252 ps
CPU time 16.62 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:52 PM PDT 24
Peak memory 205336 kb
Host smart-e6ea0cb4-7081-4da4-a38c-b791fbc929ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2953931287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2953931287
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2573055036
Short name T1908
Test name
Test status
Simulation time 10049586924 ps
CPU time 14.42 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:49 PM PDT 24
Peak memory 205212 kb
Host smart-881b579e-882f-4de2-aeb0-857840f44b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
55036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2573055036
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1971114831
Short name T751
Test name
Test status
Simulation time 10078887367 ps
CPU time 14.4 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:51 PM PDT 24
Peak memory 205464 kb
Host smart-5da4f614-67b6-4e39-a1f4-f3c0cbf45009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19711
14831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1971114831
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3995033014
Short name T63
Test name
Test status
Simulation time 10881459296 ps
CPU time 17.31 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:53 PM PDT 24
Peak memory 205312 kb
Host smart-0477afc7-582e-4a3f-b991-6f6cdc1d702a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39950
33014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3995033014
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2246315247
Short name T1265
Test name
Test status
Simulation time 10049438979 ps
CPU time 13.61 seconds
Started May 26 01:38:35 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205228 kb
Host smart-5c124f93-c68a-4611-a559-421104ab30cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22463
15247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2246315247
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2346518540
Short name T625
Test name
Test status
Simulation time 10084695032 ps
CPU time 13.44 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 205284 kb
Host smart-862042cb-9f25-4495-8ca6-4c32a36370cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
18540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2346518540
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3399522370
Short name T885
Test name
Test status
Simulation time 10820495841 ps
CPU time 16.7 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:52 PM PDT 24
Peak memory 205228 kb
Host smart-670877e3-6d19-47dd-9a13-95ed92c1782a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33995
22370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3399522370
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1270060532
Short name T1354
Test name
Test status
Simulation time 10233415792 ps
CPU time 15.22 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 205308 kb
Host smart-b1e844c3-a30d-43ad-ab10-97f254fcfc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
60532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1270060532
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.437119223
Short name T533
Test name
Test status
Simulation time 10056412484 ps
CPU time 14.17 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205436 kb
Host smart-b6016e28-38be-4e51-a7e1-f4df6113da23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43711
9223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.437119223
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.874407657
Short name T752
Test name
Test status
Simulation time 10134899949 ps
CPU time 13.23 seconds
Started May 26 01:38:45 PM PDT 24
Finished May 26 01:39:00 PM PDT 24
Peak memory 205272 kb
Host smart-34442802-3ff6-4e00-9aeb-398b0da2f7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87440
7657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.874407657
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3344323788
Short name T597
Test name
Test status
Simulation time 10102311837 ps
CPU time 14.25 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:49 PM PDT 24
Peak memory 205232 kb
Host smart-777b92f4-eaf2-4fba-bb3f-eff6a017ce3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33443
23788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3344323788
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1050668421
Short name T1052
Test name
Test status
Simulation time 10089865206 ps
CPU time 16.66 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:52 PM PDT 24
Peak memory 205236 kb
Host smart-0a7b0efc-47eb-4591-b620-4480b277490b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
68421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1050668421
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3417695572
Short name T1822
Test name
Test status
Simulation time 13184575492 ps
CPU time 15.65 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:49 PM PDT 24
Peak memory 205284 kb
Host smart-0430a490-fc16-43a9-a525-ce6fafac312d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34176
95572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3417695572
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.240031421
Short name T1921
Test name
Test status
Simulation time 10083015064 ps
CPU time 14.66 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205332 kb
Host smart-2194e3f0-3137-4618-99a4-f6c2c776b7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24003
1421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.240031421
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3711557220
Short name T1707
Test name
Test status
Simulation time 10072832590 ps
CPU time 15.16 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205308 kb
Host smart-22528d3d-66ec-4dcf-805d-19a1d435af92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
57220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3711557220
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4097760836
Short name T94
Test name
Test status
Simulation time 10110616151 ps
CPU time 15.06 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205256 kb
Host smart-74baf047-7a93-46b8-8f85-d69773d0a2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40977
60836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4097760836
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2343879752
Short name T1464
Test name
Test status
Simulation time 10091595409 ps
CPU time 14.63 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205248 kb
Host smart-fca4c969-69d7-4a7f-9281-e65240e789db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23438
79752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2343879752
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3833499580
Short name T312
Test name
Test status
Simulation time 10055845879 ps
CPU time 16 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205260 kb
Host smart-600914d7-5063-4454-9c1d-2dbb5a30187c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
99580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3833499580
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4204770414
Short name T1224
Test name
Test status
Simulation time 10112233398 ps
CPU time 14.65 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205332 kb
Host smart-74fd0637-24d3-486e-8b64-5d7638f78e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42047
70414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4204770414
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.246264429
Short name T1113
Test name
Test status
Simulation time 10138815869 ps
CPU time 14.27 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205236 kb
Host smart-a3eae551-d2f4-44f4-80af-9e4be90d3b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
4429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.246264429
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.3026794125
Short name T1437
Test name
Test status
Simulation time 10106171849 ps
CPU time 13.82 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:38:56 PM PDT 24
Peak memory 205256 kb
Host smart-681bdc63-b37a-4421-ae4c-f19980c60cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267
94125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.3026794125
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2925247088
Short name T905
Test name
Test status
Simulation time 10050324431 ps
CPU time 14.14 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205240 kb
Host smart-f782ac03-8302-4725-bdbd-c695c7a6e677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29252
47088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2925247088
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1340054643
Short name T1085
Test name
Test status
Simulation time 10043454240 ps
CPU time 17.52 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205332 kb
Host smart-81dd2505-f58c-487f-ac81-b535d5428ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13400
54643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1340054643
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2795764280
Short name T92
Test name
Test status
Simulation time 25135135699 ps
CPU time 48.45 seconds
Started May 26 01:38:35 PM PDT 24
Finished May 26 01:39:25 PM PDT 24
Peak memory 205292 kb
Host smart-299986ee-8c25-4233-ab52-0fd4b3d1f4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
64280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2795764280
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.979625510
Short name T1123
Test name
Test status
Simulation time 10069014708 ps
CPU time 14.79 seconds
Started May 26 01:38:31 PM PDT 24
Finished May 26 01:38:46 PM PDT 24
Peak memory 205224 kb
Host smart-20a7be7b-85ad-4027-acab-a6ec1fc70b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97962
5510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.979625510
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.4269967755
Short name T977
Test name
Test status
Simulation time 10131848391 ps
CPU time 13.78 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:47 PM PDT 24
Peak memory 205280 kb
Host smart-9b00a83c-c5e9-4d8d-83a0-0631b3be8cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42699
67755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.4269967755
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1326872179
Short name T1073
Test name
Test status
Simulation time 10092591429 ps
CPU time 13.9 seconds
Started May 26 01:38:35 PM PDT 24
Finished May 26 01:38:51 PM PDT 24
Peak memory 204560 kb
Host smart-33810df2-1842-49d9-85ba-81fa73ed358e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13268
72179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1326872179
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3869479702
Short name T1740
Test name
Test status
Simulation time 10040873449 ps
CPU time 15.59 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:51 PM PDT 24
Peak memory 205228 kb
Host smart-31e0db7c-4da4-4870-8136-d4648258bfbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38694
79702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3869479702
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3252667475
Short name T1059
Test name
Test status
Simulation time 10053259385 ps
CPU time 13.99 seconds
Started May 26 01:38:50 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205300 kb
Host smart-ed138256-8062-40c5-a74b-ca8fd75f6b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32526
67475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3252667475
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3257625711
Short name T654
Test name
Test status
Simulation time 10044014720 ps
CPU time 14.28 seconds
Started May 26 01:38:32 PM PDT 24
Finished May 26 01:38:48 PM PDT 24
Peak memory 205216 kb
Host smart-86f1e67b-d345-42b8-8901-2958038ebee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
25711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3257625711
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1933395432
Short name T1481
Test name
Test status
Simulation time 10104412352 ps
CPU time 15.17 seconds
Started May 26 01:38:33 PM PDT 24
Finished May 26 01:38:50 PM PDT 24
Peak memory 205264 kb
Host smart-9372fc5f-aa89-43cf-99a3-0e604dcb84ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19333
95432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1933395432
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3111248835
Short name T1029
Test name
Test status
Simulation time 10066110017 ps
CPU time 15.14 seconds
Started May 26 01:38:45 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205288 kb
Host smart-b972c399-3579-448b-ae3d-1c6a4913423e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112
48835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3111248835
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1168578046
Short name T599
Test name
Test status
Simulation time 10078235456 ps
CPU time 15.05 seconds
Started May 26 01:38:34 PM PDT 24
Finished May 26 01:38:51 PM PDT 24
Peak memory 205200 kb
Host smart-e681693e-1038-4bb9-b66d-1e1978bf2b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11685
78046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1168578046
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.2433705045
Short name T1835
Test name
Test status
Simulation time 10163536099 ps
CPU time 13.56 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205296 kb
Host smart-1be6e533-29a0-4e79-9b8e-11bff192be91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2433705045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.2433705045
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.1073686659
Short name T309
Test name
Test status
Simulation time 10072884165 ps
CPU time 17.12 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205280 kb
Host smart-58057c9b-ade8-4f0b-a1fc-aa71336acf4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1073686659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.1073686659
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.3663542391
Short name T786
Test name
Test status
Simulation time 10122274296 ps
CPU time 15.23 seconds
Started May 26 01:38:49 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205276 kb
Host smart-9ca51de6-c87a-4c86-9001-3ccb2b2f3d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36635
42391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.3663542391
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1662565666
Short name T1400
Test name
Test status
Simulation time 14065846354 ps
CPU time 18.78 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205300 kb
Host smart-8303f0b6-3d70-4f5f-8e6c-bc7100342b17
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1662565666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1662565666
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1642893409
Short name T436
Test name
Test status
Simulation time 13241614737 ps
CPU time 17.34 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205316 kb
Host smart-f82e5097-e74c-40bf-b638-52b1dcb6a6c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1642893409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1642893409
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1300679462
Short name T1561
Test name
Test status
Simulation time 13215939143 ps
CPU time 17.24 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:04 PM PDT 24
Peak memory 205356 kb
Host smart-37571611-9da9-41dc-866f-784971d9c367
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1300679462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.1300679462
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.4195691
Short name T307
Test name
Test status
Simulation time 10052180410 ps
CPU time 16.98 seconds
Started May 26 01:38:41 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205316 kb
Host smart-da56f704-1994-4909-b333-be77bd5f23db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956
91 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.4195691
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1836174607
Short name T1425
Test name
Test status
Simulation time 10669914813 ps
CPU time 15.02 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:39:00 PM PDT 24
Peak memory 205248 kb
Host smart-d9bc47e9-9887-4985-b6e1-8bd4ff0ae18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18361
74607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1836174607
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3798690274
Short name T662
Test name
Test status
Simulation time 10048034717 ps
CPU time 13.3 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205256 kb
Host smart-4685197c-c334-43a8-b254-8639085441b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37986
90274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3798690274
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.740652587
Short name T852
Test name
Test status
Simulation time 10074415340 ps
CPU time 13.32 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:38:58 PM PDT 24
Peak memory 205344 kb
Host smart-8a249c72-4136-49a8-afe7-fc735b235a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74065
2587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.740652587
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1241570724
Short name T1511
Test name
Test status
Simulation time 10835205636 ps
CPU time 17.65 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205508 kb
Host smart-b99bae69-537f-4182-9c55-7f70845b01fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12415
70724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1241570724
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2890456510
Short name T1125
Test name
Test status
Simulation time 10111027515 ps
CPU time 15.36 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:03 PM PDT 24
Peak memory 205232 kb
Host smart-a7985b4b-822c-45be-a4d3-d2b6eeff279e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28904
56510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2890456510
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2750085610
Short name T740
Test name
Test status
Simulation time 10100018725 ps
CPU time 13.19 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205292 kb
Host smart-7fc4b202-d532-4f66-8ac1-df0ce986ab5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27500
85610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2750085610
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1256757433
Short name T1197
Test name
Test status
Simulation time 10092656889 ps
CPU time 15.14 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205308 kb
Host smart-a1f6d02b-c023-47fa-9dc6-30323465bc76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12567
57433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1256757433
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3895287884
Short name T1144
Test name
Test status
Simulation time 10113441013 ps
CPU time 15.59 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205244 kb
Host smart-6b360e7e-38c6-490d-be9d-2709c2244bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
87884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3895287884
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.4188194473
Short name T1075
Test name
Test status
Simulation time 10076657826 ps
CPU time 14.35 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:03 PM PDT 24
Peak memory 205252 kb
Host smart-9f1bdf1e-f197-47ca-8503-26c5ca730ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41881
94473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.4188194473
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1564430207
Short name T1827
Test name
Test status
Simulation time 13161889588 ps
CPU time 20.02 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:39:03 PM PDT 24
Peak memory 205216 kb
Host smart-3a4ad49e-53d6-4e08-8644-0e8b3af5efd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
30207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1564430207
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2044859911
Short name T1578
Test name
Test status
Simulation time 10095770545 ps
CPU time 13.76 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205224 kb
Host smart-160dfb67-9967-417d-b551-b7e478246244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
59911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2044859911
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2658202392
Short name T319
Test name
Test status
Simulation time 10126355899 ps
CPU time 14.03 seconds
Started May 26 01:38:41 PM PDT 24
Finished May 26 01:38:56 PM PDT 24
Peak memory 205320 kb
Host smart-5dc46144-dbcb-43d2-b547-ea76ce5f1186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26582
02392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2658202392
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2647245634
Short name T1663
Test name
Test status
Simulation time 10134498981 ps
CPU time 14.64 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:39:00 PM PDT 24
Peak memory 205268 kb
Host smart-c9ca89ff-8168-48ea-b13d-bb155d7bbc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26472
45634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2647245634
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3461407539
Short name T1313
Test name
Test status
Simulation time 10095428192 ps
CPU time 14.75 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205268 kb
Host smart-91d16741-d41f-4e33-87b6-4500417444af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34614
07539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3461407539
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3657240488
Short name T408
Test name
Test status
Simulation time 10108611742 ps
CPU time 13.57 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205240 kb
Host smart-748a107b-1daa-4697-a7ec-2e5daa76b975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36572
40488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3657240488
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3556450411
Short name T888
Test name
Test status
Simulation time 10065188700 ps
CPU time 14.03 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:38:56 PM PDT 24
Peak memory 205260 kb
Host smart-5083f9d8-5e2b-4499-947f-c68f90066894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35564
50411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3556450411
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1397645456
Short name T136
Test name
Test status
Simulation time 10054159987 ps
CPU time 13.39 seconds
Started May 26 01:38:45 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205320 kb
Host smart-7091c6a5-a69d-475f-902c-78f42c2b47d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
45456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1397645456
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.3576883648
Short name T1796
Test name
Test status
Simulation time 10133458682 ps
CPU time 13.76 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205260 kb
Host smart-0c054b9e-3084-4e42-a9c4-3e9c839ebf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35768
83648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.3576883648
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2465806386
Short name T1912
Test name
Test status
Simulation time 10100121282 ps
CPU time 14.19 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205336 kb
Host smart-c478684e-d6f3-4b2f-88ed-d0ab5b50bff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
06386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2465806386
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1059648042
Short name T1228
Test name
Test status
Simulation time 10044313242 ps
CPU time 14.57 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:03 PM PDT 24
Peak memory 205252 kb
Host smart-ef7e35f8-e182-49e9-84d1-1cc69d36d6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
48042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1059648042
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.610057447
Short name T1396
Test name
Test status
Simulation time 32087465218 ps
CPU time 65.28 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:39:50 PM PDT 24
Peak memory 205240 kb
Host smart-2b221f84-97f6-4180-9a9a-46fa781ca369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61005
7447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.610057447
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4276616016
Short name T1649
Test name
Test status
Simulation time 10076139898 ps
CPU time 14.4 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:59 PM PDT 24
Peak memory 205260 kb
Host smart-98783ee4-3b30-4cc8-9289-9f09afb66727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42766
16016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4276616016
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3592613285
Short name T872
Test name
Test status
Simulation time 10081622600 ps
CPU time 17.46 seconds
Started May 26 01:38:42 PM PDT 24
Finished May 26 01:39:00 PM PDT 24
Peak memory 205228 kb
Host smart-930e2c97-04d3-4c4c-b4fe-8a70b1acb4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35926
13285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3592613285
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.573577668
Short name T694
Test name
Test status
Simulation time 10136524825 ps
CPU time 14.29 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:03 PM PDT 24
Peak memory 205288 kb
Host smart-7239a861-6407-48f9-8847-85c70a135525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57357
7668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.573577668
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.884996776
Short name T637
Test name
Test status
Simulation time 10038588776 ps
CPU time 13.15 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205252 kb
Host smart-d4ff0a88-c6df-4308-a529-c70ea9072389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88499
6776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.884996776
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.258404408
Short name T1918
Test name
Test status
Simulation time 10062418530 ps
CPU time 14.91 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205200 kb
Host smart-6ddb917e-4e14-41d0-94a8-da8ab8dbcfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25840
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.258404408
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3701016613
Short name T1435
Test name
Test status
Simulation time 10061265372 ps
CPU time 17.32 seconds
Started May 26 01:38:45 PM PDT 24
Finished May 26 01:39:04 PM PDT 24
Peak memory 205272 kb
Host smart-61a803a7-6a77-46be-bcfb-a771247da932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37010
16613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3701016613
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1701476833
Short name T135
Test name
Test status
Simulation time 10128277680 ps
CPU time 13.4 seconds
Started May 26 01:38:43 PM PDT 24
Finished May 26 01:38:57 PM PDT 24
Peak memory 205320 kb
Host smart-78b56234-a657-4b55-bf2a-8ce1d767e77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17014
76833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1701476833
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3354719569
Short name T642
Test name
Test status
Simulation time 10097259338 ps
CPU time 17.32 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:04 PM PDT 24
Peak memory 205284 kb
Host smart-ac91546b-3f08-4b79-a515-70777dd3a6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
19569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3354719569
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1442184566
Short name T1621
Test name
Test status
Simulation time 10052975362 ps
CPU time 14.74 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:04 PM PDT 24
Peak memory 205240 kb
Host smart-722c2949-b578-4fe2-8b59-4e1f602c8629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
84566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1442184566
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.2322786607
Short name T1472
Test name
Test status
Simulation time 10151248292 ps
CPU time 13.98 seconds
Started May 26 01:38:53 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205272 kb
Host smart-3403c00b-63fb-4cf4-8724-52c13e0469fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2322786607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.2322786607
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.3411456307
Short name T1465
Test name
Test status
Simulation time 10055625950 ps
CPU time 14.34 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205308 kb
Host smart-51ae7da6-de07-466e-82f4-0a8b18b5f5fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3411456307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3411456307
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.1753912051
Short name T1249
Test name
Test status
Simulation time 10051839415 ps
CPU time 14.02 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205276 kb
Host smart-f60a03f4-8c29-4fc5-8a58-97dd5ecfde30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17539
12051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.1753912051
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3391140447
Short name T501
Test name
Test status
Simulation time 13403293742 ps
CPU time 20.08 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:10 PM PDT 24
Peak memory 205312 kb
Host smart-4cd3bcb1-0b3c-4f05-bee7-fa1136eb7bfd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3391140447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3391140447
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.639607643
Short name T1714
Test name
Test status
Simulation time 13256897735 ps
CPU time 20.8 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:10 PM PDT 24
Peak memory 205284 kb
Host smart-e9781420-11d9-4290-9552-90fdfcd3cba5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=639607643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.639607643
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3229148062
Short name T1250
Test name
Test status
Simulation time 13244394082 ps
CPU time 16.74 seconds
Started May 26 01:38:49 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205300 kb
Host smart-0a4b5158-a4b4-4f33-8ae0-0b7d6f188880
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3229148062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3229148062
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1544912484
Short name T1895
Test name
Test status
Simulation time 10050975628 ps
CPU time 15.36 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205264 kb
Host smart-f19d6a64-637f-4bc7-98b9-6a5e8a976aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
12484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1544912484
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1146373847
Short name T75
Test name
Test status
Simulation time 10070394156 ps
CPU time 13.84 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205264 kb
Host smart-8cd3e635-1ac2-456a-811a-53c2552496a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11463
73847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1146373847
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.4124191376
Short name T166
Test name
Test status
Simulation time 10611712567 ps
CPU time 17.62 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205284 kb
Host smart-1e632458-abba-4d3d-b67c-3038bca22fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41241
91376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.4124191376
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1081096463
Short name T566
Test name
Test status
Simulation time 10040251087 ps
CPU time 16.45 seconds
Started May 26 01:38:49 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205260 kb
Host smart-14437933-686d-4312-b2aa-b99e5de77ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
96463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1081096463
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2498877271
Short name T1306
Test name
Test status
Simulation time 10084454101 ps
CPU time 14.27 seconds
Started May 26 01:38:49 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205256 kb
Host smart-276e976a-9f12-4e37-b2e9-2a255dee5008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24988
77271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2498877271
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3841362811
Short name T1788
Test name
Test status
Simulation time 10817111226 ps
CPU time 16.54 seconds
Started May 26 01:38:49 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205276 kb
Host smart-d24d2e6a-d987-4371-a9e6-d62c3b6307b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38413
62811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3841362811
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3536908335
Short name T1122
Test name
Test status
Simulation time 10215005616 ps
CPU time 16.74 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205268 kb
Host smart-d41f433e-ce7b-44a0-917a-3b82044b9ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35369
08335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3536908335
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3969509639
Short name T1386
Test name
Test status
Simulation time 10128668882 ps
CPU time 13.25 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205468 kb
Host smart-ce35a391-13a8-42a5-b93d-b704d305efdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39695
09639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3969509639
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2135827346
Short name T1367
Test name
Test status
Simulation time 10038244883 ps
CPU time 15.57 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:08 PM PDT 24
Peak memory 205304 kb
Host smart-69d0394f-6300-41f2-bef4-3d1a70d33fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21358
27346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2135827346
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2940544338
Short name T727
Test name
Test status
Simulation time 10164304583 ps
CPU time 13.79 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205236 kb
Host smart-b5a8a4ec-09fb-4d2c-b151-fe135b425d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
44338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2940544338
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3528916705
Short name T1782
Test name
Test status
Simulation time 10132707518 ps
CPU time 15.5 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 204648 kb
Host smart-c9804444-4b60-4364-9301-9fe4a8358ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35289
16705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3528916705
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3692072110
Short name T820
Test name
Test status
Simulation time 13278903484 ps
CPU time 21.26 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:10 PM PDT 24
Peak memory 205256 kb
Host smart-e39aadc0-d326-4e4a-8fb3-9e78e0a9d777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36920
72110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3692072110
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.307606515
Short name T396
Test name
Test status
Simulation time 10119427370 ps
CPU time 15.68 seconds
Started May 26 01:38:44 PM PDT 24
Finished May 26 01:39:00 PM PDT 24
Peak memory 205328 kb
Host smart-749316e8-91d3-4568-8add-7dd3d91bf35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30760
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.307606515
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.4205540923
Short name T1469
Test name
Test status
Simulation time 10038553699 ps
CPU time 12.4 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:02 PM PDT 24
Peak memory 205260 kb
Host smart-a0e97495-d3a4-42a7-947a-fdb00d0d3eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
40923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.4205540923
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2900637175
Short name T113
Test name
Test status
Simulation time 10117215031 ps
CPU time 13.9 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205356 kb
Host smart-114c2c85-6018-4f8c-9efe-76ca8f4665f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29006
37175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2900637175
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.4158528941
Short name T448
Test name
Test status
Simulation time 10093080254 ps
CPU time 15.15 seconds
Started May 26 01:38:48 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 204632 kb
Host smart-eb86a7d7-5eab-4c28-b7eb-c07544659d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585
28941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.4158528941
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.431784726
Short name T842
Test name
Test status
Simulation time 10079404011 ps
CPU time 18.4 seconds
Started May 26 01:38:49 PM PDT 24
Finished May 26 01:39:09 PM PDT 24
Peak memory 205288 kb
Host smart-a668b367-f736-494b-8524-d84b75b4b90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43178
4726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.431784726
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3613163337
Short name T441
Test name
Test status
Simulation time 10061746311 ps
CPU time 13.75 seconds
Started May 26 01:38:46 PM PDT 24
Finished May 26 01:39:01 PM PDT 24
Peak memory 205288 kb
Host smart-799ea9d3-88f5-47dc-8cda-6e7988bddf33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36131
63337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3613163337
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2406207855
Short name T172
Test name
Test status
Simulation time 10077922817 ps
CPU time 16.03 seconds
Started May 26 01:38:52 PM PDT 24
Finished May 26 01:39:09 PM PDT 24
Peak memory 205228 kb
Host smart-f354eb90-4869-4e55-b30c-0f4405dc90eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062
07855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2406207855
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.2252044229
Short name T2
Test name
Test status
Simulation time 10108608280 ps
CPU time 14.83 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205192 kb
Host smart-d6a11780-7fc2-406f-a2f3-769f4e7bed06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22520
44229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.2252044229
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3866981563
Short name T1064
Test name
Test status
Simulation time 10039594026 ps
CPU time 17.43 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:10 PM PDT 24
Peak memory 205308 kb
Host smart-eed96c6b-3580-4a6f-822c-718d17cfc8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
81563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3866981563
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3584860670
Short name T704
Test name
Test status
Simulation time 10036239932 ps
CPU time 13.89 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205208 kb
Host smart-1fa6e43e-a9a0-46ac-9df1-1f6e7b763153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35848
60670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3584860670
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2590339429
Short name T1299
Test name
Test status
Simulation time 27320316052 ps
CPU time 62.71 seconds
Started May 26 01:38:52 PM PDT 24
Finished May 26 01:39:56 PM PDT 24
Peak memory 205340 kb
Host smart-c44e7945-b4b0-417d-b627-0abf3f833ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25903
39429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2590339429
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2479879608
Short name T753
Test name
Test status
Simulation time 10119958683 ps
CPU time 14.68 seconds
Started May 26 01:38:50 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205264 kb
Host smart-b2a1f69b-a085-4da5-9dd2-5407ec023e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798
79608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2479879608
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2208833689
Short name T1259
Test name
Test status
Simulation time 10133168817 ps
CPU time 14.95 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:08 PM PDT 24
Peak memory 205180 kb
Host smart-80d24132-a7ac-4c8a-95d0-4240f40a97df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22088
33689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2208833689
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.2482646500
Short name T334
Test name
Test status
Simulation time 10113718193 ps
CPU time 14.51 seconds
Started May 26 01:38:50 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205172 kb
Host smart-0dafaa67-aabb-4268-8dfa-ffccdaa31902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24826
46500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.2482646500
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3240835412
Short name T58
Test name
Test status
Simulation time 10040303180 ps
CPU time 15.31 seconds
Started May 26 01:38:53 PM PDT 24
Finished May 26 01:39:09 PM PDT 24
Peak memory 205260 kb
Host smart-71c1e82c-7e0d-4366-a54c-dee5cb31ca7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32408
35412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3240835412
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3767633357
Short name T1020
Test name
Test status
Simulation time 10041129665 ps
CPU time 14.57 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205176 kb
Host smart-4947ad2e-139a-46a0-9131-2ff753738aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37676
33357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3767633357
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2412816599
Short name T1491
Test name
Test status
Simulation time 10060773126 ps
CPU time 14.04 seconds
Started May 26 01:38:52 PM PDT 24
Finished May 26 01:39:07 PM PDT 24
Peak memory 205304 kb
Host smart-25f585ae-b126-4268-8e5e-7063170eee6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
16599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2412816599
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1379232713
Short name T568
Test name
Test status
Simulation time 10123804473 ps
CPU time 16.53 seconds
Started May 26 01:38:47 PM PDT 24
Finished May 26 01:39:05 PM PDT 24
Peak memory 205300 kb
Host smart-bc70dde9-b676-4448-8b58-cf6d8752f737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13792
32713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1379232713
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2749582050
Short name T644
Test name
Test status
Simulation time 10057995251 ps
CPU time 14.69 seconds
Started May 26 01:38:51 PM PDT 24
Finished May 26 01:39:06 PM PDT 24
Peak memory 205268 kb
Host smart-6fc7a006-0b82-4046-82ef-fdf0002b94e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27495
82050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2749582050
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1029088362
Short name T1802
Test name
Test status
Simulation time 10065367572 ps
CPU time 14.43 seconds
Started May 26 01:38:52 PM PDT 24
Finished May 26 01:39:08 PM PDT 24
Peak memory 205328 kb
Host smart-0d26b45b-9339-4987-9526-80641b71203f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290
88362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1029088362
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.2520387023
Short name T1241
Test name
Test status
Simulation time 10181345035 ps
CPU time 14.7 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 205220 kb
Host smart-1b7ff265-31cb-4a45-822c-a3c8f5e6f901
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2520387023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.2520387023
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.332324087
Short name T1646
Test name
Test status
Simulation time 10060177389 ps
CPU time 16.23 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:16 PM PDT 24
Peak memory 205324 kb
Host smart-64032cbf-e999-4a14-ba50-28b86764b938
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=332324087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.332324087
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2146548732
Short name T705
Test name
Test status
Simulation time 10051157099 ps
CPU time 16.12 seconds
Started May 26 01:29:01 PM PDT 24
Finished May 26 01:29:18 PM PDT 24
Peak memory 205216 kb
Host smart-6e1d73bc-3d49-4291-8966-3f9cb7901757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
48732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2146548732
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4238113283
Short name T693
Test name
Test status
Simulation time 13640107177 ps
CPU time 18.81 seconds
Started May 26 01:28:41 PM PDT 24
Finished May 26 01:29:01 PM PDT 24
Peak memory 205248 kb
Host smart-206b3d00-fce6-4b5d-ba18-0404a1ae0acb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4238113283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.4238113283
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2083372363
Short name T1369
Test name
Test status
Simulation time 13188438940 ps
CPU time 21.6 seconds
Started May 26 01:28:41 PM PDT 24
Finished May 26 01:29:04 PM PDT 24
Peak memory 205316 kb
Host smart-4f5717aa-1e0a-4d36-a6eb-1bf65033bce3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2083372363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2083372363
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3539937346
Short name T1826
Test name
Test status
Simulation time 13296157217 ps
CPU time 18.28 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:29:02 PM PDT 24
Peak memory 205280 kb
Host smart-b8164c3c-8395-4869-a192-e9c6f7016b0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3539937346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3539937346
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1276799452
Short name T990
Test name
Test status
Simulation time 10069754648 ps
CPU time 17.15 seconds
Started May 26 01:28:40 PM PDT 24
Finished May 26 01:28:59 PM PDT 24
Peak memory 205248 kb
Host smart-8274ea05-91ae-4056-9ff6-9b8f880c445b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12767
99452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1276799452
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3818760879
Short name T1434
Test name
Test status
Simulation time 10370530113 ps
CPU time 15.72 seconds
Started May 26 01:28:42 PM PDT 24
Finished May 26 01:29:00 PM PDT 24
Peak memory 205340 kb
Host smart-fa19eba1-9015-4dc8-bb8d-b45c20d4149d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38187
60879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3818760879
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1338033906
Short name T1388
Test name
Test status
Simulation time 10046050334 ps
CPU time 18.04 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:09 PM PDT 24
Peak memory 205260 kb
Host smart-47a001dd-409d-4d6b-85d7-3e0065d2800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
33906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1338033906
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2305296980
Short name T1504
Test name
Test status
Simulation time 10075787829 ps
CPU time 18.81 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:10 PM PDT 24
Peak memory 205324 kb
Host smart-a8494513-a168-4c9a-9ff8-3b8e2ff298c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
96980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2305296980
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1421953814
Short name T1558
Test name
Test status
Simulation time 10102559649 ps
CPU time 17.84 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:09 PM PDT 24
Peak memory 205216 kb
Host smart-92029f11-018c-4da2-b724-877577ab5390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
53814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1421953814
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3812750681
Short name T557
Test name
Test status
Simulation time 10165414917 ps
CPU time 13.97 seconds
Started May 26 01:29:00 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 205436 kb
Host smart-28fd9ec3-f07c-4fcd-88f1-3abe6f4d7098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
50681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3812750681
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3448820559
Short name T1348
Test name
Test status
Simulation time 10059143382 ps
CPU time 15.47 seconds
Started May 26 01:29:07 PM PDT 24
Finished May 26 01:29:23 PM PDT 24
Peak memory 205212 kb
Host smart-48e01e36-4880-4ce6-af41-52740190259b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
20559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3448820559
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3733722897
Short name T1357
Test name
Test status
Simulation time 10060869222 ps
CPU time 14.57 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:29:07 PM PDT 24
Peak memory 205300 kb
Host smart-6fc57311-1e8b-4e36-9d4a-63223c9beeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37337
22897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3733722897
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1744538806
Short name T474
Test name
Test status
Simulation time 10079276514 ps
CPU time 13.56 seconds
Started May 26 01:28:48 PM PDT 24
Finished May 26 01:29:03 PM PDT 24
Peak memory 205256 kb
Host smart-b4d39dac-b404-41e6-9d12-3b82283d043c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17445
38806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1744538806
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1330225970
Short name T361
Test name
Test status
Simulation time 13250311228 ps
CPU time 17.21 seconds
Started May 26 01:28:52 PM PDT 24
Finished May 26 01:29:10 PM PDT 24
Peak memory 205248 kb
Host smart-194ba5d7-7f6f-424a-a3ba-d7e195877060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13302
25970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1330225970
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1928385939
Short name T1323
Test name
Test status
Simulation time 10114040762 ps
CPU time 13.97 seconds
Started May 26 01:28:52 PM PDT 24
Finished May 26 01:29:07 PM PDT 24
Peak memory 205308 kb
Host smart-46e795f7-0e12-4d82-b311-d11431940164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19283
85939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1928385939
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1758518028
Short name T998
Test name
Test status
Simulation time 10052908650 ps
CPU time 16.94 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:29:10 PM PDT 24
Peak memory 205280 kb
Host smart-3e1f1ecd-846e-4ab7-b906-40d63791bece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17585
18028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1758518028
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3154458515
Short name T1379
Test name
Test status
Simulation time 10118145936 ps
CPU time 13.93 seconds
Started May 26 01:28:49 PM PDT 24
Finished May 26 01:29:04 PM PDT 24
Peak memory 205316 kb
Host smart-be367e50-2e4f-418a-9492-aca8d4746b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
58515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3154458515
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2994151733
Short name T1930
Test name
Test status
Simulation time 10082057333 ps
CPU time 14.23 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:06 PM PDT 24
Peak memory 205268 kb
Host smart-16ccac98-fcbf-4d4f-a790-ea118b237038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29941
51733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2994151733
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1823553023
Short name T584
Test name
Test status
Simulation time 10075028402 ps
CPU time 14.41 seconds
Started May 26 01:28:49 PM PDT 24
Finished May 26 01:29:04 PM PDT 24
Peak memory 205292 kb
Host smart-099ea199-1ddc-47e1-ad7d-428d8284ab84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18235
53023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1823553023
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4195246609
Short name T651
Test name
Test status
Simulation time 10088677089 ps
CPU time 16.29 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:29:09 PM PDT 24
Peak memory 205340 kb
Host smart-cc22f35d-3bb2-49b5-b6df-274091430ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41952
46609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4195246609
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3697112906
Short name T1296
Test name
Test status
Simulation time 10091622440 ps
CPU time 14.33 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:14 PM PDT 24
Peak memory 205264 kb
Host smart-2648f505-1212-41b1-9fdf-bb3b34e351a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36971
12906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3697112906
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.1193029110
Short name T764
Test name
Test status
Simulation time 10061498279 ps
CPU time 13.41 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:13 PM PDT 24
Peak memory 205348 kb
Host smart-27776aa3-10ef-4bcb-8dec-4f86a533ba39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11930
29110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.1193029110
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.804322246
Short name T645
Test name
Test status
Simulation time 10054075105 ps
CPU time 13.54 seconds
Started May 26 01:29:00 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 205216 kb
Host smart-9b29bc6d-5d41-45e2-9815-556f692716fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80432
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.804322246
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.4014395579
Short name T44
Test name
Test status
Simulation time 10110918630 ps
CPU time 14.43 seconds
Started May 26 01:28:58 PM PDT 24
Finished May 26 01:29:13 PM PDT 24
Peak memory 205176 kb
Host smart-28ccc9f1-61e1-4c23-9854-3cef91659299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40143
95579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.4014395579
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2101271763
Short name T280
Test name
Test status
Simulation time 28763455918 ps
CPU time 57.44 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:29:49 PM PDT 24
Peak memory 205360 kb
Host smart-ef21407d-e4dd-409c-9ebf-09ac8e32a84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21012
71763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2101271763
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.626225504
Short name T1874
Test name
Test status
Simulation time 10064180714 ps
CPU time 14.27 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:05 PM PDT 24
Peak memory 205484 kb
Host smart-5888655f-218a-449c-92f2-24762ded473e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62622
5504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.626225504
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1074554699
Short name T1154
Test name
Test status
Simulation time 10146953853 ps
CPU time 14.57 seconds
Started May 26 01:28:50 PM PDT 24
Finished May 26 01:29:06 PM PDT 24
Peak memory 205304 kb
Host smart-47d14750-6716-4c67-90ac-7032f70c2315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10745
54699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1074554699
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.4074750358
Short name T1699
Test name
Test status
Simulation time 10062572568 ps
CPU time 13.87 seconds
Started May 26 01:28:51 PM PDT 24
Finished May 26 01:29:06 PM PDT 24
Peak memory 205340 kb
Host smart-d368d96f-627b-46df-ba2d-51ea2d115ebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40747
50358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.4074750358
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1376954970
Short name T530
Test name
Test status
Simulation time 10049475986 ps
CPU time 14.91 seconds
Started May 26 01:29:02 PM PDT 24
Finished May 26 01:29:17 PM PDT 24
Peak memory 205288 kb
Host smart-cf8d11c9-cfd2-44b6-a01a-3d271226ea7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13769
54970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1376954970
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1773085573
Short name T145
Test name
Test status
Simulation time 10051658098 ps
CPU time 17.92 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:18 PM PDT 24
Peak memory 205204 kb
Host smart-cd931e6c-245a-46d2-bc81-4c49625b739c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17730
85573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1773085573
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3294231036
Short name T1190
Test name
Test status
Simulation time 10052024369 ps
CPU time 14.75 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 205328 kb
Host smart-ad1bb11b-9a68-46bc-bf7f-6f5896533c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32942
31036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3294231036
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1558583227
Short name T1108
Test name
Test status
Simulation time 10089077159 ps
CPU time 14.64 seconds
Started May 26 01:28:35 PM PDT 24
Finished May 26 01:28:50 PM PDT 24
Peak memory 205272 kb
Host smart-62673e76-82bc-43a3-9269-18707c853d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
83227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1558583227
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1935445514
Short name T402
Test name
Test status
Simulation time 10088361165 ps
CPU time 14.59 seconds
Started May 26 01:28:59 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 205240 kb
Host smart-85f5e281-748d-4979-946b-89b54150b16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
45514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1935445514
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1455773715
Short name T1563
Test name
Test status
Simulation time 10111701792 ps
CPU time 16.1 seconds
Started May 26 01:28:54 PM PDT 24
Finished May 26 01:29:11 PM PDT 24
Peak memory 205264 kb
Host smart-a45739fe-1e85-4b41-9e25-aaae5d2f1517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14557
73715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1455773715
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.2397521177
Short name T379
Test name
Test status
Simulation time 10149488780 ps
CPU time 17.16 seconds
Started May 26 01:29:27 PM PDT 24
Finished May 26 01:29:45 PM PDT 24
Peak memory 205304 kb
Host smart-ed66e041-57fb-43a8-ae69-60bcd76f4ef6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2397521177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.2397521177
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.2032722897
Short name T428
Test name
Test status
Simulation time 10072210496 ps
CPU time 16.33 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 205316 kb
Host smart-2e6901a3-0d10-4a00-b1c7-08c608b02741
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2032722897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.2032722897
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.2917345618
Short name T555
Test name
Test status
Simulation time 10103148170 ps
CPU time 13.44 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:38 PM PDT 24
Peak memory 205264 kb
Host smart-1c7bf166-b718-4dbc-acc6-cfd8622d8c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29173
45618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.2917345618
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1001491679
Short name T831
Test name
Test status
Simulation time 13950074543 ps
CPU time 18.46 seconds
Started May 26 01:29:06 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 205280 kb
Host smart-00ec8b30-b898-41a4-b763-d1e40a9013db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1001491679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1001491679
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3808567365
Short name T935
Test name
Test status
Simulation time 13226941154 ps
CPU time 16.84 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:25 PM PDT 24
Peak memory 205316 kb
Host smart-c18a3058-86be-4f94-8b5b-2032580991b0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3808567365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3808567365
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2666056672
Short name T1054
Test name
Test status
Simulation time 13267255739 ps
CPU time 18.84 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:27 PM PDT 24
Peak memory 205368 kb
Host smart-952c4f1d-607c-4340-be88-f19b81583bb9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2666056672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2666056672
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2945369590
Short name T1673
Test name
Test status
Simulation time 10075134185 ps
CPU time 15.61 seconds
Started May 26 01:29:06 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 205304 kb
Host smart-761ccc25-68ed-4b7e-af12-997a286316df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29453
69590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2945369590
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2374863552
Short name T174
Test name
Test status
Simulation time 10581720335 ps
CPU time 14.56 seconds
Started May 26 01:29:09 PM PDT 24
Finished May 26 01:29:25 PM PDT 24
Peak memory 205240 kb
Host smart-376591b2-8dc0-48a2-b93a-38d1e5e44e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23748
63552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2374863552
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.1153330441
Short name T1128
Test name
Test status
Simulation time 10105068933 ps
CPU time 16.04 seconds
Started May 26 01:29:15 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 205304 kb
Host smart-cd61b935-ff04-4dbe-90d3-cd1202f94cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11533
30441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.1153330441
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1492445777
Short name T526
Test name
Test status
Simulation time 10101327388 ps
CPU time 15.45 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:25 PM PDT 24
Peak memory 205356 kb
Host smart-997a6c11-1866-4af6-b2fa-666bc1062450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14924
45777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1492445777
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1132354042
Short name T1468
Test name
Test status
Simulation time 10700613983 ps
CPU time 17.63 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 205248 kb
Host smart-853ae486-baef-40c4-83b5-473b471ec63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
54042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1132354042
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.222113713
Short name T792
Test name
Test status
Simulation time 10266434359 ps
CPU time 15 seconds
Started May 26 01:29:12 PM PDT 24
Finished May 26 01:29:28 PM PDT 24
Peak memory 205320 kb
Host smart-9a09265b-3ab3-4a27-bba4-11cb923364a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22211
3713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.222113713
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2399423457
Short name T1431
Test name
Test status
Simulation time 10137847637 ps
CPU time 16.34 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:42 PM PDT 24
Peak memory 205292 kb
Host smart-b9eb624e-3365-49ed-9bd1-93acefdd06a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23994
23457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2399423457
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2908642035
Short name T1654
Test name
Test status
Simulation time 10037138484 ps
CPU time 13.44 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:39 PM PDT 24
Peak memory 205308 kb
Host smart-c700debc-2fcf-46f4-8c3a-887c659e281d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
42035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2908642035
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.895410247
Short name T945
Test name
Test status
Simulation time 10136204485 ps
CPU time 13.57 seconds
Started May 26 01:29:06 PM PDT 24
Finished May 26 01:29:20 PM PDT 24
Peak memory 205224 kb
Host smart-8c99e161-51ba-497c-9306-4432184b97f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89541
0247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.895410247
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.585476603
Short name T910
Test name
Test status
Simulation time 10087930064 ps
CPU time 16.6 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 205264 kb
Host smart-625a6898-83ff-4250-a2b7-814c95fba87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58547
6603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.585476603
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2250371319
Short name T1641
Test name
Test status
Simulation time 13168342818 ps
CPU time 15.87 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:24 PM PDT 24
Peak memory 205248 kb
Host smart-17a4b1d2-bb5e-46c7-8156-094cef1e3f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
71319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2250371319
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2542446968
Short name T982
Test name
Test status
Simulation time 10096548830 ps
CPU time 18.12 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:26 PM PDT 24
Peak memory 205228 kb
Host smart-4447289b-02da-4949-a5f5-9dc184043fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25424
46968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2542446968
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3491642166
Short name T1596
Test name
Test status
Simulation time 10055292491 ps
CPU time 14.84 seconds
Started May 26 01:29:07 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 205324 kb
Host smart-4ed502c8-fda1-4916-8379-fa09d23cf5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34916
42166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3491642166
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1534996776
Short name T95
Test name
Test status
Simulation time 10134432298 ps
CPU time 15.69 seconds
Started May 26 01:29:19 PM PDT 24
Finished May 26 01:29:36 PM PDT 24
Peak memory 205272 kb
Host smart-c07ec79f-283e-4004-a39d-948dbbc8fcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15349
96776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1534996776
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1169609017
Short name T679
Test name
Test status
Simulation time 10097638709 ps
CPU time 14.78 seconds
Started May 26 01:29:15 PM PDT 24
Finished May 26 01:29:31 PM PDT 24
Peak memory 205324 kb
Host smart-3eef7865-fa96-492b-a40d-6d250c5ad744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11696
09017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1169609017
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.118504470
Short name T1270
Test name
Test status
Simulation time 10063548845 ps
CPU time 14.13 seconds
Started May 26 01:29:17 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 205280 kb
Host smart-395b6b0b-a86e-4240-8b25-a254b226f219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
4470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.118504470
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.3736889664
Short name T252
Test name
Test status
Simulation time 10095836085 ps
CPU time 12.58 seconds
Started May 26 01:29:15 PM PDT 24
Finished May 26 01:29:28 PM PDT 24
Peak memory 205288 kb
Host smart-96bf755e-e86d-43c1-9bb4-87a4e9996ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
89664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.3736889664
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3178541683
Short name T194
Test name
Test status
Simulation time 10095021684 ps
CPU time 16.83 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:33 PM PDT 24
Peak memory 205196 kb
Host smart-ead7f34a-d8b4-4f8e-a39d-b340c7d9a2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
41683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3178541683
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.4274299716
Short name T1812
Test name
Test status
Simulation time 10107059896 ps
CPU time 14.25 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:31 PM PDT 24
Peak memory 205316 kb
Host smart-a69a5aa2-b277-4bab-a291-b7b895d0422c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42742
99716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.4274299716
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2606733302
Short name T78
Test name
Test status
Simulation time 10055458070 ps
CPU time 14.8 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 205336 kb
Host smart-dc224e0c-c8bb-4290-9625-92c7466afddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26067
33302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2606733302
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.290877918
Short name T1273
Test name
Test status
Simulation time 10053332225 ps
CPU time 14.22 seconds
Started May 26 01:29:18 PM PDT 24
Finished May 26 01:29:33 PM PDT 24
Peak memory 205292 kb
Host smart-7f110b91-5ae8-40f8-a775-256c6b042528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29087
7918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.290877918
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.843966123
Short name T1352
Test name
Test status
Simulation time 27727129331 ps
CPU time 57.7 seconds
Started May 26 01:29:19 PM PDT 24
Finished May 26 01:30:17 PM PDT 24
Peak memory 205284 kb
Host smart-39214ce8-f58f-4cee-8c2a-694c694ec5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84396
6123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.843966123
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1353056358
Short name T1422
Test name
Test status
Simulation time 10103630404 ps
CPU time 14.79 seconds
Started May 26 01:29:19 PM PDT 24
Finished May 26 01:29:34 PM PDT 24
Peak memory 205272 kb
Host smart-0fd83556-c618-48a8-a1b0-cbfb41434d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13530
56358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1353056358
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1112436343
Short name T583
Test name
Test status
Simulation time 10059615779 ps
CPU time 17.02 seconds
Started May 26 01:29:23 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 205212 kb
Host smart-11bf1d87-8388-4fde-9c0c-42bb906a65a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11124
36343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1112436343
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.2599243744
Short name T225
Test name
Test status
Simulation time 10053081496 ps
CPU time 14.5 seconds
Started May 26 01:29:15 PM PDT 24
Finished May 26 01:29:30 PM PDT 24
Peak memory 205472 kb
Host smart-1c46781b-2a90-43d8-9bd1-3f77115ae020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25992
43744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.2599243744
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1135137203
Short name T506
Test name
Test status
Simulation time 10039539276 ps
CPU time 13.43 seconds
Started May 26 01:29:16 PM PDT 24
Finished May 26 01:29:30 PM PDT 24
Peak memory 205172 kb
Host smart-ffb82d72-67d0-4ca5-9af2-74a083ded647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
37203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1135137203
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.718777032
Short name T857
Test name
Test status
Simulation time 10060755049 ps
CPU time 13.95 seconds
Started May 26 01:29:15 PM PDT 24
Finished May 26 01:29:30 PM PDT 24
Peak memory 205264 kb
Host smart-e5376611-ce8d-439f-ad45-326d7f072b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71877
7032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.718777032
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3167158566
Short name T1813
Test name
Test status
Simulation time 10054290736 ps
CPU time 13.32 seconds
Started May 26 01:29:22 PM PDT 24
Finished May 26 01:29:36 PM PDT 24
Peak memory 205288 kb
Host smart-26aae135-f17a-4704-a16d-8dfbec0fca3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31671
58566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3167158566
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1699854122
Short name T1549
Test name
Test status
Simulation time 10147013922 ps
CPU time 13.88 seconds
Started May 26 01:29:08 PM PDT 24
Finished May 26 01:29:22 PM PDT 24
Peak memory 205300 kb
Host smart-7aa252ab-1ac4-4477-8fb1-3a02eadd1f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
54122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1699854122
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.52717760
Short name T944
Test name
Test status
Simulation time 10057435513 ps
CPU time 14.33 seconds
Started May 26 01:29:17 PM PDT 24
Finished May 26 01:29:32 PM PDT 24
Peak memory 205196 kb
Host smart-96fcd37c-c1b1-499f-a230-c08bb3314aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52717
760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.52717760
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.457540346
Short name T1500
Test name
Test status
Simulation time 10154819268 ps
CPU time 13.59 seconds
Started May 26 01:29:22 PM PDT 24
Finished May 26 01:29:36 PM PDT 24
Peak memory 205260 kb
Host smart-24fef76d-472d-452d-b839-254875f02280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45754
0346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.457540346
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.712163724
Short name T1502
Test name
Test status
Simulation time 10147222396 ps
CPU time 15.28 seconds
Started May 26 01:29:55 PM PDT 24
Finished May 26 01:30:10 PM PDT 24
Peak memory 205324 kb
Host smart-e9c64ee2-4916-4595-9d8e-4333bb3262bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=712163724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.712163724
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.225281291
Short name T1199
Test name
Test status
Simulation time 10055930271 ps
CPU time 14.47 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 205184 kb
Host smart-7380e043-b671-4b5b-970d-56041d0dfe12
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=225281291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.225281291
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.2376679065
Short name T16
Test name
Test status
Simulation time 10056466849 ps
CPU time 17.52 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:11 PM PDT 24
Peak memory 205280 kb
Host smart-836be3f0-c8d0-4b70-b1b2-cec0339c6085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766
79065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.2376679065
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3608002319
Short name T1783
Test name
Test status
Simulation time 13516796853 ps
CPU time 18.38 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:29:44 PM PDT 24
Peak memory 205240 kb
Host smart-762168b6-c13a-4487-92b0-092d3f0d8fad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3608002319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3608002319
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1168293808
Short name T970
Test name
Test status
Simulation time 13255287695 ps
CPU time 17 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:29:43 PM PDT 24
Peak memory 205324 kb
Host smart-bb0378b7-641e-4c70-9f81-f7fdffa2b338
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1168293808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1168293808
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1047932049
Short name T494
Test name
Test status
Simulation time 13357824297 ps
CPU time 22.65 seconds
Started May 26 01:29:24 PM PDT 24
Finished May 26 01:29:48 PM PDT 24
Peak memory 205248 kb
Host smart-dfccf1f7-9a48-477e-a5b2-774aa34527bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1047932049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1047932049
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1938764566
Short name T570
Test name
Test status
Simulation time 10076947454 ps
CPU time 16.06 seconds
Started May 26 01:29:27 PM PDT 24
Finished May 26 01:29:44 PM PDT 24
Peak memory 205264 kb
Host smart-42a5c132-a954-46b8-9f46-6ed3bed14232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19387
64566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1938764566
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.16213227
Short name T40
Test name
Test status
Simulation time 10040138655 ps
CPU time 13.96 seconds
Started May 26 01:29:27 PM PDT 24
Finished May 26 01:29:41 PM PDT 24
Peak memory 205276 kb
Host smart-b64042b0-f843-49ca-a854-63d34bcb6f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.16213227
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3453066434
Short name T1009
Test name
Test status
Simulation time 10312688584 ps
CPU time 15.62 seconds
Started May 26 01:29:25 PM PDT 24
Finished May 26 01:29:42 PM PDT 24
Peak memory 205308 kb
Host smart-d5483e1a-4146-457b-90da-8664b2dd48c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34530
66434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3453066434
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3683658294
Short name T1116
Test name
Test status
Simulation time 10042153726 ps
CPU time 14.05 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 205252 kb
Host smart-1da9e7bb-84a6-43ae-a965-5d45ac310461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36836
58294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3683658294
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2751155733
Short name T373
Test name
Test status
Simulation time 10053318020 ps
CPU time 15.81 seconds
Started May 26 01:29:33 PM PDT 24
Finished May 26 01:29:49 PM PDT 24
Peak memory 205380 kb
Host smart-ee289438-85c4-4d3b-94fc-3dd8ebf0fe7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27511
55733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2751155733
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3697923702
Short name T712
Test name
Test status
Simulation time 10251582577 ps
CPU time 17.52 seconds
Started May 26 01:29:32 PM PDT 24
Finished May 26 01:29:50 PM PDT 24
Peak memory 205220 kb
Host smart-5f27f8fb-c4cb-43d2-b621-585bfb195250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36979
23702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3697923702
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.4247925172
Short name T69
Test name
Test status
Simulation time 10130793172 ps
CPU time 13.23 seconds
Started May 26 01:29:58 PM PDT 24
Finished May 26 01:30:11 PM PDT 24
Peak memory 205340 kb
Host smart-cd97e9d1-91b0-4bbf-982b-86cc40f44257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479
25172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.4247925172
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2849067226
Short name T1692
Test name
Test status
Simulation time 10046527074 ps
CPU time 14.27 seconds
Started May 26 01:29:52 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 205300 kb
Host smart-3d4e0f1a-b317-4390-bec2-dab1a34ec34c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
67226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2849067226
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1130952784
Short name T345
Test name
Test status
Simulation time 10071798202 ps
CPU time 16.36 seconds
Started May 26 01:29:33 PM PDT 24
Finished May 26 01:29:50 PM PDT 24
Peak memory 205260 kb
Host smart-33a8f89f-0026-4e33-b959-9ae1c6bd6658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
52784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1130952784
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1443325757
Short name T1384
Test name
Test status
Simulation time 10105408046 ps
CPU time 14.13 seconds
Started May 26 01:29:33 PM PDT 24
Finished May 26 01:29:48 PM PDT 24
Peak memory 205284 kb
Host smart-fdc65e33-c146-42b2-af6e-e41601176441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14433
25757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1443325757
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2861180309
Short name T1924
Test name
Test status
Simulation time 13252130272 ps
CPU time 23 seconds
Started May 26 01:29:32 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 205176 kb
Host smart-4e8eedee-67d9-4021-ba50-b58af8f9ed55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
80309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2861180309
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.924161464
Short name T1074
Test name
Test status
Simulation time 10083664219 ps
CPU time 13.82 seconds
Started May 26 01:29:33 PM PDT 24
Finished May 26 01:29:48 PM PDT 24
Peak memory 205308 kb
Host smart-3c75f4bc-8893-4018-b628-f849e24d8962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92416
1464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.924161464
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2904269414
Short name T1557
Test name
Test status
Simulation time 10077790971 ps
CPU time 14.66 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 205364 kb
Host smart-b1b62222-ab8b-477f-94c5-c00a9da42ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29042
69414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2904269414
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.664207091
Short name T120
Test name
Test status
Simulation time 10101113394 ps
CPU time 17.27 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:30:00 PM PDT 24
Peak memory 205328 kb
Host smart-f4d6a04b-59a2-464c-a269-35e60969705d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66420
7091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.664207091
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.363189562
Short name T1612
Test name
Test status
Simulation time 10082999370 ps
CPU time 14.58 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:57 PM PDT 24
Peak memory 205300 kb
Host smart-34581a62-f9e8-4239-b201-3fd912617db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318
9562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.363189562
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.4231178059
Short name T900
Test name
Test status
Simulation time 10066235355 ps
CPU time 16.61 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:59 PM PDT 24
Peak memory 205292 kb
Host smart-7295b381-1794-496a-901c-b337132305b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
78059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4231178059
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1049952973
Short name T789
Test name
Test status
Simulation time 10067834918 ps
CPU time 16.42 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:29:59 PM PDT 24
Peak memory 205300 kb
Host smart-1c6efab4-7213-4ec6-ba8d-f70763f23ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10499
52973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1049952973
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.4107053085
Short name T1842
Test name
Test status
Simulation time 10059128169 ps
CPU time 13.34 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:07 PM PDT 24
Peak memory 205232 kb
Host smart-a5466810-1f99-41f2-9570-e1e23038e4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
53085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.4107053085
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.3947923846
Short name T1537
Test name
Test status
Simulation time 10087703253 ps
CPU time 15.54 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:09 PM PDT 24
Peak memory 205280 kb
Host smart-0dde2cde-9bd3-472c-a5ad-ef981cbe3b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39479
23846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.3947923846
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.329850752
Short name T1667
Test name
Test status
Simulation time 10059189766 ps
CPU time 14.42 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:57 PM PDT 24
Peak memory 205256 kb
Host smart-0a7eb403-891c-4b7a-b601-a40264ba8a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32985
0752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.329850752
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1879279080
Short name T1204
Test name
Test status
Simulation time 10067878142 ps
CPU time 13.51 seconds
Started May 26 01:29:52 PM PDT 24
Finished May 26 01:30:06 PM PDT 24
Peak memory 205352 kb
Host smart-1d411688-d636-47d8-a676-da74e820e417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18792
79080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1879279080
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1771474268
Short name T1660
Test name
Test status
Simulation time 23425880535 ps
CPU time 47.66 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 205300 kb
Host smart-70f73897-29b3-4ca1-97c5-b6723e95b092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
74268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1771474268
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1727849715
Short name T629
Test name
Test status
Simulation time 10125390104 ps
CPU time 14.84 seconds
Started May 26 01:29:43 PM PDT 24
Finished May 26 01:29:58 PM PDT 24
Peak memory 205264 kb
Host smart-2c32f990-8960-411f-a963-7e6c9ba541e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17278
49715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1727849715
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1786488610
Short name T1919
Test name
Test status
Simulation time 10151045138 ps
CPU time 16.45 seconds
Started May 26 01:29:47 PM PDT 24
Finished May 26 01:30:04 PM PDT 24
Peak memory 205288 kb
Host smart-3ef1ed89-0d62-445d-92c7-cc482462bd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17864
88610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1786488610
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.2233208751
Short name T1818
Test name
Test status
Simulation time 10071304209 ps
CPU time 14.42 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 205288 kb
Host smart-afeb25ee-d7de-4f38-a4f6-eef5d3afa27b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
08751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.2233208751
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2548739439
Short name T1666
Test name
Test status
Simulation time 10065877352 ps
CPU time 16.57 seconds
Started May 26 01:29:47 PM PDT 24
Finished May 26 01:30:04 PM PDT 24
Peak memory 205236 kb
Host smart-060641c0-0bc9-41b4-b8ea-e2c0d0ae9743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25487
39439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2548739439
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2072407806
Short name T141
Test name
Test status
Simulation time 10103641937 ps
CPU time 15.23 seconds
Started May 26 01:29:53 PM PDT 24
Finished May 26 01:30:08 PM PDT 24
Peak memory 205152 kb
Host smart-0d4c3cfa-8300-4c86-b27a-c64390d99640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
07806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2072407806
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3637031824
Short name T669
Test name
Test status
Simulation time 10045730943 ps
CPU time 15.11 seconds
Started May 26 01:29:40 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 205232 kb
Host smart-25a62459-15e2-45d7-9e73-37286837de01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36370
31824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3637031824
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2685195420
Short name T1519
Test name
Test status
Simulation time 10108853049 ps
CPU time 16.1 seconds
Started May 26 01:29:26 PM PDT 24
Finished May 26 01:29:43 PM PDT 24
Peak memory 205316 kb
Host smart-2ee380a0-30ab-43ba-8f16-c3ed96e8f299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26851
95420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2685195420
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.682875077
Short name T377
Test name
Test status
Simulation time 10078781120 ps
CPU time 13.24 seconds
Started May 26 01:29:41 PM PDT 24
Finished May 26 01:29:56 PM PDT 24
Peak memory 205332 kb
Host smart-9e9bef19-f253-400d-b1ee-42b890d633f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68287
5077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.682875077
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2740071967
Short name T1127
Test name
Test status
Simulation time 10082812074 ps
CPU time 13.41 seconds
Started May 26 01:29:42 PM PDT 24
Finished May 26 01:29:57 PM PDT 24
Peak memory 205292 kb
Host smart-f05cb882-df82-4746-9ebd-f97272bfb85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27400
71967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2740071967
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.2814874240
Short name T1159
Test name
Test status
Simulation time 10192108628 ps
CPU time 15.53 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:28 PM PDT 24
Peak memory 205284 kb
Host smart-ff613f6c-7fdf-4ba8-8ea5-44266cbe66cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2814874240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.2814874240
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.2204540192
Short name T826
Test name
Test status
Simulation time 10106527104 ps
CPU time 13.18 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:26 PM PDT 24
Peak memory 205324 kb
Host smart-b520a278-5f07-458a-a074-763224abade7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2204540192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.2204540192
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.2759602615
Short name T894
Test name
Test status
Simulation time 10129624157 ps
CPU time 13.57 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:27 PM PDT 24
Peak memory 205232 kb
Host smart-6e287cb7-1f97-4c39-aa14-8e1def4df008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
02615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.2759602615
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3559153703
Short name T881
Test name
Test status
Simulation time 13978952326 ps
CPU time 21 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:24 PM PDT 24
Peak memory 205368 kb
Host smart-68429f8b-3710-4934-b136-5ca770db3064
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3559153703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3559153703
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.170867800
Short name T649
Test name
Test status
Simulation time 13307699588 ps
CPU time 17.35 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205260 kb
Host smart-21211583-d596-4dee-803c-59c41de9eebb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=170867800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.170867800
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.659986886
Short name T699
Test name
Test status
Simulation time 13269611686 ps
CPU time 17.82 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205252 kb
Host smart-0440f692-6928-45f9-97e8-d21e31946aa9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=659986886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.659986886
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2595881679
Short name T943
Test name
Test status
Simulation time 10096280840 ps
CPU time 18.42 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205332 kb
Host smart-ce25cead-e4a7-40bf-9720-da43ae69b637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958
81679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2595881679
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2337332619
Short name T870
Test name
Test status
Simulation time 10103398725 ps
CPU time 14.89 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:17 PM PDT 24
Peak memory 205284 kb
Host smart-12329d65-52c2-48be-b898-2621fcc14524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23373
32619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2337332619
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.2018361773
Short name T1925
Test name
Test status
Simulation time 11128120457 ps
CPU time 17.63 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 205400 kb
Host smart-cc7d3955-7382-4161-a5cd-b5faca244e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20183
61773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2018361773
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1913155329
Short name T1359
Test name
Test status
Simulation time 10038693391 ps
CPU time 15.39 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:19 PM PDT 24
Peak memory 205228 kb
Host smart-54055b1c-6eed-499a-89c4-7399621a4401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
55329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1913155329
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2565555993
Short name T1624
Test name
Test status
Simulation time 10067990852 ps
CPU time 14.54 seconds
Started May 26 01:30:02 PM PDT 24
Finished May 26 01:30:18 PM PDT 24
Peak memory 205344 kb
Host smart-2e0a0e8d-8973-4314-af10-16160a83060a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
55993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2565555993
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3274810081
Short name T407
Test name
Test status
Simulation time 10789898106 ps
CPU time 15.53 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 205260 kb
Host smart-de1202ad-4ccf-4497-9d08-5e3862a28412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32748
10081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3274810081
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2867620480
Short name T1138
Test name
Test status
Simulation time 10096585780 ps
CPU time 16.79 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205236 kb
Host smart-f0e8374e-470d-45bd-8726-0bad32df934f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676
20480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2867620480
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3998454274
Short name T1157
Test name
Test status
Simulation time 10120877551 ps
CPU time 14.41 seconds
Started May 26 01:30:10 PM PDT 24
Finished May 26 01:30:25 PM PDT 24
Peak memory 205292 kb
Host smart-7745c7af-8e40-46fe-b10a-b6d84a744c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
54274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3998454274
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2808166286
Short name T499
Test name
Test status
Simulation time 10060552200 ps
CPU time 15.07 seconds
Started May 26 01:30:13 PM PDT 24
Finished May 26 01:30:29 PM PDT 24
Peak memory 205204 kb
Host smart-87f0bf2c-63ea-483f-9eac-0b568085de55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28081
66286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2808166286
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1515640525
Short name T413
Test name
Test status
Simulation time 10143916228 ps
CPU time 13.54 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:18 PM PDT 24
Peak memory 205168 kb
Host smart-c0d03c26-bcea-495c-bda4-06419379db72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
40525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1515640525
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2696146236
Short name T1312
Test name
Test status
Simulation time 10124706729 ps
CPU time 14.18 seconds
Started May 26 01:30:06 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 205352 kb
Host smart-4f29e21e-96ab-4b00-843e-9153ceb1ce44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
46236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2696146236
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1166558834
Short name T1399
Test name
Test status
Simulation time 13225677390 ps
CPU time 16.41 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205192 kb
Host smart-fd7df5ee-89f2-4079-af8b-9b287154bf45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
58834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1166558834
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3305416470
Short name T1540
Test name
Test status
Simulation time 10117020460 ps
CPU time 14.06 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205288 kb
Host smart-9305c8f1-9a0e-4379-beef-463f6e8d2fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33054
16470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3305416470
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.574593413
Short name T1410
Test name
Test status
Simulation time 10047049833 ps
CPU time 15.25 seconds
Started May 26 01:30:06 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205216 kb
Host smart-621f45ad-3be2-4e88-bc5b-3ec60eabbfa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57459
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.574593413
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.4223330629
Short name T111
Test name
Test status
Simulation time 10112706916 ps
CPU time 15.77 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 205316 kb
Host smart-b47dba29-084d-43a6-8bba-9bdd61f408e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
30629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.4223330629
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2834234120
Short name T815
Test name
Test status
Simulation time 10088586716 ps
CPU time 14.79 seconds
Started May 26 01:30:04 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 205260 kb
Host smart-0f31dafe-4b4a-49db-b796-903232a67ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342
34120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2834234120
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.69350124
Short name T1849
Test name
Test status
Simulation time 10104941724 ps
CPU time 14.11 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:18 PM PDT 24
Peak memory 205240 kb
Host smart-8555199e-1280-4fb2-ac72-1c952c608aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69350
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.69350124
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.103618708
Short name T41
Test name
Test status
Simulation time 10068521340 ps
CPU time 13.85 seconds
Started May 26 01:30:07 PM PDT 24
Finished May 26 01:30:22 PM PDT 24
Peak memory 205244 kb
Host smart-ba557bbe-b661-4411-b305-175a7c4a3248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10361
8708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.103618708
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1824708437
Short name T143
Test name
Test status
Simulation time 10097665838 ps
CPU time 16.55 seconds
Started May 26 01:30:13 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 205240 kb
Host smart-5a2c25b4-3b16-45a2-b3e8-a78fbb1482cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
08437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1824708437
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.3044547809
Short name T1149
Test name
Test status
Simulation time 10064220228 ps
CPU time 14.31 seconds
Started May 26 01:30:14 PM PDT 24
Finished May 26 01:30:29 PM PDT 24
Peak memory 205200 kb
Host smart-a59410b8-bc3f-4cd6-962d-d4d3d619df3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
47809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.3044547809
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3657537551
Short name T1876
Test name
Test status
Simulation time 10039482058 ps
CPU time 12.35 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:26 PM PDT 24
Peak memory 205300 kb
Host smart-f2adee28-b2ca-4fec-82fd-983d90ba2dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
37551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3657537551
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.4154185234
Short name T1221
Test name
Test status
Simulation time 10044318972 ps
CPU time 13.33 seconds
Started May 26 01:30:16 PM PDT 24
Finished May 26 01:30:30 PM PDT 24
Peak memory 205276 kb
Host smart-3832ead3-9f04-4f04-9481-439b7dec12bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541
85234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.4154185234
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.724781794
Short name T1572
Test name
Test status
Simulation time 19278932544 ps
CPU time 39.15 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:44 PM PDT 24
Peak memory 205328 kb
Host smart-39b8afcd-35ed-4b44-92c8-e4c42709543f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72478
1794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.724781794
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1030224418
Short name T718
Test name
Test status
Simulation time 10123083670 ps
CPU time 15.4 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:21 PM PDT 24
Peak memory 205180 kb
Host smart-dde851db-e105-4b92-bdf2-8d43cacac26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10302
24418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1030224418
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3125779440
Short name T1195
Test name
Test status
Simulation time 10113655823 ps
CPU time 16.76 seconds
Started May 26 01:30:08 PM PDT 24
Finished May 26 01:30:26 PM PDT 24
Peak memory 205280 kb
Host smart-fde23236-89a0-4efe-b8a3-756ca6aa06f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31257
79440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3125779440
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.2964999757
Short name T1770
Test name
Test status
Simulation time 10097817338 ps
CPU time 14.07 seconds
Started May 26 01:30:05 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 205308 kb
Host smart-6de2fce0-7c28-4503-84ea-49d926b83768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29649
99757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.2964999757
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.509205531
Short name T925
Test name
Test status
Simulation time 10081235235 ps
CPU time 12.76 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:26 PM PDT 24
Peak memory 205280 kb
Host smart-6cc63ab3-a76f-4578-85a0-65e35d44d39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50920
5531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.509205531
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3252418587
Short name T159
Test name
Test status
Simulation time 10063591062 ps
CPU time 14.8 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:28 PM PDT 24
Peak memory 205288 kb
Host smart-dabc309e-bd27-446c-923a-42c3af8ac083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32524
18587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3252418587
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2840186572
Short name T1730
Test name
Test status
Simulation time 10056666437 ps
CPU time 18.24 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 205256 kb
Host smart-92813308-f0bd-466a-b6f8-46a39a3b1c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
86572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2840186572
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1599301266
Short name T1341
Test name
Test status
Simulation time 10122337497 ps
CPU time 16.17 seconds
Started May 26 01:30:03 PM PDT 24
Finished May 26 01:30:20 PM PDT 24
Peak memory 205316 kb
Host smart-7a40cb17-663e-48ea-a9b8-c42a4351756f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15993
01266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1599301266
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1988004310
Short name T979
Test name
Test status
Simulation time 10106401223 ps
CPU time 16.22 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:28 PM PDT 24
Peak memory 205332 kb
Host smart-58d59cba-8899-4ec0-ab20-8dd889d30c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19880
04310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1988004310
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.360241760
Short name T338
Test name
Test status
Simulation time 10112132270 ps
CPU time 16.3 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:28 PM PDT 24
Peak memory 205204 kb
Host smart-51a0240d-0458-43d9-b2c5-5f8b7a224ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
1760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.360241760
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.605001209
Short name T1576
Test name
Test status
Simulation time 10144099688 ps
CPU time 13.25 seconds
Started May 26 01:30:46 PM PDT 24
Finished May 26 01:31:00 PM PDT 24
Peak memory 205288 kb
Host smart-02065eab-a70f-4955-9538-926d8457c99e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=605001209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.605001209
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.935081413
Short name T1033
Test name
Test status
Simulation time 10061884445 ps
CPU time 12.61 seconds
Started May 26 01:30:44 PM PDT 24
Finished May 26 01:30:58 PM PDT 24
Peak memory 205224 kb
Host smart-7da26a7d-67f2-4f29-8474-5881284bd1a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=935081413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.935081413
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.1172383400
Short name T1746
Test name
Test status
Simulation time 10098854757 ps
CPU time 16.57 seconds
Started May 26 01:30:45 PM PDT 24
Finished May 26 01:31:03 PM PDT 24
Peak memory 205216 kb
Host smart-60aed67e-c7c6-4751-95d6-e88ed0e0a8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
83400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.1172383400
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.4179540748
Short name T1023
Test name
Test status
Simulation time 14088385309 ps
CPU time 19.56 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:31 PM PDT 24
Peak memory 205260 kb
Host smart-3d5701b6-c36e-435f-be1f-9fc9f812239e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4179540748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.4179540748
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3286784660
Short name T1745
Test name
Test status
Simulation time 13191372254 ps
CPU time 17.26 seconds
Started May 26 01:30:11 PM PDT 24
Finished May 26 01:30:30 PM PDT 24
Peak memory 205272 kb
Host smart-7c487e1b-6b31-4139-929f-3a36e5598eb8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3286784660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3286784660
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3205981845
Short name T1242
Test name
Test status
Simulation time 13393825254 ps
CPU time 18.89 seconds
Started May 26 01:30:10 PM PDT 24
Finished May 26 01:30:30 PM PDT 24
Peak memory 205192 kb
Host smart-2dea0ae2-8816-4e8c-8f51-5582e4b87834
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3205981845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3205981845
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2422428485
Short name T1476
Test name
Test status
Simulation time 10065952394 ps
CPU time 16.68 seconds
Started May 26 01:30:20 PM PDT 24
Finished May 26 01:30:37 PM PDT 24
Peak memory 205336 kb
Host smart-664f380e-a699-45d1-9762-4b2534cbf638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24224
28485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2422428485
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2476420328
Short name T1155
Test name
Test status
Simulation time 10095247902 ps
CPU time 14.8 seconds
Started May 26 01:30:20 PM PDT 24
Finished May 26 01:30:36 PM PDT 24
Peak memory 205224 kb
Host smart-08adc3ee-60a0-4f5a-b993-be8908487779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764
20328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2476420328
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1030068492
Short name T1100
Test name
Test status
Simulation time 10077582139 ps
CPU time 13.98 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:51 PM PDT 24
Peak memory 205216 kb
Host smart-7a839e62-6f20-4ae8-8048-d991554cf514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10300
68492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1030068492
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1992983275
Short name T1058
Test name
Test status
Simulation time 10076796050 ps
CPU time 13.92 seconds
Started May 26 01:30:20 PM PDT 24
Finished May 26 01:30:35 PM PDT 24
Peak memory 205420 kb
Host smart-9305bab0-05f3-45ef-9795-0f720d8848b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
83275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1992983275
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.892622926
Short name T1698
Test name
Test status
Simulation time 10180074599 ps
CPU time 15.83 seconds
Started May 26 01:30:21 PM PDT 24
Finished May 26 01:30:38 PM PDT 24
Peak memory 205268 kb
Host smart-c77aa480-6a28-49be-83eb-21c4a91b50d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89262
2926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.892622926
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2243880858
Short name T1475
Test name
Test status
Simulation time 10130108350 ps
CPU time 13.84 seconds
Started May 26 01:30:40 PM PDT 24
Finished May 26 01:30:54 PM PDT 24
Peak memory 205304 kb
Host smart-95e18f87-526d-4921-bff5-02dbddcf130a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
80858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2243880858
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3695386968
Short name T1010
Test name
Test status
Simulation time 10050362057 ps
CPU time 14.2 seconds
Started May 26 01:30:35 PM PDT 24
Finished May 26 01:30:49 PM PDT 24
Peak memory 205264 kb
Host smart-dcaca4c9-037e-4812-aa7c-9b1a1d3f86e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
86968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3695386968
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3619343582
Short name T587
Test name
Test status
Simulation time 10136423090 ps
CPU time 14.94 seconds
Started May 26 01:30:21 PM PDT 24
Finished May 26 01:30:37 PM PDT 24
Peak memory 205312 kb
Host smart-ec9f5d6c-77f4-468d-9e9b-3befd9f7f757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193
43582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3619343582
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3479994099
Short name T616
Test name
Test status
Simulation time 10083115317 ps
CPU time 15.65 seconds
Started May 26 01:30:19 PM PDT 24
Finished May 26 01:30:35 PM PDT 24
Peak memory 205308 kb
Host smart-bdd3fdab-82d9-45f9-b039-686e9d656dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34799
94099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3479994099
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2073149645
Short name T392
Test name
Test status
Simulation time 13221884210 ps
CPU time 19.17 seconds
Started May 26 01:30:21 PM PDT 24
Finished May 26 01:30:41 PM PDT 24
Peak memory 205256 kb
Host smart-cb4f2044-a347-4748-b5e0-a69c70a72c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20731
49645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2073149645
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.642124002
Short name T1362
Test name
Test status
Simulation time 10121990039 ps
CPU time 15.06 seconds
Started May 26 01:30:20 PM PDT 24
Finished May 26 01:30:36 PM PDT 24
Peak memory 205224 kb
Host smart-e968fdaf-aec5-4f9d-9acf-044a9951af5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64212
4002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.642124002
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.656901936
Short name T461
Test name
Test status
Simulation time 10062147933 ps
CPU time 14.68 seconds
Started May 26 01:30:26 PM PDT 24
Finished May 26 01:30:42 PM PDT 24
Peak memory 205268 kb
Host smart-1e40ba24-93c1-4627-9339-288e93273569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65690
1936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.656901936
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.135510238
Short name T119
Test name
Test status
Simulation time 10116690942 ps
CPU time 13.94 seconds
Started May 26 01:30:30 PM PDT 24
Finished May 26 01:30:44 PM PDT 24
Peak memory 205292 kb
Host smart-bdf6b598-31fd-4d2c-8351-290695cc3d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
0238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.135510238
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2011402535
Short name T1271
Test name
Test status
Simulation time 10088542403 ps
CPU time 15.14 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:30:44 PM PDT 24
Peak memory 205280 kb
Host smart-69e51c9f-b6ab-431d-8d87-fbf7856c937a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20114
02535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2011402535
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.374546648
Short name T512
Test name
Test status
Simulation time 10051934848 ps
CPU time 16.34 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:30:45 PM PDT 24
Peak memory 205252 kb
Host smart-1bc30c2e-bc28-4c0e-a66b-233612066329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
6648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.374546648
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1239749127
Short name T515
Test name
Test status
Simulation time 10096757523 ps
CPU time 15.37 seconds
Started May 26 01:30:27 PM PDT 24
Finished May 26 01:30:43 PM PDT 24
Peak memory 205484 kb
Host smart-15c34f08-66fb-46f0-a028-8d4872db1536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
49127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1239749127
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.401533178
Short name T178
Test name
Test status
Simulation time 10055413229 ps
CPU time 14.85 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 205292 kb
Host smart-a6247c78-cc29-4e28-82dc-93ce703f0baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40153
3178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.401533178
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.3249167086
Short name T1286
Test name
Test status
Simulation time 10090854538 ps
CPU time 13.64 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:50 PM PDT 24
Peak memory 205276 kb
Host smart-eac57939-794c-4bc7-975a-94b297690450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32491
67086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.3249167086
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2463578126
Short name T959
Test name
Test status
Simulation time 10077518697 ps
CPU time 13.94 seconds
Started May 26 01:30:37 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 205312 kb
Host smart-32a6578a-63f0-40b0-9ab7-15613c1fce4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24635
78126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2463578126
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2711417556
Short name T511
Test name
Test status
Simulation time 10075120376 ps
CPU time 14.55 seconds
Started May 26 01:30:37 PM PDT 24
Finished May 26 01:30:53 PM PDT 24
Peak memory 205236 kb
Host smart-0dd14b44-ab77-4309-ab55-31655ac60243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27114
17556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2711417556
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1906379367
Short name T357
Test name
Test status
Simulation time 10124226215 ps
CPU time 17.08 seconds
Started May 26 01:30:28 PM PDT 24
Finished May 26 01:30:46 PM PDT 24
Peak memory 205276 kb
Host smart-9b556936-a816-4af2-9cd6-0cef656b328b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19063
79367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1906379367
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2270529701
Short name T1648
Test name
Test status
Simulation time 10137380167 ps
CPU time 13.7 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 205260 kb
Host smart-3c4579ae-2fea-4011-a92b-108237dc5719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22705
29701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2270529701
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.1798796628
Short name T954
Test name
Test status
Simulation time 10074532842 ps
CPU time 14.03 seconds
Started May 26 01:30:38 PM PDT 24
Finished May 26 01:30:53 PM PDT 24
Peak memory 205264 kb
Host smart-e2fe0445-784e-45c1-8c03-747e36375c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17987
96628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.1798796628
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.216773868
Short name T401
Test name
Test status
Simulation time 10042444781 ps
CPU time 14.07 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 205288 kb
Host smart-b0c464be-1cd9-4491-ae67-c380c5a0dfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21677
3868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.216773868
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.436464325
Short name T1764
Test name
Test status
Simulation time 10052009045 ps
CPU time 13.9 seconds
Started May 26 01:30:38 PM PDT 24
Finished May 26 01:30:53 PM PDT 24
Peak memory 205256 kb
Host smart-5e49c816-42de-497c-8236-3b3ddf8bf180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43646
4325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.436464325
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.4058867250
Short name T1114
Test name
Test status
Simulation time 10063862978 ps
CPU time 14.44 seconds
Started May 26 01:30:36 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 205304 kb
Host smart-3f8bba0e-71f2-4377-b194-ef8a131947d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40588
67250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.4058867250
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.630195788
Short name T1686
Test name
Test status
Simulation time 10090144308 ps
CPU time 13.94 seconds
Started May 26 01:30:12 PM PDT 24
Finished May 26 01:30:28 PM PDT 24
Peak memory 205196 kb
Host smart-6e893b4b-0ff7-453c-94b1-fe536c579592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63019
5788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.630195788
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.4095558335
Short name T1
Test name
Test status
Simulation time 10104351186 ps
CPU time 13.11 seconds
Started May 26 01:30:38 PM PDT 24
Finished May 26 01:30:52 PM PDT 24
Peak memory 205340 kb
Host smart-eb59e970-ebc0-47fb-a6a2-821cbc71e482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40955
58335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.4095558335
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1772901069
Short name T308
Test name
Test status
Simulation time 10067377572 ps
CPU time 15.03 seconds
Started May 26 01:30:38 PM PDT 24
Finished May 26 01:30:54 PM PDT 24
Peak memory 205308 kb
Host smart-ba7afcc2-4e09-4b24-9220-e318edac8ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17729
01069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1772901069
Directory /workspace/9.usbdev_stall_trans/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%