Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353	1		T2	2		T6	2		T15	5
all_values[1]	353	1		T2	2		T6	2		T15	5
all_values[2]	353	1		T2	2		T6	2		T15	5
all_values[3]	353	1		T2	2		T6	2		T15	5
all_values[4]	353	1		T2	2		T6	2		T15	5
all_values[5]	353	1		T2	2		T6	2		T15	5
all_values[6]	353	1		T2	2		T6	2		T15	5
all_values[7]	353	1		T2	2		T6	2		T15	5
all_values[8]	353	1		T2	2		T6	2		T15	5
all_values[9]	353	1		T2	2		T6	2		T15	5
all_values[10]	353	1		T2	2		T6	2		T15	5
all_values[11]	353	1		T2	2		T6	2		T15	5
all_values[12]	353	1		T2	2		T6	2		T15	5
all_values[13]	353	1		T2	2		T6	2		T15	5
all_values[14]	353	1		T2	2		T6	2		T15	5
all_values[15]	353	1		T2	2		T6	2		T15	5
all_values[16]	353	1		T2	2		T6	2		T15	5
all_values[17]	353	1		T2	2		T6	2		T15	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3542	1		T2	36		T6	36		T15	54
auto[1]	2812	1		T15	36		T7	74		T16	74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1621	1		T2	36		T6	36		T15	9
auto[1]	4733	1		T15	81		T7	125		T16	124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	71	1		T2	2		T6	2		T7	1
all_values[0]	auto[0]	auto[1]	139	1		T15	2		T7	1		T16	4
all_values[0]	auto[1]	auto[0]	22	1		T7	1		T37	1		T59	1
all_values[0]	auto[1]	auto[1]	121	1		T15	3		T7	5		T16	4
all_values[1]	auto[0]	auto[0]	63	1		T2	2		T6	2		T15	1
all_values[1]	auto[0]	auto[1]	133	1		T15	4		T7	2		T16	5
all_values[1]	auto[1]	auto[0]	22	1		T7	2		T18	2		T36	1
all_values[1]	auto[1]	auto[1]	135	1		T7	3		T16	3		T17	3
all_values[2]	auto[0]	auto[0]	71	1		T2	2		T6	2		T16	1
all_values[2]	auto[0]	auto[1]	122	1		T15	5		T7	5		T16	1
all_values[2]	auto[1]	auto[0]	34	1		T16	2		T60	1		T57	1
all_values[2]	auto[1]	auto[1]	126	1		T7	3		T16	4		T18	1
all_values[3]	auto[0]	auto[0]	69	1		T2	2		T6	2		T7	1
all_values[3]	auto[0]	auto[1]	138	1		T15	5		T7	4		T16	4
all_values[3]	auto[1]	auto[0]	40	1		T7	1		T16	1		T36	5
all_values[3]	auto[1]	auto[1]	106	1		T7	2		T16	3		T17	7
all_values[4]	auto[0]	auto[0]	68	1		T2	2		T6	2		T16	3
all_values[4]	auto[0]	auto[1]	126	1		T15	1		T7	6		T16	3
all_values[4]	auto[1]	auto[0]	25	1		T15	1		T16	1		T18	1
all_values[4]	auto[1]	auto[1]	134	1		T15	3		T7	2		T16	1
all_values[5]	auto[0]	auto[0]	67	1		T2	2		T6	2		T16	1
all_values[5]	auto[0]	auto[1]	128	1		T15	5		T7	2		T16	4
all_values[5]	auto[1]	auto[0]	32	1		T7	1		T16	2		T60	1
all_values[5]	auto[1]	auto[1]	126	1		T7	5		T16	1		T18	4
all_values[6]	auto[0]	auto[0]	67	1		T2	2		T6	2		T36	1
all_values[6]	auto[0]	auto[1]	118	1		T15	1		T7	2		T16	1
all_values[6]	auto[1]	auto[0]	36	1		T16	1		T36	1		T37	4
all_values[6]	auto[1]	auto[1]	132	1		T15	4		T7	6		T16	6
all_values[7]	auto[0]	auto[0]	60	1		T2	2		T6	2		T16	1
all_values[7]	auto[0]	auto[1]	161	1		T15	3		T7	5		T16	5
all_values[7]	auto[1]	auto[0]	12	1		T38	1		T59	3		T61	3
all_values[7]	auto[1]	auto[1]	120	1		T15	2		T7	3		T16	2
all_values[8]	auto[0]	auto[0]	67	1		T2	2		T6	2		T7	2
all_values[8]	auto[0]	auto[1]	135	1		T15	4		T7	4		T16	5
all_values[8]	auto[1]	auto[0]	10	1		T57	2		T62	1		T63	2
all_values[8]	auto[1]	auto[1]	141	1		T15	1		T7	2		T16	2
all_values[9]	auto[0]	auto[0]	66	1		T2	2		T6	2		T15	1
all_values[9]	auto[0]	auto[1]	125	1		T15	3		T7	2		T18	1
all_values[9]	auto[1]	auto[0]	23	1		T15	1		T16	1		T18	1
all_values[9]	auto[1]	auto[1]	139	1		T7	6		T16	5		T18	3
all_values[10]	auto[0]	auto[0]	60	1		T2	2		T6	2		T7	2
all_values[10]	auto[0]	auto[1]	129	1		T15	4		T7	5		T16	5
all_values[10]	auto[1]	auto[0]	21	1		T16	1		T17	1		T36	3
all_values[10]	auto[1]	auto[1]	143	1		T15	1		T7	1		T16	1
all_values[11]	auto[0]	auto[0]	75	1		T2	2		T6	2		T17	1
all_values[11]	auto[0]	auto[1]	113	1		T7	2		T16	3		T18	3
all_values[11]	auto[1]	auto[0]	26	1		T15	1		T59	1		T56	1
all_values[11]	auto[1]	auto[1]	139	1		T15	4		T7	6		T16	5
all_values[12]	auto[0]	auto[0]	55	1		T2	2		T6	2		T38	1
all_values[12]	auto[0]	auto[1]	132	1		T15	4		T7	1		T16	2
all_values[12]	auto[1]	auto[0]	28	1		T7	4		T18	1		T17	5
all_values[12]	auto[1]	auto[1]	138	1		T15	1		T7	3		T16	6
all_values[13]	auto[0]	auto[0]	67	1		T2	2		T6	2		T18	1
all_values[13]	auto[0]	auto[1]	130	1		T7	5		T16	5		T18	4
all_values[13]	auto[1]	auto[0]	32	1		T7	1		T36	1		T64	3
all_values[13]	auto[1]	auto[1]	124	1		T15	5		T7	2		T16	3
all_values[14]	auto[0]	auto[0]	61	1		T2	2		T6	2		T19	2
all_values[14]	auto[0]	auto[1]	135	1		T7	6		T16	4		T18	5
all_values[14]	auto[1]	auto[0]	31	1		T59	1		T64	1		T60	1
all_values[14]	auto[1]	auto[1]	126	1		T15	5		T7	2		T16	4
all_values[15]	auto[0]	auto[0]	67	1		T2	2		T6	2		T15	2
all_values[15]	auto[0]	auto[1]	125	1		T16	2		T18	3		T17	5
all_values[15]	auto[1]	auto[0]	27	1		T18	1		T36	1		T59	1
all_values[15]	auto[1]	auto[1]	134	1		T15	3		T7	8		T16	5
all_values[16]	auto[0]	auto[0]	50	1		T2	2		T6	2		T15	1
all_values[16]	auto[0]	auto[1]	136	1		T15	4		T7	3		T16	1
all_values[16]	auto[1]	auto[0]	13	1		T17	1		T37	1		T38	1
all_values[16]	auto[1]	auto[1]	154	1		T7	5		T16	7		T18	5
all_values[17]	auto[0]	auto[0]	61	1		T2	2		T6	2		T7	2
all_values[17]	auto[0]	auto[1]	152	1		T15	4		T7	6		T16	5
all_values[17]	auto[1]	auto[0]	22	1		T15	1		T17	1		T65	1
all_values[17]	auto[1]	auto[1]	118	1		T16	3		T18	1		T17	2