| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 68.38 | 66.22 | 61.10 | 87.37 | 0.00 | 69.99 | 97.77 | 96.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 55.07 | 55.07 | 62.27 | 62.27 | 49.10 | 49.10 | 83.73 | 83.73 | 0.00 | 0.00 | 63.19 | 63.19 | 93.85 | 93.85 | 33.33 | 33.33 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.81491927 |
| 63.22 | 8.15 | 62.97 | 0.70 | 50.83 | 1.72 | 92.45 | 8.73 | 0.00 | 0.00 | 63.36 | 0.16 | 93.85 | 0.00 | 79.10 | 45.77 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2765135947 |
| 65.88 | 2.66 | 66.04 | 3.07 | 57.94 | 7.11 | 93.87 | 1.42 | 0.00 | 0.00 | 69.91 | 6.56 | 94.13 | 0.28 | 79.28 | 0.18 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4051662946 |
| 67.38 | 1.50 | 66.04 | 0.00 | 59.40 | 1.46 | 96.23 | 2.36 | 0.00 | 0.00 | 69.99 | 0.08 | 95.53 | 1.40 | 84.50 | 5.23 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2560217085 |
| 68.13 | 0.75 | 66.04 | 0.00 | 59.40 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 95.53 | 0.00 | 89.73 | 5.23 | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1783279907 |
| 68.62 | 0.49 | 66.04 | 0.00 | 60.85 | 1.44 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.49 | 1.96 | 89.73 | 0.00 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3252614777 |
| 68.95 | 0.33 | 66.04 | 0.00 | 60.85 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.49 | 0.00 | 92.07 | 2.34 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.697063276 |
| 69.16 | 0.21 | 66.04 | 0.00 | 60.85 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.49 | 0.00 | 93.51 | 1.44 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2588984990 |
| 69.29 | 0.13 | 66.04 | 0.00 | 60.85 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.49 | 0.00 | 94.41 | 0.90 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2318884322 |
| 69.39 | 0.10 | 66.04 | 0.00 | 60.85 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.49 | 0.00 | 95.14 | 0.72 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1309596954 |
| 69.45 | 0.06 | 66.04 | 0.00 | 60.96 | 0.12 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.28 | 95.14 | 0.00 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3628975344 |
| 69.50 | 0.05 | 66.04 | 0.00 | 60.96 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 95.50 | 0.36 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4009174191 |
| 69.55 | 0.05 | 66.04 | 0.00 | 60.96 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 95.86 | 0.36 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4186158924 |
| 69.58 | 0.03 | 66.04 | 0.00 | 60.99 | 0.02 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.04 | 0.18 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1498894160 |
| 69.60 | 0.03 | 66.22 | 0.19 | 60.99 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.04 | 0.00 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1823880255 |
| 69.63 | 0.03 | 66.22 | 0.00 | 60.99 | 0.00 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.22 | 0.18 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.954146612 |
| 69.65 | 0.02 | 66.22 | 0.00 | 61.10 | 0.12 | 96.23 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.77 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3283753049 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4075168776 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.356430429 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4259619905 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2377215279 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1811888653 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1601957976 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2004954660 |
| /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2247428761 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2640185137 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1557324689 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.308683885 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.893317339 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4169094205 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1563159674 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2952223595 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.392273649 |
| /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3744069715 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1936685831 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1579991771 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1819242460 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2577539203 |
| /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4080495807 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3997000618 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2054870815 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3451175767 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2212122283 |
| /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4116820270 |
| /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.75831868 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3572790445 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2854592327 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2019715947 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.772101303 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2100170510 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.147480028 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1945971210 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1842357180 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2603739943 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.418500820 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3341446895 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.316696929 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1170651159 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1744259876 |
| /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1575140026 |
| /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3506414026 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1375467434 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2202996057 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3868635029 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.107736473 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3610262108 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4176338402 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.333571643 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2531190353 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3329615686 |
| /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1681468115 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4236622130 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2600931951 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1877356449 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2003365672 |
| /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1496954901 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.777874881 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1579998729 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1941247200 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2430399847 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.224751276 |
| /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2933927744 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3390727759 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2302366762 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3859088063 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2997435749 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.637401995 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1974203262 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1265199562 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.44996326 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3916821550 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3250578241 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3124981764 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.479130453 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3452544370 |
| /workspace/coverage/cover_reg_top/2.usbdev_intr_test.83765277 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.312113194 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2611187454 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2735848863 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1658213519 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2671046970 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.223773883 |
| /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4288805137 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1510858164 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.189538696 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4242107293 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.331163965 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2748097193 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1709283703 |
| /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3733601146 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1943643539 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3533938807 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2921263334 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3795024452 |
| /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1358754808 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1606210347 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2910879319 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2717389829 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2196292295 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.328163592 |
| /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3913728645 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2349896238 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1853332695 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.139064498 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.505525032 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2581344377 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2331576331 |
| /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2574174445 |
| /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2602322186 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.724896308 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.42360696 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.945039602 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2511109603 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1748721697 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3574392186 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4197239681 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1082451117 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3893773365 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3702875765 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2231136690 |
| /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2083658373 |
| /workspace/coverage/cover_reg_top/44.usbdev_intr_test.515503338 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1699252062 |
| /workspace/coverage/cover_reg_top/46.usbdev_intr_test.691642029 |
| /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3946139361 |
| /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4061217488 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4039455 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2709832750 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.445174571 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1516475662 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1468788771 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.272241457 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1746725031 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4026547633 |
| /workspace/coverage/cover_reg_top/6.usbdev_intr_test.604124474 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4288415965 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.476094287 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2799434039 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.142146909 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3380097023 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1023033362 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.830271122 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3446186979 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.882016174 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2604887753 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2172657478 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4188518136 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3162413185 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2528389297 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.810951418 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2397082031 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2081650584 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4223530090 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3963758333 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3698832094 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4051662946 | May 28 01:09:24 PM PDT 24 | May 28 01:09:31 PM PDT 24 | 86974548 ps | ||
| T2 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3446186979 | May 28 01:09:11 PM PDT 24 | May 28 01:09:20 PM PDT 24 | 127719401 ps | ||
| T3 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2081650584 | May 28 01:09:09 PM PDT 24 | May 28 01:09:15 PM PDT 24 | 50600016 ps | ||
| T6 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.44996326 | May 28 01:09:14 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 268239794 ps | ||
| T15 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4242107293 | May 28 01:09:03 PM PDT 24 | May 28 01:09:07 PM PDT 24 | 55473694 ps | ||
| T7 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1358754808 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 35748673 ps | ||
| T16 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2765135947 | May 28 01:09:21 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 62219306 ps | ||
| T8 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3628975344 | May 28 01:09:22 PM PDT 24 | May 28 01:09:31 PM PDT 24 | 44694362 ps | ||
| T4 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.81491927 | May 28 01:09:08 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 1254272026 ps | ||
| T18 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4009174191 | May 28 01:09:33 PM PDT 24 | May 28 01:09:37 PM PDT 24 | 39226970 ps | ||
| T9 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3124981764 | May 28 01:09:07 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 1217283164 ps | ||
| T5 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2019715947 | May 28 01:09:31 PM PDT 24 | May 28 01:09:37 PM PDT 24 | 103486375 ps | ||
| T13 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2202996057 | May 28 01:09:13 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 582332043 ps | ||
| T17 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2083658373 | May 28 01:09:26 PM PDT 24 | May 28 01:09:32 PM PDT 24 | 34002989 ps | ||
| T36 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4080495807 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 36658681 ps | ||
| T37 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4116820270 | May 28 01:09:02 PM PDT 24 | May 28 01:09:06 PM PDT 24 | 39256089 ps | ||
| T38 | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.139064498 | May 28 01:09:34 PM PDT 24 | May 28 01:09:39 PM PDT 24 | 54223054 ps | ||
| T45 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.777874881 | May 28 01:09:12 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 170701914 ps | ||
| T31 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3533938807 | May 28 01:09:08 PM PDT 24 | May 28 01:09:24 PM PDT 24 | 1665681350 ps | ||
| T19 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2560217085 | May 28 01:09:13 PM PDT 24 | May 28 01:09:24 PM PDT 24 | 212530739 ps | ||
| T59 | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4188518136 | May 28 01:09:14 PM PDT 24 | May 28 01:09:28 PM PDT 24 | 46845414 ps | ||
| T56 | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1783279907 | May 28 01:09:07 PM PDT 24 | May 28 01:09:14 PM PDT 24 | 101255886 ps | ||
| T20 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3283753049 | May 28 01:09:09 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 102706914 ps | ||
| T32 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3997000618 | May 28 01:09:23 PM PDT 24 | May 28 01:09:31 PM PDT 24 | 49739316 ps | ||
| T26 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1498894160 | May 28 01:09:02 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 1789561480 ps | ||
| T33 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2212122283 | May 28 01:09:07 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 55044361 ps | ||
| T66 | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.505525032 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 92220197 ps | ||
| T34 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.224751276 | May 28 01:09:21 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 54720114 ps | ||
| T64 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3946139361 | May 28 01:09:26 PM PDT 24 | May 28 01:09:33 PM PDT 24 | 78804114 ps | ||
| T10 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3252614777 | May 28 01:09:16 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 81358338 ps | ||
| T60 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4288805137 | May 28 01:09:09 PM PDT 24 | May 28 01:09:16 PM PDT 24 | 43612854 ps | ||
| T80 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2588984990 | May 28 01:09:10 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 47633517 ps | ||
| T21 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.476094287 | May 28 01:09:16 PM PDT 24 | May 28 01:09:28 PM PDT 24 | 325892184 ps | ||
| T57 | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2349896238 | May 28 01:09:21 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 41627909 ps | ||
| T22 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2611187454 | May 28 01:09:19 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 100184761 ps | ||
| T27 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2318884322 | May 28 01:09:15 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 718751039 ps | ||
| T28 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3916821550 | May 28 01:09:12 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 243020389 ps | ||
| T65 | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.515503338 | May 28 01:09:27 PM PDT 24 | May 28 01:09:33 PM PDT 24 | 51819160 ps | ||
| T23 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3574392186 | May 28 01:09:22 PM PDT 24 | May 28 01:09:30 PM PDT 24 | 134909430 ps | ||
| T69 | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.189538696 | May 28 01:09:15 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 64219392 ps | ||
| T29 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.333571643 | May 28 01:09:26 PM PDT 24 | May 28 01:09:35 PM PDT 24 | 1032531773 ps | ||
| T62 | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3702875765 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 34216086 ps | ||
| T35 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3390727759 | May 28 01:09:16 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 160128489 ps | ||
| T30 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1579991771 | May 28 01:09:03 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 798479631 ps | ||
| T24 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2054870815 | May 28 01:09:28 PM PDT 24 | May 28 01:09:34 PM PDT 24 | 134468415 ps | ||
| T25 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2397082031 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 98713496 ps | ||
| T46 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.75831868 | May 28 01:09:11 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 156088570 ps | ||
| T50 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1658213519 | May 28 01:08:58 PM PDT 24 | May 28 01:09:04 PM PDT 24 | 253002342 ps | ||
| T58 | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1510858164 | May 28 01:09:01 PM PDT 24 | May 28 01:09:05 PM PDT 24 | 43328674 ps | ||
| T52 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.954146612 | May 28 01:09:15 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 687737452 ps | ||
| T63 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.604124474 | May 28 01:09:06 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 61340677 ps | ||
| T79 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2600931951 | May 28 01:09:19 PM PDT 24 | May 28 01:09:30 PM PDT 24 | 494041172 ps | ||
| T70 | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2581344377 | May 28 01:09:28 PM PDT 24 | May 28 01:09:34 PM PDT 24 | 52611147 ps | ||
| T81 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2921263334 | May 28 01:09:08 PM PDT 24 | May 28 01:09:16 PM PDT 24 | 96364152 ps | ||
| T82 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3341446895 | May 28 01:09:06 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 66519138 ps | ||
| T67 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.331163965 | May 28 01:09:30 PM PDT 24 | May 28 01:09:35 PM PDT 24 | 90810977 ps | ||
| T49 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.316696929 | May 28 01:09:07 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 1121936893 ps | ||
| T83 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2004954660 | May 28 01:09:05 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 399076584 ps | ||
| T68 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.697063276 | May 28 01:09:10 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 37052865 ps | ||
| T84 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3250578241 | May 28 01:09:06 PM PDT 24 | May 28 01:09:13 PM PDT 24 | 167444751 ps | ||
| T39 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.637401995 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 58331239 ps | ||
| T61 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4039455 | May 28 01:09:19 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 45506961 ps | ||
| T47 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.772101303 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 106092874 ps | ||
| T85 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1819242460 | May 28 01:09:07 PM PDT 24 | May 28 01:09:13 PM PDT 24 | 153067836 ps | ||
| T72 | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1516475662 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 55906725 ps | ||
| T48 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3452544370 | May 28 01:09:11 PM PDT 24 | May 28 01:09:20 PM PDT 24 | 64349287 ps | ||
| T86 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1681468115 | May 28 01:09:08 PM PDT 24 | May 28 01:09:15 PM PDT 24 | 109010488 ps | ||
| T53 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.882016174 | May 28 01:09:27 PM PDT 24 | May 28 01:09:37 PM PDT 24 | 737981234 ps | ||
| T87 | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1748721697 | May 28 01:09:13 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 33498291 ps | ||
| T40 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4075168776 | May 28 01:08:49 PM PDT 24 | May 28 01:08:53 PM PDT 24 | 170131029 ps | ||
| T54 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2377215279 | May 28 01:08:52 PM PDT 24 | May 28 01:08:58 PM PDT 24 | 161540637 ps | ||
| T71 | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1709283703 | May 28 01:09:19 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 62308905 ps | ||
| T88 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.142146909 | May 28 01:09:11 PM PDT 24 | May 28 01:09:20 PM PDT 24 | 69451129 ps | ||
| T78 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.328163592 | May 28 01:09:10 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 1332148778 ps | ||
| T89 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1170651159 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 94479339 ps | ||
| T90 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2603739943 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 33050446 ps | ||
| T91 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3506414026 | May 28 01:09:15 PM PDT 24 | May 28 01:09:24 PM PDT 24 | 214919620 ps | ||
| T92 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3963758333 | May 28 01:09:16 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 233883014 ps | ||
| T55 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1877356449 | May 28 01:09:16 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 203044122 ps | ||
| T93 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3451175767 | May 28 01:09:17 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 182857966 ps | ||
| T94 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4236622130 | May 28 01:09:04 PM PDT 24 | May 28 01:09:10 PM PDT 24 | 115709796 ps | ||
| T95 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1082451117 | May 28 01:09:18 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 145757764 ps | ||
| T96 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1811888653 | May 28 01:09:00 PM PDT 24 | May 28 01:09:04 PM PDT 24 | 44995363 ps | ||
| T97 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3610262108 | May 28 01:09:11 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 207399725 ps | ||
| T41 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2172657478 | May 28 01:09:11 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 80641516 ps | ||
| T51 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3698832094 | May 28 01:09:09 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 180337600 ps | ||
| T98 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2854592327 | May 28 01:09:10 PM PDT 24 | May 28 01:09:20 PM PDT 24 | 469434393 ps | ||
| T75 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4186158924 | May 28 01:09:04 PM PDT 24 | May 28 01:09:13 PM PDT 24 | 1645397141 ps | ||
| T99 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1375467434 | May 28 01:09:11 PM PDT 24 | May 28 01:09:20 PM PDT 24 | 74751407 ps | ||
| T42 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1943643539 | May 28 01:09:03 PM PDT 24 | May 28 01:09:10 PM PDT 24 | 124204375 ps | ||
| T100 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2531190353 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 171947462 ps | ||
| T43 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2003365672 | May 28 01:09:27 PM PDT 24 | May 28 01:09:33 PM PDT 24 | 99246197 ps | ||
| T101 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2709832750 | May 28 01:09:16 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 329798134 ps | ||
| T102 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3572790445 | May 28 01:09:12 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 229887669 ps | ||
| T103 | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2100170510 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 71928075 ps | ||
| T104 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3380097023 | May 28 01:09:03 PM PDT 24 | May 28 01:09:08 PM PDT 24 | 66363778 ps | ||
| T105 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2511109603 | May 28 01:09:15 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 124981980 ps | ||
| T106 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2910879319 | May 28 01:09:03 PM PDT 24 | May 28 01:09:09 PM PDT 24 | 98511694 ps | ||
| T107 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.479130453 | May 28 01:09:08 PM PDT 24 | May 28 01:09:15 PM PDT 24 | 108088049 ps | ||
| T108 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4169094205 | May 28 01:08:59 PM PDT 24 | May 28 01:09:04 PM PDT 24 | 86057812 ps | ||
| T44 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3795024452 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 79682449 ps | ||
| T11 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.893317339 | May 28 01:08:52 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 77392238 ps | ||
| T109 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1823880255 | May 28 01:09:13 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 201878831 ps | ||
| T110 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4061217488 | May 28 01:09:13 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 64058606 ps | ||
| T111 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1309596954 | May 28 01:08:55 PM PDT 24 | May 28 01:08:59 PM PDT 24 | 41127697 ps | ||
| T112 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3162413185 | May 28 01:09:16 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 167199357 ps | ||
| T113 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4197239681 | May 28 01:09:04 PM PDT 24 | May 28 01:09:13 PM PDT 24 | 158515404 ps | ||
| T76 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1941247200 | May 28 01:09:15 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 1276119967 ps | ||
| T114 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2528389297 | May 28 01:09:04 PM PDT 24 | May 28 01:09:10 PM PDT 24 | 187767965 ps | ||
| T115 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4026547633 | May 28 01:09:08 PM PDT 24 | May 28 01:09:15 PM PDT 24 | 55233375 ps | ||
| T116 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1746725031 | May 28 01:09:05 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 166294846 ps | ||
| T117 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1936685831 | May 28 01:08:52 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 126579792 ps | ||
| T118 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.445174571 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 74755888 ps | ||
| T119 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1563159674 | May 28 01:08:50 PM PDT 24 | May 28 01:08:52 PM PDT 24 | 79221971 ps | ||
| T120 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3868635029 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 137160884 ps | ||
| T121 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2602322186 | May 28 01:09:21 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 42448511 ps | ||
| T122 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.691642029 | May 28 01:09:26 PM PDT 24 | May 28 01:09:32 PM PDT 24 | 42515550 ps | ||
| T123 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2640185137 | May 28 01:08:51 PM PDT 24 | May 28 01:08:56 PM PDT 24 | 96807098 ps | ||
| T124 | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1744259876 | May 28 01:09:21 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 71286741 ps | ||
| T125 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3733601146 | May 28 01:09:36 PM PDT 24 | May 28 01:09:40 PM PDT 24 | 51586775 ps | ||
| T126 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.312113194 | May 28 01:09:01 PM PDT 24 | May 28 01:09:07 PM PDT 24 | 175552912 ps | ||
| T127 | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1974203262 | May 28 01:09:15 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 43896345 ps | ||
| T128 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2735848863 | May 28 01:09:05 PM PDT 24 | May 28 01:09:12 PM PDT 24 | 214681472 ps | ||
| T129 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.724896308 | May 28 01:09:03 PM PDT 24 | May 28 01:09:11 PM PDT 24 | 309558764 ps | ||
| T130 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.147480028 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 205048677 ps | ||
| T131 | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2748097193 | May 28 01:09:28 PM PDT 24 | May 28 01:09:34 PM PDT 24 | 71362933 ps | ||
| T132 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1265199562 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 143678748 ps | ||
| T133 | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1699252062 | May 28 01:09:22 PM PDT 24 | May 28 01:09:30 PM PDT 24 | 48317310 ps | ||
| T134 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2302366762 | May 28 01:09:15 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 335091086 ps | ||
| T135 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1842357180 | May 28 01:09:10 PM PDT 24 | May 28 01:09:18 PM PDT 24 | 39134454 ps | ||
| T73 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3859088063 | May 28 01:09:23 PM PDT 24 | May 28 01:09:35 PM PDT 24 | 995006296 ps | ||
| T136 | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1853332695 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 33965697 ps | ||
| T137 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2799434039 | May 28 01:09:18 PM PDT 24 | May 28 01:09:29 PM PDT 24 | 972724663 ps | ||
| T138 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2952223595 | May 28 01:08:52 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 136487698 ps | ||
| T139 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3744069715 | May 28 01:08:52 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 121662213 ps | ||
| T140 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4288415965 | May 28 01:09:09 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 78678679 ps | ||
| T141 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.830271122 | May 28 01:09:13 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 122943582 ps | ||
| T142 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.392273649 | May 28 01:08:55 PM PDT 24 | May 28 01:09:01 PM PDT 24 | 362265750 ps | ||
| T14 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.945039602 | May 28 01:09:15 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 64851008 ps | ||
| T143 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1579998729 | May 28 01:09:15 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 268431277 ps | ||
| T144 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2577539203 | May 28 01:09:16 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 79544325 ps | ||
| T145 | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.223773883 | May 28 01:09:24 PM PDT 24 | May 28 01:09:31 PM PDT 24 | 79155833 ps | ||
| T146 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.83765277 | May 28 01:09:09 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 43046600 ps | ||
| T147 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.107736473 | May 28 01:09:10 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 93749018 ps | ||
| T148 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2247428761 | May 28 01:09:08 PM PDT 24 | May 28 01:09:16 PM PDT 24 | 125281897 ps | ||
| T149 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2671046970 | May 28 01:08:50 PM PDT 24 | May 28 01:08:55 PM PDT 24 | 864081933 ps | ||
| T150 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1945971210 | May 28 01:09:13 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 81018670 ps | ||
| T151 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2604887753 | May 28 01:09:03 PM PDT 24 | May 28 01:09:10 PM PDT 24 | 103660417 ps | ||
| T152 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.308683885 | May 28 01:09:06 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 997187657 ps | ||
| T153 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4223530090 | May 28 01:09:17 PM PDT 24 | May 28 01:09:26 PM PDT 24 | 40709453 ps | ||
| T154 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2430399847 | May 28 01:09:18 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 187061024 ps | ||
| T155 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2196292295 | May 28 01:09:11 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 166071887 ps | ||
| T156 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3913728645 | May 28 01:09:32 PM PDT 24 | May 28 01:09:36 PM PDT 24 | 46978017 ps | ||
| T157 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4176338402 | May 28 01:09:16 PM PDT 24 | May 28 01:09:28 PM PDT 24 | 284138162 ps | ||
| T158 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2717389829 | May 28 01:09:09 PM PDT 24 | May 28 01:09:17 PM PDT 24 | 270379347 ps | ||
| T159 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.272241457 | May 28 01:09:22 PM PDT 24 | May 28 01:09:31 PM PDT 24 | 59308164 ps | ||
| T160 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.418500820 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 82811903 ps | ||
| T161 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.356430429 | May 28 01:08:59 PM PDT 24 | May 28 01:09:08 PM PDT 24 | 1173155094 ps | ||
| T162 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1601957976 | May 28 01:08:58 PM PDT 24 | May 28 01:09:03 PM PDT 24 | 68359986 ps | ||
| T163 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1496954901 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 111748430 ps | ||
| T164 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1575140026 | May 28 01:09:10 PM PDT 24 | May 28 01:09:19 PM PDT 24 | 41417161 ps | ||
| T165 | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2331576331 | May 28 01:09:27 PM PDT 24 | May 28 01:09:33 PM PDT 24 | 43296143 ps | ||
| T166 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.42360696 | May 28 01:09:12 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 467331539 ps | ||
| T74 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3893773365 | May 28 01:09:11 PM PDT 24 | May 28 01:09:21 PM PDT 24 | 398920746 ps | ||
| T167 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1557324689 | May 28 01:08:59 PM PDT 24 | May 28 01:09:06 PM PDT 24 | 303344376 ps | ||
| T168 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2574174445 | May 28 01:09:37 PM PDT 24 | May 28 01:09:41 PM PDT 24 | 37930165 ps | ||
| T169 | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1023033362 | May 28 01:09:14 PM PDT 24 | May 28 01:09:23 PM PDT 24 | 47953505 ps | ||
| T170 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1606210347 | May 28 01:09:03 PM PDT 24 | May 28 01:09:09 PM PDT 24 | 81680959 ps | ||
| T77 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.810951418 | May 28 01:09:14 PM PDT 24 | May 28 01:09:27 PM PDT 24 | 714967375 ps | ||
| T171 | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2231136690 | May 28 01:09:23 PM PDT 24 | May 28 01:09:31 PM PDT 24 | 30534117 ps | ||
| T172 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1468788771 | May 28 01:09:12 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 246265412 ps | ||
| T173 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2997435749 | May 28 01:09:14 PM PDT 24 | May 28 01:09:24 PM PDT 24 | 227953088 ps | ||
| T174 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2933927744 | May 28 01:09:13 PM PDT 24 | May 28 01:09:22 PM PDT 24 | 42902614 ps | ||
| T175 | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3329615686 | May 28 01:09:16 PM PDT 24 | May 28 01:09:25 PM PDT 24 | 100191498 ps | ||
| T12 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4259619905 | May 28 01:08:53 PM PDT 24 | May 28 01:08:57 PM PDT 24 | 53350610 ps |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.81491927 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 1254272026 ps |
| CPU time | 3.86 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 204496 kb |
| Host | smart-34dabe94-e21f-4d80-9043-1ead610a8f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=81491927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.81491927 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2765135947 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 62219306 ps |
| CPU time | 0.71 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204132 kb |
| Host | smart-4177631a-a8d5-4b7d-9c52-9335bed6d6e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2765135947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2765135947 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4051662946 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 86974548 ps |
| CPU time | 0.95 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:09:31 PM PDT 24 |
| Peak memory | 204200 kb |
| Host | smart-b086c6b3-7ab7-4ab4-80f0-90c49b3bc9f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4051662946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4051662946 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2560217085 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 212530739 ps |
| CPU time | 2.48 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:24 PM PDT 24 |
| Peak memory | 220216 kb |
| Host | smart-b48d7cda-9a42-4147-a9e8-826ee4216265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2560217085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2560217085 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1783279907 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 101255886 ps |
| CPU time | 0.73 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:14 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-e48bdd55-9550-460e-8ff4-b5bbbb02a2e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1783279907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1783279907 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3252614777 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 81358338 ps |
| CPU time | 0.86 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204268 kb |
| Host | smart-62a0fe7d-ce77-4fcb-8124-640bd64af3ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3252614777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3252614777 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.697063276 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 37052865 ps |
| CPU time | 0.61 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 204116 kb |
| Host | smart-19cc464b-3ce1-4572-a0f8-bffe5044b18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=697063276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.697063276 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2588984990 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 47633517 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 204152 kb |
| Host | smart-cc8ce94a-603e-4676-bbbc-8d9f7754be5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2588984990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2588984990 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2318884322 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 718751039 ps |
| CPU time | 4.62 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-f7369fce-f1bc-4182-a849-961c26fbbb7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2318884322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2318884322 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1309596954 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 41127697 ps |
| CPU time | 0.63 seconds |
| Started | May 28 01:08:55 PM PDT 24 |
| Finished | May 28 01:08:59 PM PDT 24 |
| Peak memory | 204160 kb |
| Host | smart-1c78a11a-19dc-411b-8c62-4f8b6dfa90a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1309596954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1309596954 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3628975344 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 44694362 ps |
| CPU time | 0.95 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:31 PM PDT 24 |
| Peak memory | 204504 kb |
| Host | smart-3946912d-a163-4bec-9b21-6421e3831900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3628975344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3628975344 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4009174191 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 39226970 ps |
| CPU time | 0.64 seconds |
| Started | May 28 01:09:33 PM PDT 24 |
| Finished | May 28 01:09:37 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-70fadb24-1ad8-4023-9899-890227e9f2c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4009174191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4009174191 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4186158924 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1645397141 ps |
| CPU time | 5.65 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:13 PM PDT 24 |
| Peak memory | 204480 kb |
| Host | smart-654ca33b-d885-4e6d-8eb1-b5dab14304f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4186158924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.4186158924 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1498894160 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1789561480 ps |
| CPU time | 6.5 seconds |
| Started | May 28 01:09:02 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-53461996-6b9f-4905-967f-0c436b0b2e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1498894160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1498894160 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1823880255 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 201878831 ps |
| CPU time | 2.14 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204480 kb |
| Host | smart-68c029c5-9515-4585-8d86-70b8d90a1e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1823880255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1823880255 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.954146612 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 687737452 ps |
| CPU time | 3.28 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204424 kb |
| Host | smart-8cde9a0e-3e17-481e-b096-a834ca900b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=954146612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.954146612 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3283753049 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 102706914 ps |
| CPU time | 2.37 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 204372 kb |
| Host | smart-e96e48c3-5844-45a1-a989-861d3f18f7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3283753049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3283753049 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4075168776 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 170131029 ps |
| CPU time | 2.12 seconds |
| Started | May 28 01:08:49 PM PDT 24 |
| Finished | May 28 01:08:53 PM PDT 24 |
| Peak memory | 204384 kb |
| Host | smart-ad57de4b-4dbc-4043-a70f-5c3e2c6ec015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4075168776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4075168776 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.356430429 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 1173155094 ps |
| CPU time | 5.07 seconds |
| Started | May 28 01:08:59 PM PDT 24 |
| Finished | May 28 01:09:08 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-92077003-20d4-4048-8b70-d6da9f0c9fe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=356430429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.356430429 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4259619905 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 53350610 ps |
| CPU time | 0.8 seconds |
| Started | May 28 01:08:53 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 204208 kb |
| Host | smart-15910da2-242b-496c-b7fe-78a21e53759f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4259619905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.4259619905 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2377215279 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 161540637 ps |
| CPU time | 1.76 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:08:58 PM PDT 24 |
| Peak memory | 212696 kb |
| Host | smart-3f0db47e-92b5-4269-8600-51f41473e632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377215279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.2377215279 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1811888653 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 44995363 ps |
| CPU time | 0.78 seconds |
| Started | May 28 01:09:00 PM PDT 24 |
| Finished | May 28 01:09:04 PM PDT 24 |
| Peak memory | 204248 kb |
| Host | smart-2c1cb562-7d33-4192-bf76-a6dba10067d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1811888653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1811888653 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1601957976 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 68359986 ps |
| CPU time | 2.25 seconds |
| Started | May 28 01:08:58 PM PDT 24 |
| Finished | May 28 01:09:03 PM PDT 24 |
| Peak memory | 212624 kb |
| Host | smart-6ec77876-af1c-4757-980d-6c5a8c931a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1601957976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1601957976 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2004954660 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 399076584 ps |
| CPU time | 2.72 seconds |
| Started | May 28 01:09:05 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204420 kb |
| Host | smart-5ccdfa27-ed57-4d75-a38a-7731dc9ce0e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2004954660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2004954660 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2247428761 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 125281897 ps |
| CPU time | 1.48 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:16 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-9b1a8b9a-c380-455f-a73e-70951aaaad86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2247428761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2247428761 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2640185137 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 96807098 ps |
| CPU time | 2.14 seconds |
| Started | May 28 01:08:51 PM PDT 24 |
| Finished | May 28 01:08:56 PM PDT 24 |
| Peak memory | 212700 kb |
| Host | smart-6ca988e2-981a-4ca7-b7b5-43ba496cf79b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2640185137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2640185137 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1557324689 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 303344376 ps |
| CPU time | 3.5 seconds |
| Started | May 28 01:08:59 PM PDT 24 |
| Finished | May 28 01:09:06 PM PDT 24 |
| Peak memory | 204456 kb |
| Host | smart-8993c3ec-700a-470e-821c-e3574e85008c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1557324689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1557324689 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.308683885 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 997187657 ps |
| CPU time | 6.62 seconds |
| Started | May 28 01:09:06 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204476 kb |
| Host | smart-2ffd2e6a-3d8a-445b-a2e4-73735ca9a6ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=308683885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.308683885 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.893317339 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 77392238 ps |
| CPU time | 0.92 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 204244 kb |
| Host | smart-ed470432-7fb1-4383-85e9-e90f5610fd29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=893317339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.893317339 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.4169094205 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 86057812 ps |
| CPU time | 1.94 seconds |
| Started | May 28 01:08:59 PM PDT 24 |
| Finished | May 28 01:09:04 PM PDT 24 |
| Peak memory | 212608 kb |
| Host | smart-12c2bd47-b5f1-45aa-9b23-a707a14c68ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169094205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.4169094205 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1563159674 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 79221971 ps |
| CPU time | 0.87 seconds |
| Started | May 28 01:08:50 PM PDT 24 |
| Finished | May 28 01:08:52 PM PDT 24 |
| Peak memory | 204260 kb |
| Host | smart-56eca34d-6794-4a71-937d-760665edaf7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1563159674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1563159674 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2952223595 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 136487698 ps |
| CPU time | 1.44 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 204496 kb |
| Host | smart-705dd153-02c4-47d3-a5e7-5d2e6bde95a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2952223595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2952223595 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.392273649 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 362265750 ps |
| CPU time | 2.63 seconds |
| Started | May 28 01:08:55 PM PDT 24 |
| Finished | May 28 01:09:01 PM PDT 24 |
| Peak memory | 204344 kb |
| Host | smart-7218da46-4800-4310-a88c-4b9cc4fd1b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=392273649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.392273649 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3744069715 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 121662213 ps |
| CPU time | 1.07 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-e91a27ab-6410-4d84-bdd8-ab4d11d34a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3744069715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3744069715 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1936685831 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 126579792 ps |
| CPU time | 1.61 seconds |
| Started | May 28 01:08:52 PM PDT 24 |
| Finished | May 28 01:08:57 PM PDT 24 |
| Peak memory | 204364 kb |
| Host | smart-35d83176-3c02-4e13-a870-29fd6ef8fd51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1936685831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1936685831 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1579991771 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 798479631 ps |
| CPU time | 5.14 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-f648b4b1-f62c-4790-bee6-7b1f03f44a12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1579991771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1579991771 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1819242460 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 153067836 ps |
| CPU time | 1.73 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:13 PM PDT 24 |
| Peak memory | 212820 kb |
| Host | smart-884a5459-7ac2-43b1-95ad-858b0388533d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819242460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd ev_csr_mem_rw_with_rand_reset.1819242460 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2577539203 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 79544325 ps |
| CPU time | 1.08 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204556 kb |
| Host | smart-827e9953-b549-4cbc-8e03-e01c2086ec3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2577539203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2577539203 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4080495807 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 36658681 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204076 kb |
| Host | smart-8fb15f16-94e9-4a36-9c11-356d85be0bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4080495807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4080495807 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3997000618 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 49739316 ps |
| CPU time | 1.11 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:31 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-023d855d-d125-433c-ba0e-dc396747dab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3997000618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3997000618 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2054870815 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 134468415 ps |
| CPU time | 1.53 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:09:34 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-9aad0983-f2e4-4dcc-bb41-6e0e628f252f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2054870815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2054870815 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3451175767 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 182857966 ps |
| CPU time | 2.05 seconds |
| Started | May 28 01:09:17 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 220880 kb |
| Host | smart-25fb45ef-816d-471a-8460-15aa7d8bf37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451175767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.3451175767 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2212122283 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 55044361 ps |
| CPU time | 0.8 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204340 kb |
| Host | smart-3fb57306-c76b-470e-b204-66b0cf4f9465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2212122283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2212122283 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4116820270 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 39256089 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:02 PM PDT 24 |
| Finished | May 28 01:09:06 PM PDT 24 |
| Peak memory | 204176 kb |
| Host | smart-6ce4c2da-4f12-4208-bcf9-595964e2e50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4116820270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4116820270 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.75831868 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 156088570 ps |
| CPU time | 1.19 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-ad127e27-111a-4876-8089-fdeae247957a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=75831868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.75831868 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3572790445 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 229887669 ps |
| CPU time | 2.69 seconds |
| Started | May 28 01:09:12 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 220100 kb |
| Host | smart-d483befb-3d62-4e46-afbc-5342c13dbb1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3572790445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3572790445 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2854592327 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 469434393 ps |
| CPU time | 2.63 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:20 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-c383fe05-79a1-4684-8d02-bb8b3c4e1fb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2854592327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2854592327 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2019715947 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 103486375 ps |
| CPU time | 1.96 seconds |
| Started | May 28 01:09:31 PM PDT 24 |
| Finished | May 28 01:09:37 PM PDT 24 |
| Peak memory | 212788 kb |
| Host | smart-df656bbc-b675-4b4a-8643-c302fbcd4465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019715947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd ev_csr_mem_rw_with_rand_reset.2019715947 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.772101303 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 106092874 ps |
| CPU time | 1 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204448 kb |
| Host | smart-46436a40-442c-4f81-9b39-a891313a244f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=772101303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.772101303 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2100170510 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 71928075 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-fb568f47-8ca4-4b3e-97ae-a9b968379008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2100170510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2100170510 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.147480028 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 205048677 ps |
| CPU time | 1.66 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-cfa8ea28-91cc-4df3-9d63-249f8f7ad8db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=147480028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.147480028 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1945971210 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 81018670 ps |
| CPU time | 1.66 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 212632 kb |
| Host | smart-1f3b568f-f54d-4f7f-ab49-0ded97a5afda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945971210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.1945971210 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1842357180 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 39134454 ps |
| CPU time | 0.77 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 204144 kb |
| Host | smart-bd30e161-3a57-47ab-999b-435c71796763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1842357180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1842357180 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2603739943 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 33050446 ps |
| CPU time | 0.62 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204096 kb |
| Host | smart-8e2f5e01-9352-4611-98f6-a9ce8fa66884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2603739943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2603739943 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.418500820 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 82811903 ps |
| CPU time | 1.13 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 204424 kb |
| Host | smart-52fbccf6-969a-4426-8534-19e7413f4e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=418500820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.418500820 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3341446895 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 66519138 ps |
| CPU time | 1.43 seconds |
| Started | May 28 01:09:06 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-60828a34-0b66-4305-a4d4-08d5b1d94e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3341446895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3341446895 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.316696929 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1121936893 ps |
| CPU time | 5.07 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-3fcdab1e-36af-44b6-8505-48c6e28798e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=316696929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.316696929 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1170651159 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 94479339 ps |
| CPU time | 1.96 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 212720 kb |
| Host | smart-b265be61-4a07-4292-99aa-c275e2f3a93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170651159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.1170651159 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1744259876 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 71286741 ps |
| CPU time | 0.89 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204256 kb |
| Host | smart-1badc2f6-9794-41d6-bba7-371c573c26be |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1744259876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1744259876 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1575140026 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 41417161 ps |
| CPU time | 0.66 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-5f8693c3-4c18-412c-b495-47129495deb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1575140026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1575140026 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3506414026 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 214919620 ps |
| CPU time | 1.69 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:24 PM PDT 24 |
| Peak memory | 204452 kb |
| Host | smart-5ffed131-4106-461e-908b-72beaed63990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3506414026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3506414026 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1375467434 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 74751407 ps |
| CPU time | 1.83 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:20 PM PDT 24 |
| Peak memory | 204524 kb |
| Host | smart-2b20c76e-f4c5-4a6d-bb4d-a656785dd905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1375467434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1375467434 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2202996057 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 582332043 ps |
| CPU time | 3.89 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-4210fe42-82f2-4733-a7d9-6f99d28a9f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2202996057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2202996057 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3868635029 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 137160884 ps |
| CPU time | 1.29 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 212648 kb |
| Host | smart-07bbb83b-8135-4c06-a3fd-14a51d371b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868635029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.3868635029 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.107736473 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 93749018 ps |
| CPU time | 0.82 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 204168 kb |
| Host | smart-14ddd797-fef7-4cbf-8e55-25bc587fdb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=107736473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.107736473 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3610262108 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 207399725 ps |
| CPU time | 1.74 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-328c42d6-9e6e-4c30-a856-9f7678b4b55f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3610262108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3610262108 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.4176338402 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 284138162 ps |
| CPU time | 2.96 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:28 PM PDT 24 |
| Peak memory | 204464 kb |
| Host | smart-6d87229e-8994-4f3c-b07e-a19d2482f13a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4176338402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.4176338402 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.333571643 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1032531773 ps |
| CPU time | 2.86 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:09:35 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-9ea2fd3f-a6cd-459a-a49f-84fa2a75bc19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=333571643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.333571643 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2531190353 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 171947462 ps |
| CPU time | 1.32 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 212712 kb |
| Host | smart-ebe436ca-be07-4b17-ba70-4a34d9c86fbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531190353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.2531190353 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3329615686 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 100191498 ps |
| CPU time | 1.04 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204480 kb |
| Host | smart-c4b418ae-a427-4e2b-91e3-f53771d6dab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3329615686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3329615686 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1681468115 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 109010488 ps |
| CPU time | 0.78 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:15 PM PDT 24 |
| Peak memory | 204080 kb |
| Host | smart-783eded7-35a3-4c9e-959d-766daaecf8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1681468115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1681468115 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4236622130 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 115709796 ps |
| CPU time | 1.62 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:10 PM PDT 24 |
| Peak memory | 204380 kb |
| Host | smart-861958f4-d9df-47f4-aee6-1fdfc8351bdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4236622130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.4236622130 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2600931951 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 494041172 ps |
| CPU time | 2.54 seconds |
| Started | May 28 01:09:19 PM PDT 24 |
| Finished | May 28 01:09:30 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-84d4a84a-1109-46d4-aa06-30b3373697f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2600931951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2600931951 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1877356449 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 203044122 ps |
| CPU time | 1.72 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 212636 kb |
| Host | smart-7735d257-0dc0-440a-b26b-8392f5e34cc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877356449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.1877356449 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2003365672 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 99246197 ps |
| CPU time | 0.82 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:33 PM PDT 24 |
| Peak memory | 204160 kb |
| Host | smart-1dc9161f-e269-4663-ac17-5eca678ea273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2003365672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2003365672 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1496954901 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 111748430 ps |
| CPU time | 0.77 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-e4546c84-de89-48af-819d-315ae6c753a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1496954901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1496954901 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.777874881 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 170701914 ps |
| CPU time | 1.56 seconds |
| Started | May 28 01:09:12 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204452 kb |
| Host | smart-3d4119e5-2f11-43aa-82ac-a4eac2c2a316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=777874881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.777874881 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1579998729 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 268431277 ps |
| CPU time | 3.05 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 212612 kb |
| Host | smart-f6e120c5-7984-4588-9548-30f90780c663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1579998729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1579998729 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1941247200 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1276119967 ps |
| CPU time | 5.74 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-4b96e71a-a260-43d4-af39-2632bdb20b21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1941247200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1941247200 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2430399847 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 187061024 ps |
| CPU time | 1.48 seconds |
| Started | May 28 01:09:18 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 220848 kb |
| Host | smart-948fdb9d-1245-429e-8bff-ad25616a540f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430399847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.2430399847 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.224751276 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 54720114 ps |
| CPU time | 1.01 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204464 kb |
| Host | smart-f87532a9-c958-4aae-9937-4154c809cded |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=224751276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.224751276 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2933927744 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 42902614 ps |
| CPU time | 0.69 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204112 kb |
| Host | smart-0e5b6621-8b7d-482d-9905-a8f41e6397b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2933927744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2933927744 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3390727759 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 160128489 ps |
| CPU time | 1.37 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-889264fe-6b6e-44a5-bbd1-2ac064761ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3390727759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3390727759 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2302366762 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 335091086 ps |
| CPU time | 3.31 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-1cdb5632-4f12-4f43-829d-4aee9ca91621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2302366762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2302366762 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3859088063 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 995006296 ps |
| CPU time | 4.87 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:35 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-ce175f04-8883-44a4-82a7-1a9ab97b8641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3859088063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3859088063 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2997435749 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 227953088 ps |
| CPU time | 1.81 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:24 PM PDT 24 |
| Peak memory | 212736 kb |
| Host | smart-e77362aa-ac0c-4969-ae31-63e2129649cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997435749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.2997435749 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.637401995 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 58331239 ps |
| CPU time | 0.86 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204228 kb |
| Host | smart-945340d4-0c14-4ae1-b864-d8ea3b0a2ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=637401995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.637401995 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1974203262 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 43896345 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204116 kb |
| Host | smart-2c45650c-1692-41bf-8fdd-0ebaed5ad59b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1974203262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1974203262 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1265199562 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 143678748 ps |
| CPU time | 1.41 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-acac01e4-cb11-49fd-9099-e8b1b1b6d15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1265199562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1265199562 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.44996326 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 268239794 ps |
| CPU time | 2.89 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 220200 kb |
| Host | smart-be16e2aa-782c-482d-86a9-be33d5f97e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=44996326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.44996326 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3916821550 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 243020389 ps |
| CPU time | 2.38 seconds |
| Started | May 28 01:09:12 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-9935d574-ed50-467e-9e91-62ec80798c5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3916821550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3916821550 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3250578241 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 167444751 ps |
| CPU time | 2.15 seconds |
| Started | May 28 01:09:06 PM PDT 24 |
| Finished | May 28 01:09:13 PM PDT 24 |
| Peak memory | 204320 kb |
| Host | smart-7d38d97e-ebdd-4672-bdd2-27f09d43d8bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3250578241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3250578241 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3124981764 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1217283164 ps |
| CPU time | 9.73 seconds |
| Started | May 28 01:09:07 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 204436 kb |
| Host | smart-a1838327-eb40-4640-bc83-2895dc23dceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3124981764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3124981764 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.479130453 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 108088049 ps |
| CPU time | 1.5 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:15 PM PDT 24 |
| Peak memory | 212720 kb |
| Host | smart-c682929b-730d-4e08-860c-6b5796f2ffd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479130453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev _csr_mem_rw_with_rand_reset.479130453 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3452544370 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 64349287 ps |
| CPU time | 0.85 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:20 PM PDT 24 |
| Peak memory | 204144 kb |
| Host | smart-87feda15-cf71-4611-b605-6437443bfeba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3452544370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3452544370 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.83765277 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 43046600 ps |
| CPU time | 0.7 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 204104 kb |
| Host | smart-0cc008b7-ad99-41f0-b90b-c48af114e9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=83765277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.83765277 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.312113194 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 175552912 ps |
| CPU time | 1.45 seconds |
| Started | May 28 01:09:01 PM PDT 24 |
| Finished | May 28 01:09:07 PM PDT 24 |
| Peak memory | 212488 kb |
| Host | smart-8fa47f5a-3240-4ac8-89e9-1113c6d4543f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=312113194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.312113194 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2611187454 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 100184761 ps |
| CPU time | 2.2 seconds |
| Started | May 28 01:09:19 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204348 kb |
| Host | smart-af082f62-a1cd-4063-af32-e5cc39344ed6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2611187454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2611187454 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2735848863 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 214681472 ps |
| CPU time | 1.86 seconds |
| Started | May 28 01:09:05 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-710562cc-6a24-4a00-8366-498e978dbdab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2735848863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2735848863 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1658213519 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 253002342 ps |
| CPU time | 3.03 seconds |
| Started | May 28 01:08:58 PM PDT 24 |
| Finished | May 28 01:09:04 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-981f0c70-2d70-49e5-aee8-8a128fedc8d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1658213519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1658213519 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2671046970 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 864081933 ps |
| CPU time | 3.19 seconds |
| Started | May 28 01:08:50 PM PDT 24 |
| Finished | May 28 01:08:55 PM PDT 24 |
| Peak memory | 204432 kb |
| Host | smart-a1f8f533-11ac-47a1-848e-b62d05fec785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2671046970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2671046970 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.223773883 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 79155833 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:24 PM PDT 24 |
| Finished | May 28 01:09:31 PM PDT 24 |
| Peak memory | 204096 kb |
| Host | smart-0af56bdb-d22d-4025-a017-76a04291510a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=223773883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.223773883 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4288805137 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 43612854 ps |
| CPU time | 0.72 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:16 PM PDT 24 |
| Peak memory | 204112 kb |
| Host | smart-6c7ed42c-a123-4672-b007-aba5ed4dfec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4288805137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4288805137 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1510858164 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 43328674 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:01 PM PDT 24 |
| Finished | May 28 01:09:05 PM PDT 24 |
| Peak memory | 204176 kb |
| Host | smart-0936fa6c-fad8-441e-b8da-c08c2987abde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1510858164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1510858164 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.189538696 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 64219392 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204188 kb |
| Host | smart-1deeed7f-5556-4c61-b198-081054aee03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=189538696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.189538696 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4242107293 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 55473694 ps |
| CPU time | 0.69 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:07 PM PDT 24 |
| Peak memory | 204092 kb |
| Host | smart-46719a7b-0aa2-491f-afb0-953e122d4511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4242107293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4242107293 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.331163965 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 90810977 ps |
| CPU time | 0.7 seconds |
| Started | May 28 01:09:30 PM PDT 24 |
| Finished | May 28 01:09:35 PM PDT 24 |
| Peak memory | 204092 kb |
| Host | smart-8226bd9e-a6a0-448b-9f62-9991ae013499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=331163965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.331163965 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2748097193 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 71362933 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:09:34 PM PDT 24 |
| Peak memory | 204008 kb |
| Host | smart-03cc32bf-466f-478b-a44c-6cfa0a850eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2748097193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2748097193 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1709283703 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 62308905 ps |
| CPU time | 0.78 seconds |
| Started | May 28 01:09:19 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204068 kb |
| Host | smart-cb191f0b-d1c0-418d-ab00-ace70d49e1ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1709283703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1709283703 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3733601146 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 51586775 ps |
| CPU time | 0.77 seconds |
| Started | May 28 01:09:36 PM PDT 24 |
| Finished | May 28 01:09:40 PM PDT 24 |
| Peak memory | 204192 kb |
| Host | smart-40c714d3-6b76-44b2-a952-dbaa36b4fa14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3733601146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3733601146 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1943643539 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 124204375 ps |
| CPU time | 3.26 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:10 PM PDT 24 |
| Peak memory | 204336 kb |
| Host | smart-6c5fd1de-93ce-49d7-aa9a-66f497bcdeec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1943643539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1943643539 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3533938807 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1665681350 ps |
| CPU time | 9.28 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:24 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-bb89907c-a31f-4735-9edc-4e193d63672c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3533938807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3533938807 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2921263334 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 96364152 ps |
| CPU time | 1.34 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:16 PM PDT 24 |
| Peak memory | 212704 kb |
| Host | smart-24f05059-c21a-4a6b-9006-a01f13292e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921263334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.2921263334 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3795024452 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 79682449 ps |
| CPU time | 1.05 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:19 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-6466eca9-c627-42b3-bf54-772ef4dbd262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3795024452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3795024452 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1358754808 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 35748673 ps |
| CPU time | 0.69 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204192 kb |
| Host | smart-8a60daef-43ee-4cd3-8362-6dbe38cf6df9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1358754808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1358754808 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1606210347 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 81680959 ps |
| CPU time | 2.12 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:09 PM PDT 24 |
| Peak memory | 212612 kb |
| Host | smart-52e3f1bf-3e18-43a9-91dd-85bd3d36e88b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1606210347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1606210347 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2910879319 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 98511694 ps |
| CPU time | 2.43 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:09 PM PDT 24 |
| Peak memory | 204332 kb |
| Host | smart-9f625fa3-eada-4fdc-85ce-d0f311a0e553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2910879319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2910879319 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2717389829 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 270379347 ps |
| CPU time | 1.63 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-3d625a5d-acb9-4cfb-81fa-ff445ce3e192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2717389829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2717389829 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2196292295 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 166071887 ps |
| CPU time | 1.76 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 204436 kb |
| Host | smart-09316962-f0bf-49ef-bfeb-54b0a5933580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2196292295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2196292295 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.328163592 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1332148778 ps |
| CPU time | 5.41 seconds |
| Started | May 28 01:09:10 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204404 kb |
| Host | smart-1258aa32-7910-4e16-91ff-58658a75e10c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=328163592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.328163592 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3913728645 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 46978017 ps |
| CPU time | 0.66 seconds |
| Started | May 28 01:09:32 PM PDT 24 |
| Finished | May 28 01:09:36 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-1620194a-385f-4512-8e75-eb25399e6946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3913728645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3913728645 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2349896238 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 41627909 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204152 kb |
| Host | smart-dfddb733-12db-4001-8a6d-8d1cc550d7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2349896238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2349896238 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1853332695 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 33965697 ps |
| CPU time | 0.65 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204080 kb |
| Host | smart-0ab4f312-5ec0-4f97-a4ee-3bc49c3b5347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1853332695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1853332695 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.139064498 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 54223054 ps |
| CPU time | 0.76 seconds |
| Started | May 28 01:09:34 PM PDT 24 |
| Finished | May 28 01:09:39 PM PDT 24 |
| Peak memory | 204092 kb |
| Host | smart-ad32cf27-133f-477e-a1c9-4ba7254e0127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=139064498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.139064498 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.505525032 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 92220197 ps |
| CPU time | 0.73 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204084 kb |
| Host | smart-e86792a8-7bf0-41b4-8bd5-98083c3abded |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=505525032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.505525032 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2581344377 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 52611147 ps |
| CPU time | 0.69 seconds |
| Started | May 28 01:09:28 PM PDT 24 |
| Finished | May 28 01:09:34 PM PDT 24 |
| Peak memory | 204080 kb |
| Host | smart-a36abd26-8924-407e-9c5e-d571f004e694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2581344377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2581344377 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2331576331 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 43296143 ps |
| CPU time | 0.63 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:33 PM PDT 24 |
| Peak memory | 204096 kb |
| Host | smart-985253bf-a5bc-425c-b7ae-967834f25046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2331576331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2331576331 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2574174445 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 37930165 ps |
| CPU time | 0.69 seconds |
| Started | May 28 01:09:37 PM PDT 24 |
| Finished | May 28 01:09:41 PM PDT 24 |
| Peak memory | 204064 kb |
| Host | smart-fe055a52-85b3-44c7-8bb6-2b4ff8c5cc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2574174445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2574174445 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2602322186 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 42448511 ps |
| CPU time | 0.66 seconds |
| Started | May 28 01:09:21 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204156 kb |
| Host | smart-9e8469ae-0dd5-4683-b0eb-5ab66ab760cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2602322186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2602322186 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.724896308 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 309558764 ps |
| CPU time | 3.54 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:11 PM PDT 24 |
| Peak memory | 204428 kb |
| Host | smart-5ddda6ab-0bcf-427f-8d05-02e1d3f19c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=724896308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.724896308 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.42360696 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 467331539 ps |
| CPU time | 7.14 seconds |
| Started | May 28 01:09:12 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204452 kb |
| Host | smart-f33e07d7-b146-4b7e-9b4d-635aebc451e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=42360696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.42360696 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.945039602 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 64851008 ps |
| CPU time | 0.83 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204236 kb |
| Host | smart-39e17cf1-47b1-4597-9afd-995d110b7747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=945039602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.945039602 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2511109603 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 124981980 ps |
| CPU time | 2.35 seconds |
| Started | May 28 01:09:15 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 212868 kb |
| Host | smart-642c0ad7-dd6a-4f1e-841f-dd59c6c0125e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511109603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.2511109603 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1748721697 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 33498291 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204036 kb |
| Host | smart-4fa255fc-1ebc-4ef0-9cd6-821002b0d110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1748721697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1748721697 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3574392186 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 134909430 ps |
| CPU time | 1.44 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:30 PM PDT 24 |
| Peak memory | 212496 kb |
| Host | smart-f8abbf1d-f6ab-47a8-ba25-6aa6853d6a38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3574392186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3574392186 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4197239681 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 158515404 ps |
| CPU time | 4.01 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:13 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-3f096f65-2547-49d7-881e-e3e0224d08d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4197239681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4197239681 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1082451117 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 145757764 ps |
| CPU time | 1.46 seconds |
| Started | May 28 01:09:18 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204532 kb |
| Host | smart-ba054343-a09f-4b19-b487-c63cb70b4e02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1082451117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1082451117 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3893773365 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 398920746 ps |
| CPU time | 2.95 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 204480 kb |
| Host | smart-9cc43780-1129-4759-a299-b7fe877ac682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3893773365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3893773365 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3702875765 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 34216086 ps |
| CPU time | 0.66 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204072 kb |
| Host | smart-23473783-0094-47d2-90ba-ea5b666ecad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3702875765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3702875765 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2231136690 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 30534117 ps |
| CPU time | 0.64 seconds |
| Started | May 28 01:09:23 PM PDT 24 |
| Finished | May 28 01:09:31 PM PDT 24 |
| Peak memory | 204060 kb |
| Host | smart-12fa4971-07d0-42e7-8930-054eac0dd235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2231136690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2231136690 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2083658373 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 34002989 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:09:32 PM PDT 24 |
| Peak memory | 204092 kb |
| Host | smart-4b3f9ef4-a8ea-481b-b9ba-48477d56a133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2083658373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2083658373 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.515503338 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 51819160 ps |
| CPU time | 0.64 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:33 PM PDT 24 |
| Peak memory | 204168 kb |
| Host | smart-d0da0bdd-88b5-485b-b5bd-c067b70f2864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=515503338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.515503338 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1699252062 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 48317310 ps |
| CPU time | 0.72 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:30 PM PDT 24 |
| Peak memory | 204088 kb |
| Host | smart-d9cf8164-466e-4574-81ec-016967c46bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1699252062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1699252062 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.691642029 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 42515550 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:09:32 PM PDT 24 |
| Peak memory | 204104 kb |
| Host | smart-d245927f-016b-4611-9242-39befcf09b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=691642029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.691642029 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3946139361 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 78804114 ps |
| CPU time | 0.76 seconds |
| Started | May 28 01:09:26 PM PDT 24 |
| Finished | May 28 01:09:33 PM PDT 24 |
| Peak memory | 204088 kb |
| Host | smart-d62b38cf-147d-4d0e-a288-cdcb5e63aa12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3946139361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3946139361 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4061217488 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 64058606 ps |
| CPU time | 0.68 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204012 kb |
| Host | smart-aee9306c-ba35-4bbc-b397-c9c92d8b2943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4061217488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.4061217488 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.4039455 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 45506961 ps |
| CPU time | 0.65 seconds |
| Started | May 28 01:09:19 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204196 kb |
| Host | smart-d9227558-4f2d-499d-b8be-10f58901015b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4039455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.4039455 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2709832750 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 329798134 ps |
| CPU time | 1.94 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 212684 kb |
| Host | smart-60ebf417-80cd-4f66-b35f-e8c162290ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709832750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.2709832750 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.445174571 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 74755888 ps |
| CPU time | 1.03 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204444 kb |
| Host | smart-00d8a0c6-def2-40f3-b6e2-d45eec0ac891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=445174571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.445174571 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1516475662 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 55906725 ps |
| CPU time | 0.7 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:25 PM PDT 24 |
| Peak memory | 204108 kb |
| Host | smart-49ebee3c-8c0b-4098-b4e4-93634f87763d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1516475662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1516475662 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1468788771 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 246265412 ps |
| CPU time | 1.54 seconds |
| Started | May 28 01:09:12 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204452 kb |
| Host | smart-5f73082e-d981-4dfe-985b-5ffcbb9ff601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1468788771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1468788771 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.272241457 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 59308164 ps |
| CPU time | 1.59 seconds |
| Started | May 28 01:09:22 PM PDT 24 |
| Finished | May 28 01:09:31 PM PDT 24 |
| Peak memory | 204600 kb |
| Host | smart-6d1db496-ba76-42da-9d9d-98f2d59273b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=272241457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.272241457 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1746725031 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 166294846 ps |
| CPU time | 1.77 seconds |
| Started | May 28 01:09:05 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 212700 kb |
| Host | smart-4c6f10c9-fa26-42c4-9a96-c4af1987b55a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746725031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.1746725031 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4026547633 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 55233375 ps |
| CPU time | 0.81 seconds |
| Started | May 28 01:09:08 PM PDT 24 |
| Finished | May 28 01:09:15 PM PDT 24 |
| Peak memory | 204244 kb |
| Host | smart-389b83b4-376c-4a03-a2bc-de0b36e3eb1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4026547633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4026547633 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.604124474 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 61340677 ps |
| CPU time | 0.69 seconds |
| Started | May 28 01:09:06 PM PDT 24 |
| Finished | May 28 01:09:12 PM PDT 24 |
| Peak memory | 204100 kb |
| Host | smart-fb80c30f-6254-40dd-9c3a-d63ba9dbe71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=604124474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.604124474 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4288415965 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 78678679 ps |
| CPU time | 1.42 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:17 PM PDT 24 |
| Peak memory | 204456 kb |
| Host | smart-f69fafe4-66c6-40dc-9bbe-31557b202263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4288415965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4288415965 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.476094287 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 325892184 ps |
| CPU time | 3.46 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:28 PM PDT 24 |
| Peak memory | 220460 kb |
| Host | smart-53ef3e96-b4e8-493d-8fe1-fe43d31bcf75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=476094287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.476094287 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2799434039 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 972724663 ps |
| CPU time | 3.34 seconds |
| Started | May 28 01:09:18 PM PDT 24 |
| Finished | May 28 01:09:29 PM PDT 24 |
| Peak memory | 204440 kb |
| Host | smart-49a7fddf-532e-4ba8-aad6-cb3c01def09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2799434039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2799434039 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.142146909 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 69451129 ps |
| CPU time | 1.24 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:20 PM PDT 24 |
| Peak memory | 212684 kb |
| Host | smart-7ac32db3-c65b-4c82-ab3b-c7f953a12647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142146909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev _csr_mem_rw_with_rand_reset.142146909 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3380097023 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 66363778 ps |
| CPU time | 0.98 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:08 PM PDT 24 |
| Peak memory | 204452 kb |
| Host | smart-603f92c8-1162-431b-98f0-c54d1d0a4822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3380097023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3380097023 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.1023033362 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 47953505 ps |
| CPU time | 0.7 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 204196 kb |
| Host | smart-a01f773a-b54f-476c-b298-65ba826121f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1023033362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1023033362 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.830271122 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 122943582 ps |
| CPU time | 1.13 seconds |
| Started | May 28 01:09:13 PM PDT 24 |
| Finished | May 28 01:09:22 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-1cbfdd66-29bb-42ad-acd7-df5f21596bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=830271122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.830271122 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3446186979 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 127719401 ps |
| CPU time | 1.81 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:20 PM PDT 24 |
| Peak memory | 212736 kb |
| Host | smart-aef353ba-2fa8-4d1f-b358-be44122f1626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3446186979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3446186979 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.882016174 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 737981234 ps |
| CPU time | 4.85 seconds |
| Started | May 28 01:09:27 PM PDT 24 |
| Finished | May 28 01:09:37 PM PDT 24 |
| Peak memory | 204416 kb |
| Host | smart-c57da96d-fa7f-40ca-bb4a-06ad3899baa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=882016174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.882016174 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2604887753 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 103660417 ps |
| CPU time | 2.63 seconds |
| Started | May 28 01:09:03 PM PDT 24 |
| Finished | May 28 01:09:10 PM PDT 24 |
| Peak memory | 212792 kb |
| Host | smart-a6a26733-0749-48c2-9371-f63bdc7a2cd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604887753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.2604887753 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2172657478 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 80641516 ps |
| CPU time | 1.05 seconds |
| Started | May 28 01:09:11 PM PDT 24 |
| Finished | May 28 01:09:21 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-172520dc-2e31-42c7-bcbf-cee732f6ff2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2172657478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2172657478 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4188518136 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 46845414 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:28 PM PDT 24 |
| Peak memory | 204096 kb |
| Host | smart-c6a6d06f-284b-41b6-9945-86a18cd5957c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4188518136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4188518136 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3162413185 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 167199357 ps |
| CPU time | 1.73 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204468 kb |
| Host | smart-6622d651-96fa-404e-9849-46fad1a6d3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3162413185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3162413185 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2528389297 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 187767965 ps |
| CPU time | 2.27 seconds |
| Started | May 28 01:09:04 PM PDT 24 |
| Finished | May 28 01:09:10 PM PDT 24 |
| Peak memory | 204552 kb |
| Host | smart-2523c9eb-238d-48b3-8ab1-367c3a6982a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2528389297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2528389297 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.810951418 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 714967375 ps |
| CPU time | 4.48 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:27 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-537b4498-68cb-4367-a4dc-440efc7d48d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=810951418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.810951418 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2397082031 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 98713496 ps |
| CPU time | 1.35 seconds |
| Started | May 28 01:09:14 PM PDT 24 |
| Finished | May 28 01:09:23 PM PDT 24 |
| Peak memory | 214556 kb |
| Host | smart-e20764bb-caa8-4251-a0e0-8b2a3c23ba5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397082031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.2397082031 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2081650584 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 50600016 ps |
| CPU time | 0.8 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:15 PM PDT 24 |
| Peak memory | 204148 kb |
| Host | smart-bd756101-dba7-4534-8918-67b623bbeada |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2081650584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2081650584 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4223530090 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 40709453 ps |
| CPU time | 0.67 seconds |
| Started | May 28 01:09:17 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204196 kb |
| Host | smart-54ad8c50-8657-4f9d-bac7-9882d00a595c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4223530090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4223530090 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3963758333 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 233883014 ps |
| CPU time | 1.48 seconds |
| Started | May 28 01:09:16 PM PDT 24 |
| Finished | May 28 01:09:26 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-840bc6ea-154b-42c8-b0ba-959146feb852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3963758333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3963758333 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3698832094 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 180337600 ps |
| CPU time | 2.25 seconds |
| Started | May 28 01:09:09 PM PDT 24 |
| Finished | May 28 01:09:18 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-3bf4154e-796e-457c-9dab-ce3b8b79d487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3698832094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3698832094 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |