Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353	1		T2	2		T6	2		T15	5
all_pins[1]	353	1		T2	2		T6	2		T15	5
all_pins[2]	353	1		T2	2		T6	2		T15	5
all_pins[3]	353	1		T2	2		T6	2		T15	5
all_pins[4]	353	1		T2	2		T6	2		T15	5
all_pins[5]	353	1		T2	2		T6	2		T15	5
all_pins[6]	353	1		T2	2		T6	2		T15	5
all_pins[7]	353	1		T2	2		T6	2		T15	5
all_pins[8]	353	1		T2	2		T6	2		T15	5
all_pins[9]	353	1		T2	2		T6	2		T15	5
all_pins[10]	353	1		T2	2		T6	2		T15	5
all_pins[11]	353	1		T2	2		T6	2		T15	5
all_pins[12]	353	1		T2	2		T6	2		T15	5
all_pins[13]	353	1		T2	2		T6	2		T15	5
all_pins[14]	353	1		T2	2		T6	2		T15	5
all_pins[15]	353	1		T2	2		T6	2		T15	5
all_pins[16]	353	1		T2	2		T6	2		T15	5
all_pins[17]	353	1		T2	2		T6	2		T15	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5266	1		T2	36		T6	36		T15	71
values[0x1]	1088	1		T15	19		T7	32		T16	36
transitions[0x0=>0x1]	826	1		T15	14		T7	22		T16	26
transitions[0x1=>0x0]	838	1		T15	14		T7	22		T16	27

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	300	1		T2	2		T6	2		T15	4
all_pins[0]	values[0x1]	53	1		T15	1		T7	2		T16	3
all_pins[0]	transitions[0x0=>0x1]	37	1		T15	1		T7	1		T16	1
all_pins[0]	transitions[0x1=>0x0]	42	1		T16	1		T38	3		T56	1
all_pins[1]	values[0x0]	295	1		T2	2		T6	2		T15	5
all_pins[1]	values[0x1]	58	1		T7	1		T16	3		T17	1
all_pins[1]	transitions[0x0=>0x1]	39	1		T7	1		T16	3		T38	1
all_pins[1]	transitions[0x1=>0x0]	50	1		T7	3		T16	2		T17	1
all_pins[2]	values[0x0]	284	1		T2	2		T6	2		T15	5
all_pins[2]	values[0x1]	69	1		T7	3		T16	2		T17	2
all_pins[2]	transitions[0x0=>0x1]	56	1		T7	2		T16	2		T36	1
all_pins[2]	transitions[0x1=>0x0]	38	1		T16	1		T17	4		T38	1
all_pins[3]	values[0x0]	302	1		T2	2		T6	2		T15	5
all_pins[3]	values[0x1]	51	1		T7	1		T16	1		T17	6
all_pins[3]	transitions[0x0=>0x1]	45	1		T7	1		T16	1		T17	6
all_pins[3]	transitions[0x1=>0x0]	51	1		T15	2		T16	1		T18	2
all_pins[4]	values[0x0]	296	1		T2	2		T6	2		T15	3
all_pins[4]	values[0x1]	57	1		T15	2		T16	1		T18	2
all_pins[4]	transitions[0x0=>0x1]	45	1		T15	2		T16	1		T36	3
all_pins[4]	transitions[0x1=>0x0]	53	1		T7	3		T16	1		T18	1
all_pins[5]	values[0x0]	288	1		T2	2		T6	2		T15	5
all_pins[5]	values[0x1]	65	1		T7	3		T16	1		T18	3
all_pins[5]	transitions[0x0=>0x1]	47	1		T16	1		T18	1		T36	1
all_pins[5]	transitions[0x1=>0x0]	31	1		T15	2		T7	2		T16	2
all_pins[6]	values[0x0]	304	1		T2	2		T6	2		T15	3
all_pins[6]	values[0x1]	49	1		T15	2		T7	5		T16	2
all_pins[6]	transitions[0x0=>0x1]	41	1		T15	2		T7	3		T16	2
all_pins[6]	transitions[0x1=>0x0]	50	1		T15	1		T7	1		T16	2
all_pins[7]	values[0x0]	295	1		T2	2		T6	2		T15	4
all_pins[7]	values[0x1]	58	1		T15	1		T7	3		T16	2
all_pins[7]	transitions[0x0=>0x1]	43	1		T15	1		T7	2		T16	1
all_pins[7]	transitions[0x1=>0x0]	34	1		T17	2		T36	1		T59	1
all_pins[8]	values[0x0]	304	1		T2	2		T6	2		T15	5
all_pins[8]	values[0x1]	49	1		T7	1		T16	1		T17	2
all_pins[8]	transitions[0x0=>0x1]	38	1		T7	1		T16	1		T17	2
all_pins[8]	transitions[0x1=>0x0]	55	1		T7	1		T16	3		T17	1
all_pins[9]	values[0x0]	287	1		T2	2		T6	2		T15	5
all_pins[9]	values[0x1]	66	1		T7	1		T16	3		T17	1
all_pins[9]	transitions[0x0=>0x1]	49	1		T7	1		T16	3		T17	1
all_pins[9]	transitions[0x1=>0x0]	52	1		T15	1		T7	1		T16	1
all_pins[10]	values[0x0]	284	1		T2	2		T6	2		T15	4
all_pins[10]	values[0x1]	69	1		T15	1		T7	1		T16	1
all_pins[10]	transitions[0x0=>0x1]	50	1		T15	1		T7	1		T16	1
all_pins[10]	transitions[0x1=>0x0]	43	1		T15	3		T7	2		T16	1
all_pins[11]	values[0x0]	291	1		T2	2		T6	2		T15	2
all_pins[11]	values[0x1]	62	1		T15	3		T7	2		T16	1
all_pins[11]	transitions[0x0=>0x1]	48	1		T15	2		T7	2		T16	1
all_pins[11]	transitions[0x1=>0x0]	46	1		T7	2		T16	4		T18	3
all_pins[12]	values[0x0]	293	1		T2	2		T6	2		T15	4
all_pins[12]	values[0x1]	60	1		T15	1		T7	2		T16	4
all_pins[12]	transitions[0x0=>0x1]	48	1		T15	1		T7	2		T16	2
all_pins[12]	transitions[0x1=>0x0]	49	1		T15	2		T17	3		T38	3
all_pins[13]	values[0x0]	292	1		T2	2		T6	2		T15	3
all_pins[13]	values[0x1]	61	1		T15	2		T16	2		T17	3
all_pins[13]	transitions[0x0=>0x1]	48	1		T16	2		T17	2		T38	2
all_pins[13]	transitions[0x1=>0x0]	46	1		T15	2		T7	2		T17	1
all_pins[14]	values[0x0]	294	1		T2	2		T6	2		T15	1
all_pins[14]	values[0x1]	59	1		T15	4		T7	2		T17	2
all_pins[14]	transitions[0x0=>0x1]	47	1		T15	2		T17	1		T36	3
all_pins[14]	transitions[0x1=>0x0]	56	1		T7	2		T16	3		T18	1
all_pins[15]	values[0x0]	285	1		T2	2		T6	2		T15	3
all_pins[15]	values[0x1]	68	1		T15	2		T7	4		T16	3
all_pins[15]	transitions[0x0=>0x1]	50	1		T15	2		T7	4		T18	1
all_pins[15]	transitions[0x1=>0x0]	57	1		T7	1		T16	2		T18	1
all_pins[16]	values[0x0]	278	1		T2	2		T6	2		T15	5
all_pins[16]	values[0x1]	75	1		T7	1		T16	5		T18	1
all_pins[16]	transitions[0x0=>0x1]	61	1		T7	1		T16	4		T18	1
all_pins[16]	transitions[0x1=>0x0]	45	1		T18	1		T17	2		T37	1
all_pins[17]	values[0x0]	294	1		T2	2		T6	2		T15	5
all_pins[17]	values[0x1]	59	1		T16	1		T18	1		T17	2
all_pins[17]	transitions[0x0=>0x1]	34	1		T17	1		T37	1		T38	2
all_pins[17]	transitions[0x1=>0x0]	40	1		T15	1		T7	2		T16	3