Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6859104	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	519799	1		T1	7		T2	11634		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	7083093	1		T1	3697		T2	10138		T3	3558
values[0x0]	147745	1		T1	4		T2	2908		T3	5
values[0x1]	148065	1		T1	5		T2	2902		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5141946	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	2236957	1		T1	901		T2	12685		T3	861

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	35702	1		T1	11		T2	9		T3	10
valid_sources[0x01]	26155	1		T1	11		T2	216		T3	8
valid_sources[0x02]	40805	1		T1	10		T2	7		T3	18
valid_sources[0x03]	25979	1		T1	13		T2	61		T3	12
valid_sources[0x04]	29673	1		T1	6		T2	3		T3	16
valid_sources[0x05]	25813	1		T1	15		T2	1		T3	18
valid_sources[0x06]	22712	1		T1	13		T2	4		T3	10
valid_sources[0x07]	29302	1		T1	16		T2	6		T3	14
valid_sources[0x08]	25365	1		T1	15		T2	5		T3	3
valid_sources[0x09]	29922	1		T1	13		T2	4		T3	5
valid_sources[0x0a]	25006	1		T1	12		T2	145		T3	34
valid_sources[0x0b]	24748	1		T1	19		T3	20		T25	10
valid_sources[0x0c]	25389	1		T1	14		T2	230		T3	11
valid_sources[0x0d]	26135	1		T1	8		T2	10		T3	7
valid_sources[0x0e]	26417	1		T1	20		T2	11		T3	18
valid_sources[0x0f]	25457	1		T1	11		T2	82		T3	32
valid_sources[0x10]	21721	1		T1	17		T2	5		T3	19
valid_sources[0x11]	28634	1		T1	18		T2	105		T3	3
valid_sources[0x12]	22576	1		T1	7		T2	6		T3	15
valid_sources[0x13]	21798	1		T1	11		T2	60		T3	16
valid_sources[0x14]	31299	1		T1	14		T2	3		T3	23
valid_sources[0x15]	32078	1		T1	21		T2	3		T3	1
valid_sources[0x16]	47704	1		T1	10		T2	57		T3	14
valid_sources[0x17]	30010	1		T1	6		T2	38		T3	13
valid_sources[0x18]	24550	1		T1	8		T2	2		T3	10
valid_sources[0x19]	32601	1		T1	12		T2	8		T3	12
valid_sources[0x1a]	29339	1		T1	8		T2	6		T3	4
valid_sources[0x1b]	33402	1		T1	19		T2	438		T3	11
valid_sources[0x1c]	29644	1		T1	14		T2	93		T3	19
valid_sources[0x1d]	22348	1		T1	9		T2	4		T3	20
valid_sources[0x1e]	29958	1		T1	13		T2	2		T3	15
valid_sources[0x1f]	31835	1		T1	20		T2	3		T3	21
valid_sources[0x20]	43696	1		T1	19		T2	3		T3	14
valid_sources[0x21]	43032	1		T1	20		T2	51		T3	7
valid_sources[0x22]	25156	1		T1	15		T2	1		T3	14
valid_sources[0x23]	24132	1		T1	21		T2	106		T3	7
valid_sources[0x24]	24626	1		T1	15		T2	7		T3	7
valid_sources[0x25]	33008	1		T1	31		T2	282		T3	12
valid_sources[0x26]	21334	1		T1	8		T2	7		T3	17
valid_sources[0x27]	21558	1		T1	11		T2	136		T3	3
valid_sources[0x28]	21689	1		T1	14		T2	1		T3	12
valid_sources[0x29]	26053	1		T1	21		T2	3		T3	14
valid_sources[0x2a]	33502	1		T1	21		T2	2		T3	12
valid_sources[0x2b]	25240	1		T1	6		T2	157		T3	12
valid_sources[0x2c]	25771	1		T1	15		T2	27		T3	3
valid_sources[0x2d]	36579	1		T1	23		T2	5		T3	12
valid_sources[0x2e]	41228	1		T1	18		T2	6		T3	10
valid_sources[0x2f]	28258	1		T1	6		T2	4		T3	12
valid_sources[0x30]	22340	1		T1	18		T2	262		T3	8
valid_sources[0x31]	25000	1		T1	11		T2	4		T3	8
valid_sources[0x32]	32912	1		T1	16		T2	7		T3	32
valid_sources[0x33]	26070	1		T1	18		T2	35		T3	11
valid_sources[0x34]	21362	1		T1	19		T2	1		T3	23
valid_sources[0x35]	29320	1		T1	13		T2	1		T3	16
valid_sources[0x36]	21883	1		T1	14		T2	5		T3	18
valid_sources[0x37]	25900	1		T1	14		T2	1		T3	4
valid_sources[0x38]	25269	1		T1	16		T2	431		T3	11
valid_sources[0x39]	21891	1		T1	13		T2	1		T3	16
valid_sources[0x3a]	25544	1		T1	17		T2	5		T3	14
valid_sources[0x3b]	32744	1		T1	13		T2	1		T3	19
valid_sources[0x3c]	25148	1		T1	15		T2	6		T3	18
valid_sources[0x3d]	32433	1		T1	19		T2	7		T3	14
valid_sources[0x3e]	29066	1		T1	7		T2	160		T3	3
valid_sources[0x3f]	33955	1		T1	15		T2	7		T3	16
valid_sources[0x40]	41556	1		T1	3		T2	2		T3	16
valid_sources[0x41]	28699	1		T1	21		T2	6		T3	5
valid_sources[0x42]	25138	1		T1	14		T2	5		T3	13
valid_sources[0x43]	29678	1		T1	15		T2	3		T3	16
valid_sources[0x44]	25863	1		T1	10		T2	666		T3	12
valid_sources[0x45]	28154	1		T1	16		T2	2		T3	9
valid_sources[0x46]	31712	1		T1	9		T2	3		T3	3
valid_sources[0x47]	39952	1		T1	14		T2	5		T3	10
valid_sources[0x48]	25270	1		T1	13		T2	3		T3	16
valid_sources[0x49]	32128	1		T1	21		T2	9		T3	10
valid_sources[0x4a]	21203	1		T1	9		T2	2		T3	6
valid_sources[0x4b]	25478	1		T1	20		T2	2		T3	10
valid_sources[0x4c]	29683	1		T1	25		T2	9		T3	9
valid_sources[0x4d]	24701	1		T1	12		T2	6		T3	12
valid_sources[0x4e]	29801	1		T1	21		T2	2		T3	25
valid_sources[0x4f]	26199	1		T1	19		T3	5		T25	19
valid_sources[0x50]	32777	1		T1	18		T2	2		T3	9
valid_sources[0x51]	28636	1		T1	14		T2	3		T3	10
valid_sources[0x52]	25595	1		T1	10		T2	7		T3	20
valid_sources[0x53]	24999	1		T1	15		T2	9		T3	22
valid_sources[0x54]	33516	1		T1	12		T2	6		T3	8
valid_sources[0x55]	26257	1		T1	31		T2	6		T3	17
valid_sources[0x56]	28888	1		T1	12		T2	2		T3	19
valid_sources[0x57]	25315	1		T1	15		T2	19		T3	11
valid_sources[0x58]	32464	1		T1	15		T2	10		T3	19
valid_sources[0x59]	29395	1		T1	7		T2	2		T3	19
valid_sources[0x5a]	30465	1		T1	14		T2	3		T3	14
valid_sources[0x5b]	29396	1		T1	18		T2	3		T3	15
valid_sources[0x5c]	22528	1		T1	11		T2	138		T3	8
valid_sources[0x5d]	30569	1		T1	11		T2	11		T3	20
valid_sources[0x5e]	25421	1		T1	14		T2	2		T3	5
valid_sources[0x5f]	24967	1		T1	20		T2	7		T3	17
valid_sources[0x60]	24368	1		T1	1		T2	2		T3	12
valid_sources[0x61]	33381	1		T1	15		T2	6		T3	7
valid_sources[0x62]	36751	1		T1	17		T2	6		T3	10
valid_sources[0x63]	21879	1		T1	16		T3	16		T25	14
valid_sources[0x64]	32116	1		T1	12		T2	6		T3	5
valid_sources[0x65]	39349	1		T1	4		T2	6		T3	16
valid_sources[0x66]	22069	1		T1	18		T2	109		T3	13
valid_sources[0x67]	24384	1		T1	16		T2	5		T3	11
valid_sources[0x68]	28170	1		T1	16		T2	7		T3	8
valid_sources[0x69]	29007	1		T1	18		T2	9		T3	12
valid_sources[0x6a]	32985	1		T1	16		T3	10		T25	15
valid_sources[0x6b]	28189	1		T1	20		T2	2		T3	16
valid_sources[0x6c]	32508	1		T1	17		T2	51		T3	11
valid_sources[0x6d]	32248	1		T1	10		T2	4		T3	18
valid_sources[0x6e]	36477	1		T1	19		T2	2		T3	16
valid_sources[0x6f]	28520	1		T1	11		T3	11		T25	8
valid_sources[0x70]	35592	1		T1	16		T2	20		T3	5
valid_sources[0x71]	28759	1		T1	11		T2	2		T3	15
valid_sources[0x72]	36893	1		T1	10		T2	368		T3	10
valid_sources[0x73]	36290	1		T1	3		T2	6		T3	9
valid_sources[0x74]	25902	1		T1	12		T2	2		T3	21
valid_sources[0x75]	21414	1		T1	12		T2	4		T3	12
valid_sources[0x76]	26042	1		T1	13		T2	5		T3	15
valid_sources[0x77]	25366	1		T1	13		T2	3		T25	16
valid_sources[0x78]	28891	1		T1	8		T2	6		T3	18
valid_sources[0x79]	26028	1		T1	15		T2	5		T3	9
valid_sources[0x7a]	24915	1		T1	15		T2	9		T3	16
valid_sources[0x7b]	29207	1		T1	6		T2	5		T3	23
valid_sources[0x7c]	26214	1		T1	13		T2	61		T3	13
valid_sources[0x7d]	32694	1		T1	7		T2	3		T3	17
valid_sources[0x7e]	35506	1		T1	17		T2	4		T3	4
valid_sources[0x7f]	33928	1		T1	16		T2	2		T3	11
valid_sources[0x80]	32682	1		T1	16		T2	376		T3	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

280720

1

T2

6186

T3

1

T25

17

values[0x0]

all_enables

biggest_size

124205

1

T1

3

T2

2750

T3

4

values[0x1]

all_enables

biggest_size

114874

1

T1

4

T2

2698

T3

1