Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	974473335	11813	0	0
ep_in_enable_rd_A	974473335	4265	0	0
ep_out_enable_rd_A	974473335	3850	0	0
in_iso_rd_A	974473335	3215	0	0
intr_enable_rd_A	974473335	4313	0	0
out_iso_rd_A	974473335	4008	0	0
phy_config_rd_A	974473335	2472	0	0
phy_pins_drive_rd_A	974473335	2688	0	0
rxenable_setup_rd_A	974473335	3463	0	0
set_nak_out_rd_A	974473335	4088	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	11813	0	0
T195	11037	576	0	0
T196	7679	14	0	0
T197	68219	5	0	0
T209	3903	458	0	0
T212	6655	350	0	0
T215	44870	3	0	0
T217	4530	12	0	0
T218	13554	922	0	0
T224	4204	10	0	0
T225	5767	9	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	4265	0	0
T196	7679	40	0	0
T197	68219	558	0	0
T199	4862	1	0	0
T200	67540	262	0	0
T243	3741	59	0	0
T244	3527	2	0	0
T245	2626	22	0	0
T247	35663	98	0	0
T258	9142	8	0	0
T259	60260	374	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	3850	0	0
T196	7679	11	0	0
T197	68219	484	0	0
T199	4862	39	0	0
T200	67540	280	0	0
T243	3741	42	0	0
T244	3527	34	0	0
T247	35663	134	0	0
T248	3993	4	0	0
T258	9142	61	0	0
T259	60260	286	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	3215	0	0
T195	11037	4	0	0
T196	7679	52	0	0
T197	68219	461	0	0
T199	4862	6	0	0
T200	67540	254	0	0
T243	3741	68	0	0
T244	3527	13	0	0
T247	35663	142	0	0
T258	9142	1	0	0
T259	60260	275	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	4313	0	0
T96	3653	32	0	0
T196	7679	67	0	0
T197	68219	518	0	0
T199	4862	22	0	0
T200	67540	295	0	0
T202	4167	18	0	0
T204	2137	3	0	0
T258	9142	8	0	0
T260	4177	6	0	0
T261	1824	13	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	4008	0	0
T196	7679	33	0	0
T197	68219	416	0	0
T199	4862	10	0	0
T200	67540	343	0	0
T243	3741	79	0	0
T244	3527	59	0	0
T247	35663	124	0	0
T248	3993	3	0	0
T258	9142	57	0	0
T259	60260	278	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	2472	0	0
T196	7679	23	0	0
T197	68219	186	0	0
T199	4862	7	0	0
T200	67540	236	0	0
T243	3741	14	0	0
T244	3527	39	0	0
T245	2626	5	0	0
T247	35663	121	0	0
T258	9142	11	0	0
T259	60260	156	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	2688	0	0
T196	7679	26	0	0
T197	68219	286	0	0
T199	4862	5	0	0
T200	67540	188	0	0
T243	3741	28	0	0
T244	3527	33	0	0
T245	2626	8	0	0
T247	35663	109	0	0
T258	9142	14	0	0
T259	60260	151	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	3463	0	0
T196	7679	39	0	0
T197	68219	550	0	0
T199	4862	11	0	0
T200	67540	287	0	0
T243	3741	4	0	0
T244	3527	38	0	0
T245	2626	29	0	0
T247	35663	159	0	0
T258	9142	50	0	0
T259	60260	196	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	4088	0	0
T196	7679	19	0	0
T197	68219	543	0	0
T199	4862	15	0	0
T200	67540	275	0	0
T243	3741	33	0	0
T244	3527	66	0	0
T245	2626	2	0	0
T247	35663	149	0	0
T258	9142	63	0	0
T259	60260	235	0	0