Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.55	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.55	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.55	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T82,T83,T84
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T25,T30,T53

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T25,T30,T53

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T25,T30,T53
1	1	0	Not Covered
1	1	1	Covered	T25,T30,T53

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T25,T30,T53
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	972666991	587355	0	0
DepthKnown_A	972666991	972520939	0	0
RvalidKnown_A	972666991	972520939	0	0
WreadyKnown_A	972666991	972520939	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	972666991	587355	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	587355	0	0
T22	483622	0	0	0
T25	487018	569	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	552	0	0
T31	482859	0	0	0
T32	482965	0	0	0
T34	482588	0	0	0
T53	0	561	0	0
T63	0	562	0	0
T64	0	582	0	0
T82	0	2925	0	0
T83	0	4830	0	0
T87	0	1686	0	0
T88	0	1638	0	0
T89	0	1327	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	587355	0	0
T22	483622	0	0	0
T25	487018	569	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	552	0	0
T31	482859	0	0	0
T32	482965	0	0	0
T34	482588	0	0	0
T53	0	561	0	0
T63	0	562	0	0
T64	0	582	0	0
T82	0	2925	0	0
T83	0	4830	0	0
T87	0	1686	0	0
T88	0	1638	0	0
T89	0	1327	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T82,T83,T84
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T25

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	972666991	27294629	0	0
DepthKnown_A	972666991	972520939	0	0
RvalidKnown_A	972666991	972520939	0	0
WreadyKnown_A	972666991	972520939	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	972666991	27294629	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	27294629	0	0
T1	486784	2365	0	0
T2	151151	646982	0	0
T3	482908	1335	0	0
T22	483622	0	0	0
T25	487018	1885	0	0
T26	486948	2354	0	0
T27	486200	2006	0	0
T28	487827	2361	0	0
T29	486951	2338	0	0
T30	0	340	0	0
T34	482588	1209	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	27294629	0	0
T1	486784	2365	0	0
T2	151151	646982	0	0
T3	482908	1335	0	0
T22	483622	0	0	0
T25	487018	1885	0	0
T26	486948	2354	0	0
T27	486200	2006	0	0
T28	487827	2361	0	0
T29	486951	2338	0	0
T30	0	340	0	0
T34	482588	1209	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T25

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T25

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T25
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T25
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T25
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	972666991	2543527	0	0
DepthKnown_A	972666991	972520939	0	0
RvalidKnown_A	972666991	972520939	0	0
WreadyKnown_A	972666991	972520939	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	972666991	2543527	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	2543527	0	0
T1	486784	3544	0	0
T2	151151	47713	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	211	0	0
T26	486948	3547	0	0
T27	486200	2922	0	0
T28	487827	3489	0	0
T29	486951	3143	0	0
T30	0	196	0	0
T31	0	1277	0	0
T32	0	89	0	0
T34	482588	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	2543527	0	0
T1	486784	3544	0	0
T2	151151	47713	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	211	0	0
T26	486948	3547	0	0
T27	486200	2922	0	0
T28	487827	3489	0	0
T29	486951	3143	0	0
T30	0	196	0	0
T31	0	1277	0	0
T32	0	89	0	0
T34	482588	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	974473335	7662912	0	0
DepthKnown_A	974473335	974270823	0	0
RvalidKnown_A	974473335	974270823	0	0
WreadyKnown_A	974473335	974270823	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	7662912	0	0
T1	486784	3706	0	0
T2	151151	18097	0	0
T3	482908	3566	0	0
T22	483622	3704	0	0
T25	487018	3516	0	0
T26	486948	3707	0	0
T27	486200	3576	0	0
T28	487827	3570	0	0
T29	486951	3710	0	0
T34	482588	3704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T22	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	974473335	13587215	0	0
DepthKnown_A	974473335	974270823	0	0
RvalidKnown_A	974473335	974270823	0	0
WreadyKnown_A	974473335	974270823	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	13587215	0	0
T1	486784	3706	0	0
T2	151151	15948	0	0
T3	482908	3566	0	0
T22	483622	3704	0	0
T25	487018	15307	0	0
T26	486948	3707	0	0
T27	486200	3576	0	0
T28	487827	3570	0	0
T29	486951	3710	0	0
T34	482588	3704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T22	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	974473335	404752	0	0
DepthKnown_A	974473335	974270823	0	0
RvalidKnown_A	974473335	974270823	0	0
WreadyKnown_A	974473335	974270823	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	404752	0	0
T2	151151	10272	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	24	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	14	0	0
T32	0	5	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	15	0	0
T85	0	10	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T22	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	974473335	654984	0	0
DepthKnown_A	974473335	974270823	0	0
RvalidKnown_A	974473335	974270823	0	0
WreadyKnown_A	974473335	974270823	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	654984	0	0
T2	151151	10272	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	112	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	14	0	0
T32	0	11	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	81	0	0
T85	0	10	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T22	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	974473335	7194608	0	0
DepthKnown_A	974473335	974270823	0	0
RvalidKnown_A	974473335	974270823	0	0
WreadyKnown_A	974473335	974270823	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	7194608	0	0
T1	486784	3706	0	0
T2	151151	5676	0	0
T3	482908	3566	0	0
T22	483622	3704	0	0
T25	487018	3492	0	0
T26	486948	3707	0	0
T27	486200	3576	0	0
T28	487827	3570	0	0
T29	486951	3710	0	0
T34	482588	3704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T22	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	974473335	12932231	0	0
DepthKnown_A	974473335	974270823	0	0
RvalidKnown_A	974473335	974270823	0	0
WreadyKnown_A	974473335	974270823	0	0
gen_passthru_fifo.paramCheckPass	2042	2042	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	12932231	0	0
T1	486784	3706	0	0
T2	151151	5676	0	0
T3	482908	3566	0	0
T22	483622	3704	0	0
T25	487018	15195	0	0
T26	486948	3707	0	0
T27	486200	3576	0	0
T28	487827	3570	0	0
T29	486951	3710	0	0
T34	482588	3704	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	974473335	974270823	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T22	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T34	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T25,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T25,T32
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T25,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T25,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	972666991	609037	0	0
DepthKnown_A	972666991	972520939	0	0
RvalidKnown_A	972666991	972520939	0	0
WreadyKnown_A	972666991	972520939	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	972666991	609037	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	609037	0	0
T2	151151	10272	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	112	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	14	0	0
T32	0	11	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	81	0	0
T85	0	10	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	609037	0	0
T2	151151	10272	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	112	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	14	0	0
T32	0	11	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	81	0	0
T85	0	10	0	0
T86	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T25,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T25,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T25,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	972666991	223315	0	0
DepthKnown_A	972666991	972520939	0	0
RvalidKnown_A	972666991	972520939	0	0
WreadyKnown_A	972666991	972520939	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	972666991	223315	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	223315	0	0
T2	151151	5956	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	15	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	3	0	0
T32	0	5	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	15	0	0
T85	0	10	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	223315	0	0
T2	151151	5956	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	15	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	3	0	0
T32	0	5	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	15	0	0
T85	0	10	0	0
T86	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T25,T32,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T25,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T25,T32
1	1	0	Not Covered
1	1	1	Covered	T2,T25,T30

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T25,T30

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T25,T30

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T25,T32,T81
1	0	Covered	T2,T25,T30
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T25,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T25,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T25,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	972666991	374603	0	0
DepthKnown_A	972666991	972520939	0	0
RvalidKnown_A	972666991	972520939	0	0
WreadyKnown_A	972666991	972520939	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	972666991	374603	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	374603	0	0
T2	151151	5956	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	80	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	3	0	0
T32	0	11	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	81	0	0
T85	0	10	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	972520939	0	0
T1	486784	486684	0	0
T2	151151	151142	0	0
T3	482908	482841	0	0
T22	483622	483561	0	0
T25	487018	486960	0	0
T26	486948	486874	0	0
T27	486200	486142	0	0
T28	487827	487738	0	0
T29	486951	486859	0	0
T34	482588	482501	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	972666991	374603	0	0
T2	151151	5956	0	0
T3	482908	0	0	0
T22	483622	0	0	0
T25	487018	80	0	0
T26	486948	0	0	0
T27	486200	0	0	0
T28	487827	0	0	0
T29	486951	0	0	0
T30	485504	3	0	0
T32	0	11	0	0
T34	482588	0	0	0
T44	0	147	0	0
T68	0	7	0	0
T78	0	16	0	0
T81	0	81	0	0
T85	0	10	0	0
T86	0	16	0	0