Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.57 97.44 91.93 97.86 70.31 95.72 98.17 96.58


Total test records in report: 2042
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T1818 /workspace/coverage/default/10.usbdev_pkt_buffer.3129139440 May 30 03:43:36 PM PDT 24 May 30 03:44:06 PM PDT 24 17061933729 ps
T1819 /workspace/coverage/default/27.min_length_in_transaction.2740154361 May 30 03:45:40 PM PDT 24 May 30 03:45:58 PM PDT 24 10131662467 ps
T1820 /workspace/coverage/default/19.usbdev_phy_pins_sense.3514646275 May 30 03:44:51 PM PDT 24 May 30 03:45:12 PM PDT 24 10045680430 ps
T1821 /workspace/coverage/default/31.usbdev_aon_wake_resume.3927221196 May 30 03:45:58 PM PDT 24 May 30 03:46:23 PM PDT 24 13210036053 ps
T1822 /workspace/coverage/default/9.usbdev_stall_trans.2759653978 May 30 03:43:35 PM PDT 24 May 30 03:43:50 PM PDT 24 10053570890 ps
T1823 /workspace/coverage/default/44.usbdev_data_toggle_restore.2652034485 May 30 03:47:25 PM PDT 24 May 30 03:47:44 PM PDT 24 11020672935 ps
T1824 /workspace/coverage/default/0.usbdev_rx_crc_err.2184337019 May 30 03:42:11 PM PDT 24 May 30 03:42:28 PM PDT 24 10045667674 ps
T1825 /workspace/coverage/default/4.usbdev_in_stall.1591975777 May 30 03:42:52 PM PDT 24 May 30 03:43:08 PM PDT 24 10048823267 ps
T1826 /workspace/coverage/default/31.usbdev_smoke.118931526 May 30 03:46:02 PM PDT 24 May 30 03:46:23 PM PDT 24 10113853562 ps
T1827 /workspace/coverage/default/24.usbdev_data_toggle_restore.254615241 May 30 03:45:20 PM PDT 24 May 30 03:45:38 PM PDT 24 10965057235 ps
T1828 /workspace/coverage/default/6.random_length_in_trans.470444580 May 30 03:43:23 PM PDT 24 May 30 03:43:39 PM PDT 24 10060683733 ps
T1829 /workspace/coverage/default/24.usbdev_pkt_sent.2393753195 May 30 03:45:23 PM PDT 24 May 30 03:45:38 PM PDT 24 10060008223 ps
T1830 /workspace/coverage/default/27.usbdev_in_trans.2474337682 May 30 03:45:45 PM PDT 24 May 30 03:46:03 PM PDT 24 10133600712 ps
T1831 /workspace/coverage/default/41.usbdev_aon_wake_disconnect.769132725 May 30 03:47:05 PM PDT 24 May 30 03:47:28 PM PDT 24 13583466181 ps
T1832 /workspace/coverage/default/35.usbdev_fifo_rst.3514592624 May 30 03:46:34 PM PDT 24 May 30 03:46:55 PM PDT 24 10272213859 ps
T1833 /workspace/coverage/default/18.random_length_in_trans.3178550 May 30 03:44:39 PM PDT 24 May 30 03:44:56 PM PDT 24 10121744538 ps
T1834 /workspace/coverage/default/23.usbdev_rx_crc_err.1559129208 May 30 03:45:15 PM PDT 24 May 30 03:45:32 PM PDT 24 10079342492 ps
T1835 /workspace/coverage/default/46.usbdev_aon_wake_reset.969220655 May 30 03:47:34 PM PDT 24 May 30 03:47:54 PM PDT 24 13239521230 ps
T1836 /workspace/coverage/default/32.max_length_in_transaction.3706443518 May 30 03:46:12 PM PDT 24 May 30 03:46:32 PM PDT 24 10151652869 ps
T1837 /workspace/coverage/default/31.usbdev_in_stall.39823789 May 30 03:46:04 PM PDT 24 May 30 03:46:23 PM PDT 24 10039540123 ps
T1838 /workspace/coverage/default/49.usbdev_av_buffer.2652106225 May 30 03:48:00 PM PDT 24 May 30 03:48:18 PM PDT 24 10070585750 ps
T1839 /workspace/coverage/default/42.usbdev_nak_trans.3035543687 May 30 03:47:08 PM PDT 24 May 30 03:47:30 PM PDT 24 10106100147 ps
T1840 /workspace/coverage/default/5.usbdev_fifo_rst.3519163852 May 30 03:42:49 PM PDT 24 May 30 03:43:04 PM PDT 24 10206077074 ps
T1841 /workspace/coverage/default/34.usbdev_random_length_out_trans.2224714289 May 30 03:46:24 PM PDT 24 May 30 03:46:42 PM PDT 24 10134541992 ps
T1842 /workspace/coverage/default/48.usbdev_endpoint_access.1554842057 May 30 03:47:48 PM PDT 24 May 30 03:48:07 PM PDT 24 10649100094 ps
T1843 /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.1099832487 May 30 03:47:47 PM PDT 24 May 30 03:48:05 PM PDT 24 10091892190 ps
T1844 /workspace/coverage/default/32.usbdev_data_toggle_restore.1552340003 May 30 03:46:13 PM PDT 24 May 30 03:46:33 PM PDT 24 10903733242 ps
T1845 /workspace/coverage/default/45.usbdev_fifo_rst.3268437311 May 30 03:47:36 PM PDT 24 May 30 03:47:55 PM PDT 24 10173123896 ps
T1846 /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3078291595 May 30 03:47:43 PM PDT 24 May 30 03:47:59 PM PDT 24 10052094439 ps
T1847 /workspace/coverage/default/21.usbdev_pkt_received.1303832540 May 30 03:44:58 PM PDT 24 May 30 03:45:15 PM PDT 24 10054530777 ps
T1848 /workspace/coverage/default/15.usbdev_pkt_buffer.1292811803 May 30 03:44:23 PM PDT 24 May 30 03:45:18 PM PDT 24 25327635986 ps
T1849 /workspace/coverage/default/14.usbdev_aon_wake_resume.1078644240 May 30 03:44:10 PM PDT 24 May 30 03:44:30 PM PDT 24 13233184851 ps
T1850 /workspace/coverage/default/48.usbdev_enable.1921548498 May 30 03:47:56 PM PDT 24 May 30 03:48:14 PM PDT 24 10104249641 ps
T1851 /workspace/coverage/default/25.max_length_in_transaction.2068057593 May 30 03:45:30 PM PDT 24 May 30 03:45:47 PM PDT 24 10165223737 ps
T55 /workspace/coverage/default/15.usbdev_bitstuff_err.2517469030 May 30 03:44:11 PM PDT 24 May 30 03:44:28 PM PDT 24 10096663412 ps
T1852 /workspace/coverage/default/16.usbdev_out_iso.1522084186 May 30 03:44:23 PM PDT 24 May 30 03:44:41 PM PDT 24 10106733070 ps
T1853 /workspace/coverage/default/23.usbdev_aon_wake_resume.3598675646 May 30 03:45:15 PM PDT 24 May 30 03:45:36 PM PDT 24 13254144171 ps
T1854 /workspace/coverage/default/3.usbdev_in_stall.2929864708 May 30 03:42:39 PM PDT 24 May 30 03:42:55 PM PDT 24 10082089296 ps
T1855 /workspace/coverage/default/36.usbdev_disconnected.2441955791 May 30 03:46:34 PM PDT 24 May 30 03:46:52 PM PDT 24 10038277160 ps
T1856 /workspace/coverage/default/27.usbdev_stall_trans.969998500 May 30 03:45:38 PM PDT 24 May 30 03:45:55 PM PDT 24 10085972369 ps
T1857 /workspace/coverage/default/27.usbdev_phy_pins_sense.106907846 May 30 03:45:41 PM PDT 24 May 30 03:45:58 PM PDT 24 10069068480 ps
T1858 /workspace/coverage/default/27.usbdev_setup_stage.2537153799 May 30 03:45:41 PM PDT 24 May 30 03:45:59 PM PDT 24 10052149266 ps
T1859 /workspace/coverage/default/45.usbdev_in_iso.2000820780 May 30 03:47:34 PM PDT 24 May 30 03:47:51 PM PDT 24 10177605567 ps
T1860 /workspace/coverage/default/5.usbdev_out_iso.4115391670 May 30 03:42:49 PM PDT 24 May 30 03:43:04 PM PDT 24 10094620277 ps
T1861 /workspace/coverage/default/48.usbdev_in_trans.3493494826 May 30 03:47:56 PM PDT 24 May 30 03:48:15 PM PDT 24 10105111277 ps
T1862 /workspace/coverage/default/20.usbdev_out_iso.267911135 May 30 03:44:49 PM PDT 24 May 30 03:45:07 PM PDT 24 10102783315 ps
T1863 /workspace/coverage/default/25.usbdev_setup_stage.2121308450 May 30 03:45:29 PM PDT 24 May 30 03:45:47 PM PDT 24 10080250770 ps
T1864 /workspace/coverage/default/46.usbdev_enable.3522195113 May 30 03:47:35 PM PDT 24 May 30 03:47:55 PM PDT 24 10054678419 ps
T1865 /workspace/coverage/default/7.usbdev_min_length_out_transaction.795328757 May 30 03:43:22 PM PDT 24 May 30 03:43:37 PM PDT 24 10046007353 ps
T1866 /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1866741042 May 30 03:46:58 PM PDT 24 May 30 03:47:17 PM PDT 24 10039688072 ps
T1867 /workspace/coverage/default/40.usbdev_link_suspend.3183127388 May 30 03:46:55 PM PDT 24 May 30 03:47:17 PM PDT 24 13180136359 ps
T1868 /workspace/coverage/default/20.min_length_in_transaction.2881895119 May 30 03:44:55 PM PDT 24 May 30 03:45:12 PM PDT 24 10062686173 ps
T1869 /workspace/coverage/default/7.usbdev_smoke.926297251 May 30 03:43:24 PM PDT 24 May 30 03:43:40 PM PDT 24 10078517732 ps
T1870 /workspace/coverage/default/0.usbdev_endpoint_access.832994221 May 30 03:42:14 PM PDT 24 May 30 03:42:32 PM PDT 24 10749701840 ps
T1871 /workspace/coverage/default/18.usbdev_pkt_buffer.1702868648 May 30 03:44:37 PM PDT 24 May 30 03:45:48 PM PDT 24 30139535259 ps
T1872 /workspace/coverage/default/29.usbdev_data_toggle_restore.4166771630 May 30 03:45:51 PM PDT 24 May 30 03:46:09 PM PDT 24 10244998275 ps
T1873 /workspace/coverage/default/36.usbdev_nak_trans.1192485010 May 30 03:46:38 PM PDT 24 May 30 03:46:58 PM PDT 24 10123364542 ps
T1874 /workspace/coverage/default/45.usbdev_aon_wake_reset.664416610 May 30 03:47:35 PM PDT 24 May 30 03:47:55 PM PDT 24 13316203202 ps
T1875 /workspace/coverage/default/14.usbdev_enable.1723707704 May 30 03:44:11 PM PDT 24 May 30 03:44:29 PM PDT 24 10054491333 ps
T1876 /workspace/coverage/default/39.usbdev_out_trans_nak.1885191728 May 30 03:46:56 PM PDT 24 May 30 03:47:14 PM PDT 24 10163855682 ps
T1877 /workspace/coverage/default/45.usbdev_stall_trans.3294798195 May 30 03:47:35 PM PDT 24 May 30 03:47:55 PM PDT 24 10062025747 ps
T1878 /workspace/coverage/default/23.usbdev_pkt_sent.2393942347 May 30 03:45:14 PM PDT 24 May 30 03:45:30 PM PDT 24 10117300042 ps
T1879 /workspace/coverage/default/22.usbdev_pkt_buffer.1563257681 May 30 03:45:05 PM PDT 24 May 30 03:45:44 PM PDT 24 20747331647 ps
T1880 /workspace/coverage/default/12.usbdev_out_trans_nak.1669666636 May 30 03:43:49 PM PDT 24 May 30 03:44:07 PM PDT 24 10095421717 ps
T1881 /workspace/coverage/default/28.usbdev_setup_stage.1752392784 May 30 03:45:41 PM PDT 24 May 30 03:45:58 PM PDT 24 10064892854 ps
T1882 /workspace/coverage/default/10.usbdev_av_buffer.494114563 May 30 03:43:37 PM PDT 24 May 30 03:43:54 PM PDT 24 10078051266 ps
T1883 /workspace/coverage/default/8.usbdev_out_trans_nak.3864425162 May 30 03:43:23 PM PDT 24 May 30 03:43:41 PM PDT 24 10093804540 ps
T1884 /workspace/coverage/default/25.usbdev_pending_in_trans.468860114 May 30 03:45:28 PM PDT 24 May 30 03:45:45 PM PDT 24 10111042969 ps
T1885 /workspace/coverage/default/30.usbdev_endpoint_access.2930492946 May 30 03:45:54 PM PDT 24 May 30 03:46:13 PM PDT 24 10923192627 ps
T1886 /workspace/coverage/default/46.usbdev_smoke.4133474292 May 30 03:47:33 PM PDT 24 May 30 03:47:49 PM PDT 24 10124431074 ps
T1887 /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.479801709 May 30 03:46:48 PM PDT 24 May 30 03:47:08 PM PDT 24 10042257359 ps
T1888 /workspace/coverage/default/33.usbdev_data_toggle_restore.1699066777 May 30 03:46:08 PM PDT 24 May 30 03:46:28 PM PDT 24 10903360684 ps
T1889 /workspace/coverage/default/9.usbdev_max_length_out_transaction.682514343 May 30 03:43:36 PM PDT 24 May 30 03:43:51 PM PDT 24 10162491432 ps
T1890 /workspace/coverage/default/33.usbdev_setup_stage.3071873895 May 30 03:46:21 PM PDT 24 May 30 03:46:38 PM PDT 24 10049420813 ps
T1891 /workspace/coverage/default/33.usbdev_out_stall.190185744 May 30 03:46:25 PM PDT 24 May 30 03:46:41 PM PDT 24 10065923013 ps
T1892 /workspace/coverage/default/17.usbdev_out_stall.2400710413 May 30 03:44:38 PM PDT 24 May 30 03:44:56 PM PDT 24 10058791204 ps
T1893 /workspace/coverage/default/27.usbdev_link_suspend.688380287 May 30 03:45:38 PM PDT 24 May 30 03:46:00 PM PDT 24 13233686952 ps
T1894 /workspace/coverage/default/5.usbdev_max_length_out_transaction.985148323 May 30 03:42:50 PM PDT 24 May 30 03:43:06 PM PDT 24 10102213856 ps
T1895 /workspace/coverage/default/14.usbdev_aon_wake_reset.1274028726 May 30 03:44:02 PM PDT 24 May 30 03:44:24 PM PDT 24 13227201670 ps
T1896 /workspace/coverage/default/38.random_length_in_trans.2375432527 May 30 03:46:47 PM PDT 24 May 30 03:47:09 PM PDT 24 10074931934 ps
T1897 /workspace/coverage/default/18.usbdev_stall_trans.1964630138 May 30 03:44:36 PM PDT 24 May 30 03:44:53 PM PDT 24 10062696832 ps
T1898 /workspace/coverage/default/41.usbdev_phy_pins_sense.286659546 May 30 03:47:04 PM PDT 24 May 30 03:47:26 PM PDT 24 10045802393 ps
T1899 /workspace/coverage/default/48.usbdev_in_stall.1367492619 May 30 03:47:57 PM PDT 24 May 30 03:48:15 PM PDT 24 10043157351 ps
T116 /workspace/coverage/default/49.usbdev_nak_trans.1229333959 May 30 03:47:55 PM PDT 24 May 30 03:48:14 PM PDT 24 10114574016 ps
T1900 /workspace/coverage/default/31.usbdev_fifo_rst.2216193851 May 30 03:45:59 PM PDT 24 May 30 03:46:23 PM PDT 24 10085154644 ps
T1901 /workspace/coverage/default/15.min_length_in_transaction.1570614789 May 30 03:44:23 PM PDT 24 May 30 03:44:40 PM PDT 24 10053949813 ps
T1902 /workspace/coverage/default/38.usbdev_data_toggle_restore.1309472143 May 30 03:46:43 PM PDT 24 May 30 03:47:05 PM PDT 24 11068029894 ps
T1903 /workspace/coverage/default/6.usbdev_pkt_sent.2097061663 May 30 03:43:11 PM PDT 24 May 30 03:43:27 PM PDT 24 10125706692 ps
T1904 /workspace/coverage/default/45.usbdev_pkt_sent.3033740843 May 30 03:47:33 PM PDT 24 May 30 03:47:49 PM PDT 24 10130966145 ps
T1905 /workspace/coverage/default/15.usbdev_link_in_err.1757734597 May 30 03:44:24 PM PDT 24 May 30 03:44:43 PM PDT 24 10104558690 ps
T1906 /workspace/coverage/default/26.usbdev_out_stall.2984913934 May 30 03:45:31 PM PDT 24 May 30 03:45:52 PM PDT 24 10056245478 ps
T1907 /workspace/coverage/default/23.usbdev_in_trans.2790345640 May 30 03:45:14 PM PDT 24 May 30 03:45:30 PM PDT 24 10222575360 ps
T1908 /workspace/coverage/default/32.usbdev_setup_stage.4077834399 May 30 03:46:11 PM PDT 24 May 30 03:46:30 PM PDT 24 10058274129 ps
T1909 /workspace/coverage/default/31.min_length_in_transaction.2235948931 May 30 03:46:05 PM PDT 24 May 30 03:46:23 PM PDT 24 10088921936 ps
T1910 /workspace/coverage/default/17.usbdev_pkt_sent.287688586 May 30 03:44:37 PM PDT 24 May 30 03:44:56 PM PDT 24 10079615266 ps
T1911 /workspace/coverage/default/20.usbdev_phy_pins_sense.3417033097 May 30 03:44:50 PM PDT 24 May 30 03:45:09 PM PDT 24 10050744891 ps
T1912 /workspace/coverage/default/3.max_length_in_transaction.980995828 May 30 03:42:43 PM PDT 24 May 30 03:43:00 PM PDT 24 10142123392 ps
T1913 /workspace/coverage/default/45.usbdev_bitstuff_err.600658088 May 30 03:47:34 PM PDT 24 May 30 03:47:53 PM PDT 24 10069441425 ps
T1914 /workspace/coverage/default/24.min_length_in_transaction.301088693 May 30 03:45:29 PM PDT 24 May 30 03:45:47 PM PDT 24 10066284392 ps
T1915 /workspace/coverage/default/17.max_length_in_transaction.3498939325 May 30 03:44:40 PM PDT 24 May 30 03:44:57 PM PDT 24 10194994615 ps
T1916 /workspace/coverage/default/6.usbdev_setup_trans_ignored.3202964098 May 30 03:43:12 PM PDT 24 May 30 03:43:28 PM PDT 24 10054181410 ps
T1917 /workspace/coverage/default/12.usbdev_disconnected.114784467 May 30 03:43:48 PM PDT 24 May 30 03:44:08 PM PDT 24 10051971596 ps
T1918 /workspace/coverage/default/31.usbdev_av_buffer.2337272130 May 30 03:45:57 PM PDT 24 May 30 03:46:16 PM PDT 24 10058200340 ps
T1919 /workspace/coverage/default/7.usbdev_aon_wake_reset.3257781959 May 30 03:43:23 PM PDT 24 May 30 03:43:45 PM PDT 24 13314055477 ps
T1920 /workspace/coverage/default/45.usbdev_link_in_err.3111529249 May 30 03:47:36 PM PDT 24 May 30 03:47:55 PM PDT 24 10077643936 ps
T1921 /workspace/coverage/default/6.usbdev_in_stall.3296128662 May 30 03:43:22 PM PDT 24 May 30 03:43:39 PM PDT 24 10080250579 ps
T1922 /workspace/coverage/default/16.usbdev_smoke.1992962364 May 30 03:44:26 PM PDT 24 May 30 03:44:48 PM PDT 24 10132660041 ps
T1923 /workspace/coverage/default/12.usbdev_nak_trans.276574807 May 30 03:43:58 PM PDT 24 May 30 03:44:13 PM PDT 24 10106205109 ps
T1924 /workspace/coverage/default/18.usbdev_link_suspend.1840614232 May 30 03:44:35 PM PDT 24 May 30 03:44:53 PM PDT 24 13259940720 ps
T1925 /workspace/coverage/default/38.usbdev_pkt_buffer.970041175 May 30 03:46:49 PM PDT 24 May 30 03:47:52 PM PDT 24 31457542234 ps
T1926 /workspace/coverage/default/32.usbdev_out_iso.2970733833 May 30 03:46:09 PM PDT 24 May 30 03:46:27 PM PDT 24 10107424479 ps
T1927 /workspace/coverage/default/39.usbdev_in_stall.3257483521 May 30 03:46:54 PM PDT 24 May 30 03:47:13 PM PDT 24 10056074114 ps
T1928 /workspace/coverage/default/35.usbdev_phy_pins_sense.1549415674 May 30 03:46:30 PM PDT 24 May 30 03:46:46 PM PDT 24 10040661829 ps
T1929 /workspace/coverage/default/18.usbdev_aon_wake_reset.4190394240 May 30 03:44:37 PM PDT 24 May 30 03:44:56 PM PDT 24 13272673070 ps
T1930 /workspace/coverage/default/19.usbdev_av_buffer.2053276812 May 30 03:44:35 PM PDT 24 May 30 03:44:51 PM PDT 24 10075986050 ps
T1931 /workspace/coverage/default/32.usbdev_disconnected.511848962 May 30 03:46:12 PM PDT 24 May 30 03:46:29 PM PDT 24 10055776513 ps
T1932 /workspace/coverage/default/2.usbdev_min_length_out_transaction.2289204233 May 30 03:42:28 PM PDT 24 May 30 03:42:44 PM PDT 24 10049056042 ps
T95 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4184085140 May 30 03:34:48 PM PDT 24 May 30 03:34:50 PM PDT 24 52863246 ps
T195 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3192379982 May 30 03:34:36 PM PDT 24 May 30 03:34:40 PM PDT 24 229962642 ps
T96 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4129236394 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 76132718 ps
T196 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4280466086 May 30 03:34:10 PM PDT 24 May 30 03:34:14 PM PDT 24 159990226 ps
T97 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.312708665 May 30 03:34:48 PM PDT 24 May 30 03:34:50 PM PDT 24 39963131 ps
T197 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3992391520 May 30 03:34:23 PM PDT 24 May 30 03:34:30 PM PDT 24 1421226866 ps
T202 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2086576162 May 30 03:34:52 PM PDT 24 May 30 03:34:55 PM PDT 24 86825114 ps
T209 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1305782279 May 30 03:34:31 PM PDT 24 May 30 03:34:34 PM PDT 24 81327251 ps
T199 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2237898505 May 30 03:34:45 PM PDT 24 May 30 03:34:47 PM PDT 24 101302319 ps
T201 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3693354614 May 30 03:33:59 PM PDT 24 May 30 03:34:03 PM PDT 24 340647746 ps
T204 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.506200074 May 30 03:34:59 PM PDT 24 May 30 03:35:01 PM PDT 24 44560304 ps
T205 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2064760717 May 30 03:34:19 PM PDT 24 May 30 03:34:21 PM PDT 24 138736044 ps
T266 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1341652943 May 30 03:34:57 PM PDT 24 May 30 03:34:59 PM PDT 24 38375899 ps
T1933 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1788277536 May 30 03:33:49 PM PDT 24 May 30 03:33:55 PM PDT 24 183331661 ps
T203 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3669083173 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 39551896 ps
T200 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.424493403 May 30 03:34:20 PM PDT 24 May 30 03:34:30 PM PDT 24 1407089856 ps
T262 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3124937784 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 41306796 ps
T252 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2754651565 May 30 03:34:42 PM PDT 24 May 30 03:34:45 PM PDT 24 182269007 ps
T260 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3720902929 May 30 03:34:59 PM PDT 24 May 30 03:35:01 PM PDT 24 87046513 ps
T217 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3229315056 May 30 03:34:31 PM PDT 24 May 30 03:34:33 PM PDT 24 94401065 ps
T240 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.166948860 May 30 03:34:50 PM PDT 24 May 30 03:34:52 PM PDT 24 58859657 ps
T241 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1336601064 May 30 03:34:10 PM PDT 24 May 30 03:34:13 PM PDT 24 158073249 ps
T212 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3994326171 May 30 03:34:33 PM PDT 24 May 30 03:34:36 PM PDT 24 138664916 ps
T218 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1208414097 May 30 03:34:43 PM PDT 24 May 30 03:34:47 PM PDT 24 282395027 ps
T225 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4023629060 May 30 03:34:33 PM PDT 24 May 30 03:34:35 PM PDT 24 120172817 ps
T215 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1754653363 May 30 03:34:10 PM PDT 24 May 30 03:34:14 PM PDT 24 934799195 ps
T261 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.983939862 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 38022202 ps
T224 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1442487965 May 30 03:34:47 PM PDT 24 May 30 03:34:50 PM PDT 24 87606460 ps
T223 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.308170851 May 30 03:34:23 PM PDT 24 May 30 03:34:26 PM PDT 24 163137068 ps
T216 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4014497280 May 30 03:34:20 PM PDT 24 May 30 03:34:27 PM PDT 24 1268505369 ps
T242 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3560156924 May 30 03:34:09 PM PDT 24 May 30 03:34:11 PM PDT 24 75099768 ps
T258 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1686025106 May 30 03:34:32 PM PDT 24 May 30 03:34:34 PM PDT 24 190471702 ps
T253 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1664382854 May 30 03:34:19 PM PDT 24 May 30 03:34:21 PM PDT 24 112452609 ps
T1934 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2885840537 May 30 03:33:59 PM PDT 24 May 30 03:34:01 PM PDT 24 108527206 ps
T243 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1899337199 May 30 03:33:58 PM PDT 24 May 30 03:34:00 PM PDT 24 77956146 ps
T264 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.666637532 May 30 03:34:40 PM PDT 24 May 30 03:34:42 PM PDT 24 77899391 ps
T265 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1330147043 May 30 03:34:50 PM PDT 24 May 30 03:34:52 PM PDT 24 61071244 ps
T273 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.566261486 May 30 03:34:42 PM PDT 24 May 30 03:34:48 PM PDT 24 847653419 ps
T220 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2264023834 May 30 03:34:21 PM PDT 24 May 30 03:34:26 PM PDT 24 332238419 ps
T274 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1259414477 May 30 03:34:45 PM PDT 24 May 30 03:34:49 PM PDT 24 298722327 ps
T267 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2500990103 May 30 03:34:59 PM PDT 24 May 30 03:35:01 PM PDT 24 29923584 ps
T263 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2210305214 May 30 03:34:42 PM PDT 24 May 30 03:34:44 PM PDT 24 110951715 ps
T270 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2654098801 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 46933258 ps
T244 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3222713451 May 30 03:34:47 PM PDT 24 May 30 03:34:50 PM PDT 24 73497666 ps
T271 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3112853722 May 30 03:34:22 PM PDT 24 May 30 03:34:24 PM PDT 24 54779034 ps
T245 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.628156350 May 30 03:34:33 PM PDT 24 May 30 03:34:35 PM PDT 24 54741280 ps
T246 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3995669584 May 30 03:34:47 PM PDT 24 May 30 03:34:50 PM PDT 24 55795182 ps
T247 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2968875738 May 30 03:34:10 PM PDT 24 May 30 03:34:17 PM PDT 24 742983136 ps
T259 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3565961219 May 30 03:34:45 PM PDT 24 May 30 03:34:52 PM PDT 24 1255419757 ps
T254 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3393470782 May 30 03:34:48 PM PDT 24 May 30 03:34:51 PM PDT 24 64921099 ps
T1935 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3272237982 May 30 03:34:51 PM PDT 24 May 30 03:34:54 PM PDT 24 100807822 ps
T255 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.58273361 May 30 03:34:43 PM PDT 24 May 30 03:34:46 PM PDT 24 110382765 ps
T277 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.401027737 May 30 03:34:10 PM PDT 24 May 30 03:34:15 PM PDT 24 601352184 ps
T1936 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3910253822 May 30 03:34:51 PM PDT 24 May 30 03:34:54 PM PDT 24 48421041 ps
T1937 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.568295583 May 30 03:34:10 PM PDT 24 May 30 03:34:15 PM PDT 24 256314111 ps
T248 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3492439440 May 30 03:34:42 PM PDT 24 May 30 03:34:44 PM PDT 24 83215677 ps
T221 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1712804579 May 30 03:34:20 PM PDT 24 May 30 03:34:23 PM PDT 24 169174051 ps
T1938 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3845036415 May 30 03:34:48 PM PDT 24 May 30 03:34:51 PM PDT 24 65226795 ps
T222 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4009874632 May 30 03:34:34 PM PDT 24 May 30 03:34:38 PM PDT 24 130642504 ps
T249 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3941112723 May 30 03:33:58 PM PDT 24 May 30 03:34:01 PM PDT 24 84547819 ps
T268 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2976758688 May 30 03:34:59 PM PDT 24 May 30 03:35:01 PM PDT 24 55837879 ps
T1939 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1574338966 May 30 03:34:49 PM PDT 24 May 30 03:34:52 PM PDT 24 112869939 ps
T1940 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.655213459 May 30 03:34:21 PM PDT 24 May 30 03:34:23 PM PDT 24 104586982 ps
T250 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2723739070 May 30 03:34:08 PM PDT 24 May 30 03:34:12 PM PDT 24 203618127 ps
T251 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2730905663 May 30 03:34:20 PM PDT 24 May 30 03:34:25 PM PDT 24 142403861 ps
T1941 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1202848553 May 30 03:34:49 PM PDT 24 May 30 03:34:54 PM PDT 24 273364350 ps
T1942 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.4225705933 May 30 03:34:42 PM PDT 24 May 30 03:34:45 PM PDT 24 157345628 ps
T272 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4154278826 May 30 03:34:34 PM PDT 24 May 30 03:34:36 PM PDT 24 74234423 ps
T1943 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.34901552 May 30 03:33:51 PM PDT 24 May 30 03:33:54 PM PDT 24 106403678 ps
T1944 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.125065461 May 30 03:34:09 PM PDT 24 May 30 03:34:11 PM PDT 24 43015903 ps
T1945 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1893348044 May 30 03:34:19 PM PDT 24 May 30 03:34:25 PM PDT 24 1185773691 ps
T1946 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3904007280 May 30 03:34:59 PM PDT 24 May 30 03:35:01 PM PDT 24 78146877 ps
T1947 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.340910322 May 30 03:34:19 PM PDT 24 May 30 03:34:21 PM PDT 24 210203886 ps
T1948 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1830945779 May 30 03:34:32 PM PDT 24 May 30 03:34:36 PM PDT 24 782796731 ps
T1949 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2236496750 May 30 03:34:48 PM PDT 24 May 30 03:34:50 PM PDT 24 71178125 ps
T1950 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3082670047 May 30 03:34:57 PM PDT 24 May 30 03:34:59 PM PDT 24 44453268 ps
T1951 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.291715264 May 30 03:34:57 PM PDT 24 May 30 03:34:59 PM PDT 24 29538910 ps
T1952 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1243018534 May 30 03:34:23 PM PDT 24 May 30 03:34:25 PM PDT 24 80254458 ps
T1953 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1751471531 May 30 03:34:49 PM PDT 24 May 30 03:34:51 PM PDT 24 61358186 ps
T1954 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1847448763 May 30 03:34:45 PM PDT 24 May 30 03:34:47 PM PDT 24 76409765 ps
T1955 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3198609457 May 30 03:34:10 PM PDT 24 May 30 03:34:12 PM PDT 24 275861161 ps
T1956 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.742731705 May 30 03:34:36 PM PDT 24 May 30 03:34:38 PM PDT 24 86234929 ps
T1957 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2028977580 May 30 03:34:59 PM PDT 24 May 30 03:35:02 PM PDT 24 35113105 ps
T1958 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1463449392 May 30 03:34:54 PM PDT 24 May 30 03:34:57 PM PDT 24 196409024 ps
T1959 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3100402506 May 30 03:34:45 PM PDT 24 May 30 03:34:47 PM PDT 24 46815446 ps
T1960 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2086925439 May 30 03:33:58 PM PDT 24 May 30 03:34:07 PM PDT 24 650096678 ps
T1961 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1785475327 May 30 03:34:10 PM PDT 24 May 30 03:34:14 PM PDT 24 80847643 ps
T1962 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.472938340 May 30 03:34:34 PM PDT 24 May 30 03:34:36 PM PDT 24 126074108 ps
T1963 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1743481911 May 30 03:34:47 PM PDT 24 May 30 03:34:50 PM PDT 24 96463403 ps
T1964 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.363422680 May 30 03:34:21 PM PDT 24 May 30 03:34:23 PM PDT 24 114609584 ps
T1965 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1927444564 May 30 03:34:09 PM PDT 24 May 30 03:34:12 PM PDT 24 77151708 ps
T1966 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2116326911 May 30 03:34:11 PM PDT 24 May 30 03:34:14 PM PDT 24 85357636 ps
T275 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3539605958 May 30 03:34:55 PM PDT 24 May 30 03:35:00 PM PDT 24 507382677 ps
T1967 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2643002860 May 30 03:34:32 PM PDT 24 May 30 03:34:34 PM PDT 24 78065917 ps
T1968 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2046703762 May 30 03:34:51 PM PDT 24 May 30 03:34:55 PM PDT 24 229628971 ps
T281 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2638771008 May 30 03:34:49 PM PDT 24 May 30 03:34:56 PM PDT 24 1077463756 ps
T1969 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1873595405 May 30 03:34:41 PM PDT 24 May 30 03:34:43 PM PDT 24 84352123 ps
T1970 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.235172712 May 30 03:34:09 PM PDT 24 May 30 03:34:12 PM PDT 24 71252848 ps
T276 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3051706588 May 30 03:34:34 PM PDT 24 May 30 03:34:38 PM PDT 24 1009529323 ps
T1971 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.479099870 May 30 03:34:31 PM PDT 24 May 30 03:34:33 PM PDT 24 39074210 ps
T1972 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1275022543 May 30 03:34:09 PM PDT 24 May 30 03:34:12 PM PDT 24 164611227 ps
T1973 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4132232945 May 30 03:34:21 PM PDT 24 May 30 03:34:23 PM PDT 24 122644541 ps
T1974 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3691866323 May 30 03:34:49 PM PDT 24 May 30 03:34:51 PM PDT 24 47106178 ps
T1975 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2761116784 May 30 03:34:47 PM PDT 24 May 30 03:34:54 PM PDT 24 1034585933 ps
T1976 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.365231585 May 30 03:33:59 PM PDT 24 May 30 03:34:03 PM PDT 24 780408552 ps
T1977 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.726512596 May 30 03:34:41 PM PDT 24 May 30 03:34:43 PM PDT 24 109816216 ps
T1978 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.352572879 May 30 03:34:35 PM PDT 24 May 30 03:34:37 PM PDT 24 73780082 ps
T1979 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3660012603 May 30 03:34:45 PM PDT 24 May 30 03:34:50 PM PDT 24 531216081 ps
T1980 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3473540476 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 33879857 ps
T278 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1459171909 May 30 03:34:21 PM PDT 24 May 30 03:34:27 PM PDT 24 832002685 ps
T280 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.801580600 May 30 03:34:36 PM PDT 24 May 30 03:34:43 PM PDT 24 827441826 ps
T1981 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.64754453 May 30 03:34:21 PM PDT 24 May 30 03:34:24 PM PDT 24 108111578 ps
T1982 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.9093762 May 30 03:34:47 PM PDT 24 May 30 03:34:49 PM PDT 24 49681571 ps
T1983 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.484473453 May 30 03:34:42 PM PDT 24 May 30 03:34:46 PM PDT 24 243414382 ps
T1984 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3453608376 May 30 03:33:59 PM PDT 24 May 30 03:34:00 PM PDT 24 50122583 ps
T1985 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.40656408 May 30 03:34:21 PM PDT 24 May 30 03:34:23 PM PDT 24 39841544 ps
T1986 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4184530041 May 30 03:34:21 PM PDT 24 May 30 03:34:26 PM PDT 24 173021755 ps
T1987 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1066727929 May 30 03:34:41 PM PDT 24 May 30 03:34:43 PM PDT 24 174532243 ps
T1988 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1529966753 May 30 03:34:49 PM PDT 24 May 30 03:34:52 PM PDT 24 69952673 ps
T1989 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.400608300 May 30 03:33:50 PM PDT 24 May 30 03:33:52 PM PDT 24 33582928 ps
T1990 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1935779992 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 53054557 ps
T1991 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1558790632 May 30 03:34:10 PM PDT 24 May 30 03:34:16 PM PDT 24 836764531 ps
T1992 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2154317925 May 30 03:34:32 PM PDT 24 May 30 03:34:34 PM PDT 24 71070468 ps
T1993 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2241202151 May 30 03:33:49 PM PDT 24 May 30 03:33:53 PM PDT 24 199894911 ps
T1994 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.80949860 May 30 03:34:20 PM PDT 24 May 30 03:34:24 PM PDT 24 291579112 ps
T1995 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3875659951 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 48030516 ps
T1996 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.765549401 May 30 03:34:34 PM PDT 24 May 30 03:34:37 PM PDT 24 149883004 ps
T1997 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2221252090 May 30 03:34:51 PM PDT 24 May 30 03:34:55 PM PDT 24 157253443 ps
T1998 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2824950590 May 30 03:34:41 PM PDT 24 May 30 03:34:44 PM PDT 24 88907108 ps
T1999 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.483451370 May 30 03:34:42 PM PDT 24 May 30 03:34:45 PM PDT 24 261734784 ps
T2000 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.622535826 May 30 03:34:42 PM PDT 24 May 30 03:34:45 PM PDT 24 139050150 ps
T2001 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1195829182 May 30 03:34:45 PM PDT 24 May 30 03:34:47 PM PDT 24 58419465 ps
T2002 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3087510187 May 30 03:34:10 PM PDT 24 May 30 03:34:16 PM PDT 24 223871911 ps
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