Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.57 97.44 91.93 97.86 70.31 95.72 98.17 96.58


Total test records in report: 2042
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T2003 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1574078745 May 30 03:34:42 PM PDT 24 May 30 03:34:44 PM PDT 24 38474358 ps
T2004 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2378979605 May 30 03:34:42 PM PDT 24 May 30 03:34:46 PM PDT 24 125646958 ps
T2005 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1473857640 May 30 03:34:50 PM PDT 24 May 30 03:34:53 PM PDT 24 74820726 ps
T2006 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.816641494 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 41968530 ps
T2007 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.873985257 May 30 03:34:49 PM PDT 24 May 30 03:34:53 PM PDT 24 115026515 ps
T2008 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2240400651 May 30 03:34:20 PM PDT 24 May 30 03:34:23 PM PDT 24 108087420 ps
T2009 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2506693716 May 30 03:34:19 PM PDT 24 May 30 03:34:21 PM PDT 24 72967564 ps
T2010 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1250835885 May 30 03:34:34 PM PDT 24 May 30 03:34:39 PM PDT 24 503069015 ps
T2011 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3452682065 May 30 03:34:57 PM PDT 24 May 30 03:34:59 PM PDT 24 43863681 ps
T2012 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2313841471 May 30 03:34:21 PM PDT 24 May 30 03:34:23 PM PDT 24 72742521 ps
T2013 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2267842890 May 30 03:34:00 PM PDT 24 May 30 03:34:02 PM PDT 24 171939461 ps
T2014 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2390609443 May 30 03:34:20 PM PDT 24 May 30 03:34:22 PM PDT 24 57466473 ps
T2015 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3997839098 May 30 03:34:19 PM PDT 24 May 30 03:34:23 PM PDT 24 82504207 ps
T2016 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1589544289 May 30 03:34:49 PM PDT 24 May 30 03:34:53 PM PDT 24 93290557 ps
T2017 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.593458322 May 30 03:34:10 PM PDT 24 May 30 03:34:12 PM PDT 24 88175867 ps
T2018 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2804364316 May 30 03:33:50 PM PDT 24 May 30 03:33:54 PM PDT 24 400756237 ps
T2019 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2904695028 May 30 03:34:32 PM PDT 24 May 30 03:34:34 PM PDT 24 43540340 ps
T2020 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2638066685 May 30 03:35:06 PM PDT 24 May 30 03:35:08 PM PDT 24 38992623 ps
T2021 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2313099624 May 30 03:34:51 PM PDT 24 May 30 03:34:54 PM PDT 24 50151223 ps
T2022 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3627608576 May 30 03:34:40 PM PDT 24 May 30 03:34:44 PM PDT 24 102902716 ps
T2023 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2070854106 May 30 03:34:10 PM PDT 24 May 30 03:34:13 PM PDT 24 142993067 ps
T2024 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1012817041 May 30 03:34:20 PM PDT 24 May 30 03:34:23 PM PDT 24 108328057 ps
T2025 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1456686932 May 30 03:34:57 PM PDT 24 May 30 03:34:59 PM PDT 24 67967107 ps
T2026 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.791418384 May 30 03:35:06 PM PDT 24 May 30 03:35:08 PM PDT 24 53066159 ps
T2027 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1853422185 May 30 03:34:09 PM PDT 24 May 30 03:34:12 PM PDT 24 186033877 ps
T282 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1610207618 May 30 03:34:47 PM PDT 24 May 30 03:34:53 PM PDT 24 678217782 ps
T2028 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2985224692 May 30 03:34:21 PM PDT 24 May 30 03:34:23 PM PDT 24 55195888 ps
T2029 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2324548437 May 30 03:33:58 PM PDT 24 May 30 03:34:03 PM PDT 24 167202709 ps
T2030 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4154725909 May 30 03:34:45 PM PDT 24 May 30 03:34:48 PM PDT 24 125945446 ps
T2031 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2964291509 May 30 03:34:58 PM PDT 24 May 30 03:35:00 PM PDT 24 72102545 ps
T2032 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1473636297 May 30 03:33:58 PM PDT 24 May 30 03:34:02 PM PDT 24 152343098 ps
T2033 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.390882155 May 30 03:34:41 PM PDT 24 May 30 03:34:43 PM PDT 24 73704300 ps
T2034 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.683102035 May 30 03:34:46 PM PDT 24 May 30 03:34:49 PM PDT 24 199811482 ps
T2035 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1476116138 May 30 03:34:30 PM PDT 24 May 30 03:34:32 PM PDT 24 122793133 ps
T2036 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3100934170 May 30 03:34:11 PM PDT 24 May 30 03:34:13 PM PDT 24 89471249 ps
T2037 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.67290937 May 30 03:33:59 PM PDT 24 May 30 03:34:02 PM PDT 24 59098233 ps
T2038 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3596542851 May 30 03:34:49 PM PDT 24 May 30 03:34:53 PM PDT 24 69768232 ps
T2039 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4234076403 May 30 03:34:09 PM PDT 24 May 30 03:34:14 PM PDT 24 120094836 ps
T2040 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.154628970 May 30 03:34:41 PM PDT 24 May 30 03:34:44 PM PDT 24 67049187 ps
T279 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3868096201 May 30 03:34:42 PM PDT 24 May 30 03:34:49 PM PDT 24 966298866 ps
T2041 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.691327674 May 30 03:34:57 PM PDT 24 May 30 03:34:59 PM PDT 24 43055133 ps
T2042 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1119640453 May 30 03:34:42 PM PDT 24 May 30 03:34:48 PM PDT 24 328322877 ps

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.469885103
Short name T2
Test name
Test status
Simulation time 31489346154 ps
CPU time 58.51 seconds
Started May 30 03:47:24 PM PDT 24
Finished May 30 03:48:27 PM PDT 24
Peak memory 205620 kb
Host smart-4b1aeeae-e056-4402-9deb-ac1c660dafe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46988
5103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.469885103
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4129236394
Short name T96
Test name
Test status
Simulation time 76132718 ps
CPU time 0.71 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204196 kb
Host smart-8b97d7f4-41ea-4ab2-80c6-9a3368c9cae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4129236394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4129236394
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.392691317
Short name T5
Test name
Test status
Simulation time 13323587639 ps
CPU time 17.82 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:46 PM PDT 24
Peak memory 205272 kb
Host smart-6b04d4d5-8a2a-4354-a829-e858ad42dba5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=392691317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.392691317
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3992391520
Short name T197
Test name
Test status
Simulation time 1421226866 ps
CPU time 5.72 seconds
Started May 30 03:34:23 PM PDT 24
Finished May 30 03:34:30 PM PDT 24
Peak memory 204476 kb
Host smart-9b05c3ab-a8ef-49af-a242-b7cf0e07b3f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3992391520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3992391520
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/23.usbdev_smoke.968620434
Short name T25
Test name
Test status
Simulation time 10146072593 ps
CPU time 13.27 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:20 PM PDT 24
Peak memory 205536 kb
Host smart-bbfc5ebf-410e-4eb7-8f9c-3e1c213e0d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96862
0434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.968620434
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.1759275786
Short name T15
Test name
Test status
Simulation time 10090794913 ps
CPU time 13.17 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205540 kb
Host smart-755a551c-7aa9-480c-b523-67581a100f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17592
75786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1759275786
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1330147043
Short name T265
Test name
Test status
Simulation time 61071244 ps
CPU time 0.71 seconds
Started May 30 03:34:50 PM PDT 24
Finished May 30 03:34:52 PM PDT 24
Peak memory 204152 kb
Host smart-456875f7-4ba4-42a5-a327-ea0f634b1b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1330147043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1330147043
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2642603938
Short name T285
Test name
Test status
Simulation time 10132487085 ps
CPU time 13.19 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205504 kb
Host smart-c517a1ac-838a-4270-bed6-e401762dd559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26426
03938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2642603938
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.58665504
Short name T40
Test name
Test status
Simulation time 10042839517 ps
CPU time 12.73 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:10 PM PDT 24
Peak memory 205572 kb
Host smart-59ce0a05-5713-4692-8c9d-5427ad4f13b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58665
504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.58665504
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2127195701
Short name T66
Test name
Test status
Simulation time 10043491818 ps
CPU time 12.87 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 204928 kb
Host smart-f87085a9-896e-48d4-83b8-03015dfa8ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21271
95701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2127195701
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2006180493
Short name T71
Test name
Test status
Simulation time 10063798966 ps
CPU time 12.81 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205516 kb
Host smart-7a222ef1-0303-42a7-938b-e81882fe0de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20061
80493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2006180493
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3287913517
Short name T11
Test name
Test status
Simulation time 13326668702 ps
CPU time 17.3 seconds
Started May 30 03:44:53 PM PDT 24
Finished May 30 03:45:14 PM PDT 24
Peak memory 205580 kb
Host smart-3a7fa69d-72aa-480a-94d7-f692a71fe2c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3287913517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.3287913517
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3192379982
Short name T195
Test name
Test status
Simulation time 229962642 ps
CPU time 2.55 seconds
Started May 30 03:34:36 PM PDT 24
Finished May 30 03:34:40 PM PDT 24
Peak memory 220056 kb
Host smart-ef05536c-160c-4d7b-bd42-76314a808ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192379982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3192379982
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1761304096
Short name T23
Test name
Test status
Simulation time 10054465405 ps
CPU time 13.35 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205536 kb
Host smart-86ac062b-4cbc-4c29-b60b-0c43e8d50648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
04096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1761304096
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3257662215
Short name T56
Test name
Test status
Simulation time 10717426133 ps
CPU time 15.36 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:13 PM PDT 24
Peak memory 205604 kb
Host smart-6ace5890-362e-4b32-96ae-9b00030ce4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32576
62215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3257662215
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3720902929
Short name T260
Test name
Test status
Simulation time 87046513 ps
CPU time 0.72 seconds
Started May 30 03:34:59 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 204160 kb
Host smart-0d1adcd4-08a7-477d-9627-b0247601b9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3720902929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3720902929
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1817989332
Short name T72
Test name
Test status
Simulation time 10080428334 ps
CPU time 16.51 seconds
Started May 30 03:43:51 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205552 kb
Host smart-696478fd-838e-4ab0-b211-1e8e0068660a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18179
89332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1817989332
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.4099768714
Short name T192
Test name
Test status
Simulation time 723651808 ps
CPU time 1.72 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 221732 kb
Host smart-81039e03-95f6-4910-93de-f1d2895185e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4099768714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4099768714
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.151469821
Short name T342
Test name
Test status
Simulation time 10340740387 ps
CPU time 17.04 seconds
Started May 30 03:43:50 PM PDT 24
Finished May 30 03:44:10 PM PDT 24
Peak memory 205552 kb
Host smart-3fc03399-998c-4c8e-8a54-6bb43a43aac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
9821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.151469821
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2200639543
Short name T4
Test name
Test status
Simulation time 13349338649 ps
CPU time 16.6 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205564 kb
Host smart-93bb5eca-05db-42dc-beaf-fbd00e90d140
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2200639543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2200639543
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1899337199
Short name T243
Test name
Test status
Simulation time 77956146 ps
CPU time 1 seconds
Started May 30 03:33:58 PM PDT 24
Finished May 30 03:34:00 PM PDT 24
Peak memory 204588 kb
Host smart-3dc252ed-c5c9-431e-8f97-cd0f0fc576b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1899337199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1899337199
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.983939862
Short name T261
Test name
Test status
Simulation time 38022202 ps
CPU time 0.64 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204200 kb
Host smart-0db51ef3-aa1f-4d0b-88ee-625ac9e4b5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=983939862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.983939862
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1715975180
Short name T50
Test name
Test status
Simulation time 10083067604 ps
CPU time 14.48 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205564 kb
Host smart-dc1ee2f5-8ef2-4ba0-b8c4-50e2e5c5d406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159
75180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1715975180
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.566261486
Short name T273
Test name
Test status
Simulation time 847653419 ps
CPU time 4.7 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:48 PM PDT 24
Peak memory 204604 kb
Host smart-09e16b16-03a1-4aba-9c99-6426c589eb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=566261486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.566261486
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.666637532
Short name T264
Test name
Test status
Simulation time 77899391 ps
CPU time 0.7 seconds
Started May 30 03:34:40 PM PDT 24
Finished May 30 03:34:42 PM PDT 24
Peak memory 204216 kb
Host smart-75a441c3-67d4-44e9-a563-3c03cd918970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=666637532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.666637532
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/15.usbdev_enable.1535385789
Short name T333
Test name
Test status
Simulation time 10057864242 ps
CPU time 15.82 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205580 kb
Host smart-4cd75bd2-65cc-4707-94b2-71d7361b76d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15353
85789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1535385789
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.801580600
Short name T280
Test name
Test status
Simulation time 827441826 ps
CPU time 5.62 seconds
Started May 30 03:34:36 PM PDT 24
Finished May 30 03:34:43 PM PDT 24
Peak memory 204160 kb
Host smart-0fa03cf3-8d16-4eb9-9bdb-8ef5b5caffeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=801580600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.801580600
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4001451525
Short name T12
Test name
Test status
Simulation time 14191241115 ps
CPU time 16.59 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:33 PM PDT 24
Peak memory 205500 kb
Host smart-b9d5b36e-564a-40e1-bda3-14742b2dc4ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4001451525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.4001451525
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.369993251
Short name T184
Test name
Test status
Simulation time 31015995505 ps
CPU time 59.86 seconds
Started May 30 03:45:54 PM PDT 24
Finished May 30 03:46:57 PM PDT 24
Peak memory 205576 kb
Host smart-193b03ed-bc64-40a0-9237-7b5219e20404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999
3251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.369993251
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3609702638
Short name T208
Test name
Test status
Simulation time 5138383775 ps
CPU time 41.37 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:54 PM PDT 24
Peak memory 205584 kb
Host smart-03066f4a-90c4-4f11-9bde-7cd84e199021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36097
02638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3609702638
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2138500613
Short name T448
Test name
Test status
Simulation time 10044553681 ps
CPU time 13.52 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205484 kb
Host smart-34a954b9-db3c-41cd-83b8-19704c8e2be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21385
00613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2138500613
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3868096201
Short name T279
Test name
Test status
Simulation time 966298866 ps
CPU time 4.84 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:49 PM PDT 24
Peak memory 204540 kb
Host smart-d61ca154-c998-4b2f-95ac-6d55c22da23d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3868096201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3868096201
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2559467628
Short name T125
Test name
Test status
Simulation time 10764569741 ps
CPU time 14.28 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:17 PM PDT 24
Peak memory 205552 kb
Host smart-d2509db5-155c-44db-a06a-f795b42dd2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594
67628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2559467628
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3081314886
Short name T145
Test name
Test status
Simulation time 10066290677 ps
CPU time 13.34 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205572 kb
Host smart-21888849-eb52-4654-952b-1cc8168fe556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30813
14886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3081314886
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.1512381705
Short name T189
Test name
Test status
Simulation time 13275667440 ps
CPU time 16.84 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205520 kb
Host smart-76752b56-7659-4a94-a86e-9c1615a7af78
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1512381705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.1512381705
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.34901552
Short name T1943
Test name
Test status
Simulation time 106403678 ps
CPU time 2.54 seconds
Started May 30 03:33:51 PM PDT 24
Finished May 30 03:33:54 PM PDT 24
Peak memory 204636 kb
Host smart-7fbeee61-1582-4a44-8408-f147f3f398de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=34901552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.34901552
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3019952801
Short name T143
Test name
Test status
Simulation time 10101931348 ps
CPU time 12.43 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205528 kb
Host smart-a31fe5f2-2359-43ca-82d2-5494bc9345e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30199
52801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3019952801
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.4009246605
Short name T372
Test name
Test status
Simulation time 10088053807 ps
CPU time 13.24 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205544 kb
Host smart-aa846ebc-a9a7-463d-b70d-2fb756fec6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40092
46605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.4009246605
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1182031589
Short name T165
Test name
Test status
Simulation time 10065817908 ps
CPU time 14.01 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205540 kb
Host smart-884eb85c-7e32-4472-bf0c-caf243636690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
31589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1182031589
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2686780716
Short name T183
Test name
Test status
Simulation time 10097311251 ps
CPU time 17.07 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:45:01 PM PDT 24
Peak memory 205596 kb
Host smart-f5c15337-01b1-47ee-9175-4adb540abdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26867
80716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2686780716
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1612683642
Short name T176
Test name
Test status
Simulation time 10119824610 ps
CPU time 13.87 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205604 kb
Host smart-8f7d20d5-ff74-4f8b-a605-bc049b5a4d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16126
83642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1612683642
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.645817265
Short name T88
Test name
Test status
Simulation time 10144719746 ps
CPU time 15.47 seconds
Started May 30 03:42:25 PM PDT 24
Finished May 30 03:42:42 PM PDT 24
Peak memory 205572 kb
Host smart-91c4dd33-b748-4032-969c-08f903111ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64581
7265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.645817265
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2980216629
Short name T188
Test name
Test status
Simulation time 10066193140 ps
CPU time 13.35 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:56 PM PDT 24
Peak memory 205588 kb
Host smart-12b3960e-364e-4c0b-9fa2-58daceb96381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29802
16629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2980216629
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1735645877
Short name T187
Test name
Test status
Simulation time 10056475891 ps
CPU time 13.52 seconds
Started May 30 03:46:03 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205552 kb
Host smart-2130f354-fa91-4cd1-a1c1-e2fdad626f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17356
45877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1735645877
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1005972751
Short name T172
Test name
Test status
Simulation time 10064456207 ps
CPU time 14.08 seconds
Started May 30 03:47:01 PM PDT 24
Finished May 30 03:47:19 PM PDT 24
Peak memory 205484 kb
Host smart-62fe0fb1-b65c-4a63-9fed-c5ade5868580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10059
72751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1005972751
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2538485409
Short name T152
Test name
Test status
Simulation time 10067782011 ps
CPU time 13.36 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:48 PM PDT 24
Peak memory 205588 kb
Host smart-5adae31c-ab06-4a6e-a75f-7e6456c8da17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
85409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2538485409
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.617152556
Short name T16
Test name
Test status
Simulation time 10066118874 ps
CPU time 15.03 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205572 kb
Host smart-ad3da5fc-337b-4115-a67b-6fb81dd7e5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61715
2556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.617152556
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.965922400
Short name T257
Test name
Test status
Simulation time 30767789842 ps
CPU time 57.36 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:43:12 PM PDT 24
Peak memory 205636 kb
Host smart-ef198391-864f-4853-a7b9-3295ef4f9261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96592
2400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.965922400
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3334475579
Short name T24
Test name
Test status
Simulation time 10050854023 ps
CPU time 16.15 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205496 kb
Host smart-fd972706-36a0-4f03-a984-49e806823997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
75579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3334475579
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2517469030
Short name T55
Test name
Test status
Simulation time 10096663412 ps
CPU time 12.78 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205568 kb
Host smart-b2ee0f7b-660b-44b5-ba46-e2a03edf68a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
69030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2517469030
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1725685502
Short name T48
Test name
Test status
Simulation time 13245270745 ps
CPU time 18.1 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:48 PM PDT 24
Peak memory 205548 kb
Host smart-62847952-9a12-4921-bc3b-f351565e67dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1725685502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1725685502
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3111803139
Short name T1627
Test name
Test status
Simulation time 31646722998 ps
CPU time 62.63 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:46:45 PM PDT 24
Peak memory 205608 kb
Host smart-64767a17-5e1a-4858-aadc-05aa6798cf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31118
03139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3111803139
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.239910354
Short name T102
Test name
Test status
Simulation time 10096596883 ps
CPU time 13.69 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:27 PM PDT 24
Peak memory 205544 kb
Host smart-13e35c5e-bd31-4571-b1af-6233af0f0750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23991
0354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.239910354
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3499321593
Short name T1397
Test name
Test status
Simulation time 10084120326 ps
CPU time 15.21 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:34 PM PDT 24
Peak memory 205572 kb
Host smart-b901f066-1eb1-453b-9c5c-2c38e07b730d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34993
21593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3499321593
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.254105215
Short name T103
Test name
Test status
Simulation time 10110828280 ps
CPU time 15.1 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205472 kb
Host smart-10a7a626-ddec-4088-99ba-bb4c090099bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
5215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.254105215
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.4160309883
Short name T132
Test name
Test status
Simulation time 10067957067 ps
CPU time 13.02 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205536 kb
Host smart-19e806d2-b861-438d-92b6-8d2c103c0597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
09883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.4160309883
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2661263150
Short name T106
Test name
Test status
Simulation time 10084883521 ps
CPU time 13.86 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205572 kb
Host smart-b31ea07f-99d4-4a0d-bbbd-8d702b58f257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26612
63150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2661263150
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.276574807
Short name T1923
Test name
Test status
Simulation time 10106205109 ps
CPU time 13.36 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205300 kb
Host smart-5d63b492-73e1-4ad0-95c1-cfcaf0023fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
4807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.276574807
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1371479332
Short name T91
Test name
Test status
Simulation time 31342838917 ps
CPU time 60.71 seconds
Started May 30 03:44:06 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205640 kb
Host smart-037564d9-4f24-4b37-b460-bbca0faff31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
79332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1371479332
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1699841729
Short name T119
Test name
Test status
Simulation time 10132773469 ps
CPU time 13.82 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:37 PM PDT 24
Peak memory 205576 kb
Host smart-c7efbcbf-4726-48c7-a137-8d13b4a516cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
41729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1699841729
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.540899440
Short name T98
Test name
Test status
Simulation time 10077526685 ps
CPU time 13.6 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:42 PM PDT 24
Peak memory 205588 kb
Host smart-2c835785-febb-47ea-b451-faed0d26ce02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54089
9440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.540899440
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2548902428
Short name T123
Test name
Test status
Simulation time 10179834996 ps
CPU time 14.25 seconds
Started May 30 03:44:42 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205560 kb
Host smart-a45ef251-27d2-4b47-924b-5e813491179c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25489
02428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2548902428
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4142992458
Short name T110
Test name
Test status
Simulation time 10124504469 ps
CPU time 13.27 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205524 kb
Host smart-53898431-58d3-46d0-881e-a6e2191591ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41429
92458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4142992458
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1129238432
Short name T168
Test name
Test status
Simulation time 10068021073 ps
CPU time 13.1 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:16 PM PDT 24
Peak memory 205576 kb
Host smart-a26f995a-5b95-446d-bb77-0040c184fc83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292
38432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1129238432
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3739023290
Short name T1639
Test name
Test status
Simulation time 10150975358 ps
CPU time 15.15 seconds
Started May 30 03:45:46 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205544 kb
Host smart-2bd80c82-4a1e-4591-af99-7c8844c45aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37390
23290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3739023290
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3693354614
Short name T201
Test name
Test status
Simulation time 340647746 ps
CPU time 3.63 seconds
Started May 30 03:33:59 PM PDT 24
Finished May 30 03:34:03 PM PDT 24
Peak memory 204564 kb
Host smart-ca8b6afc-9881-452b-87cf-97f89a6d0520
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3693354614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3693354614
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2086925439
Short name T1960
Test name
Test status
Simulation time 650096678 ps
CPU time 7.56 seconds
Started May 30 03:33:58 PM PDT 24
Finished May 30 03:34:07 PM PDT 24
Peak memory 204564 kb
Host smart-4b3f9218-8af5-4850-bb84-48656d62b8f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2086925439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2086925439
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2267842890
Short name T2013
Test name
Test status
Simulation time 171939461 ps
CPU time 0.87 seconds
Started May 30 03:34:00 PM PDT 24
Finished May 30 03:34:02 PM PDT 24
Peak memory 204240 kb
Host smart-8e477fd0-ff70-4c81-a5de-5383b716697b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2267842890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2267842890
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2885840537
Short name T1934
Test name
Test status
Simulation time 108527206 ps
CPU time 1.44 seconds
Started May 30 03:33:59 PM PDT 24
Finished May 30 03:34:01 PM PDT 24
Peak memory 220836 kb
Host smart-dceb725d-b743-4074-b463-c3d58fc166e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885840537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2885840537
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.400608300
Short name T1989
Test name
Test status
Simulation time 33582928 ps
CPU time 0.65 seconds
Started May 30 03:33:50 PM PDT 24
Finished May 30 03:33:52 PM PDT 24
Peak memory 204212 kb
Host smart-38ae9226-3c0e-41c7-a811-94723d63b1d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=400608300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.400608300
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2241202151
Short name T1993
Test name
Test status
Simulation time 199894911 ps
CPU time 2.39 seconds
Started May 30 03:33:49 PM PDT 24
Finished May 30 03:33:53 PM PDT 24
Peak memory 212660 kb
Host smart-c215b4ea-d27a-46ca-aab2-5c728179f6f3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2241202151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2241202151
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1788277536
Short name T1933
Test name
Test status
Simulation time 183331661 ps
CPU time 4.04 seconds
Started May 30 03:33:49 PM PDT 24
Finished May 30 03:33:55 PM PDT 24
Peak memory 204444 kb
Host smart-4f1c12fa-b1d1-430b-a6c9-9d2af003fb3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1788277536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1788277536
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.67290937
Short name T2037
Test name
Test status
Simulation time 59098233 ps
CPU time 1.02 seconds
Started May 30 03:33:59 PM PDT 24
Finished May 30 03:34:02 PM PDT 24
Peak memory 204584 kb
Host smart-59f0f520-fdb8-4870-ad97-f26bfac137b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=67290937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.67290937
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2804364316
Short name T2018
Test name
Test status
Simulation time 400756237 ps
CPU time 2.78 seconds
Started May 30 03:33:50 PM PDT 24
Finished May 30 03:33:54 PM PDT 24
Peak memory 204512 kb
Host smart-d628063f-d661-4c21-b244-669d94e35046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2804364316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2804364316
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4234076403
Short name T2039
Test name
Test status
Simulation time 120094836 ps
CPU time 3.2 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:14 PM PDT 24
Peak memory 204644 kb
Host smart-7c688dd4-4e0b-477a-9d38-4ac386d08b85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4234076403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4234076403
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1558790632
Short name T1991
Test name
Test status
Simulation time 836764531 ps
CPU time 5.12 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:16 PM PDT 24
Peak memory 204540 kb
Host smart-6c5e85a8-65b1-4c69-a1ec-c16982eea2a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1558790632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1558790632
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1336601064
Short name T241
Test name
Test status
Simulation time 158073249 ps
CPU time 0.87 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:13 PM PDT 24
Peak memory 204264 kb
Host smart-6ef9ac5a-cdc8-4378-9d62-b88b7ef6c2bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1336601064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1336601064
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2070854106
Short name T2023
Test name
Test status
Simulation time 142993067 ps
CPU time 1.35 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:13 PM PDT 24
Peak memory 212812 kb
Host smart-bf20c1e6-1647-4e16-b0b1-de18862e6812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070854106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2070854106
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3100934170
Short name T2036
Test name
Test status
Simulation time 89471249 ps
CPU time 1.03 seconds
Started May 30 03:34:11 PM PDT 24
Finished May 30 03:34:13 PM PDT 24
Peak memory 204516 kb
Host smart-c74434d1-3a70-4cf0-b7d1-049eb35fdf4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3100934170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3100934170
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3453608376
Short name T1984
Test name
Test status
Simulation time 50122583 ps
CPU time 0.7 seconds
Started May 30 03:33:59 PM PDT 24
Finished May 30 03:34:00 PM PDT 24
Peak memory 204188 kb
Host smart-5b0980b5-ac8c-4308-bf73-44484c97ec38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3453608376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3453608376
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3941112723
Short name T249
Test name
Test status
Simulation time 84547819 ps
CPU time 2.23 seconds
Started May 30 03:33:58 PM PDT 24
Finished May 30 03:34:01 PM PDT 24
Peak memory 212736 kb
Host smart-a9483f53-1f88-4e37-ad66-4846fbd57dc2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3941112723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3941112723
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2324548437
Short name T2029
Test name
Test status
Simulation time 167202709 ps
CPU time 3.81 seconds
Started May 30 03:33:58 PM PDT 24
Finished May 30 03:34:03 PM PDT 24
Peak memory 204460 kb
Host smart-598ebec2-081b-4e5d-a4e3-e01c784434e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2324548437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2324548437
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1275022543
Short name T1972
Test name
Test status
Simulation time 164611227 ps
CPU time 1.31 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 204556 kb
Host smart-6ce05d7e-391b-4430-a7c4-2353440f3a8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1275022543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1275022543
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1473636297
Short name T2032
Test name
Test status
Simulation time 152343098 ps
CPU time 2.66 seconds
Started May 30 03:33:58 PM PDT 24
Finished May 30 03:34:02 PM PDT 24
Peak memory 220136 kb
Host smart-95c524dc-4afd-4d27-b34b-cde263cf2a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1473636297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1473636297
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.365231585
Short name T1976
Test name
Test status
Simulation time 780408552 ps
CPU time 3.01 seconds
Started May 30 03:33:59 PM PDT 24
Finished May 30 03:34:03 PM PDT 24
Peak memory 204532 kb
Host smart-e6711b40-8599-4f23-9930-8eca32c00230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=365231585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.365231585
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.484473453
Short name T1983
Test name
Test status
Simulation time 243414382 ps
CPU time 2.21 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:46 PM PDT 24
Peak memory 212764 kb
Host smart-a05c6801-eebd-4550-ac8d-538bea0f3426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484473453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde
v_csr_mem_rw_with_rand_reset.484473453
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.390882155
Short name T2033
Test name
Test status
Simulation time 73704300 ps
CPU time 0.84 seconds
Started May 30 03:34:41 PM PDT 24
Finished May 30 03:34:43 PM PDT 24
Peak memory 204292 kb
Host smart-165ea8ed-0853-4ca9-80f7-a3571fd6d37d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=390882155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.390882155
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2643002860
Short name T1967
Test name
Test status
Simulation time 78065917 ps
CPU time 0.7 seconds
Started May 30 03:34:32 PM PDT 24
Finished May 30 03:34:34 PM PDT 24
Peak memory 204172 kb
Host smart-93ae8782-9434-44a1-8109-6d9cf1fb1695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2643002860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2643002860
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1066727929
Short name T1987
Test name
Test status
Simulation time 174532243 ps
CPU time 1.75 seconds
Started May 30 03:34:41 PM PDT 24
Finished May 30 03:34:43 PM PDT 24
Peak memory 204572 kb
Host smart-92b5c8ce-07da-4259-a141-04b094f17e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1066727929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1066727929
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.4009874632
Short name T222
Test name
Test status
Simulation time 130642504 ps
CPU time 2.55 seconds
Started May 30 03:34:34 PM PDT 24
Finished May 30 03:34:38 PM PDT 24
Peak memory 220128 kb
Host smart-64b296ea-4d06-406a-8091-aa61a8cf1901
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4009874632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.4009874632
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3051706588
Short name T276
Test name
Test status
Simulation time 1009529323 ps
CPU time 3.06 seconds
Started May 30 03:34:34 PM PDT 24
Finished May 30 03:34:38 PM PDT 24
Peak memory 204508 kb
Host smart-b9ea4452-5845-47c1-9559-17ceee160510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3051706588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3051706588
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3627608576
Short name T2022
Test name
Test status
Simulation time 102902716 ps
CPU time 2.77 seconds
Started May 30 03:34:40 PM PDT 24
Finished May 30 03:34:44 PM PDT 24
Peak memory 212820 kb
Host smart-b7057711-0418-4292-86dc-fc539282be2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627608576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3627608576
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1574078745
Short name T2003
Test name
Test status
Simulation time 38474358 ps
CPU time 0.83 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:44 PM PDT 24
Peak memory 204356 kb
Host smart-58e37060-e998-41a1-92ea-47ac2c82f42b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1574078745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1574078745
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.726512596
Short name T1977
Test name
Test status
Simulation time 109816216 ps
CPU time 0.76 seconds
Started May 30 03:34:41 PM PDT 24
Finished May 30 03:34:43 PM PDT 24
Peak memory 204196 kb
Host smart-0aa96da7-b1c2-4be6-8aa8-e2b3f161282e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=726512596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.726512596
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.4154725909
Short name T2030
Test name
Test status
Simulation time 125945446 ps
CPU time 1.58 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:48 PM PDT 24
Peak memory 204556 kb
Host smart-b10fd5de-de8b-4a65-9437-5304d2125be4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4154725909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.4154725909
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.4225705933
Short name T1942
Test name
Test status
Simulation time 157345628 ps
CPU time 1.86 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:45 PM PDT 24
Peak memory 204500 kb
Host smart-3274dbda-9992-4ab6-affc-c664ef1a28de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4225705933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.4225705933
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.154628970
Short name T2040
Test name
Test status
Simulation time 67049187 ps
CPU time 1.37 seconds
Started May 30 03:34:41 PM PDT 24
Finished May 30 03:34:44 PM PDT 24
Peak memory 215488 kb
Host smart-034892e8-3604-44b5-9a6e-d302b59d88c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154628970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.154628970
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1873595405
Short name T1969
Test name
Test status
Simulation time 84352123 ps
CPU time 0.99 seconds
Started May 30 03:34:41 PM PDT 24
Finished May 30 03:34:43 PM PDT 24
Peak memory 204600 kb
Host smart-29a94482-f0c0-4fb3-8708-603c0f250be4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1873595405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1873595405
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.622535826
Short name T2000
Test name
Test status
Simulation time 139050150 ps
CPU time 1.27 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:45 PM PDT 24
Peak memory 204560 kb
Host smart-62c8587d-37f8-488c-970b-cda5b2458455
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622535826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.622535826
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2378979605
Short name T2004
Test name
Test status
Simulation time 125646958 ps
CPU time 2.64 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:46 PM PDT 24
Peak memory 220140 kb
Host smart-2b00f0d6-e845-461f-9d9d-e187969cce2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2378979605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2378979605
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1259414477
Short name T274
Test name
Test status
Simulation time 298722327 ps
CPU time 2.49 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:49 PM PDT 24
Peak memory 204580 kb
Host smart-f48c2540-412e-4cdf-b443-47238f038c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1259414477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1259414477
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.483451370
Short name T1999
Test name
Test status
Simulation time 261734784 ps
CPU time 2.11 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:45 PM PDT 24
Peak memory 212848 kb
Host smart-209a9cdf-bb25-40ec-b358-6bfaaab48bda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483451370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.483451370
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3492439440
Short name T248
Test name
Test status
Simulation time 83215677 ps
CPU time 1.02 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:44 PM PDT 24
Peak memory 204584 kb
Host smart-210c3316-4548-4e43-9722-b92e30583001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3492439440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3492439440
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2210305214
Short name T263
Test name
Test status
Simulation time 110951715 ps
CPU time 0.77 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:44 PM PDT 24
Peak memory 204172 kb
Host smart-dbb15928-6885-4696-bd3c-d33809f0dd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2210305214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2210305214
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2237898505
Short name T199
Test name
Test status
Simulation time 101302319 ps
CPU time 1.14 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:47 PM PDT 24
Peak memory 204564 kb
Host smart-048881ff-d5ec-404e-890a-7aa8fb57d3e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2237898505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2237898505
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2824950590
Short name T1998
Test name
Test status
Simulation time 88907108 ps
CPU time 1.95 seconds
Started May 30 03:34:41 PM PDT 24
Finished May 30 03:34:44 PM PDT 24
Peak memory 204536 kb
Host smart-a692a5b7-6dd4-429b-b4ad-a5da25b55fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2824950590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2824950590
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1442487965
Short name T224
Test name
Test status
Simulation time 87606460 ps
CPU time 1.23 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 212696 kb
Host smart-29b64f92-82c1-4fd7-b64e-13aad1739a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442487965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1442487965
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.9093762
Short name T1982
Test name
Test status
Simulation time 49681571 ps
CPU time 0.92 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:49 PM PDT 24
Peak memory 204500 kb
Host smart-4c527baf-3761-421c-92da-7bbfa067874a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=9093762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.9093762
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1195829182
Short name T2001
Test name
Test status
Simulation time 58419465 ps
CPU time 0.69 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:47 PM PDT 24
Peak memory 204212 kb
Host smart-3ce478e0-3abe-46b8-ba77-33512ae03c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1195829182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1195829182
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2754651565
Short name T252
Test name
Test status
Simulation time 182269007 ps
CPU time 1.62 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:45 PM PDT 24
Peak memory 204536 kb
Host smart-b5cecac7-9d42-445e-8236-24806b51b9f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754651565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2754651565
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1119640453
Short name T2042
Test name
Test status
Simulation time 328322877 ps
CPU time 3.32 seconds
Started May 30 03:34:42 PM PDT 24
Finished May 30 03:34:48 PM PDT 24
Peak memory 220216 kb
Host smart-0124d70c-323f-4501-b1be-c02ca57dfaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1119640453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1119640453
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3565961219
Short name T259
Test name
Test status
Simulation time 1255419757 ps
CPU time 5.22 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:52 PM PDT 24
Peak memory 204640 kb
Host smart-75daecb9-a739-4ad9-827c-25caab7b78f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3565961219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3565961219
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3596542851
Short name T2038
Test name
Test status
Simulation time 69768232 ps
CPU time 1.48 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:53 PM PDT 24
Peak memory 212784 kb
Host smart-879911ab-8f9c-40d7-af0f-5f4fe97800dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596542851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3596542851
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3995669584
Short name T246
Test name
Test status
Simulation time 55795182 ps
CPU time 0.82 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 204208 kb
Host smart-a35c12b8-896d-42a6-a562-b777f7d82b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3995669584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3995669584
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3100402506
Short name T1959
Test name
Test status
Simulation time 46815446 ps
CPU time 0.71 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:47 PM PDT 24
Peak memory 204208 kb
Host smart-0d6c28fe-0d18-4905-9d72-be9b53ccf6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3100402506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3100402506
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.58273361
Short name T255
Test name
Test status
Simulation time 110382765 ps
CPU time 1.72 seconds
Started May 30 03:34:43 PM PDT 24
Finished May 30 03:34:46 PM PDT 24
Peak memory 204548 kb
Host smart-4812ea79-e5b1-4951-a4e5-d3c56314c78c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=58273361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.58273361
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1208414097
Short name T218
Test name
Test status
Simulation time 282395027 ps
CPU time 2.89 seconds
Started May 30 03:34:43 PM PDT 24
Finished May 30 03:34:47 PM PDT 24
Peak memory 204588 kb
Host smart-53131a81-2d01-4b49-8548-74e7b076a790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1208414097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1208414097
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3660012603
Short name T1979
Test name
Test status
Simulation time 531216081 ps
CPU time 4.31 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 204604 kb
Host smart-a01626a6-9640-420f-8995-a88b907d49e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3660012603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3660012603
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.873985257
Short name T2007
Test name
Test status
Simulation time 115026515 ps
CPU time 2.12 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:53 PM PDT 24
Peak memory 212716 kb
Host smart-b1daa8b7-099d-4a1d-91ab-617697081d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873985257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.873985257
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1847448763
Short name T1954
Test name
Test status
Simulation time 76409765 ps
CPU time 0.91 seconds
Started May 30 03:34:45 PM PDT 24
Finished May 30 03:34:47 PM PDT 24
Peak memory 204376 kb
Host smart-5c2bcc10-8321-4c04-8ee5-921b4179bddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1847448763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1847448763
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1751471531
Short name T1953
Test name
Test status
Simulation time 61358186 ps
CPU time 0.7 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:51 PM PDT 24
Peak memory 204164 kb
Host smart-2a68c207-1d65-4691-9954-1819fd8166ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1751471531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1751471531
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3845036415
Short name T1938
Test name
Test status
Simulation time 65226795 ps
CPU time 1.04 seconds
Started May 30 03:34:48 PM PDT 24
Finished May 30 03:34:51 PM PDT 24
Peak memory 204544 kb
Host smart-ec3a7d2e-dda5-42ae-a991-31af2ea84e7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3845036415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3845036415
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1589544289
Short name T2016
Test name
Test status
Simulation time 93290557 ps
CPU time 1.95 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:53 PM PDT 24
Peak memory 204484 kb
Host smart-c1d43992-fc1a-4def-9dd8-b69293d6f1fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1589544289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1589544289
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2638771008
Short name T281
Test name
Test status
Simulation time 1077463756 ps
CPU time 5.53 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:56 PM PDT 24
Peak memory 204552 kb
Host smart-26f04b56-a67a-4b34-a635-d3f6e3244525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2638771008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2638771008
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1574338966
Short name T1939
Test name
Test status
Simulation time 112869939 ps
CPU time 1.4 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:52 PM PDT 24
Peak memory 212768 kb
Host smart-76ad6c10-80c3-40cd-833b-35ea5c2ada5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574338966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1574338966
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1529966753
Short name T1988
Test name
Test status
Simulation time 69952673 ps
CPU time 0.83 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:52 PM PDT 24
Peak memory 204268 kb
Host smart-78f8fcdc-b458-4dcd-9d68-276228c07e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1529966753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1529966753
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3910253822
Short name T1936
Test name
Test status
Simulation time 48421041 ps
CPU time 0.74 seconds
Started May 30 03:34:51 PM PDT 24
Finished May 30 03:34:54 PM PDT 24
Peak memory 204192 kb
Host smart-4958afc7-b93f-4c36-abc6-e798a5095c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3910253822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3910253822
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2046703762
Short name T1968
Test name
Test status
Simulation time 229628971 ps
CPU time 1.81 seconds
Started May 30 03:34:51 PM PDT 24
Finished May 30 03:34:55 PM PDT 24
Peak memory 204572 kb
Host smart-5ec5e86a-1236-48a5-b012-8be912c04789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2046703762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2046703762
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1202848553
Short name T1941
Test name
Test status
Simulation time 273364350 ps
CPU time 3.22 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:54 PM PDT 24
Peak memory 220368 kb
Host smart-370b15f4-f0d4-4bcd-abcb-ba21d600ca9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202848553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1202848553
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3539605958
Short name T275
Test name
Test status
Simulation time 507382677 ps
CPU time 4.04 seconds
Started May 30 03:34:55 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204544 kb
Host smart-7b39cfe2-bce5-4e7e-b58f-cf28339ebd28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3539605958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3539605958
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1743481911
Short name T1963
Test name
Test status
Simulation time 96463403 ps
CPU time 1.39 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 212760 kb
Host smart-6c66e938-e66e-4eba-852b-b619e40f3e26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743481911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1743481911
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3222713451
Short name T244
Test name
Test status
Simulation time 73497666 ps
CPU time 1 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 204512 kb
Host smart-7b3a2309-ceeb-47fa-a54a-b92c523745da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3222713451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3222713451
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.312708665
Short name T97
Test name
Test status
Simulation time 39963131 ps
CPU time 0.65 seconds
Started May 30 03:34:48 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 204228 kb
Host smart-037f1d1b-44a6-4e3d-a3a6-bee096214cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=312708665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.312708665
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3393470782
Short name T254
Test name
Test status
Simulation time 64921099 ps
CPU time 1 seconds
Started May 30 03:34:48 PM PDT 24
Finished May 30 03:34:51 PM PDT 24
Peak memory 204584 kb
Host smart-e143f97f-6aa0-4394-9336-1db9e578c883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3393470782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3393470782
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1463449392
Short name T1958
Test name
Test status
Simulation time 196409024 ps
CPU time 1.58 seconds
Started May 30 03:34:54 PM PDT 24
Finished May 30 03:34:57 PM PDT 24
Peak memory 204480 kb
Host smart-1d8a96cc-c5d2-4bbe-b758-56495366d69c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1463449392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1463449392
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1610207618
Short name T282
Test name
Test status
Simulation time 678217782 ps
CPU time 4.39 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:53 PM PDT 24
Peak memory 204620 kb
Host smart-d040cbfd-ba64-4623-9b57-f842f4cd63cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1610207618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1610207618
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3272237982
Short name T1935
Test name
Test status
Simulation time 100807822 ps
CPU time 2 seconds
Started May 30 03:34:51 PM PDT 24
Finished May 30 03:34:54 PM PDT 24
Peak memory 212804 kb
Host smart-5f34c9d6-8952-426c-8712-967f32cc1501
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272237982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3272237982
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.166948860
Short name T240
Test name
Test status
Simulation time 58859657 ps
CPU time 0.77 seconds
Started May 30 03:34:50 PM PDT 24
Finished May 30 03:34:52 PM PDT 24
Peak memory 204340 kb
Host smart-b65cba32-740a-4823-bec7-1dbe9ff27108
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=166948860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.166948860
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2313099624
Short name T2021
Test name
Test status
Simulation time 50151223 ps
CPU time 0.71 seconds
Started May 30 03:34:51 PM PDT 24
Finished May 30 03:34:54 PM PDT 24
Peak memory 204192 kb
Host smart-cebb2f8f-78c0-4b5e-8249-28ff19eb0885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2313099624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2313099624
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2221252090
Short name T1997
Test name
Test status
Simulation time 157253443 ps
CPU time 1.62 seconds
Started May 30 03:34:51 PM PDT 24
Finished May 30 03:34:55 PM PDT 24
Peak memory 204564 kb
Host smart-8a2de599-30d1-4fa4-b2f2-8f2c9ffc3448
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2221252090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2221252090
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.683102035
Short name T2034
Test name
Test status
Simulation time 199811482 ps
CPU time 1.95 seconds
Started May 30 03:34:46 PM PDT 24
Finished May 30 03:34:49 PM PDT 24
Peak memory 204556 kb
Host smart-b709dee4-6ebc-43ed-b791-a174fc204b75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=683102035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.683102035
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2761116784
Short name T1975
Test name
Test status
Simulation time 1034585933 ps
CPU time 4.67 seconds
Started May 30 03:34:47 PM PDT 24
Finished May 30 03:34:54 PM PDT 24
Peak memory 204572 kb
Host smart-e810b989-5336-4ed0-a393-e499e648ada9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2761116784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2761116784
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.235172712
Short name T1970
Test name
Test status
Simulation time 71252848 ps
CPU time 1.92 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 204528 kb
Host smart-7eefd989-e3a9-4357-9a67-95f61630fe5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=235172712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.235172712
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2968875738
Short name T247
Test name
Test status
Simulation time 742983136 ps
CPU time 4.94 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:17 PM PDT 24
Peak memory 204596 kb
Host smart-303d0ca0-f560-4a00-8058-d271051062ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2968875738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2968875738
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3198609457
Short name T1955
Test name
Test status
Simulation time 275861161 ps
CPU time 1.18 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 204212 kb
Host smart-2940abbc-37c6-4798-9c80-b136feead07e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3198609457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3198609457
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.4280466086
Short name T196
Test name
Test status
Simulation time 159990226 ps
CPU time 1.89 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:14 PM PDT 24
Peak memory 212784 kb
Host smart-122f8599-b084-4748-b282-57c2b7b5f558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280466086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.4280466086
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3560156924
Short name T242
Test name
Test status
Simulation time 75099768 ps
CPU time 0.85 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:11 PM PDT 24
Peak memory 204316 kb
Host smart-daa5a178-50dc-4931-873d-0e61b19d0401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3560156924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3560156924
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1927444564
Short name T1965
Test name
Test status
Simulation time 77151708 ps
CPU time 0.69 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 204216 kb
Host smart-36ec972e-23b4-45fe-856e-40bcf8f294db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1927444564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1927444564
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2723739070
Short name T250
Test name
Test status
Simulation time 203618127 ps
CPU time 2.28 seconds
Started May 30 03:34:08 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 212604 kb
Host smart-42bb7ca3-9715-4180-96a4-d87d236e0c04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2723739070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2723739070
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.568295583
Short name T1937
Test name
Test status
Simulation time 256314111 ps
CPU time 2.44 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:15 PM PDT 24
Peak memory 204460 kb
Host smart-0c722ae3-4d78-4016-acf6-5de308a77d5b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=568295583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.568295583
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.593458322
Short name T2017
Test name
Test status
Simulation time 88175867 ps
CPU time 1.03 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 204616 kb
Host smart-287529bf-6165-4afc-8e04-8a302585890a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=593458322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.593458322
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2116326911
Short name T1966
Test name
Test status
Simulation time 85357636 ps
CPU time 1.28 seconds
Started May 30 03:34:11 PM PDT 24
Finished May 30 03:34:14 PM PDT 24
Peak memory 204564 kb
Host smart-3e0be314-30b8-42e8-9dee-85540ebd53b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2116326911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2116326911
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1754653363
Short name T215
Test name
Test status
Simulation time 934799195 ps
CPU time 3.08 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:14 PM PDT 24
Peak memory 204520 kb
Host smart-f2934fd9-e951-4ccc-a521-2806966a9046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1754653363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1754653363
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3691866323
Short name T1974
Test name
Test status
Simulation time 47106178 ps
CPU time 0.74 seconds
Started May 30 03:34:49 PM PDT 24
Finished May 30 03:34:51 PM PDT 24
Peak memory 204196 kb
Host smart-1a3d5b06-7d2b-4eeb-9091-b6ef038d76a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3691866323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3691866323
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2086576162
Short name T202
Test name
Test status
Simulation time 86825114 ps
CPU time 0.71 seconds
Started May 30 03:34:52 PM PDT 24
Finished May 30 03:34:55 PM PDT 24
Peak memory 204144 kb
Host smart-4f7a3715-b164-40fa-b46f-d4feda43d087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2086576162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2086576162
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2236496750
Short name T1949
Test name
Test status
Simulation time 71178125 ps
CPU time 0.69 seconds
Started May 30 03:34:48 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 204152 kb
Host smart-5f96c154-a409-4bb6-8c9f-57ceef97a3a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2236496750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2236496750
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4184085140
Short name T95
Test name
Test status
Simulation time 52863246 ps
CPU time 0.74 seconds
Started May 30 03:34:48 PM PDT 24
Finished May 30 03:34:50 PM PDT 24
Peak memory 204180 kb
Host smart-aef90c3a-4199-4154-a685-2cd67953e79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4184085140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4184085140
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1473857640
Short name T2005
Test name
Test status
Simulation time 74820726 ps
CPU time 0.73 seconds
Started May 30 03:34:50 PM PDT 24
Finished May 30 03:34:53 PM PDT 24
Peak memory 204180 kb
Host smart-f54b5a8b-1f23-4921-bd0a-f25bd4c5cada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1473857640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1473857640
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.506200074
Short name T204
Test name
Test status
Simulation time 44560304 ps
CPU time 0.68 seconds
Started May 30 03:34:59 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 204200 kb
Host smart-5e3ffbe0-8527-4286-b0d9-82aa44be6201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=506200074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.506200074
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3904007280
Short name T1946
Test name
Test status
Simulation time 78146877 ps
CPU time 0.73 seconds
Started May 30 03:34:59 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 204188 kb
Host smart-ddf070fc-25d6-432a-8ff2-626b19efa827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3904007280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3904007280
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2028977580
Short name T1957
Test name
Test status
Simulation time 35113105 ps
CPU time 0.68 seconds
Started May 30 03:34:59 PM PDT 24
Finished May 30 03:35:02 PM PDT 24
Peak memory 204208 kb
Host smart-fc3ed5c7-c9dc-435b-b947-58aed3a97c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2028977580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2028977580
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2964291509
Short name T2031
Test name
Test status
Simulation time 72102545 ps
CPU time 0.66 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204200 kb
Host smart-a7bdeeea-d46a-4f62-a76d-3b750df0f403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2964291509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2964291509
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2730905663
Short name T251
Test name
Test status
Simulation time 142403861 ps
CPU time 3.29 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:25 PM PDT 24
Peak memory 204500 kb
Host smart-4fbcded3-bc7a-419e-bf6a-d513cba9a249
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2730905663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2730905663
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.424493403
Short name T200
Test name
Test status
Simulation time 1407089856 ps
CPU time 8.56 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:30 PM PDT 24
Peak memory 204572 kb
Host smart-1f2b2e3b-4d7c-41a2-8269-5974e5ec30e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=424493403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.424493403
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2064760717
Short name T205
Test name
Test status
Simulation time 138736044 ps
CPU time 0.85 seconds
Started May 30 03:34:19 PM PDT 24
Finished May 30 03:34:21 PM PDT 24
Peak memory 204284 kb
Host smart-9ffe0451-419a-4b01-8084-e42e57f78e7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2064760717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2064760717
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.308170851
Short name T223
Test name
Test status
Simulation time 163137068 ps
CPU time 1.88 seconds
Started May 30 03:34:23 PM PDT 24
Finished May 30 03:34:26 PM PDT 24
Peak memory 216816 kb
Host smart-ea18f5f3-8ccb-4521-93cb-5b9be22cbe90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308170851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev
_csr_mem_rw_with_rand_reset.308170851
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2985224692
Short name T2028
Test name
Test status
Simulation time 55195888 ps
CPU time 0.99 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204632 kb
Host smart-a5a62d45-7a2f-4c0d-9872-ae9ccddd498d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2985224692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2985224692
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.125065461
Short name T1944
Test name
Test status
Simulation time 43015903 ps
CPU time 0.68 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:11 PM PDT 24
Peak memory 204204 kb
Host smart-6329f218-a09a-47e3-8b65-38275a99efd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=125065461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.125065461
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1785475327
Short name T1961
Test name
Test status
Simulation time 80847643 ps
CPU time 2.14 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:14 PM PDT 24
Peak memory 212716 kb
Host smart-32d925cc-6def-4f2f-bc72-3af3fc407d07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1785475327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1785475327
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3087510187
Short name T2002
Test name
Test status
Simulation time 223871911 ps
CPU time 4.07 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:16 PM PDT 24
Peak memory 204480 kb
Host smart-987121c0-3e53-4ac4-9f18-2a1878888a9c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3087510187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3087510187
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.340910322
Short name T1947
Test name
Test status
Simulation time 210203886 ps
CPU time 1.8 seconds
Started May 30 03:34:19 PM PDT 24
Finished May 30 03:34:21 PM PDT 24
Peak memory 204612 kb
Host smart-f6d65999-7b55-4a66-b38e-2b236d9935ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=340910322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.340910322
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1853422185
Short name T2027
Test name
Test status
Simulation time 186033877 ps
CPU time 2.11 seconds
Started May 30 03:34:09 PM PDT 24
Finished May 30 03:34:12 PM PDT 24
Peak memory 220236 kb
Host smart-21886ebf-254e-443d-888a-886a557a80d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1853422185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1853422185
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.401027737
Short name T277
Test name
Test status
Simulation time 601352184 ps
CPU time 2.78 seconds
Started May 30 03:34:10 PM PDT 24
Finished May 30 03:34:15 PM PDT 24
Peak memory 204556 kb
Host smart-fa646246-883f-453a-8df2-188d83d7058f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=401027737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.401027737
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3473540476
Short name T1980
Test name
Test status
Simulation time 33879857 ps
CPU time 0.67 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204192 kb
Host smart-bf79f8c5-c8a5-4b29-a391-43a8186ad6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3473540476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3473540476
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3124937784
Short name T262
Test name
Test status
Simulation time 41306796 ps
CPU time 0.69 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204200 kb
Host smart-1ba45462-502c-4f37-88fe-4cce5dfebe29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3124937784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3124937784
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.291715264
Short name T1951
Test name
Test status
Simulation time 29538910 ps
CPU time 0.65 seconds
Started May 30 03:34:57 PM PDT 24
Finished May 30 03:34:59 PM PDT 24
Peak memory 204200 kb
Host smart-c009b937-c2a4-4060-9d4c-d234aa9f1eb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=291715264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.291715264
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.816641494
Short name T2006
Test name
Test status
Simulation time 41968530 ps
CPU time 0.68 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204152 kb
Host smart-8012682f-a24c-4605-847a-715d3ab5bfc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=816641494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.816641494
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3082670047
Short name T1950
Test name
Test status
Simulation time 44453268 ps
CPU time 0.63 seconds
Started May 30 03:34:57 PM PDT 24
Finished May 30 03:34:59 PM PDT 24
Peak memory 204200 kb
Host smart-6135c86f-f960-49db-83ec-98ec31faca5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3082670047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3082670047
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.691327674
Short name T2041
Test name
Test status
Simulation time 43055133 ps
CPU time 0.69 seconds
Started May 30 03:34:57 PM PDT 24
Finished May 30 03:34:59 PM PDT 24
Peak memory 204232 kb
Host smart-89468094-93f1-4e2e-b2f7-cde4f975a102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=691327674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.691327674
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3669083173
Short name T203
Test name
Test status
Simulation time 39551896 ps
CPU time 0.64 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204200 kb
Host smart-91ecc824-2b43-474d-956f-2b89f2478e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3669083173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3669083173
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1935779992
Short name T1990
Test name
Test status
Simulation time 53054557 ps
CPU time 0.66 seconds
Started May 30 03:34:58 PM PDT 24
Finished May 30 03:35:00 PM PDT 24
Peak memory 204220 kb
Host smart-31da9332-896a-423b-9a95-7be6bdfa2cbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1935779992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1935779992
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3997839098
Short name T2015
Test name
Test status
Simulation time 82504207 ps
CPU time 2.15 seconds
Started May 30 03:34:19 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204596 kb
Host smart-4393281a-06b0-4e02-ab4f-cb30e2d016e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3997839098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3997839098
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1893348044
Short name T1945
Test name
Test status
Simulation time 1185773691 ps
CPU time 5.06 seconds
Started May 30 03:34:19 PM PDT 24
Finished May 30 03:34:25 PM PDT 24
Peak memory 204620 kb
Host smart-17c499e6-912e-480e-b55e-d97856617134
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1893348044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1893348044
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2240400651
Short name T2008
Test name
Test status
Simulation time 108087420 ps
CPU time 0.97 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204296 kb
Host smart-91a592e1-932a-44b5-b2d3-201543dc113a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2240400651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2240400651
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1012817041
Short name T2024
Test name
Test status
Simulation time 108328057 ps
CPU time 2.05 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 216544 kb
Host smart-bd4e2bc9-be0e-4f5e-ad28-7b140454041e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012817041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1012817041
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2506693716
Short name T2009
Test name
Test status
Simulation time 72967564 ps
CPU time 0.86 seconds
Started May 30 03:34:19 PM PDT 24
Finished May 30 03:34:21 PM PDT 24
Peak memory 204260 kb
Host smart-0167d38c-12c3-43c2-9f07-2a796fd0a5fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2506693716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2506693716
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3112853722
Short name T271
Test name
Test status
Simulation time 54779034 ps
CPU time 0.68 seconds
Started May 30 03:34:22 PM PDT 24
Finished May 30 03:34:24 PM PDT 24
Peak memory 204212 kb
Host smart-ea9aa0b1-50e2-4b65-bfe8-5fddc5ba42b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3112853722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3112853722
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2390609443
Short name T2014
Test name
Test status
Simulation time 57466473 ps
CPU time 1.3 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:22 PM PDT 24
Peak memory 212652 kb
Host smart-8f85060d-58c5-484d-bdd6-69b56c864e49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2390609443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2390609443
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4184530041
Short name T1986
Test name
Test status
Simulation time 173021755 ps
CPU time 3.83 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:26 PM PDT 24
Peak memory 204444 kb
Host smart-4675642e-57ef-4b03-b670-c82ee241835f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4184530041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4184530041
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1664382854
Short name T253
Test name
Test status
Simulation time 112452609 ps
CPU time 1.24 seconds
Started May 30 03:34:19 PM PDT 24
Finished May 30 03:34:21 PM PDT 24
Peak memory 204544 kb
Host smart-594d68a5-d28c-46a0-b331-bfef4ef7b14b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1664382854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1664382854
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.80949860
Short name T1994
Test name
Test status
Simulation time 291579112 ps
CPU time 3.56 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:24 PM PDT 24
Peak memory 204572 kb
Host smart-9bfdf930-c821-4dbe-8051-bcceeef31e99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=80949860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.80949860
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1341652943
Short name T266
Test name
Test status
Simulation time 38375899 ps
CPU time 0.67 seconds
Started May 30 03:34:57 PM PDT 24
Finished May 30 03:34:59 PM PDT 24
Peak memory 204164 kb
Host smart-dcf26b2f-4889-4841-975a-35241ce384c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1341652943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1341652943
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2976758688
Short name T268
Test name
Test status
Simulation time 55837879 ps
CPU time 0.64 seconds
Started May 30 03:34:59 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 204108 kb
Host smart-9a07e733-9c0f-4639-b6c8-fbe05c0cadde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2976758688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2976758688
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2500990103
Short name T267
Test name
Test status
Simulation time 29923584 ps
CPU time 0.72 seconds
Started May 30 03:34:59 PM PDT 24
Finished May 30 03:35:01 PM PDT 24
Peak memory 204180 kb
Host smart-d9f364ec-a23d-4ea4-aa13-64a22dd95b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2500990103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2500990103
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3452682065
Short name T2011
Test name
Test status
Simulation time 43863681 ps
CPU time 0.67 seconds
Started May 30 03:34:57 PM PDT 24
Finished May 30 03:34:59 PM PDT 24
Peak memory 204168 kb
Host smart-2cf64173-3e8b-4716-a127-7c8c05e2c8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452682065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3452682065
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1456686932
Short name T2025
Test name
Test status
Simulation time 67967107 ps
CPU time 0.75 seconds
Started May 30 03:34:57 PM PDT 24
Finished May 30 03:34:59 PM PDT 24
Peak memory 204172 kb
Host smart-fc6ab0c5-2cfa-42f8-a740-223626c8a091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1456686932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1456686932
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2654098801
Short name T270
Test name
Test status
Simulation time 46933258 ps
CPU time 0.68 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 204184 kb
Host smart-6059d208-08ea-4b06-9619-421fe66c80c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2654098801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2654098801
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3875659951
Short name T1995
Test name
Test status
Simulation time 48030516 ps
CPU time 0.67 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 204164 kb
Host smart-c0400267-9203-490d-9c2b-1ff5eb0e7f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875659951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3875659951
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.791418384
Short name T2026
Test name
Test status
Simulation time 53066159 ps
CPU time 0.64 seconds
Started May 30 03:35:06 PM PDT 24
Finished May 30 03:35:08 PM PDT 24
Peak memory 204208 kb
Host smart-e085f3a6-d078-4c10-95b5-c7384d36e0f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=791418384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.791418384
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2638066685
Short name T2020
Test name
Test status
Simulation time 38992623 ps
CPU time 0.69 seconds
Started May 30 03:35:06 PM PDT 24
Finished May 30 03:35:08 PM PDT 24
Peak memory 204160 kb
Host smart-20a6f1c4-06c8-4bc4-a4f5-72b1999102b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2638066685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2638066685
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.363422680
Short name T1964
Test name
Test status
Simulation time 114609584 ps
CPU time 1.22 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 212780 kb
Host smart-79658425-fcef-492e-8c4c-d3c1af48ab35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363422680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.363422680
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.64754453
Short name T1981
Test name
Test status
Simulation time 108111578 ps
CPU time 0.87 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:24 PM PDT 24
Peak memory 204272 kb
Host smart-893f74ba-12fb-4bad-bb81-0e160becb893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=64754453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.64754453
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.40656408
Short name T1985
Test name
Test status
Simulation time 39841544 ps
CPU time 0.68 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204200 kb
Host smart-ca7fcf45-22be-42ee-a49a-65b1b716f4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=40656408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.40656408
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4132232945
Short name T1973
Test name
Test status
Simulation time 122644541 ps
CPU time 1.17 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204540 kb
Host smart-e2c2a9ab-e922-4b9d-ad49-a6f09f8f294f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4132232945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.4132232945
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2264023834
Short name T220
Test name
Test status
Simulation time 332238419 ps
CPU time 3.34 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:26 PM PDT 24
Peak memory 220104 kb
Host smart-574287fe-3bd6-4d3c-884c-3d3bae28461c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2264023834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2264023834
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1459171909
Short name T278
Test name
Test status
Simulation time 832002685 ps
CPU time 4.69 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:27 PM PDT 24
Peak memory 204488 kb
Host smart-dabb075d-e961-4e02-a130-53f6195cca76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1459171909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1459171909
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3229315056
Short name T217
Test name
Test status
Simulation time 94401065 ps
CPU time 1.23 seconds
Started May 30 03:34:31 PM PDT 24
Finished May 30 03:34:33 PM PDT 24
Peak memory 221064 kb
Host smart-047abc73-b23f-4e7b-bc45-47b38089d04f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229315056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3229315056
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2313841471
Short name T2012
Test name
Test status
Simulation time 72742521 ps
CPU time 0.98 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204460 kb
Host smart-edf1d993-adce-4c90-87ab-906b75324848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2313841471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2313841471
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.655213459
Short name T1940
Test name
Test status
Simulation time 104586982 ps
CPU time 0.74 seconds
Started May 30 03:34:21 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204192 kb
Host smart-2fcde766-c998-4035-a294-bb03a9121f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=655213459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.655213459
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1243018534
Short name T1952
Test name
Test status
Simulation time 80254458 ps
CPU time 1.05 seconds
Started May 30 03:34:23 PM PDT 24
Finished May 30 03:34:25 PM PDT 24
Peak memory 204432 kb
Host smart-8f5989ec-2926-40b0-a98c-774a17fc0a75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1243018534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1243018534
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1712804579
Short name T221
Test name
Test status
Simulation time 169174051 ps
CPU time 1.6 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:23 PM PDT 24
Peak memory 204640 kb
Host smart-9d89535d-1a4e-42df-893f-f2ae3f16ecf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1712804579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1712804579
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.4014497280
Short name T216
Test name
Test status
Simulation time 1268505369 ps
CPU time 5.6 seconds
Started May 30 03:34:20 PM PDT 24
Finished May 30 03:34:27 PM PDT 24
Peak memory 204616 kb
Host smart-bc6977ff-eecc-400b-95ee-f69927b8c9c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4014497280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.4014497280
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.765549401
Short name T1996
Test name
Test status
Simulation time 149883004 ps
CPU time 1.64 seconds
Started May 30 03:34:34 PM PDT 24
Finished May 30 03:34:37 PM PDT 24
Peak memory 212724 kb
Host smart-df84ffc0-e59f-47d9-974a-6a2e878b648c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765549401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.765549401
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.628156350
Short name T245
Test name
Test status
Simulation time 54741280 ps
CPU time 0.8 seconds
Started May 30 03:34:33 PM PDT 24
Finished May 30 03:34:35 PM PDT 24
Peak memory 204320 kb
Host smart-88ec646f-de2a-49fe-a2a0-6d000101e0b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=628156350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.628156350
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4154278826
Short name T272
Test name
Test status
Simulation time 74234423 ps
CPU time 0.72 seconds
Started May 30 03:34:34 PM PDT 24
Finished May 30 03:34:36 PM PDT 24
Peak memory 204168 kb
Host smart-fe9b4954-1616-4a74-8ce5-4a69ca0d72a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4154278826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4154278826
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.742731705
Short name T1956
Test name
Test status
Simulation time 86234929 ps
CPU time 1.1 seconds
Started May 30 03:34:36 PM PDT 24
Finished May 30 03:34:38 PM PDT 24
Peak memory 204252 kb
Host smart-d005ac3c-09b1-4d9d-9697-21a60e08a4fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=742731705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.742731705
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3994326171
Short name T212
Test name
Test status
Simulation time 138664916 ps
CPU time 1.77 seconds
Started May 30 03:34:33 PM PDT 24
Finished May 30 03:34:36 PM PDT 24
Peak memory 204552 kb
Host smart-3b99b67c-6d8c-4d7c-9f8e-3716dd4a604f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3994326171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3994326171
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1686025106
Short name T258
Test name
Test status
Simulation time 190471702 ps
CPU time 1.28 seconds
Started May 30 03:34:32 PM PDT 24
Finished May 30 03:34:34 PM PDT 24
Peak memory 214416 kb
Host smart-ece5f1a6-39b3-42ff-ae8b-524e80841d9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686025106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.1686025106
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.352572879
Short name T1978
Test name
Test status
Simulation time 73780082 ps
CPU time 0.92 seconds
Started May 30 03:34:35 PM PDT 24
Finished May 30 03:34:37 PM PDT 24
Peak memory 204564 kb
Host smart-ef7c878c-fa54-403c-86e7-5f48adc52ffd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=352572879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.352572879
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2904695028
Short name T2019
Test name
Test status
Simulation time 43540340 ps
CPU time 0.65 seconds
Started May 30 03:34:32 PM PDT 24
Finished May 30 03:34:34 PM PDT 24
Peak memory 204184 kb
Host smart-170fad8f-1055-499c-a02d-eaa9661e2ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2904695028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2904695028
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1476116138
Short name T2035
Test name
Test status
Simulation time 122793133 ps
CPU time 1.33 seconds
Started May 30 03:34:30 PM PDT 24
Finished May 30 03:34:32 PM PDT 24
Peak memory 204544 kb
Host smart-788f308f-abee-428f-a0b2-066f9ca0d988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1476116138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1476116138
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1305782279
Short name T209
Test name
Test status
Simulation time 81327251 ps
CPU time 2.15 seconds
Started May 30 03:34:31 PM PDT 24
Finished May 30 03:34:34 PM PDT 24
Peak memory 212756 kb
Host smart-ea3d4fa3-2e5b-426f-8eaa-8c3091d2b409
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1305782279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1305782279
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1830945779
Short name T1948
Test name
Test status
Simulation time 782796731 ps
CPU time 2.99 seconds
Started May 30 03:34:32 PM PDT 24
Finished May 30 03:34:36 PM PDT 24
Peak memory 204528 kb
Host smart-3e62b7d4-de1a-413e-a663-1fbd2ded4af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1830945779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1830945779
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.4023629060
Short name T225
Test name
Test status
Simulation time 120172817 ps
CPU time 1.42 seconds
Started May 30 03:34:33 PM PDT 24
Finished May 30 03:34:35 PM PDT 24
Peak memory 212784 kb
Host smart-2545688c-8abd-4e81-9bc5-7c4c6b20cee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023629060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.4023629060
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2154317925
Short name T1992
Test name
Test status
Simulation time 71070468 ps
CPU time 1.01 seconds
Started May 30 03:34:32 PM PDT 24
Finished May 30 03:34:34 PM PDT 24
Peak memory 204560 kb
Host smart-f6a1eba0-4f42-4442-a336-99cc87848815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2154317925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2154317925
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.479099870
Short name T1971
Test name
Test status
Simulation time 39074210 ps
CPU time 0.67 seconds
Started May 30 03:34:31 PM PDT 24
Finished May 30 03:34:33 PM PDT 24
Peak memory 204220 kb
Host smart-3719e635-9040-4ff2-ba41-33780eb1be96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=479099870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.479099870
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.472938340
Short name T1962
Test name
Test status
Simulation time 126074108 ps
CPU time 1.2 seconds
Started May 30 03:34:34 PM PDT 24
Finished May 30 03:34:36 PM PDT 24
Peak memory 204480 kb
Host smart-e92fa80e-d8da-431c-85d3-7b98f6441dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=472938340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.472938340
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1250835885
Short name T2010
Test name
Test status
Simulation time 503069015 ps
CPU time 4.2 seconds
Started May 30 03:34:34 PM PDT 24
Finished May 30 03:34:39 PM PDT 24
Peak memory 204496 kb
Host smart-3bc3f9cc-4428-4382-aec9-24a7d6ce909e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1250835885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1250835885
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.max_length_in_transaction.2825379069
Short name T348
Test name
Test status
Simulation time 10178056983 ps
CPU time 13.65 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205540 kb
Host smart-6959084c-1c62-441e-b788-67c8c7caf17b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2825379069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.max_length_in_transaction.2825379069
Directory /workspace/0.max_length_in_transaction/latest

Test location /workspace/coverage/default/0.min_length_in_transaction.1373472615
Short name T1413
Test name
Test status
Simulation time 10068643194 ps
CPU time 13.1 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205528 kb
Host smart-9241ee67-f28d-482b-b9ce-818462280bf9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1373472615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.min_length_in_transaction.1373472615
Directory /workspace/0.min_length_in_transaction/latest

Test location /workspace/coverage/default/0.random_length_in_trans.3073961354
Short name T1196
Test name
Test status
Simulation time 10163646907 ps
CPU time 15.48 seconds
Started May 30 03:42:16 PM PDT 24
Finished May 30 03:42:35 PM PDT 24
Peak memory 205544 kb
Host smart-04a30807-a915-4188-85bb-545d1153c845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739
61354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.random_length_in_trans.3073961354
Directory /workspace/0.random_length_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.626605861
Short name T1458
Test name
Test status
Simulation time 14299960495 ps
CPU time 17.81 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:36 PM PDT 24
Peak memory 205652 kb
Host smart-e724a405-ac49-4f55-9e90-23dd07057a59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=626605861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.626605861
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1069046695
Short name T350
Test name
Test status
Simulation time 13236595687 ps
CPU time 18.14 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:36 PM PDT 24
Peak memory 205516 kb
Host smart-68921a01-f5ae-4e2f-932e-07022cfd4fab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1069046695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1069046695
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1483388713
Short name T659
Test name
Test status
Simulation time 13287610619 ps
CPU time 16.95 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:30 PM PDT 24
Peak memory 205568 kb
Host smart-3df756e6-7888-4459-a40f-428fa78fac2c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1483388713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.1483388713
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.387080507
Short name T796
Test name
Test status
Simulation time 10083990732 ps
CPU time 13.14 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:27 PM PDT 24
Peak memory 205548 kb
Host smart-c842aeda-2ff8-43a6-a644-32062822a7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38708
0507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.387080507
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2898596709
Short name T831
Test name
Test status
Simulation time 10404705003 ps
CPU time 14.01 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205636 kb
Host smart-6a3487b4-1456-4183-b542-b5788fdea495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28985
96709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2898596709
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4185931045
Short name T612
Test name
Test status
Simulation time 10090634863 ps
CPU time 13.51 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:26 PM PDT 24
Peak memory 205524 kb
Host smart-996c6914-1a2e-4048-954b-7b514cce2e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41859
31045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4185931045
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.1641080222
Short name T672
Test name
Test status
Simulation time 10048013068 ps
CPU time 13.56 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205636 kb
Host smart-691307f2-327f-46dc-b26a-f811c83c7268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16410
80222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1641080222
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.832994221
Short name T1870
Test name
Test status
Simulation time 10749701840 ps
CPU time 14.37 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205256 kb
Host smart-6e5a9052-a279-49b1-aefe-fb72797789c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83299
4221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.832994221
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2163567705
Short name T1003
Test name
Test status
Simulation time 10191527261 ps
CPU time 15.16 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:29 PM PDT 24
Peak memory 205548 kb
Host smart-caa40f1d-1d4f-4ff1-81d0-f3fb88bc83d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21635
67705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2163567705
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.4151216421
Short name T985
Test name
Test status
Simulation time 10109702317 ps
CPU time 13.22 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:29 PM PDT 24
Peak memory 205572 kb
Host smart-c8e34368-785c-4d2e-a269-aec55efaefc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
16421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.4151216421
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.753702538
Short name T1120
Test name
Test status
Simulation time 10056241523 ps
CPU time 15.05 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:29 PM PDT 24
Peak memory 205496 kb
Host smart-e313b31f-f6d2-4298-97f6-6021c31b4ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75370
2538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.753702538
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2557398701
Short name T1276
Test name
Test status
Simulation time 10130157891 ps
CPU time 14.65 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205528 kb
Host smart-0dcb4f34-1b03-4aad-be7f-253a01eb2dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25573
98701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2557398701
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3642627073
Short name T564
Test name
Test status
Simulation time 10094702708 ps
CPU time 13.06 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205572 kb
Host smart-046ecba4-974a-4220-8194-04a31296084f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
27073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3642627073
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.1163587927
Short name T637
Test name
Test status
Simulation time 13160810468 ps
CPU time 17.02 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:34 PM PDT 24
Peak memory 205544 kb
Host smart-e2815903-6e21-424b-8b15-62b585f5e6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635
87927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1163587927
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.4203566643
Short name T320
Test name
Test status
Simulation time 10088337354 ps
CPU time 13.83 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205612 kb
Host smart-77342d47-cfa1-4248-8a3f-7893fdb5ab30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42035
66643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.4203566643
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2910786426
Short name T956
Test name
Test status
Simulation time 10046361741 ps
CPU time 15.6 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:34 PM PDT 24
Peak memory 205572 kb
Host smart-a1d37106-fe4b-476c-ba45-0abf9babc07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29107
86426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2910786426
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.85545868
Short name T296
Test name
Test status
Simulation time 10095695090 ps
CPU time 14.26 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205528 kb
Host smart-ed8da614-63b5-4fb8-8217-0f3f3e774750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85545
868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.85545868
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.49517962
Short name T1817
Test name
Test status
Simulation time 10079808205 ps
CPU time 14.59 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205540 kb
Host smart-3c1b2d04-3c4b-49b0-8945-20c8e063bf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49517
962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.49517962
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.882573358
Short name T325
Test name
Test status
Simulation time 10063397784 ps
CPU time 14.4 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205560 kb
Host smart-74ff0891-a016-4dd0-ae2a-8560b6c998f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88257
3358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.882573358
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1971565826
Short name T1705
Test name
Test status
Simulation time 10061597061 ps
CPU time 13.63 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:30 PM PDT 24
Peak memory 205596 kb
Host smart-1e14509c-7c83-4e04-a4c2-e5def8a08a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
65826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1971565826
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.501615558
Short name T972
Test name
Test status
Simulation time 10083249154 ps
CPU time 15.08 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205572 kb
Host smart-8e6a6058-1018-454e-a5b1-d25c35b0a338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50161
5558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.501615558
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3086718888
Short name T644
Test name
Test status
Simulation time 10075000101 ps
CPU time 13.64 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205560 kb
Host smart-41dc866a-15ff-4853-bf21-f72e02baefc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30867
18888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3086718888
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1292419020
Short name T742
Test name
Test status
Simulation time 10047942758 ps
CPU time 12.54 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205532 kb
Host smart-4fa3ba94-8fb1-47a9-8f5c-03642b1ece1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12924
19020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1292419020
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3440559601
Short name T785
Test name
Test status
Simulation time 20563318410 ps
CPU time 36.92 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:54 PM PDT 24
Peak memory 205604 kb
Host smart-dd955ca8-8349-4d9e-95e5-d23f66a60db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34405
59601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3440559601
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2181011516
Short name T508
Test name
Test status
Simulation time 10110181561 ps
CPU time 17.47 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:36 PM PDT 24
Peak memory 205520 kb
Host smart-e428af88-b0c6-418d-81b5-14f76f48e97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21810
11516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2181011516
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2977035979
Short name T1489
Test name
Test status
Simulation time 10144825954 ps
CPU time 13.67 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205540 kb
Host smart-b0f66648-7fd9-46d8-b4db-ac3bda99ad4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29770
35979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2977035979
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_trans.3636429840
Short name T1592
Test name
Test status
Simulation time 10086172495 ps
CPU time 13.33 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205532 kb
Host smart-4a341172-02c5-45d2-94be-ffad8a8f979b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36364
29840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_trans.3636429840
Directory /workspace/0.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2184337019
Short name T1824
Test name
Test status
Simulation time 10045667674 ps
CPU time 14.94 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205524 kb
Host smart-47b6b6b8-d885-4055-afb4-e744045a4f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21843
37019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2184337019
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1354463581
Short name T194
Test name
Test status
Simulation time 824153766 ps
CPU time 1.64 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:17 PM PDT 24
Peak memory 222780 kb
Host smart-6fd4c2ff-dddd-4364-b9f0-dd4cb2a3c656
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1354463581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1354463581
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.295297280
Short name T968
Test name
Test status
Simulation time 10070516214 ps
CPU time 14.37 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205644 kb
Host smart-2dc039b5-817d-4f03-8422-aa33d5cc1177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
7280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.295297280
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3375776212
Short name T1394
Test name
Test status
Simulation time 10081774927 ps
CPU time 12.81 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205580 kb
Host smart-06d1a98a-9808-48cb-b324-7be555fc1cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33757
76212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3375776212
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1100717053
Short name T1392
Test name
Test status
Simulation time 10199844120 ps
CPU time 12.89 seconds
Started May 30 03:41:58 PM PDT 24
Finished May 30 03:42:13 PM PDT 24
Peak memory 205544 kb
Host smart-db1f2e0c-72ea-4332-bc1b-9c214e506065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11007
17053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1100717053
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1732804785
Short name T792
Test name
Test status
Simulation time 10063130489 ps
CPU time 13.49 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205548 kb
Host smart-489eaaa4-a7ca-4e5f-8fe3-0f05a20340df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17328
04785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1732804785
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2837407437
Short name T1109
Test name
Test status
Simulation time 10113636584 ps
CPU time 14.06 seconds
Started May 30 03:42:16 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205500 kb
Host smart-dd124463-d70a-4944-910e-f5265c777c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
07437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2837407437
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.max_length_in_transaction.2570507195
Short name T992
Test name
Test status
Simulation time 10143929130 ps
CPU time 13.7 seconds
Started May 30 03:42:30 PM PDT 24
Finished May 30 03:42:46 PM PDT 24
Peak memory 205584 kb
Host smart-4ddd2ae6-42b5-41be-9061-06f65251a92e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2570507195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.max_length_in_transaction.2570507195
Directory /workspace/1.max_length_in_transaction/latest

Test location /workspace/coverage/default/1.min_length_in_transaction.2274730821
Short name T1668
Test name
Test status
Simulation time 10109981158 ps
CPU time 14.38 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205544 kb
Host smart-31c4bd6a-7d2f-49a0-a0d0-d28b4fdadb05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2274730821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.min_length_in_transaction.2274730821
Directory /workspace/1.min_length_in_transaction/latest

Test location /workspace/coverage/default/1.random_length_in_trans.2680873569
Short name T1807
Test name
Test status
Simulation time 10063768981 ps
CPU time 13.79 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205332 kb
Host smart-f79b21f5-ddb8-4cfe-9314-fe026083104b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808
73569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.random_length_in_trans.2680873569
Directory /workspace/1.random_length_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1625697132
Short name T653
Test name
Test status
Simulation time 13809809965 ps
CPU time 18.59 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:36 PM PDT 24
Peak memory 205588 kb
Host smart-1ed1a1d1-0706-4edb-b71c-9d8e344afa31
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1625697132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1625697132
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3122839901
Short name T880
Test name
Test status
Simulation time 13290311318 ps
CPU time 19.73 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205544 kb
Host smart-dc80bf5d-5b37-4d5a-9a51-f8500d49cc82
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3122839901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3122839901
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1133577040
Short name T1089
Test name
Test status
Simulation time 13392118325 ps
CPU time 18.48 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:36 PM PDT 24
Peak memory 205560 kb
Host smart-d18f77e1-1ad8-4a28-8ee3-460f3e2f4634
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1133577040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1133577040
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2824561949
Short name T696
Test name
Test status
Simulation time 10050952830 ps
CPU time 12.87 seconds
Started May 30 03:42:17 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205520 kb
Host smart-a93db9dc-58c1-4705-9375-e83ce1ea13fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
61949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2824561949
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4175840145
Short name T721
Test name
Test status
Simulation time 10764949314 ps
CPU time 14.9 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:29 PM PDT 24
Peak memory 205664 kb
Host smart-71763536-12eb-4d2a-acf5-edd8d75184fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
40145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4175840145
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.483159000
Short name T1449
Test name
Test status
Simulation time 10098712971 ps
CPU time 14.67 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:34 PM PDT 24
Peak memory 205512 kb
Host smart-2baa9e00-6b88-4af0-9826-2c3d69e49da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48315
9000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.483159000
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2878144398
Short name T685
Test name
Test status
Simulation time 10048881604 ps
CPU time 14.34 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205152 kb
Host smart-27a9ef9f-0ec2-49db-81ba-58015a4916df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
44398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2878144398
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.3896747068
Short name T1474
Test name
Test status
Simulation time 10647597246 ps
CPU time 14.45 seconds
Started May 30 03:42:11 PM PDT 24
Finished May 30 03:42:27 PM PDT 24
Peak memory 205556 kb
Host smart-cecfb2a5-0fcd-4940-ade0-baa681d85003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38967
47068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.3896747068
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3839809696
Short name T1014
Test name
Test status
Simulation time 10124127244 ps
CPU time 14.92 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205500 kb
Host smart-8edb86ac-1f0b-4a44-b149-b2f9f2f83c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
09696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3839809696
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3087208557
Short name T31
Test name
Test status
Simulation time 10059426716 ps
CPU time 13.05 seconds
Started May 30 03:42:30 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205572 kb
Host smart-2e00f4b0-9129-4bfc-8531-d22026a01fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30872
08557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3087208557
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.231812990
Short name T1775
Test name
Test status
Simulation time 10084175738 ps
CPU time 13.62 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205504 kb
Host smart-b4865ce5-ddfb-4fca-a96e-55564d6a6e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23181
2990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.231812990
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2250610966
Short name T711
Test name
Test status
Simulation time 10086690489 ps
CPU time 14.86 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:34 PM PDT 24
Peak memory 205480 kb
Host smart-fcd49bfd-c742-4d9a-9bfb-5511b7829d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22506
10966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2250610966
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.4169613755
Short name T635
Test name
Test status
Simulation time 13165583917 ps
CPU time 19.7 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:37 PM PDT 24
Peak memory 205464 kb
Host smart-391eeac9-477e-4fe1-acfb-ceefb962f0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
13755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.4169613755
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.945613516
Short name T1799
Test name
Test status
Simulation time 10143672889 ps
CPU time 13.72 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205520 kb
Host smart-9e903462-0926-4c9a-999e-df35f36b36e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94561
3516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.945613516
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.456773405
Short name T1811
Test name
Test status
Simulation time 10075206004 ps
CPU time 14.64 seconds
Started May 30 03:42:15 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205552 kb
Host smart-8b170e32-71ba-44c3-b5fb-4139d739c63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45677
3405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.456773405
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.2396566721
Short name T867
Test name
Test status
Simulation time 10091352359 ps
CPU time 14.55 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205576 kb
Host smart-edc286c4-4d4a-4e90-9828-1a3706924d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
66721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2396566721
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3462771780
Short name T1696
Test name
Test status
Simulation time 10076496891 ps
CPU time 13.87 seconds
Started May 30 03:42:16 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205544 kb
Host smart-25c18308-47a0-4982-9006-d22f38ca0852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34627
71780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3462771780
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2402161647
Short name T1315
Test name
Test status
Simulation time 10072146270 ps
CPU time 13.4 seconds
Started May 30 03:42:14 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205556 kb
Host smart-375b2fa7-1e65-4e0d-84ba-34cbdf8b871a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24021
61647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2402161647
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.2543551380
Short name T1740
Test name
Test status
Simulation time 10078510437 ps
CPU time 13.31 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205516 kb
Host smart-f91babbe-4b6d-445b-ba5e-d9aaaf5ef216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25435
51380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.2543551380
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2999529500
Short name T1362
Test name
Test status
Simulation time 10041757936 ps
CPU time 14.17 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205552 kb
Host smart-d612c3ac-295d-4fb0-a476-0c10fc595cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995
29500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2999529500
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3659293662
Short name T1791
Test name
Test status
Simulation time 10040020373 ps
CPU time 13.57 seconds
Started May 30 03:42:25 PM PDT 24
Finished May 30 03:42:40 PM PDT 24
Peak memory 205568 kb
Host smart-731b3c05-ee06-42af-abd7-2951a74aad48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36592
93662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3659293662
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1325948174
Short name T1344
Test name
Test status
Simulation time 10090680645 ps
CPU time 15.17 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 205548 kb
Host smart-4f72d3ea-eeeb-4c0f-86b6-12e445d59c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13259
48174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1325948174
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2622709864
Short name T569
Test name
Test status
Simulation time 10173985952 ps
CPU time 14.65 seconds
Started May 30 03:42:13 PM PDT 24
Finished May 30 03:42:31 PM PDT 24
Peak memory 205488 kb
Host smart-7503d1d8-4d25-47f3-8bea-1df1ee039e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26227
09864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2622709864
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_trans.1593715416
Short name T1778
Test name
Test status
Simulation time 10097063689 ps
CPU time 13.23 seconds
Started May 30 03:42:16 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205568 kb
Host smart-4bed13fa-e50b-4263-8821-fd213a3dca1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15937
15416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_trans.1593715416
Directory /workspace/1.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2724480113
Short name T1463
Test name
Test status
Simulation time 10038672219 ps
CPU time 13.84 seconds
Started May 30 03:42:16 PM PDT 24
Finished May 30 03:42:33 PM PDT 24
Peak memory 205540 kb
Host smart-4dac400e-4c70-4a46-8a45-8dcb21f42a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
80113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2724480113
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1816702083
Short name T694
Test name
Test status
Simulation time 10076911536 ps
CPU time 15.61 seconds
Started May 30 03:42:24 PM PDT 24
Finished May 30 03:42:41 PM PDT 24
Peak memory 205552 kb
Host smart-64172e73-2dea-40bb-b4ba-cedd05c4947e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
02083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1816702083
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3499658381
Short name T1575
Test name
Test status
Simulation time 10092015795 ps
CPU time 14 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:42 PM PDT 24
Peak memory 205612 kb
Host smart-50baa47a-76ae-400f-9ba2-c2c7efddcb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34996
58381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3499658381
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3980505280
Short name T838
Test name
Test status
Simulation time 10124658391 ps
CPU time 13.2 seconds
Started May 30 03:42:12 PM PDT 24
Finished May 30 03:42:28 PM PDT 24
Peak memory 205572 kb
Host smart-cd7d9553-a4bf-4062-867c-bf2dada58286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
05280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3980505280
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1870973266
Short name T691
Test name
Test status
Simulation time 10071494307 ps
CPU time 13.5 seconds
Started May 30 03:42:24 PM PDT 24
Finished May 30 03:42:39 PM PDT 24
Peak memory 205556 kb
Host smart-25f8b1f4-f1c8-4f85-980e-de7f1822e428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709
73266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1870973266
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.4160421141
Short name T472
Test name
Test status
Simulation time 10082023334 ps
CPU time 14.23 seconds
Started May 30 03:42:16 PM PDT 24
Finished May 30 03:42:34 PM PDT 24
Peak memory 205560 kb
Host smart-aa26b347-8caf-4c85-8c3d-91d7dec04f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41604
21141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.4160421141
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.max_length_in_transaction.3482670838
Short name T650
Test name
Test status
Simulation time 10160952218 ps
CPU time 15.04 seconds
Started May 30 03:43:45 PM PDT 24
Finished May 30 03:44:02 PM PDT 24
Peak memory 205540 kb
Host smart-51cc4828-8168-40e3-8212-f5a67e8d64d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3482670838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.max_length_in_transaction.3482670838
Directory /workspace/10.max_length_in_transaction/latest

Test location /workspace/coverage/default/10.min_length_in_transaction.2804997821
Short name T1349
Test name
Test status
Simulation time 10057147100 ps
CPU time 12.62 seconds
Started May 30 03:43:46 PM PDT 24
Finished May 30 03:44:01 PM PDT 24
Peak memory 205580 kb
Host smart-9638d63a-b66d-4fbe-8e4c-63bb84865818
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2804997821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.min_length_in_transaction.2804997821
Directory /workspace/10.min_length_in_transaction/latest

Test location /workspace/coverage/default/10.random_length_in_trans.3354826164
Short name T294
Test name
Test status
Simulation time 10182388447 ps
CPU time 13.02 seconds
Started May 30 03:43:45 PM PDT 24
Finished May 30 03:44:00 PM PDT 24
Peak memory 205552 kb
Host smart-57bf84ac-a0b1-478b-b82d-84eb491e338c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
26164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.random_length_in_trans.3354826164
Directory /workspace/10.random_length_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1620401832
Short name T559
Test name
Test status
Simulation time 13787855732 ps
CPU time 17.56 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205612 kb
Host smart-0835cea9-a428-432e-9c46-13d73b962e37
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1620401832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1620401832
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.932527270
Short name T1641
Test name
Test status
Simulation time 13228659383 ps
CPU time 18.19 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:56 PM PDT 24
Peak memory 205536 kb
Host smart-e111ddff-69d9-4f03-a511-61b4623d80db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=932527270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.932527270
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2221291208
Short name T1148
Test name
Test status
Simulation time 13249290575 ps
CPU time 16.25 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205552 kb
Host smart-d46a586b-d2bc-486f-b87a-e0dd2e94d605
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2221291208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.2221291208
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.494114563
Short name T1882
Test name
Test status
Simulation time 10078051266 ps
CPU time 13.56 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205512 kb
Host smart-ef975ec4-9dbd-4946-94a5-f9be44156fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49411
4563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.494114563
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3191253026
Short name T164
Test name
Test status
Simulation time 11142463456 ps
CPU time 17.38 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205604 kb
Host smart-df52754b-e813-440b-80d4-ebfab4483d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
53026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3191253026
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2914645671
Short name T761
Test name
Test status
Simulation time 10053739054 ps
CPU time 13.75 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205480 kb
Host smart-6f86efbc-cec1-45a0-ba3b-ba2b6bc07e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29146
45671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2914645671
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.1064211655
Short name T910
Test name
Test status
Simulation time 10143015703 ps
CPU time 14.01 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205600 kb
Host smart-e3587403-4fee-49f6-982d-0ff8b0e9246e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
11655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1064211655
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.951735057
Short name T1601
Test name
Test status
Simulation time 10750228599 ps
CPU time 18.61 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205568 kb
Host smart-f3f83548-0d45-4519-be1d-aacd889c8593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95173
5057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.951735057
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2705994011
Short name T1554
Test name
Test status
Simulation time 10205614109 ps
CPU time 14.45 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205556 kb
Host smart-41639c42-5975-4442-b046-2cbde7f06232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
94011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2705994011
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3478996370
Short name T746
Test name
Test status
Simulation time 10066529965 ps
CPU time 13.41 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205544 kb
Host smart-7d9f79d6-8b35-4d0f-b1d5-b9bc59000b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34789
96370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3478996370
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2670996918
Short name T861
Test name
Test status
Simulation time 10119263922 ps
CPU time 16.07 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205492 kb
Host smart-e6962d9c-a2b3-4ca1-a79c-e8351b40aedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26709
96918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2670996918
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.4263247099
Short name T57
Test name
Test status
Simulation time 10076221332 ps
CPU time 14.08 seconds
Started May 30 03:43:38 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205548 kb
Host smart-e8e71150-ede4-4cef-ad3a-c4226285c9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42632
47099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.4263247099
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.678755922
Short name T1034
Test name
Test status
Simulation time 13221069410 ps
CPU time 16.75 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205572 kb
Host smart-f354442c-6c16-4bcd-a0ae-65f6e00c1f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67875
5922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.678755922
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2609022380
Short name T1607
Test name
Test status
Simulation time 10118683851 ps
CPU time 15.06 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205576 kb
Host smart-9e159cc4-3d1e-47db-bd8e-d6111bda63d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26090
22380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2609022380
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.4243208140
Short name T1560
Test name
Test status
Simulation time 10060191052 ps
CPU time 13.82 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205576 kb
Host smart-3ab25948-60bb-49a1-b97d-cdb5dbf94866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42432
08140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.4243208140
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1041597224
Short name T646
Test name
Test status
Simulation time 10095411888 ps
CPU time 15.9 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:56 PM PDT 24
Peak memory 205496 kb
Host smart-c4fffccf-a01c-4147-b7a7-c012cb377a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10415
97224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1041597224
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.921886270
Short name T1616
Test name
Test status
Simulation time 10107465068 ps
CPU time 13.97 seconds
Started May 30 03:43:38 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205544 kb
Host smart-d0f3e192-85ad-47ec-b6d5-ea6ebcdb1f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92188
6270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.921886270
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.724065439
Short name T1574
Test name
Test status
Simulation time 10043517232 ps
CPU time 13.58 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205508 kb
Host smart-fbeeb39b-f1bd-438e-95f1-484f83b8c1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72406
5439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.724065439
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.2569486759
Short name T468
Test name
Test status
Simulation time 10076301346 ps
CPU time 13.03 seconds
Started May 30 03:43:38 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205572 kb
Host smart-fd743072-70f4-43c7-89ac-1f873d0bb212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25694
86759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.2569486759
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3758324973
Short name T1788
Test name
Test status
Simulation time 10065030376 ps
CPU time 13.47 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205484 kb
Host smart-b2bb0702-a1d6-4e08-9b7d-bf261ca44b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
24973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3758324973
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2583105690
Short name T1019
Test name
Test status
Simulation time 10045084501 ps
CPU time 15.6 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205516 kb
Host smart-0a87bdc7-0b8a-4814-a299-284bf1793446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25831
05690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2583105690
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3129139440
Short name T1818
Test name
Test status
Simulation time 17061933729 ps
CPU time 28.6 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205616 kb
Host smart-aba90905-c62b-4f6f-87a4-a2ceb4968aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31291
39440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3129139440
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1401630523
Short name T1401
Test name
Test status
Simulation time 10083981642 ps
CPU time 15.89 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205520 kb
Host smart-ef0f5808-9e3e-4887-bf11-49c213ab489b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14016
30523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1401630523
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.231733635
Short name T458
Test name
Test status
Simulation time 10123061347 ps
CPU time 14.98 seconds
Started May 30 03:43:39 PM PDT 24
Finished May 30 03:43:56 PM PDT 24
Peak memory 205540 kb
Host smart-eb22be74-6ba3-438c-853e-6b8ac92da93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
3635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.231733635
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_trans.2758355530
Short name T1357
Test name
Test status
Simulation time 10090779761 ps
CPU time 13.87 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205552 kb
Host smart-6592ce3d-4760-4e21-b160-056d7faae654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583
55530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_trans.2758355530
Directory /workspace/10.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.3078808763
Short name T768
Test name
Test status
Simulation time 10063760616 ps
CPU time 15.45 seconds
Started May 30 03:43:38 PM PDT 24
Finished May 30 03:43:56 PM PDT 24
Peak memory 205528 kb
Host smart-bbceb0fd-217a-4c58-9cf2-6c6199c44e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30788
08763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.3078808763
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3215916434
Short name T1035
Test name
Test status
Simulation time 10052497720 ps
CPU time 13.56 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205536 kb
Host smart-0a6c2035-69e8-4147-98b9-5ead45943393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32159
16434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3215916434
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.626812720
Short name T135
Test name
Test status
Simulation time 10113373659 ps
CPU time 14.84 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205536 kb
Host smart-7eb584ac-063d-4c75-86a3-6f7fb35e9aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62681
2720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.626812720
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2874269752
Short name T514
Test name
Test status
Simulation time 10050577197 ps
CPU time 13.94 seconds
Started May 30 03:43:39 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205604 kb
Host smart-6c6a33eb-773d-42ce-a7b7-e03dfd8f30a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
69752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2874269752
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2613554222
Short name T537
Test name
Test status
Simulation time 10060300814 ps
CPU time 13 seconds
Started May 30 03:43:39 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205572 kb
Host smart-01d65e24-14ad-4c49-9a42-9ca9159e69a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26135
54222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2613554222
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.max_length_in_transaction.4169399797
Short name T1099
Test name
Test status
Simulation time 10149462356 ps
CPU time 13.52 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205536 kb
Host smart-24f88436-c9c7-4067-b959-b44cddef3a9c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4169399797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.max_length_in_transaction.4169399797
Directory /workspace/11.max_length_in_transaction/latest

Test location /workspace/coverage/default/11.min_length_in_transaction.1248454389
Short name T1378
Test name
Test status
Simulation time 10059684737 ps
CPU time 14.96 seconds
Started May 30 03:43:53 PM PDT 24
Finished May 30 03:44:10 PM PDT 24
Peak memory 205272 kb
Host smart-35b5c8e9-38b3-4633-a1eb-ac08e43c9b44
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1248454389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.min_length_in_transaction.1248454389
Directory /workspace/11.min_length_in_transaction/latest

Test location /workspace/coverage/default/11.random_length_in_trans.1143978030
Short name T1666
Test name
Test status
Simulation time 10126928933 ps
CPU time 14.43 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205552 kb
Host smart-02ad9102-8e31-407a-8568-b64b7277d5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11439
78030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.random_length_in_trans.1143978030
Directory /workspace/11.random_length_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2625780303
Short name T467
Test name
Test status
Simulation time 13444152601 ps
CPU time 17.15 seconds
Started May 30 03:43:51 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205616 kb
Host smart-6c92dba9-37d9-4ca1-94fa-963e48f9d330
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625780303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2625780303
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.2106492190
Short name T1264
Test name
Test status
Simulation time 13336183854 ps
CPU time 16.94 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205560 kb
Host smart-8ed1b553-afba-4d3f-8673-57d52411ebd5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2106492190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.2106492190
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4211897703
Short name T926
Test name
Test status
Simulation time 13334578395 ps
CPU time 20.05 seconds
Started May 30 03:43:45 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205564 kb
Host smart-170709c2-4cde-4fcb-b4c9-0c7973d6d74b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4211897703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.4211897703
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.607899324
Short name T572
Test name
Test status
Simulation time 10061068177 ps
CPU time 14.46 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 204948 kb
Host smart-84fe25da-7d40-4546-b28b-5cf08435fff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60789
9324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.607899324
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1556607999
Short name T1684
Test name
Test status
Simulation time 10185904229 ps
CPU time 14.08 seconds
Started May 30 03:43:46 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205616 kb
Host smart-615fb002-77a3-4a70-89f9-3ac526e427f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
07999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1556607999
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2589554953
Short name T892
Test name
Test status
Simulation time 10101315957 ps
CPU time 15.72 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205564 kb
Host smart-cd434ff8-12b7-4be3-85c4-7c8860705846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25895
54953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2589554953
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1248269363
Short name T477
Test name
Test status
Simulation time 10069448466 ps
CPU time 13.07 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 205532 kb
Host smart-cf33ffc2-a805-478e-8835-a51c8db6b37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12482
69363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1248269363
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.780793672
Short name T567
Test name
Test status
Simulation time 10876168314 ps
CPU time 16.08 seconds
Started May 30 03:43:45 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205528 kb
Host smart-39f20663-87b7-4c9d-be6a-3940d12ac034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78079
3672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.780793672
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2442381291
Short name T941
Test name
Test status
Simulation time 10118178819 ps
CPU time 12.9 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205492 kb
Host smart-62cce123-17cd-4d29-9846-9574cdd3cafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24423
81291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2442381291
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2939115626
Short name T1721
Test name
Test status
Simulation time 10036744793 ps
CPU time 12.99 seconds
Started May 30 03:43:45 PM PDT 24
Finished May 30 03:44:00 PM PDT 24
Peak memory 205592 kb
Host smart-34b0597f-86b9-4918-b1f9-57dfa1fe145d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29391
15626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2939115626
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.233167189
Short name T1163
Test name
Test status
Simulation time 10121930463 ps
CPU time 14.22 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205488 kb
Host smart-04edccde-330c-4d85-b35a-0aa997170e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23316
7189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.233167189
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.506142376
Short name T1741
Test name
Test status
Simulation time 10103283799 ps
CPU time 13.72 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 205572 kb
Host smart-0b346d3c-042a-4168-be6b-cea668784b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50614
2376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.506142376
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.341280818
Short name T1118
Test name
Test status
Simulation time 13256450458 ps
CPU time 19.64 seconds
Started May 30 03:43:46 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205524 kb
Host smart-36a70e6b-3c63-436c-979d-0630914bb108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
0818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.341280818
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.625722576
Short name T1816
Test name
Test status
Simulation time 10095894108 ps
CPU time 13.79 seconds
Started May 30 03:43:50 PM PDT 24
Finished May 30 03:44:07 PM PDT 24
Peak memory 205532 kb
Host smart-176346b4-893a-4f4c-bcf9-1980ce6db27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62572
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.625722576
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2809082028
Short name T1284
Test name
Test status
Simulation time 10076734995 ps
CPU time 15.09 seconds
Started May 30 03:43:45 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205516 kb
Host smart-4ff6b9b1-4d4b-4e05-adf7-5c45787abd83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28090
82028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2809082028
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.376961542
Short name T1425
Test name
Test status
Simulation time 10088049309 ps
CPU time 13.67 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205324 kb
Host smart-daaa4ec3-984a-4d74-8ab5-eb2fca1871f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37696
1542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.376961542
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2244949386
Short name T1121
Test name
Test status
Simulation time 10075909575 ps
CPU time 12.66 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205592 kb
Host smart-ea5b48fe-7ef8-4e0c-a9c8-ad629c3413b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22449
49386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2244949386
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.890557576
Short name T1225
Test name
Test status
Simulation time 10127083127 ps
CPU time 15.98 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 205548 kb
Host smart-fdd9060f-c2c0-4cfd-b7aa-eec1591bd29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89055
7576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.890557576
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2415112280
Short name T173
Test name
Test status
Simulation time 10133005461 ps
CPU time 16.23 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:07 PM PDT 24
Peak memory 205548 kb
Host smart-c1162998-15fc-47aa-9f26-11805f16413b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24151
12280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2415112280
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.241750338
Short name T311
Test name
Test status
Simulation time 10133611403 ps
CPU time 15.63 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205068 kb
Host smart-f8d2bcf7-05af-491a-b18b-fc431e344472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24175
0338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.241750338
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3739738991
Short name T818
Test name
Test status
Simulation time 10057742262 ps
CPU time 15.23 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205372 kb
Host smart-ee973e76-7dab-495d-bca5-a3f20eb10f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37397
38991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3739738991
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2966226005
Short name T1540
Test name
Test status
Simulation time 17062530262 ps
CPU time 29 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:20 PM PDT 24
Peak memory 205604 kb
Host smart-15dd68ec-a555-40c9-9db0-0b5e6a103364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
26005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2966226005
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3984446535
Short name T811
Test name
Test status
Simulation time 10066502589 ps
CPU time 15.08 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205564 kb
Host smart-28fd7f01-6296-4fcf-b32f-af8a7d51eb98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39844
46535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3984446535
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.446760674
Short name T1172
Test name
Test status
Simulation time 10192543098 ps
CPU time 14.33 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205488 kb
Host smart-f8b004c8-9580-42f4-8b9d-a63cdc03a560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44676
0674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.446760674
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_trans.2684139076
Short name T427
Test name
Test status
Simulation time 10063025491 ps
CPU time 14.19 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205548 kb
Host smart-6c78ca55-a6d5-4849-aec7-7fcfe07aaa3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26841
39076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_trans.2684139076
Directory /workspace/11.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2622562396
Short name T879
Test name
Test status
Simulation time 10041111852 ps
CPU time 13.02 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205572 kb
Host smart-cbe5006f-6021-4eb3-a531-61c5d80d00c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
62396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2622562396
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.261697478
Short name T1469
Test name
Test status
Simulation time 10045020974 ps
CPU time 14.01 seconds
Started May 30 03:43:50 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205540 kb
Host smart-9b07599f-726f-4fe0-aa40-a8ffe19f0f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26169
7478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.261697478
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3604709423
Short name T1290
Test name
Test status
Simulation time 10067214452 ps
CPU time 14.59 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:07 PM PDT 24
Peak memory 205528 kb
Host smart-adb11df4-9c64-4faa-afb5-98792b478007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36047
09423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3604709423
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.93139274
Short name T148
Test name
Test status
Simulation time 10089570909 ps
CPU time 13.11 seconds
Started May 30 03:43:53 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205568 kb
Host smart-14b9f64d-0d34-48df-acea-9de64d15a525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93139
274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.93139274
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3989204543
Short name T938
Test name
Test status
Simulation time 10106707103 ps
CPU time 13.25 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205544 kb
Host smart-40391895-fcbf-43b5-8f79-4ae271005b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39892
04543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3989204543
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.445063467
Short name T700
Test name
Test status
Simulation time 10080431007 ps
CPU time 15.87 seconds
Started May 30 03:43:44 PM PDT 24
Finished May 30 03:44:02 PM PDT 24
Peak memory 205544 kb
Host smart-c6450869-4e0c-47cf-8aee-0db4a544a840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44506
3467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.445063467
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.max_length_in_transaction.4122704955
Short name T1136
Test name
Test status
Simulation time 10147700662 ps
CPU time 16.04 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205508 kb
Host smart-2378c2e9-c48e-48c4-b014-37d99de373bf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4122704955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.max_length_in_transaction.4122704955
Directory /workspace/12.max_length_in_transaction/latest

Test location /workspace/coverage/default/12.min_length_in_transaction.1887494859
Short name T492
Test name
Test status
Simulation time 10057418387 ps
CPU time 13.77 seconds
Started May 30 03:43:51 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205564 kb
Host smart-bf3e2002-f6be-486c-a383-bba39ffbcfab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1887494859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.min_length_in_transaction.1887494859
Directory /workspace/12.min_length_in_transaction/latest

Test location /workspace/coverage/default/12.random_length_in_trans.768932824
Short name T1590
Test name
Test status
Simulation time 10101792573 ps
CPU time 14.46 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205536 kb
Host smart-1468c93d-4ecf-4f0c-8efe-5778ae0cfecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76893
2824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.random_length_in_trans.768932824
Directory /workspace/12.random_length_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.691334140
Short name T663
Test name
Test status
Simulation time 13941041748 ps
CPU time 16.66 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205576 kb
Host smart-caa24a97-ac11-49af-ab0a-08b043b82d9a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=691334140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.691334140
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3452528519
Short name T1283
Test name
Test status
Simulation time 13306639184 ps
CPU time 20.72 seconds
Started May 30 03:43:50 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205564 kb
Host smart-fd5fcc61-eb31-4764-9c2b-aecc99b93f48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3452528519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3452528519
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3634728072
Short name T526
Test name
Test status
Simulation time 13260160739 ps
CPU time 16.06 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205596 kb
Host smart-b8a63bd7-bb1a-4ba5-8c07-b45157a95953
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3634728072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.3634728072
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.93408078
Short name T510
Test name
Test status
Simulation time 10063638916 ps
CPU time 13.92 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 205460 kb
Host smart-f3c03155-c347-41d7-888d-18aff64133b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93408
078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.93408078
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1802584461
Short name T1162
Test name
Test status
Simulation time 10546278077 ps
CPU time 14.51 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205540 kb
Host smart-0fc33d30-1758-4bcc-9865-33860b060fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
84461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1802584461
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.114784467
Short name T1917
Test name
Test status
Simulation time 10051971596 ps
CPU time 16.36 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205524 kb
Host smart-e035c066-40b2-4032-a216-572ce578dccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
4467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.114784467
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1883693050
Short name T417
Test name
Test status
Simulation time 10078166319 ps
CPU time 13.9 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 205612 kb
Host smart-35224648-aaf1-489a-81cd-461ee521b02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18836
93050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1883693050
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1704380108
Short name T1055
Test name
Test status
Simulation time 10882013001 ps
CPU time 14.7 seconds
Started May 30 03:43:53 PM PDT 24
Finished May 30 03:44:10 PM PDT 24
Peak memory 205556 kb
Host smart-1b0d9cce-142c-4c92-99e4-323181cd3baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17043
80108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1704380108
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2981245817
Short name T1681
Test name
Test status
Simulation time 10313670990 ps
CPU time 16.4 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205544 kb
Host smart-64a3cdea-8afc-43c1-8439-1892ee6181bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29812
45817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2981245817
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2524158853
Short name T962
Test name
Test status
Simulation time 10059884454 ps
CPU time 15.13 seconds
Started May 30 03:43:53 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205536 kb
Host smart-56c0cd47-e3a1-43cf-b455-d790d547a5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25241
58853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2524158853
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2688981067
Short name T354
Test name
Test status
Simulation time 10061708142 ps
CPU time 14.72 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205580 kb
Host smart-2b1bfaae-0386-4ac5-b572-f64e01d6cf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889
81067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2688981067
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1961372291
Short name T948
Test name
Test status
Simulation time 10087334950 ps
CPU time 14.49 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:07 PM PDT 24
Peak memory 205540 kb
Host smart-0c2e59f0-8269-4b83-bfb2-8a6153313082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
72291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1961372291
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2973101189
Short name T469
Test name
Test status
Simulation time 10095732162 ps
CPU time 14.36 seconds
Started May 30 03:43:57 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205572 kb
Host smart-5b148d5d-6e2b-47c6-bc21-cad7dd583ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29731
01189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2973101189
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2080725744
Short name T1249
Test name
Test status
Simulation time 13210612880 ps
CPU time 17.42 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:15 PM PDT 24
Peak memory 205516 kb
Host smart-8b99ff7f-47eb-4571-a602-16dd15774e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
25744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2080725744
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3443106984
Short name T1354
Test name
Test status
Simulation time 10082970801 ps
CPU time 15.86 seconds
Started May 30 03:43:53 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205284 kb
Host smart-32a4ab1e-f006-41e6-a5a4-a8603db02b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
06984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3443106984
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.4045091931
Short name T633
Test name
Test status
Simulation time 10052482749 ps
CPU time 13.97 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205588 kb
Host smart-88381e22-f72d-41a1-8123-911cb70c8a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40450
91931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.4045091931
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.4212594184
Short name T903
Test name
Test status
Simulation time 10099065928 ps
CPU time 14.26 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205548 kb
Host smart-8a374d65-caa0-4fda-a785-5790e3dd8090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42125
94184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.4212594184
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3329421970
Short name T1465
Test name
Test status
Simulation time 10080462079 ps
CPU time 13.7 seconds
Started May 30 03:43:57 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205560 kb
Host smart-2e61af8a-ec8c-44b3-aeee-a87a6fda6619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33294
21970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3329421970
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1669666636
Short name T1880
Test name
Test status
Simulation time 10095421717 ps
CPU time 14.84 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:07 PM PDT 24
Peak memory 205572 kb
Host smart-a5a83f75-77d1-48ca-b883-d08b07cf7d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
66636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1669666636
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.781253774
Short name T1725
Test name
Test status
Simulation time 10158142517 ps
CPU time 13.16 seconds
Started May 30 03:43:53 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205552 kb
Host smart-180c1da3-3a45-41f9-b12b-791018d41a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78125
3774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.781253774
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.4184574964
Short name T1680
Test name
Test status
Simulation time 10097917729 ps
CPU time 14.66 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205464 kb
Host smart-8d57d2da-bc32-44ed-a60b-b24fb2a661ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
74964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.4184574964
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1442361793
Short name T555
Test name
Test status
Simulation time 10041595520 ps
CPU time 13.21 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205576 kb
Host smart-8958904b-42ce-44a7-8043-65a8d93b7e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423
61793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1442361793
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.219849497
Short name T1612
Test name
Test status
Simulation time 10062073563 ps
CPU time 15.68 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205532 kb
Host smart-971c4669-d3bf-486f-9c4a-741181c0ae4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21984
9497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.219849497
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2705282970
Short name T1346
Test name
Test status
Simulation time 19539991111 ps
CPU time 35.44 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:33 PM PDT 24
Peak memory 205540 kb
Host smart-1e45626c-0d9e-40e9-b369-e720992901da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27052
82970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2705282970
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3248781777
Short name T1407
Test name
Test status
Simulation time 10129156680 ps
CPU time 13.06 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205572 kb
Host smart-bceec43e-0ea1-4532-a4ab-2598e53c4117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32487
81777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3248781777
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2510948038
Short name T446
Test name
Test status
Simulation time 10130323372 ps
CPU time 13.57 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205580 kb
Host smart-44565417-8aa7-4347-ac50-8925df483e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
48038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2510948038
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_trans.453954077
Short name T1750
Test name
Test status
Simulation time 10090613489 ps
CPU time 13.36 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205520 kb
Host smart-fe2423bb-2463-4e84-8bb5-57e05e5d9745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45395
4077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_trans.453954077
Directory /workspace/12.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.883453614
Short name T52
Test name
Test status
Simulation time 10058647829 ps
CPU time 13.3 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:06 PM PDT 24
Peak memory 205524 kb
Host smart-ede33cd0-85c2-429a-bdce-3b5dd42c916c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88345
3614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.883453614
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2129079215
Short name T789
Test name
Test status
Simulation time 10048784598 ps
CPU time 15.68 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:15 PM PDT 24
Peak memory 205460 kb
Host smart-c79ba7a9-894b-4e97-bf59-a1823906566a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21290
79215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2129079215
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1286278046
Short name T1518
Test name
Test status
Simulation time 10107337280 ps
CPU time 14.11 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205160 kb
Host smart-b3d67d8f-86f0-469f-8e27-6a5f59f959fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12862
78046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1286278046
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.770990749
Short name T652
Test name
Test status
Simulation time 10125803353 ps
CPU time 14.31 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:04 PM PDT 24
Peak memory 205496 kb
Host smart-7fc74a69-a686-4330-9547-30bedb84e5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77099
0749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.770990749
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.517119650
Short name T1073
Test name
Test status
Simulation time 10090111793 ps
CPU time 13.68 seconds
Started May 30 03:43:52 PM PDT 24
Finished May 30 03:44:09 PM PDT 24
Peak memory 205520 kb
Host smart-5edaa507-4d62-48ab-b5ab-baf99268fa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51711
9650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.517119650
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.804526187
Short name T1028
Test name
Test status
Simulation time 10058534256 ps
CPU time 13.77 seconds
Started May 30 03:43:48 PM PDT 24
Finished May 30 03:44:05 PM PDT 24
Peak memory 205500 kb
Host smart-a35639ed-216a-4549-93dc-cbb9fefdac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80452
6187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.804526187
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.max_length_in_transaction.1920618351
Short name T1615
Test name
Test status
Simulation time 10144193352 ps
CPU time 14.31 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205544 kb
Host smart-010a0e21-e85c-4f3e-a994-297684ee1d99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1920618351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.max_length_in_transaction.1920618351
Directory /workspace/13.max_length_in_transaction/latest

Test location /workspace/coverage/default/13.min_length_in_transaction.3783673379
Short name T422
Test name
Test status
Simulation time 10054427615 ps
CPU time 13.76 seconds
Started May 30 03:44:02 PM PDT 24
Finished May 30 03:44:17 PM PDT 24
Peak memory 205588 kb
Host smart-36d35724-e588-4e2e-820a-a6bc4d751d58
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3783673379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.min_length_in_transaction.3783673379
Directory /workspace/13.min_length_in_transaction/latest

Test location /workspace/coverage/default/13.random_length_in_trans.3733239259
Short name T600
Test name
Test status
Simulation time 10078448464 ps
CPU time 13.2 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205576 kb
Host smart-51a2850f-f018-4df0-a700-5101780a68ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332
39259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.random_length_in_trans.3733239259
Directory /workspace/13.random_length_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2811214788
Short name T1718
Test name
Test status
Simulation time 14090996192 ps
CPU time 18.21 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:08 PM PDT 24
Peak memory 205520 kb
Host smart-e73b1ae0-adca-47db-8ebe-613cc2315dfa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2811214788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2811214788
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.464440967
Short name T232
Test name
Test status
Simulation time 13283298196 ps
CPU time 16.63 seconds
Started May 30 03:43:47 PM PDT 24
Finished May 30 03:44:07 PM PDT 24
Peak memory 205544 kb
Host smart-5f2ee0c8-91cf-4186-87ab-04fc71e13af5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=464440967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.464440967
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.2870255938
Short name T909
Test name
Test status
Simulation time 13313025878 ps
CPU time 17.16 seconds
Started May 30 03:43:49 PM PDT 24
Finished May 30 03:44:10 PM PDT 24
Peak memory 205584 kb
Host smart-21fb9ee1-bd68-4a91-bebd-89b599c80fe7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2870255938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.2870255938
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2776539141
Short name T1030
Test name
Test status
Simulation time 10060135852 ps
CPU time 13.46 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205568 kb
Host smart-03bf8502-d1e2-48d4-bda4-31708f96cd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765
39141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2776539141
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3166085626
Short name T73
Test name
Test status
Simulation time 10118290815 ps
CPU time 16.27 seconds
Started May 30 03:44:03 PM PDT 24
Finished May 30 03:44:21 PM PDT 24
Peak memory 205500 kb
Host smart-5811184e-e551-4e38-95f7-e83dafd6ecae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
85626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3166085626
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3687510772
Short name T1763
Test name
Test status
Simulation time 10482438821 ps
CPU time 17.45 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:30 PM PDT 24
Peak memory 205620 kb
Host smart-29d20006-1628-4fb5-88ce-9a5a9b7215e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36875
10772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3687510772
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2854856482
Short name T611
Test name
Test status
Simulation time 10044494330 ps
CPU time 13.11 seconds
Started May 30 03:44:07 PM PDT 24
Finished May 30 03:44:23 PM PDT 24
Peak memory 205548 kb
Host smart-b99dd20c-fc83-45d2-a26e-0b75034d0b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28548
56482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2854856482
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2869805036
Short name T1647
Test name
Test status
Simulation time 10050501474 ps
CPU time 13.51 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205644 kb
Host smart-2a4d36ad-c63e-4d55-9cbc-e2b318b32ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28698
05036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2869805036
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.3934190412
Short name T680
Test name
Test status
Simulation time 10801724116 ps
CPU time 14.07 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205540 kb
Host smart-edbf0e94-7e06-4db5-b0fd-126c49955c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39341
90412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3934190412
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2126609571
Short name T82
Test name
Test status
Simulation time 10188124560 ps
CPU time 13.94 seconds
Started May 30 03:43:59 PM PDT 24
Finished May 30 03:44:15 PM PDT 24
Peak memory 205572 kb
Host smart-884803c8-3836-402a-b24a-c5400904f43f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21266
09571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2126609571
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.157525476
Short name T347
Test name
Test status
Simulation time 10075702216 ps
CPU time 13.58 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205524 kb
Host smart-b5481a86-dbbe-4056-8bd2-e09290383e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
5476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.157525476
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2724787695
Short name T1757
Test name
Test status
Simulation time 10049478589 ps
CPU time 13.58 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205528 kb
Host smart-0e72d924-a04c-4400-8136-59011a15d607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27247
87695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2724787695
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.390153422
Short name T1201
Test name
Test status
Simulation time 10154137493 ps
CPU time 13.52 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205548 kb
Host smart-c26fe0a7-a1aa-4741-8dcf-8ec250f83d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39015
3422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.390153422
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1454232533
Short name T745
Test name
Test status
Simulation time 10101085036 ps
CPU time 13.6 seconds
Started May 30 03:43:57 PM PDT 24
Finished May 30 03:44:12 PM PDT 24
Peak memory 205596 kb
Host smart-32220bd9-88e7-4143-aab3-190f403984e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14542
32533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1454232533
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2095411153
Short name T419
Test name
Test status
Simulation time 13198073729 ps
CPU time 15.98 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205540 kb
Host smart-2a7b6d34-26c6-4657-8be6-4001435852f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20954
11153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2095411153
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1278061819
Short name T538
Test name
Test status
Simulation time 10116398840 ps
CPU time 13.38 seconds
Started May 30 03:44:00 PM PDT 24
Finished May 30 03:44:16 PM PDT 24
Peak memory 205488 kb
Host smart-0485e8e5-5c28-47bc-add6-34df48858923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12780
61819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1278061819
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2363228602
Short name T1285
Test name
Test status
Simulation time 10044303102 ps
CPU time 13.33 seconds
Started May 30 03:43:56 PM PDT 24
Finished May 30 03:44:12 PM PDT 24
Peak memory 205528 kb
Host smart-7bbdc5d9-6f2b-4103-a5f4-05056efb10c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
28602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2363228602
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1173996734
Short name T1208
Test name
Test status
Simulation time 10123434564 ps
CPU time 12.91 seconds
Started May 30 03:43:58 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205528 kb
Host smart-fda8c704-6ecd-4090-922b-ad38b32e9be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11739
96734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1173996734
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1321875217
Short name T719
Test name
Test status
Simulation time 10048252577 ps
CPU time 14.82 seconds
Started May 30 03:43:59 PM PDT 24
Finished May 30 03:44:16 PM PDT 24
Peak memory 205532 kb
Host smart-af14ef3b-2bfc-41c0-a58c-2e214173bc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13218
75217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1321875217
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2517816751
Short name T924
Test name
Test status
Simulation time 10060916464 ps
CPU time 13.05 seconds
Started May 30 03:43:55 PM PDT 24
Finished May 30 03:44:10 PM PDT 24
Peak memory 205612 kb
Host smart-c4a138b1-42d8-4f42-8ff7-09a614e03227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178
16751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2517816751
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2073034159
Short name T1417
Test name
Test status
Simulation time 10102441062 ps
CPU time 16.7 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:29 PM PDT 24
Peak memory 205596 kb
Host smart-11c42796-1874-4484-a13e-b507989f8949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
34159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2073034159
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.4016185472
Short name T1062
Test name
Test status
Simulation time 10124328492 ps
CPU time 13.84 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205548 kb
Host smart-1cf70d1b-eb3a-4dcb-9361-0e0a12d6b3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40161
85472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.4016185472
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.4032379776
Short name T1492
Test name
Test status
Simulation time 10063774421 ps
CPU time 15.35 seconds
Started May 30 03:43:55 PM PDT 24
Finished May 30 03:44:13 PM PDT 24
Peak memory 205508 kb
Host smart-8167c767-dc34-4410-8083-b3b79c08676d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40323
79776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.4032379776
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2328649804
Short name T1512
Test name
Test status
Simulation time 10055150495 ps
CPU time 13.94 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:24 PM PDT 24
Peak memory 205536 kb
Host smart-c7364f66-aebd-4394-b810-df3f480e2bee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23286
49804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2328649804
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1502629816
Short name T234
Test name
Test status
Simulation time 27906688440 ps
CPU time 53.78 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205604 kb
Host smart-e93cff64-ecbc-4fed-8c5e-c3de1b62ff8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15026
29816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1502629816
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3621866404
Short name T563
Test name
Test status
Simulation time 10102604308 ps
CPU time 13.83 seconds
Started May 30 03:44:01 PM PDT 24
Finished May 30 03:44:16 PM PDT 24
Peak memory 205556 kb
Host smart-e6f5a0e0-cad7-4344-91cb-67beaa3dde44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36218
66404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3621866404
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1586140956
Short name T1481
Test name
Test status
Simulation time 10123762239 ps
CPU time 14.1 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205568 kb
Host smart-b697b2d7-cbf3-4c9f-b834-4f1c481b283d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
40956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1586140956
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_trans.156715566
Short name T1071
Test name
Test status
Simulation time 10085063986 ps
CPU time 14.37 seconds
Started May 30 03:44:00 PM PDT 24
Finished May 30 03:44:17 PM PDT 24
Peak memory 205568 kb
Host smart-0c20c9d9-b337-4295-8090-50c1104a9887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15671
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_trans.156715566
Directory /workspace/13.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1889595338
Short name T1738
Test name
Test status
Simulation time 10033757629 ps
CPU time 14.25 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205532 kb
Host smart-a3b775b9-1692-4100-a379-9b58d6c864d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18895
95338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1889595338
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3845130770
Short name T1731
Test name
Test status
Simulation time 10055926942 ps
CPU time 13.43 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205556 kb
Host smart-15a12883-1fc4-4263-9407-c727dac8711f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38451
30770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3845130770
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2095365971
Short name T1116
Test name
Test status
Simulation time 10049286062 ps
CPU time 14.81 seconds
Started May 30 03:43:59 PM PDT 24
Finished May 30 03:44:16 PM PDT 24
Peak memory 205500 kb
Host smart-24ee4a98-3d3e-4456-90e8-7a6e32ddd204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20953
65971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2095365971
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1870245029
Short name T150
Test name
Test status
Simulation time 10098166722 ps
CPU time 15.11 seconds
Started May 30 03:43:46 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205536 kb
Host smart-9d00f2d6-5c83-4647-9415-0c8002f794ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18702
45029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1870245029
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.4219287433
Short name T231
Test name
Test status
Simulation time 10060234507 ps
CPU time 13.05 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:24 PM PDT 24
Peak memory 205580 kb
Host smart-31534feb-0bac-408a-8f1a-043e07281cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42192
87433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.4219287433
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.max_length_in_transaction.4128298265
Short name T284
Test name
Test status
Simulation time 10146918217 ps
CPU time 12.78 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205528 kb
Host smart-bf4b0194-9bb2-4eda-98ce-aaed8b116ca6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4128298265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.max_length_in_transaction.4128298265
Directory /workspace/14.max_length_in_transaction/latest

Test location /workspace/coverage/default/14.min_length_in_transaction.2186936642
Short name T1812
Test name
Test status
Simulation time 10054442899 ps
CPU time 15.68 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205572 kb
Host smart-586e7874-cd48-4f77-913a-c5a17b00ce14
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2186936642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.min_length_in_transaction.2186936642
Directory /workspace/14.min_length_in_transaction/latest

Test location /workspace/coverage/default/14.random_length_in_trans.1287745090
Short name T1564
Test name
Test status
Simulation time 10130169825 ps
CPU time 15.72 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205564 kb
Host smart-addf3c3c-0520-42be-806a-5e10e61fc2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12877
45090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.random_length_in_trans.1287745090
Directory /workspace/14.random_length_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3402969683
Short name T9
Test name
Test status
Simulation time 14185829637 ps
CPU time 17.74 seconds
Started May 30 03:43:59 PM PDT 24
Finished May 30 03:44:19 PM PDT 24
Peak memory 205572 kb
Host smart-d3830740-32c0-4c17-8ded-c53bba9f90ea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3402969683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3402969683
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1274028726
Short name T1895
Test name
Test status
Simulation time 13227201670 ps
CPU time 20.63 seconds
Started May 30 03:44:02 PM PDT 24
Finished May 30 03:44:24 PM PDT 24
Peak memory 205520 kb
Host smart-ae58e8f5-0b5c-482d-a488-84fb68700f6b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1274028726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1274028726
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1078644240
Short name T1849
Test name
Test status
Simulation time 13233184851 ps
CPU time 16.28 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:30 PM PDT 24
Peak memory 205548 kb
Host smart-e2a69ff2-22dc-4225-8474-048189e5611a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1078644240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1078644240
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.3390526476
Short name T307
Test name
Test status
Simulation time 10085019897 ps
CPU time 12.83 seconds
Started May 30 03:43:59 PM PDT 24
Finished May 30 03:44:14 PM PDT 24
Peak memory 205508 kb
Host smart-15eb1907-9878-42b0-92ca-d3507deb4058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33905
26476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.3390526476
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2967227666
Short name T1282
Test name
Test status
Simulation time 10903013130 ps
CPU time 16.94 seconds
Started May 30 03:44:14 PM PDT 24
Finished May 30 03:44:33 PM PDT 24
Peak memory 205724 kb
Host smart-66087070-ba95-4c6b-b1ae-a805d2f10f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29672
27666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2967227666
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2558723948
Short name T760
Test name
Test status
Simulation time 10085763940 ps
CPU time 14.07 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:25 PM PDT 24
Peak memory 205504 kb
Host smart-8b6b7d63-eb39-454b-8787-2040d1d0ed16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25587
23948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2558723948
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1723707704
Short name T1875
Test name
Test status
Simulation time 10054491333 ps
CPU time 13.95 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:29 PM PDT 24
Peak memory 205572 kb
Host smart-024a4211-51d5-4fc1-b94f-9afd85b24dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
07704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1723707704
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1544760467
Short name T396
Test name
Test status
Simulation time 10638897372 ps
CPU time 15.19 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205540 kb
Host smart-ca38f0c9-150c-4e0d-9ff4-85dcb61c0e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15447
60467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1544760467
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.59566922
Short name T1502
Test name
Test status
Simulation time 10180455971 ps
CPU time 16.02 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205624 kb
Host smart-92b0b5b9-e513-47d3-aa90-c096e0e9e229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59566
922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.59566922
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.251742719
Short name T1202
Test name
Test status
Simulation time 10099213303 ps
CPU time 15.43 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:30 PM PDT 24
Peak memory 205568 kb
Host smart-7fd51b60-f784-4fb5-8000-ea12222025fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
2719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.251742719
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3990062677
Short name T460
Test name
Test status
Simulation time 10049936319 ps
CPU time 13.16 seconds
Started May 30 03:44:06 PM PDT 24
Finished May 30 03:44:21 PM PDT 24
Peak memory 205576 kb
Host smart-e7639d79-3f9c-428d-aa5b-bb2949a7520f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
62677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3990062677
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3337998313
Short name T1260
Test name
Test status
Simulation time 10128751284 ps
CPU time 13.79 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205532 kb
Host smart-dd07ccc1-afbd-47f4-ac75-fb1e15d8464f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33379
98313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3337998313
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1637329086
Short name T1667
Test name
Test status
Simulation time 10079297082 ps
CPU time 13.11 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:25 PM PDT 24
Peak memory 205520 kb
Host smart-3019ecdd-b6da-49e5-8e39-c99065431363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16373
29086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1637329086
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.4021603426
Short name T1633
Test name
Test status
Simulation time 13229845318 ps
CPU time 16.96 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:32 PM PDT 24
Peak memory 205512 kb
Host smart-cf7da74a-97ca-498e-a2f7-56fa1f00b189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40216
03426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.4021603426
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.625358276
Short name T1342
Test name
Test status
Simulation time 10124592002 ps
CPU time 13.4 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205536 kb
Host smart-6e3ed028-6584-49d9-9dbb-5b2bb8f2c302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62535
8276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.625358276
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.1758362715
Short name T744
Test name
Test status
Simulation time 10070184099 ps
CPU time 14.34 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:25 PM PDT 24
Peak memory 205568 kb
Host smart-60591067-d3be-4ea7-86c6-b6ff35efc1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17583
62715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.1758362715
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.4033071420
Short name T1480
Test name
Test status
Simulation time 10102545193 ps
CPU time 13.73 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205560 kb
Host smart-d086dd80-d140-41ef-87ed-443d667a9afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40330
71420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4033071420
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3990425276
Short name T1078
Test name
Test status
Simulation time 10104633370 ps
CPU time 13.64 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205516 kb
Host smart-3158a1af-dd0c-473a-a1bd-39288a7e5a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39904
25276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3990425276
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.191823164
Short name T842
Test name
Test status
Simulation time 10086425848 ps
CPU time 13.41 seconds
Started May 30 03:44:14 PM PDT 24
Finished May 30 03:44:30 PM PDT 24
Peak memory 205552 kb
Host smart-1939dae3-0094-41f2-ae12-c92f3c9769a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182
3164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.191823164
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2600894487
Short name T933
Test name
Test status
Simulation time 10054924148 ps
CPU time 14.74 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205504 kb
Host smart-5d95b3cc-54e0-4a40-8a84-779565d51e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26008
94487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2600894487
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3488743684
Short name T1509
Test name
Test status
Simulation time 10062682823 ps
CPU time 12.66 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:23 PM PDT 24
Peak memory 205592 kb
Host smart-18345e31-4ca1-4e55-b867-454356830960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34887
43684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3488743684
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.3191998705
Short name T1048
Test name
Test status
Simulation time 10097421417 ps
CPU time 15.48 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205500 kb
Host smart-7f2f902f-f325-4bfe-902c-43b3386b41f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919
98705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.3191998705
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3058684452
Short name T603
Test name
Test status
Simulation time 10041584762 ps
CPU time 13.66 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:25 PM PDT 24
Peak memory 205544 kb
Host smart-2a4fab08-4e63-4e64-b146-61cd2c9b009b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30586
84452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3058684452
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2428783025
Short name T1227
Test name
Test status
Simulation time 10057756347 ps
CPU time 14.23 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:27 PM PDT 24
Peak memory 205552 kb
Host smart-359390b8-154c-44bf-a969-18651a8e4432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24287
83025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2428783025
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.745062288
Short name T1061
Test name
Test status
Simulation time 10139179785 ps
CPU time 13.73 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205524 kb
Host smart-a0114067-1f36-433d-9dd4-7b33a3179e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74506
2288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.745062288
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_trans.2736996387
Short name T1453
Test name
Test status
Simulation time 10100996002 ps
CPU time 13.15 seconds
Started May 30 03:44:07 PM PDT 24
Finished May 30 03:44:23 PM PDT 24
Peak memory 205540 kb
Host smart-cdee3995-4bbc-42f1-89f7-0a6fca52e4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369
96387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_trans.2736996387
Directory /workspace/14.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4139696708
Short name T1367
Test name
Test status
Simulation time 10072832712 ps
CPU time 13.76 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205532 kb
Host smart-7d950fbb-d9ea-42ad-b1d5-513d579f1e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41396
96708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4139696708
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.2009305519
Short name T1688
Test name
Test status
Simulation time 10051696092 ps
CPU time 13.59 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205536 kb
Host smart-5ca1f857-492a-49e5-aa63-4a1300497356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20093
05519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.2009305519
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2109404197
Short name T764
Test name
Test status
Simulation time 10117093957 ps
CPU time 14.52 seconds
Started May 30 03:44:01 PM PDT 24
Finished May 30 03:44:17 PM PDT 24
Peak memory 205564 kb
Host smart-bf5306ac-10de-4709-a55c-3e0e4abd4744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
04197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2109404197
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.302442657
Short name T898
Test name
Test status
Simulation time 10051825909 ps
CPU time 13.34 seconds
Started May 30 03:44:09 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205520 kb
Host smart-19b81a0f-5fd0-4f1e-afc5-80869a5d9943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
2657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.302442657
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3742834941
Short name T1097
Test name
Test status
Simulation time 10107546344 ps
CPU time 13.21 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:24 PM PDT 24
Peak memory 205592 kb
Host smart-6e9e2b71-ed68-4ffb-a81e-0b6e1cc9249d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37428
34941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3742834941
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.max_length_in_transaction.2458210011
Short name T1086
Test name
Test status
Simulation time 10149635203 ps
CPU time 14.31 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205592 kb
Host smart-ecb1e98e-e10e-424a-879c-449198628c79
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2458210011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.max_length_in_transaction.2458210011
Directory /workspace/15.max_length_in_transaction/latest

Test location /workspace/coverage/default/15.min_length_in_transaction.1570614789
Short name T1901
Test name
Test status
Simulation time 10053949813 ps
CPU time 13.98 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:40 PM PDT 24
Peak memory 205580 kb
Host smart-4cfb2685-a25d-4568-9800-fdf5d91f2a7f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1570614789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.min_length_in_transaction.1570614789
Directory /workspace/15.min_length_in_transaction/latest

Test location /workspace/coverage/default/15.random_length_in_trans.738553974
Short name T1559
Test name
Test status
Simulation time 10151865845 ps
CPU time 13.62 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205520 kb
Host smart-d27d10b2-e380-4ea7-90b5-72f0ef033cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73855
3974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.random_length_in_trans.738553974
Directory /workspace/15.random_length_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3606085821
Short name T441
Test name
Test status
Simulation time 13498185505 ps
CPU time 18.76 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:33 PM PDT 24
Peak memory 205516 kb
Host smart-98f88561-666f-4d46-810b-39d9286d5768
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3606085821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.3606085821
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1331320897
Short name T627
Test name
Test status
Simulation time 13276868688 ps
CPU time 16.63 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:30 PM PDT 24
Peak memory 205524 kb
Host smart-424104a3-6b41-4953-98b2-06e984238509
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1331320897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1331320897
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1271026295
Short name T389
Test name
Test status
Simulation time 13218636346 ps
CPU time 16.5 seconds
Started May 30 03:44:07 PM PDT 24
Finished May 30 03:44:26 PM PDT 24
Peak memory 205572 kb
Host smart-a490e982-c5f6-435e-b2dd-800ee61fb8e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1271026295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1271026295
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1224451175
Short name T1234
Test name
Test status
Simulation time 10063318234 ps
CPU time 14.42 seconds
Started May 30 03:44:08 PM PDT 24
Finished May 30 03:44:25 PM PDT 24
Peak memory 205540 kb
Host smart-0d18ee7e-0e3d-4fde-94f7-c116531a5e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12244
51175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1224451175
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3822991356
Short name T1317
Test name
Test status
Simulation time 11355270720 ps
CPU time 18.17 seconds
Started May 30 03:44:11 PM PDT 24
Finished May 30 03:44:33 PM PDT 24
Peak memory 205616 kb
Host smart-c96b59b7-9044-4665-aadb-a0a455f789f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38229
91356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3822991356
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3608875473
Short name T1024
Test name
Test status
Simulation time 10058077862 ps
CPU time 13.45 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205504 kb
Host smart-ef2cdbf4-9a33-4484-a599-74530b4af3ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36088
75473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3608875473
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.699203413
Short name T1262
Test name
Test status
Simulation time 10748617661 ps
CPU time 15.17 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:40 PM PDT 24
Peak memory 205560 kb
Host smart-2a0e9f8d-ffca-47fe-814d-ee41c4f906d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69920
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.699203413
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2574830661
Short name T83
Test name
Test status
Simulation time 10161978577 ps
CPU time 15.04 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:46 PM PDT 24
Peak memory 205532 kb
Host smart-3171db60-a793-4a7a-b44e-2d576aa92581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
30661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2574830661
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1438278049
Short name T666
Test name
Test status
Simulation time 10069839696 ps
CPU time 15.07 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:38 PM PDT 24
Peak memory 205520 kb
Host smart-af50da32-07eb-41ea-926d-1d42c2b667a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14382
78049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1438278049
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.4166707290
Short name T692
Test name
Test status
Simulation time 10044981465 ps
CPU time 13.71 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205556 kb
Host smart-d0451d3c-2385-4f22-b9bb-2162c9f75675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
07290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.4166707290
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.3071149619
Short name T1142
Test name
Test status
Simulation time 10128240245 ps
CPU time 15.83 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205544 kb
Host smart-28566270-9570-4a2d-a229-61b22aa696ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30711
49619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3071149619
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1757734597
Short name T1905
Test name
Test status
Simulation time 10104558690 ps
CPU time 13.43 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205552 kb
Host smart-9d907c67-ff46-4229-9dff-4de8cb97e733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
34597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1757734597
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3323433724
Short name T886
Test name
Test status
Simulation time 13236315730 ps
CPU time 17.08 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:46 PM PDT 24
Peak memory 205564 kb
Host smart-05d4edb5-f8a3-40a4-8290-b5308d0901e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
33724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3323433724
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2754229026
Short name T527
Test name
Test status
Simulation time 10093177296 ps
CPU time 14.16 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:40 PM PDT 24
Peak memory 205528 kb
Host smart-88bb8f4e-c44b-41a5-93b1-d603dd6dad7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27542
29026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2754229026
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3015485121
Short name T439
Test name
Test status
Simulation time 10067158044 ps
CPU time 14.5 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:37 PM PDT 24
Peak memory 205564 kb
Host smart-26f9d0e1-a08e-46fa-97b2-30c0d481464d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30154
85121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3015485121
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.515468078
Short name T1529
Test name
Test status
Simulation time 10089976352 ps
CPU time 13.06 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:39 PM PDT 24
Peak memory 205596 kb
Host smart-6ee0b25f-734c-4cec-8c2d-409834057163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51546
8078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.515468078
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.562428518
Short name T316
Test name
Test status
Simulation time 10085893302 ps
CPU time 15.11 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205592 kb
Host smart-e5bf5fe2-1a79-4e43-a9c7-99da5337e6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56242
8518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.562428518
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.233361763
Short name T645
Test name
Test status
Simulation time 10056365384 ps
CPU time 16.43 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:42 PM PDT 24
Peak memory 205576 kb
Host smart-94a0a81e-78cc-4e1a-aee2-a2087fe1871f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23336
1763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.233361763
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.3741820108
Short name T1009
Test name
Test status
Simulation time 10078394146 ps
CPU time 15.15 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205512 kb
Host smart-087cef6c-80fe-4468-b198-dadfb11d7b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
20108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.3741820108
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3225653581
Short name T1403
Test name
Test status
Simulation time 10046451355 ps
CPU time 16.03 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205492 kb
Host smart-bd39aeb7-6cf7-41d7-a3f9-d90f882650b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32256
53581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3225653581
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1292811803
Short name T1848
Test name
Test status
Simulation time 25327635986 ps
CPU time 49.33 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205600 kb
Host smart-f3bc8edc-5ddd-4b89-ac30-de6e78e5e0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
11803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1292811803
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.4083677640
Short name T1494
Test name
Test status
Simulation time 10095205634 ps
CPU time 14.44 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205528 kb
Host smart-7da7d9b5-7a8b-4115-b790-7b72118dc06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40836
77640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.4083677640
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1197124408
Short name T1446
Test name
Test status
Simulation time 10094833107 ps
CPU time 15.09 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205484 kb
Host smart-736da8b8-1f59-462e-9ee5-76f1653df637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11971
24408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1197124408
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_trans.2419226049
Short name T856
Test name
Test status
Simulation time 10064931380 ps
CPU time 14.71 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205532 kb
Host smart-8cb39247-e205-4ad6-b997-aa19e318ad75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24192
26049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_trans.2419226049
Directory /workspace/15.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.411373763
Short name T1488
Test name
Test status
Simulation time 10101220970 ps
CPU time 14.5 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205496 kb
Host smart-4bff4f44-e7c3-4061-83e7-cee845aa5e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
3763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.411373763
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3473883014
Short name T1370
Test name
Test status
Simulation time 10049679807 ps
CPU time 12.96 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:38 PM PDT 24
Peak memory 205540 kb
Host smart-b8fe5a4a-4f92-40bd-aa76-c358f09eb96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34738
83014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3473883014
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.794847451
Short name T1000
Test name
Test status
Simulation time 10089964640 ps
CPU time 16.04 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:40 PM PDT 24
Peak memory 205544 kb
Host smart-2f32d43d-91f6-416c-9324-da56bccb33bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79484
7451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.794847451
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.56234467
Short name T1809
Test name
Test status
Simulation time 10125401915 ps
CPU time 14.52 seconds
Started May 30 03:44:10 PM PDT 24
Finished May 30 03:44:28 PM PDT 24
Peak memory 205512 kb
Host smart-db03dd3c-4040-4b9b-82b6-bad4dff3d4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56234
467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.56234467
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.91724377
Short name T397
Test name
Test status
Simulation time 10083824123 ps
CPU time 15.7 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205548 kb
Host smart-dbf2c827-dcbd-4439-8ce0-8c9b28a34492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91724
377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.91724377
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1781825964
Short name T1581
Test name
Test status
Simulation time 10068399969 ps
CPU time 13.03 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205496 kb
Host smart-fe6e5fab-cd98-4b8f-a6b2-0808621bd6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17818
25964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1781825964
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.max_length_in_transaction.2677823793
Short name T1300
Test name
Test status
Simulation time 10141736079 ps
CPU time 16.43 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:42 PM PDT 24
Peak memory 205568 kb
Host smart-9e2be488-b019-4018-ac8d-8f7b5ffb22c2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2677823793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.max_length_in_transaction.2677823793
Directory /workspace/16.max_length_in_transaction/latest

Test location /workspace/coverage/default/16.min_length_in_transaction.795671726
Short name T1195
Test name
Test status
Simulation time 10061197003 ps
CPU time 16.8 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205588 kb
Host smart-bae5ab10-56fc-4bdf-8b02-5b04bfbac5a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=795671726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.min_length_in_transaction.795671726
Directory /workspace/16.min_length_in_transaction/latest

Test location /workspace/coverage/default/16.random_length_in_trans.185999427
Short name T552
Test name
Test status
Simulation time 10050704572 ps
CPU time 14.03 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205528 kb
Host smart-6c73a479-848f-4371-afb4-e55fbb3155d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18599
9427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.random_length_in_trans.185999427
Directory /workspace/16.random_length_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1421700602
Short name T382
Test name
Test status
Simulation time 13774833312 ps
CPU time 21.44 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205540 kb
Host smart-d7ee42bb-255f-44e1-a659-167bad9b9e33
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1421700602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1421700602
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1523522307
Short name T10
Test name
Test status
Simulation time 13454175896 ps
CPU time 17.02 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205540 kb
Host smart-31a6f3d1-948c-4718-91cb-719804b269bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1523522307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1523522307
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.4166416816
Short name T1444
Test name
Test status
Simulation time 13310196204 ps
CPU time 17.57 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205604 kb
Host smart-13932d1b-b7df-4bc1-a64f-a769d54f8197
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4166416816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.4166416816
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3849157490
Short name T1039
Test name
Test status
Simulation time 10049957394 ps
CPU time 14.83 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205564 kb
Host smart-a1c5d6d8-be12-4229-913f-bfb2f6a71d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
57490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3849157490
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3314695020
Short name T75
Test name
Test status
Simulation time 10113718897 ps
CPU time 13.72 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205524 kb
Host smart-d2af3f3d-bf08-411f-8397-ff44176ab25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
95020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3314695020
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1159814550
Short name T1552
Test name
Test status
Simulation time 10792255245 ps
CPU time 14.42 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205564 kb
Host smart-1d5a334d-cd77-4fd0-bc4e-2040d72778be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11598
14550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1159814550
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3376617029
Short name T1424
Test name
Test status
Simulation time 10071503389 ps
CPU time 16.45 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:46 PM PDT 24
Peak memory 205572 kb
Host smart-f3c27021-d74d-4e5e-aeea-ecee19e55975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
17029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3376617029
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2633495931
Short name T1623
Test name
Test status
Simulation time 10055666332 ps
CPU time 15.15 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:43 PM PDT 24
Peak memory 205516 kb
Host smart-9a78bba9-1b70-4292-9c91-399228b4bfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26334
95931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2633495931
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1338569114
Short name T1418
Test name
Test status
Simulation time 10872103085 ps
CPU time 15.08 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205560 kb
Host smart-57b1e0e7-4033-48d7-ac3e-7cc9f0e29b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
69114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1338569114
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.1738901041
Short name T1102
Test name
Test status
Simulation time 10095906948 ps
CPU time 16.6 seconds
Started May 30 03:44:21 PM PDT 24
Finished May 30 03:44:39 PM PDT 24
Peak memory 205508 kb
Host smart-90e21e55-05dd-4be1-821f-21de8c235d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
01041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.1738901041
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.2998659975
Short name T1724
Test name
Test status
Simulation time 10098210352 ps
CPU time 14.02 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205564 kb
Host smart-f9e877b2-7665-475b-b5ac-feb90093961e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29986
59975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.2998659975
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.4147574026
Short name T994
Test name
Test status
Simulation time 10039040941 ps
CPU time 14.73 seconds
Started May 30 03:44:30 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205540 kb
Host smart-fd6fac39-ead8-4473-9140-6138edfd39f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41475
74026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.4147574026
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2173950975
Short name T998
Test name
Test status
Simulation time 10114979822 ps
CPU time 14.82 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:40 PM PDT 24
Peak memory 205548 kb
Host smart-0c776004-b729-430f-a30e-f3fcd319249d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21739
50975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2173950975
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1331555111
Short name T1487
Test name
Test status
Simulation time 10062510250 ps
CPU time 15.62 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:41 PM PDT 24
Peak memory 205560 kb
Host smart-ab3ad964-c9fa-42be-848f-b54d3e708a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13315
55111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1331555111
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3830427736
Short name T1350
Test name
Test status
Simulation time 13173225423 ps
CPU time 21.07 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205524 kb
Host smart-d21667ab-1d89-4f50-a721-e780f77aee5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38304
27736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3830427736
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2849525258
Short name T298
Test name
Test status
Simulation time 10105907462 ps
CPU time 12.77 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:42 PM PDT 24
Peak memory 205576 kb
Host smart-9d51c5fb-bf18-4ecf-a87e-24853e1a1f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
25258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2849525258
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2439249528
Short name T1365
Test name
Test status
Simulation time 10054933455 ps
CPU time 15.37 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:46 PM PDT 24
Peak memory 205564 kb
Host smart-123d5d90-77a1-417d-a8b5-4a2e6015b5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392
49528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2439249528
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1522084186
Short name T1852
Test name
Test status
Simulation time 10106733070 ps
CPU time 15.04 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:41 PM PDT 24
Peak memory 205656 kb
Host smart-21311b4c-f2c2-43f6-8ad2-0cdb086f5d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
84186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1522084186
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1050527188
Short name T1423
Test name
Test status
Simulation time 10076673174 ps
CPU time 14.94 seconds
Started May 30 03:44:22 PM PDT 24
Finished May 30 03:44:38 PM PDT 24
Peak memory 205556 kb
Host smart-c817b722-5210-487f-8b68-07117eedcb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505
27188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1050527188
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.926355696
Short name T484
Test name
Test status
Simulation time 10088346388 ps
CPU time 14.61 seconds
Started May 30 03:44:30 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205552 kb
Host smart-6c0eeeec-1ee5-43ec-910c-e3d65d5e29c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92635
5696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.926355696
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.115222053
Short name T1153
Test name
Test status
Simulation time 10078338289 ps
CPU time 13.51 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205368 kb
Host smart-88496332-5d4d-41d3-ba43-dc9fd836e1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11522
2053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.115222053
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.2575982078
Short name T1013
Test name
Test status
Simulation time 10096242974 ps
CPU time 14.13 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205264 kb
Host smart-93a63b08-2c3e-4ef0-ab98-20da3b5335e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
82078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.2575982078
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.639102079
Short name T1437
Test name
Test status
Simulation time 10055785679 ps
CPU time 13.79 seconds
Started May 30 03:44:30 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205552 kb
Host smart-92041566-aff7-4ee3-a477-e8eb1abb5c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63910
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.639102079
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.1061234122
Short name T1256
Test name
Test status
Simulation time 10047299097 ps
CPU time 16.18 seconds
Started May 30 03:44:23 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205536 kb
Host smart-c5cd4a97-1583-4bbe-9ec9-d61eabd55601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10612
34122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.1061234122
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.4190472775
Short name T238
Test name
Test status
Simulation time 29160481293 ps
CPU time 59.78 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205580 kb
Host smart-aefcf73e-7f72-46e6-9f13-e9cec6c2c39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41904
72775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.4190472775
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.60887294
Short name T406
Test name
Test status
Simulation time 10105390593 ps
CPU time 13.93 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:46 PM PDT 24
Peak memory 205484 kb
Host smart-f14fb151-a6c6-4fe2-a2a8-ca19d7a3f859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60887
294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.60887294
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1942359832
Short name T434
Test name
Test status
Simulation time 10144553976 ps
CPU time 12.95 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205456 kb
Host smart-149c6215-6c1e-4727-9bf1-ae8d0629c084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
59832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1942359832
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_trans.2069954094
Short name T520
Test name
Test status
Simulation time 10095701689 ps
CPU time 14.19 seconds
Started May 30 03:44:30 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205528 kb
Host smart-590dbd0e-aa59-4448-acf8-4990c9835bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20699
54094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_trans.2069954094
Directory /workspace/16.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3554027172
Short name T1012
Test name
Test status
Simulation time 10046743096 ps
CPU time 15.36 seconds
Started May 30 03:44:27 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205380 kb
Host smart-87c88a36-dee0-4d55-bc95-02d40f561235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35540
27172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3554027172
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.364691588
Short name T141
Test name
Test status
Simulation time 10076866247 ps
CPU time 13.89 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205496 kb
Host smart-c73c5aa9-4dce-4daf-a396-e31d64337314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36469
1588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.364691588
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1417739857
Short name T495
Test name
Test status
Simulation time 10088126270 ps
CPU time 12.58 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205576 kb
Host smart-635e663e-8770-472d-9bf3-3dbc1cad18ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14177
39857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1417739857
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1992962364
Short name T1922
Test name
Test status
Simulation time 10132660041 ps
CPU time 16.79 seconds
Started May 30 03:44:26 PM PDT 24
Finished May 30 03:44:48 PM PDT 24
Peak memory 205536 kb
Host smart-2722ab7b-13d6-4fc8-83df-2fbd62ecb5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
62364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1992962364
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2588922346
Short name T823
Test name
Test status
Simulation time 10060641702 ps
CPU time 14.4 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:45 PM PDT 24
Peak memory 205612 kb
Host smart-9c4d8c8e-8276-447d-a587-c9de3b375ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
22346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2588922346
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2615974494
Short name T491
Test name
Test status
Simulation time 10058498685 ps
CPU time 13.64 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:44 PM PDT 24
Peak memory 205496 kb
Host smart-5f386d8b-8e37-4cd0-8477-c6a6cfc8858c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26159
74494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2615974494
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.max_length_in_transaction.3498939325
Short name T1915
Test name
Test status
Simulation time 10194994615 ps
CPU time 14.39 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205560 kb
Host smart-f320ba80-49e6-4dac-89e5-9e864751cba8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3498939325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.max_length_in_transaction.3498939325
Directory /workspace/17.max_length_in_transaction/latest

Test location /workspace/coverage/default/17.min_length_in_transaction.2593587191
Short name T1528
Test name
Test status
Simulation time 10056263629 ps
CPU time 13.43 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205584 kb
Host smart-94c2dcdb-1d5a-4a3e-9f30-42b799b328fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2593587191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.min_length_in_transaction.2593587191
Directory /workspace/17.min_length_in_transaction/latest

Test location /workspace/coverage/default/17.random_length_in_trans.4197742243
Short name T931
Test name
Test status
Simulation time 10109771656 ps
CPU time 14.28 seconds
Started May 30 03:44:34 PM PDT 24
Finished May 30 03:44:50 PM PDT 24
Peak memory 205572 kb
Host smart-9a651ac6-06d4-46e9-839b-524f007ae73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41977
42243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.random_length_in_trans.4197742243
Directory /workspace/17.random_length_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.110927167
Short name T6
Test name
Test status
Simulation time 13682331809 ps
CPU time 16.11 seconds
Started May 30 03:44:25 PM PDT 24
Finished May 30 03:44:47 PM PDT 24
Peak memory 205592 kb
Host smart-71bc7904-21ed-4349-875f-0b38a867d28b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=110927167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.110927167
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.4174356848
Short name T1580
Test name
Test status
Simulation time 13269012428 ps
CPU time 20.23 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205540 kb
Host smart-1a15ff62-2444-4b07-90cb-1e99ed244ee8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4174356848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.4174356848
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.401199254
Short name T1040
Test name
Test status
Simulation time 13204877478 ps
CPU time 16.02 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205580 kb
Host smart-8f5820c2-d65b-4d0b-a029-6bde653607b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=401199254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.401199254
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.601680838
Short name T366
Test name
Test status
Simulation time 10054971522 ps
CPU time 15.16 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:55 PM PDT 24
Peak memory 205540 kb
Host smart-5dc4cd1e-b91d-4c1e-a8fb-c44972061678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60168
0838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.601680838
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1684222182
Short name T159
Test name
Test status
Simulation time 11112956454 ps
CPU time 17.33 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205540 kb
Host smart-377198cc-eb63-4888-a4c1-b814ff5c8f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
22182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1684222182
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.549591830
Short name T673
Test name
Test status
Simulation time 10039889217 ps
CPU time 15.18 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205560 kb
Host smart-5f8bef10-3dd2-4a60-b4a0-985013fa4543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54959
1830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.549591830
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3956811680
Short name T1318
Test name
Test status
Simulation time 10066735974 ps
CPU time 14.16 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205596 kb
Host smart-7f55e231-91f7-42a4-a282-1347cee1a53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
11680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3956811680
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.836211057
Short name T1634
Test name
Test status
Simulation time 10795549458 ps
CPU time 17.77 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205600 kb
Host smart-b23aea4d-514c-43ef-9c9a-5c9b5e8d32a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83621
1057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.836211057
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1377096847
Short name T566
Test name
Test status
Simulation time 10068027175 ps
CPU time 15.15 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205452 kb
Host smart-8c0b4a41-bf28-4410-bb8d-07c716a9dee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
96847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1377096847
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1989110535
Short name T29
Test name
Test status
Simulation time 10144679827 ps
CPU time 16.31 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205508 kb
Host smart-225d758e-ea7f-4fc5-8d00-8615a852335f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
10535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1989110535
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2548633935
Short name T384
Test name
Test status
Simulation time 10043592520 ps
CPU time 13.51 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205512 kb
Host smart-f69d10ab-d3b4-45cb-aa23-e22e6a425e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25486
33935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2548633935
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1027438883
Short name T499
Test name
Test status
Simulation time 10122626314 ps
CPU time 13.76 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205492 kb
Host smart-5323733f-81d6-437d-8894-01ff699fcd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
38883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1027438883
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.804009698
Short name T1209
Test name
Test status
Simulation time 10086272077 ps
CPU time 13.48 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205608 kb
Host smart-e477efd8-2d78-4a86-a76d-c80b87f49ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80400
9698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.804009698
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.620408854
Short name T1496
Test name
Test status
Simulation time 13216051189 ps
CPU time 15.89 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205516 kb
Host smart-cdb91d05-6b56-4829-aaed-e976d3654fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62040
8854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.620408854
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2565123168
Short name T1100
Test name
Test status
Simulation time 10098081979 ps
CPU time 13.89 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205528 kb
Host smart-bf1835e6-3e22-4477-991a-93c1f1e31937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25651
23168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2565123168
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1886479222
Short name T1610
Test name
Test status
Simulation time 10046942310 ps
CPU time 16.05 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205588 kb
Host smart-31d3097b-dd13-4157-9d96-b88c6478effc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18864
79222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1886479222
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1266971095
Short name T108
Test name
Test status
Simulation time 10138015386 ps
CPU time 14.25 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:51 PM PDT 24
Peak memory 205624 kb
Host smart-ae5e862a-3970-4f56-88f2-4458c150d43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12669
71095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1266971095
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.879304994
Short name T697
Test name
Test status
Simulation time 10087839748 ps
CPU time 15.26 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205504 kb
Host smart-cec2910e-cb87-4588-aabc-9dae057969ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87930
4994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.879304994
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2400710413
Short name T1892
Test name
Test status
Simulation time 10058791204 ps
CPU time 14.75 seconds
Started May 30 03:44:38 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205544 kb
Host smart-5c72b9f8-4552-4786-bd3b-c5dd1ad6bc8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24007
10413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2400710413
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1973291677
Short name T695
Test name
Test status
Simulation time 10103298510 ps
CPU time 13.18 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:44:55 PM PDT 24
Peak memory 205480 kb
Host smart-51b4981a-680e-4c31-a8d1-0e332afe752f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19732
91677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1973291677
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.1744348458
Short name T32
Test name
Test status
Simulation time 10061624473 ps
CPU time 14.04 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205596 kb
Host smart-a909a699-bd56-43cf-b670-2d041b927027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17443
48458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.1744348458
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.236017298
Short name T782
Test name
Test status
Simulation time 10100894617 ps
CPU time 13.29 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:51 PM PDT 24
Peak memory 205580 kb
Host smart-72355f4f-0cec-426d-8d82-77249dda49a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23601
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.236017298
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2761887415
Short name T1351
Test name
Test status
Simulation time 10045311682 ps
CPU time 17.08 seconds
Started May 30 03:44:38 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205556 kb
Host smart-90bd1b04-a926-4095-894d-833387bcb9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
87415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2761887415
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1526017133
Short name T180
Test name
Test status
Simulation time 21086328104 ps
CPU time 41.31 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:45:24 PM PDT 24
Peak memory 205592 kb
Host smart-0bc855b6-b47a-4c05-afd6-5cb790dbc13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15260
17133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1526017133
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1013589283
Short name T891
Test name
Test status
Simulation time 10055880552 ps
CPU time 13.52 seconds
Started May 30 03:44:38 PM PDT 24
Finished May 30 03:44:55 PM PDT 24
Peak memory 205572 kb
Host smart-624e0b51-aad4-4269-a72a-f58ce8f3ef2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10135
89283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1013589283
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.287688586
Short name T1910
Test name
Test status
Simulation time 10079615266 ps
CPU time 15.45 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205512 kb
Host smart-db1e64a9-3ae6-491b-b14c-dbb0811d34a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768
8586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.287688586
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_trans.90758937
Short name T399
Test name
Test status
Simulation time 10092380089 ps
CPU time 13.71 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205468 kb
Host smart-b39d7c3b-c5f4-4dcb-8b7a-080b4857d7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90758
937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_trans.90758937
Directory /workspace/17.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1799803370
Short name T51
Test name
Test status
Simulation time 10039382253 ps
CPU time 13.17 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:50 PM PDT 24
Peak memory 205552 kb
Host smart-b3df2e9f-a9e5-4fa4-85e8-578b762f1729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17998
03370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1799803370
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.528617975
Short name T1814
Test name
Test status
Simulation time 10061045002 ps
CPU time 13.82 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205560 kb
Host smart-16142be8-d45d-4b6a-8afc-e6da084b7059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52861
7975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.528617975
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1991898164
Short name T1412
Test name
Test status
Simulation time 10059428891 ps
CPU time 13.25 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205568 kb
Host smart-eee89b9c-83a8-420a-a63a-60086c4e3b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19918
98164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1991898164
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2480031071
Short name T144
Test name
Test status
Simulation time 10118766125 ps
CPU time 13.21 seconds
Started May 30 03:44:24 PM PDT 24
Finished May 30 03:44:42 PM PDT 24
Peak memory 205548 kb
Host smart-9ab5c462-2066-4f70-8b36-4e99b6791538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24800
31071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2480031071
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2200111144
Short name T854
Test name
Test status
Simulation time 10066092368 ps
CPU time 16.12 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205616 kb
Host smart-9ac2181d-7ec2-4e3f-be9b-5a0f1672a985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22001
11144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2200111144
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2069255180
Short name T995
Test name
Test status
Simulation time 10054066677 ps
CPU time 14.65 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205540 kb
Host smart-4abc25c4-f4e3-41e0-bd09-d062112fd20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20692
55180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2069255180
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.max_length_in_transaction.1280956127
Short name T987
Test name
Test status
Simulation time 10157414873 ps
CPU time 13.27 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205540 kb
Host smart-a17b395c-afc4-49c9-a32f-beada17d1c80
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1280956127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.max_length_in_transaction.1280956127
Directory /workspace/18.max_length_in_transaction/latest

Test location /workspace/coverage/default/18.min_length_in_transaction.2278659326
Short name T1752
Test name
Test status
Simulation time 10061204188 ps
CPU time 13.23 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205616 kb
Host smart-bcb2cc2c-92ec-479b-b20e-d850fd4b5e7f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2278659326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.min_length_in_transaction.2278659326
Directory /workspace/18.min_length_in_transaction/latest

Test location /workspace/coverage/default/18.random_length_in_trans.3178550
Short name T1833
Test name
Test status
Simulation time 10121744538 ps
CPU time 13.85 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205556 kb
Host smart-d22ffc74-a651-443d-860a-79aa2d5ae05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
50 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.random_length_in_trans.3178550
Directory /workspace/18.random_length_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3186758586
Short name T7
Test name
Test status
Simulation time 13797586763 ps
CPU time 18.77 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:45:02 PM PDT 24
Peak memory 205568 kb
Host smart-2c6cab1e-eea0-4e92-81c7-34305a074987
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3186758586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3186758586
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4190394240
Short name T1929
Test name
Test status
Simulation time 13272673070 ps
CPU time 15.97 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205584 kb
Host smart-a769241a-3ced-427c-a39f-9880d4b90fd9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4190394240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4190394240
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2404696509
Short name T727
Test name
Test status
Simulation time 13281007001 ps
CPU time 16.49 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205560 kb
Host smart-d5d51f2c-048f-4b69-a59b-ae1bd9439b4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2404696509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2404696509
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1803665900
Short name T1659
Test name
Test status
Simulation time 10128189819 ps
CPU time 14.19 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205516 kb
Host smart-fa539431-4deb-4b08-83ca-4c003eb8fd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18036
65900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1803665900
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2069755581
Short name T178
Test name
Test status
Simulation time 10723083404 ps
CPU time 15.46 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205624 kb
Host smart-36f468fd-6d3b-4562-be7e-088a013a335f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20697
55581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2069755581
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2724111645
Short name T930
Test name
Test status
Simulation time 10060845169 ps
CPU time 13.99 seconds
Started May 30 03:44:33 PM PDT 24
Finished May 30 03:44:49 PM PDT 24
Peak memory 205552 kb
Host smart-b159ed38-4841-40e3-9f75-f21afc722ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
11645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2724111645
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.737310454
Short name T738
Test name
Test status
Simulation time 10054970191 ps
CPU time 13.42 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:51 PM PDT 24
Peak memory 205560 kb
Host smart-25fb1624-a464-40c0-88bf-103d8c0f2c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73731
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.737310454
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2819681439
Short name T1715
Test name
Test status
Simulation time 10779954833 ps
CPU time 14.25 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205556 kb
Host smart-92d11db8-44dc-4eeb-aef3-fb5935811d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28196
81439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2819681439
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2721107447
Short name T1224
Test name
Test status
Simulation time 10068833525 ps
CPU time 14.28 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205464 kb
Host smart-cd8389f3-b7c3-4bc5-90d1-464b33df60e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27211
07447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2721107447
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3769481715
Short name T21
Test name
Test status
Simulation time 10065570656 ps
CPU time 15.06 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205520 kb
Host smart-2607045a-8e7d-45ed-919d-eadce92ddf52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37694
81715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3769481715
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3820054001
Short name T334
Test name
Test status
Simulation time 10050499390 ps
CPU time 14.01 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205548 kb
Host smart-c188192a-7625-423f-93b1-83a015edeac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38200
54001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3820054001
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2491807183
Short name T1432
Test name
Test status
Simulation time 10103785825 ps
CPU time 13.23 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205568 kb
Host smart-c5bf32a0-9593-4982-89de-06283712e67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24918
07183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2491807183
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4077308282
Short name T445
Test name
Test status
Simulation time 10111034163 ps
CPU time 17.12 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205496 kb
Host smart-6d481909-cd19-4625-8f70-d296e30ad4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
08282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4077308282
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1840614232
Short name T1924
Test name
Test status
Simulation time 13259940720 ps
CPU time 16.6 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205572 kb
Host smart-be4e6dff-b730-4860-88b3-a74b6075ecb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18406
14232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1840614232
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1370360847
Short name T329
Test name
Test status
Simulation time 10136002938 ps
CPU time 15.47 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205520 kb
Host smart-91b1bb63-87d6-41da-b4c4-3c505cb60e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13703
60847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1370360847
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1865773970
Short name T1220
Test name
Test status
Simulation time 10053400442 ps
CPU time 15.08 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205536 kb
Host smart-355d4e99-5872-4d0b-8603-a4c6ad0e61bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
73970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1865773970
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1800325608
Short name T665
Test name
Test status
Simulation time 10143217684 ps
CPU time 13.1 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205504 kb
Host smart-30ecb6d7-9c0d-4696-b267-f9380bf4ff86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18003
25608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1800325608
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4019033868
Short name T1742
Test name
Test status
Simulation time 10100985210 ps
CPU time 12.88 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205528 kb
Host smart-29dafc4d-ba83-4d3e-83e5-72c77c43ab72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40190
33868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4019033868
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1257942455
Short name T402
Test name
Test status
Simulation time 10088498889 ps
CPU time 14.91 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205480 kb
Host smart-f1ca99c6-52fe-4612-91c1-4a466ab3c717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12579
42455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1257942455
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.1893328727
Short name T353
Test name
Test status
Simulation time 10067031958 ps
CPU time 13.53 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205560 kb
Host smart-0e1daaef-a0a1-4707-adb7-2360d6665ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
28727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.1893328727
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1652612382
Short name T661
Test name
Test status
Simulation time 10045799817 ps
CPU time 15.93 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205528 kb
Host smart-b01aeb2d-ef8f-4b3c-9497-b71ed2937b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16526
12382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1652612382
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3030006875
Short name T766
Test name
Test status
Simulation time 10034801783 ps
CPU time 13.18 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205536 kb
Host smart-f8ca20f7-e898-4877-8a6f-936042c7f1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30300
06875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3030006875
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1702868648
Short name T1871
Test name
Test status
Simulation time 30139535259 ps
CPU time 67.81 seconds
Started May 30 03:44:37 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205576 kb
Host smart-8b3e3cfd-3583-4348-bff2-c43ba7fb84f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17028
68648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1702868648
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1856672603
Short name T932
Test name
Test status
Simulation time 10077794903 ps
CPU time 13.74 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205588 kb
Host smart-529443cc-7093-49e6-865f-a1ab0abe8fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566
72603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1856672603
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3494642937
Short name T636
Test name
Test status
Simulation time 10090632474 ps
CPU time 13.33 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205592 kb
Host smart-85fafdd8-1479-4baa-904b-5181745299ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
42937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3494642937
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_trans.3093048470
Short name T1017
Test name
Test status
Simulation time 10115544505 ps
CPU time 15.14 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:54 PM PDT 24
Peak memory 205568 kb
Host smart-bf27f258-4c11-42ea-a064-7a7e7a5eda3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30930
48470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_trans.3093048470
Directory /workspace/18.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3090952717
Short name T832
Test name
Test status
Simulation time 10049985635 ps
CPU time 13.91 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:58 PM PDT 24
Peak memory 205516 kb
Host smart-8a109b52-2771-41f4-8aee-4d78a97aa654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
52717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3090952717
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.769654464
Short name T53
Test name
Test status
Simulation time 10065941067 ps
CPU time 13.11 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:45:00 PM PDT 24
Peak memory 205280 kb
Host smart-d154b65e-2928-450c-9381-864477e972e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76965
4464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.769654464
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1523676137
Short name T488
Test name
Test status
Simulation time 10047045363 ps
CPU time 13.27 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:44:55 PM PDT 24
Peak memory 205464 kb
Host smart-efce5354-c414-462b-8764-23752cc8285f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236
76137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1523676137
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.261855054
Short name T622
Test name
Test status
Simulation time 10117495170 ps
CPU time 14.88 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:52 PM PDT 24
Peak memory 205564 kb
Host smart-03f384b5-a566-4e74-944b-eda5768eb7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26185
5054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.261855054
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2298410040
Short name T1105
Test name
Test status
Simulation time 10069921900 ps
CPU time 13.74 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205520 kb
Host smart-528569d7-8130-4f25-b75c-a1ba0ac492a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22984
10040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2298410040
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1964630138
Short name T1897
Test name
Test status
Simulation time 10062696832 ps
CPU time 15.1 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205528 kb
Host smart-5e16bc2c-efec-4050-aebd-ebe6753f7a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19646
30138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1964630138
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.max_length_in_transaction.3635702751
Short name T1274
Test name
Test status
Simulation time 10136338301 ps
CPU time 15.26 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:06 PM PDT 24
Peak memory 205540 kb
Host smart-fcad1616-3807-49bf-8969-9ac62c266594
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3635702751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.max_length_in_transaction.3635702751
Directory /workspace/19.max_length_in_transaction/latest

Test location /workspace/coverage/default/19.min_length_in_transaction.4102952289
Short name T609
Test name
Test status
Simulation time 10099610488 ps
CPU time 14.02 seconds
Started May 30 03:44:49 PM PDT 24
Finished May 30 03:45:06 PM PDT 24
Peak memory 205548 kb
Host smart-b6f4a50f-7003-4f38-ac64-71e043fbf469
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4102952289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.min_length_in_transaction.4102952289
Directory /workspace/19.min_length_in_transaction/latest

Test location /workspace/coverage/default/19.random_length_in_trans.2860564481
Short name T309
Test name
Test status
Simulation time 10141451937 ps
CPU time 13.05 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205344 kb
Host smart-1e94cfc0-4a9a-4dfa-ba32-40aadc354c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28605
64481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.random_length_in_trans.2860564481
Directory /workspace/19.random_length_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1214859019
Short name T1125
Test name
Test status
Simulation time 13883989053 ps
CPU time 16.62 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 205288 kb
Host smart-e752ff07-d3a7-478b-86fd-8960c981a7d6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1214859019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1214859019
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.634496679
Short name T405
Test name
Test status
Simulation time 13282479548 ps
CPU time 16.49 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:45:02 PM PDT 24
Peak memory 205548 kb
Host smart-be57614c-8cdf-46b4-adbe-b361a57746df
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=634496679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.634496679
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1166850267
Short name T598
Test name
Test status
Simulation time 13264552958 ps
CPU time 19.21 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205528 kb
Host smart-462b2eb4-f986-458b-8d4d-dcdf69ff837f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1166850267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1166850267
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2053276812
Short name T1930
Test name
Test status
Simulation time 10075986050 ps
CPU time 13.63 seconds
Started May 30 03:44:35 PM PDT 24
Finished May 30 03:44:51 PM PDT 24
Peak memory 205540 kb
Host smart-0934dedf-1659-4d57-9013-1c06aa14c47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20532
76812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2053276812
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3328831481
Short name T1621
Test name
Test status
Simulation time 10292147208 ps
CPU time 13.68 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205596 kb
Host smart-86b0883f-cf9b-44ed-9bd6-d570bb66fce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33288
31481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3328831481
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.855964396
Short name T1617
Test name
Test status
Simulation time 10050619161 ps
CPU time 13.36 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205564 kb
Host smart-1b10a0f0-1c5a-48a6-a0e6-1ab89df772b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85596
4396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.855964396
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3510347924
Short name T1780
Test name
Test status
Simulation time 10135221855 ps
CPU time 15.51 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:45:01 PM PDT 24
Peak memory 205436 kb
Host smart-78e41f19-ec2a-41e1-bcf0-a2eb14b1ac4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35103
47924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3510347924
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.76327731
Short name T1745
Test name
Test status
Simulation time 10057982614 ps
CPU time 14.15 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205488 kb
Host smart-c20aeb81-67b0-48b5-8231-aaf664b9f5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76327
731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.76327731
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.77864184
Short name T1748
Test name
Test status
Simulation time 10116983491 ps
CPU time 13.03 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 205532 kb
Host smart-f9e5b508-a8ee-4f41-a17e-5fda1ec00fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77864
184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.77864184
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2272750221
Short name T1331
Test name
Test status
Simulation time 10039811060 ps
CPU time 12.77 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:02 PM PDT 24
Peak memory 205472 kb
Host smart-767f332e-af23-489b-aa62-a715058ff1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22727
50221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2272750221
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2954085835
Short name T845
Test name
Test status
Simulation time 10076095767 ps
CPU time 13.8 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:45:00 PM PDT 24
Peak memory 205352 kb
Host smart-285c91a5-4d83-4ec0-93b6-22c5f46e5a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29540
85835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2954085835
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1000580169
Short name T1230
Test name
Test status
Simulation time 10118233626 ps
CPU time 12.74 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:57 PM PDT 24
Peak memory 205568 kb
Host smart-c3d76a39-9df0-4d8f-ad1f-c34928019200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10005
80169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1000580169
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1542348074
Short name T493
Test name
Test status
Simulation time 13233688578 ps
CPU time 18.26 seconds
Started May 30 03:44:39 PM PDT 24
Finished May 30 03:45:00 PM PDT 24
Peak memory 205540 kb
Host smart-542ad0bc-e47f-412e-90f2-51cc82d99e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15423
48074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1542348074
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1734863600
Short name T1179
Test name
Test status
Simulation time 10123153408 ps
CPU time 14.46 seconds
Started May 30 03:44:42 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205580 kb
Host smart-59219726-c2c6-4d47-86b3-c460708ec662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17348
63600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1734863600
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.650801849
Short name T364
Test name
Test status
Simulation time 10079962095 ps
CPU time 13.55 seconds
Started May 30 03:44:36 PM PDT 24
Finished May 30 03:44:53 PM PDT 24
Peak memory 205532 kb
Host smart-023bcb68-4a38-4bf0-a38b-8be9535aab38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65080
1849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.650801849
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.994913477
Short name T993
Test name
Test status
Simulation time 10085639769 ps
CPU time 13.34 seconds
Started May 30 03:44:43 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205580 kb
Host smart-e5490db0-1f60-4466-a7e2-071ca59ad351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99491
3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.994913477
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2892866139
Short name T1335
Test name
Test status
Simulation time 10068461759 ps
CPU time 15.02 seconds
Started May 30 03:44:41 PM PDT 24
Finished May 30 03:44:59 PM PDT 24
Peak memory 205568 kb
Host smart-fe8394ed-186a-4286-bdc0-eb834c7780ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28928
66139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2892866139
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.791466897
Short name T1112
Test name
Test status
Simulation time 10073409345 ps
CPU time 14.18 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205604 kb
Host smart-2480e048-b3bc-4a3e-b07d-8ff1ad45d16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79146
6897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.791466897
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.1413877819
Short name T1326
Test name
Test status
Simulation time 10099922587 ps
CPU time 13.07 seconds
Started May 30 03:44:49 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205520 kb
Host smart-59b7dcd6-d38c-4656-87de-b3e29cb72c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
77819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.1413877819
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2824564117
Short name T233
Test name
Test status
Simulation time 10067305141 ps
CPU time 13.75 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205524 kb
Host smart-e90cf059-4aa0-4f55-8eae-354ee2f1dc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
64117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2824564117
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3514646275
Short name T1820
Test name
Test status
Simulation time 10045680430 ps
CPU time 17.6 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:12 PM PDT 24
Peak memory 205540 kb
Host smart-ac1ddf08-d627-49a6-a7d6-3cdf96b8be95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35146
46275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3514646275
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.3776075525
Short name T1483
Test name
Test status
Simulation time 19843538214 ps
CPU time 35 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:28 PM PDT 24
Peak memory 205604 kb
Host smart-affea6f4-753a-4c0d-8fac-51fa13d02e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37760
75525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.3776075525
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.4273886344
Short name T578
Test name
Test status
Simulation time 10071039598 ps
CPU time 16.36 seconds
Started May 30 03:44:46 PM PDT 24
Finished May 30 03:45:06 PM PDT 24
Peak memory 205524 kb
Host smart-10ff57bf-2ffc-47ab-ba25-167a6246c732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
86344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.4273886344
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1193613632
Short name T606
Test name
Test status
Simulation time 10141409334 ps
CPU time 12.63 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 205552 kb
Host smart-c5b2fd40-fa40-4930-8a5c-ab4a21a2cbff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
13632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1193613632
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_trans.3411330003
Short name T1410
Test name
Test status
Simulation time 10094321414 ps
CPU time 14.08 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:04 PM PDT 24
Peak memory 205596 kb
Host smart-a0e7055c-47d3-4987-a8a0-35647bbcfcc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34113
30003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_trans.3411330003
Directory /workspace/19.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3785324312
Short name T651
Test name
Test status
Simulation time 10040444686 ps
CPU time 14.05 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:08 PM PDT 24
Peak memory 205544 kb
Host smart-b7c7354f-a8f5-4e5a-83bb-ce6c3696fb23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37853
24312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3785324312
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3509300913
Short name T139
Test name
Test status
Simulation time 10064480167 ps
CPU time 16.32 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:06 PM PDT 24
Peak memory 205528 kb
Host smart-c4b69141-486d-40f2-8c9d-5313a9b6da7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35093
00913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3509300913
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3418271505
Short name T1515
Test name
Test status
Simulation time 10083983078 ps
CPU time 14.61 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205544 kb
Host smart-64d60b79-32c8-4e68-98f1-50346d0f26d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34182
71505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3418271505
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.678666195
Short name T1531
Test name
Test status
Simulation time 10140115049 ps
CPU time 13.8 seconds
Started May 30 03:44:40 PM PDT 24
Finished May 30 03:44:56 PM PDT 24
Peak memory 205636 kb
Host smart-8b538a35-309b-499e-9d9b-04c411f2a425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67866
6195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.678666195
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.716626074
Short name T914
Test name
Test status
Simulation time 10086493315 ps
CPU time 16.45 seconds
Started May 30 03:44:53 PM PDT 24
Finished May 30 03:45:13 PM PDT 24
Peak memory 205572 kb
Host smart-2c9dc332-01aa-4466-86ea-8e9906d1710d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71662
6074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.716626074
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1307602950
Short name T1783
Test name
Test status
Simulation time 10071024969 ps
CPU time 12.88 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 205540 kb
Host smart-6f7c860f-37e7-4e91-a50d-adca2b5959df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13076
02950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1307602950
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.max_length_in_transaction.2702685143
Short name T1665
Test name
Test status
Simulation time 10141497365 ps
CPU time 13.19 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205568 kb
Host smart-01e11749-cbe1-403b-98e8-8206d14e4f50
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2702685143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.max_length_in_transaction.2702685143
Directory /workspace/2.max_length_in_transaction/latest

Test location /workspace/coverage/default/2.min_length_in_transaction.2564625447
Short name T128
Test name
Test status
Simulation time 10075483972 ps
CPU time 12.76 seconds
Started May 30 03:42:30 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205560 kb
Host smart-336c4a6b-2b96-4690-b37b-0151d04856ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2564625447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.min_length_in_transaction.2564625447
Directory /workspace/2.min_length_in_transaction/latest

Test location /workspace/coverage/default/2.random_length_in_trans.2951255615
Short name T466
Test name
Test status
Simulation time 10133879392 ps
CPU time 14.47 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205552 kb
Host smart-c927b67b-7739-41f1-957f-769a27b53053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29512
55615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.random_length_in_trans.2951255615
Directory /workspace/2.random_length_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.835647097
Short name T545
Test name
Test status
Simulation time 13684624560 ps
CPU time 18.29 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:48 PM PDT 24
Peak memory 205604 kb
Host smart-1f1faf1b-d5b2-49f7-9b50-22ecb305ef75
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=835647097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.835647097
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3709253919
Short name T1547
Test name
Test status
Simulation time 13211707713 ps
CPU time 16.12 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:47 PM PDT 24
Peak memory 205548 kb
Host smart-ce83c3be-47e1-46d8-b480-ef5db43da44f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3709253919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.3709253919
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.248744005
Short name T1083
Test name
Test status
Simulation time 10096932130 ps
CPU time 14.81 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:46 PM PDT 24
Peak memory 204868 kb
Host smart-0ebf2ef7-7a28-42a1-9b51-00f3e252c5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
4005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.248744005
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2339222502
Short name T1183
Test name
Test status
Simulation time 10045603271 ps
CPU time 15.39 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205524 kb
Host smart-65c33d2e-60cc-429d-83b0-44b7946a02b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23392
22502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2339222502
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3200507080
Short name T44
Test name
Test status
Simulation time 11155351773 ps
CPU time 15.38 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:47 PM PDT 24
Peak memory 205624 kb
Host smart-f7434f82-3ba2-4dc4-8563-afa974d7cf0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32005
07080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3200507080
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.3967550355
Short name T809
Test name
Test status
Simulation time 10084655851 ps
CPU time 13.32 seconds
Started May 30 03:42:30 PM PDT 24
Finished May 30 03:42:46 PM PDT 24
Peak memory 205524 kb
Host smart-2f1998a2-763c-4793-b5ec-1e732f844cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
50355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.3967550355
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3406593498
Short name T1677
Test name
Test status
Simulation time 10043734225 ps
CPU time 13.86 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205524 kb
Host smart-b138fee4-1957-4f78-bb17-a826085b0ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
93498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3406593498
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.4037700383
Short name T1056
Test name
Test status
Simulation time 10884554243 ps
CPU time 16.74 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205544 kb
Host smart-01106ef8-83f4-4ff1-b56f-79f96ed09405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
00383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.4037700383
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2843091149
Short name T1277
Test name
Test status
Simulation time 10087697499 ps
CPU time 15.05 seconds
Started May 30 03:42:30 PM PDT 24
Finished May 30 03:42:48 PM PDT 24
Peak memory 205492 kb
Host smart-79b35072-0f0b-4111-86a1-14b587cac594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28430
91149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2843091149
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3481247853
Short name T943
Test name
Test status
Simulation time 10079298317 ps
CPU time 13.75 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205508 kb
Host smart-884f7cf9-b7c5-404b-95bd-fe5948eeef8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34812
47853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3481247853
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3292775604
Short name T1319
Test name
Test status
Simulation time 10056781599 ps
CPU time 14.07 seconds
Started May 30 03:42:25 PM PDT 24
Finished May 30 03:42:41 PM PDT 24
Peak memory 205504 kb
Host smart-4092af39-6ad4-4be2-bee8-a3b571ae70a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32927
75604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3292775604
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.4040221727
Short name T1020
Test name
Test status
Simulation time 10129218382 ps
CPU time 12.95 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:42 PM PDT 24
Peak memory 205516 kb
Host smart-748f9439-9155-4455-9d9e-0b9ecad37583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40402
21727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.4040221727
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1232361082
Short name T1309
Test name
Test status
Simulation time 10086244966 ps
CPU time 12.93 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205500 kb
Host smart-502ba2d1-0a31-4151-88f8-f06247cac45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
61082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1232361082
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1174143798
Short name T707
Test name
Test status
Simulation time 13225081346 ps
CPU time 16.88 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:48 PM PDT 24
Peak memory 205536 kb
Host smart-66978521-e946-4050-b860-8b9e859e7916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11741
43798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1174143798
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2023844535
Short name T639
Test name
Test status
Simulation time 10096838574 ps
CPU time 15.05 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205504 kb
Host smart-cfd66375-abe1-48dd-bc89-685781293283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
44535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2023844535
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2289204233
Short name T1932
Test name
Test status
Simulation time 10049056042 ps
CPU time 13.42 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205548 kb
Host smart-648878fa-cb51-444d-97ed-1e4b2a13f203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
04233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2289204233
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3187355637
Short name T481
Test name
Test status
Simulation time 10131430515 ps
CPU time 15.52 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:47 PM PDT 24
Peak memory 205368 kb
Host smart-9e363260-db8f-487c-aa16-751f00513a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31873
55637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3187355637
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3044269399
Short name T1156
Test name
Test status
Simulation time 10063025070 ps
CPU time 15.33 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205544 kb
Host smart-011e0434-4c01-4f29-9bfe-346d69ae79e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30442
69399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3044269399
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2359617962
Short name T821
Test name
Test status
Simulation time 10043501410 ps
CPU time 13.73 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205652 kb
Host smart-65c58728-c4fd-4c4c-91d6-70f50c428c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596
17962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2359617962
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.1772494829
Short name T1761
Test name
Test status
Simulation time 10113938020 ps
CPU time 15.11 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205572 kb
Host smart-0acb20eb-bd55-47a7-ad73-a88b21b3e7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
94829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.1772494829
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2953948165
Short name T1654
Test name
Test status
Simulation time 10074786730 ps
CPU time 13.65 seconds
Started May 30 03:42:29 PM PDT 24
Finished May 30 03:42:45 PM PDT 24
Peak memory 205572 kb
Host smart-99ce1e83-b5ae-408c-ac2b-347ca41eb5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29539
48165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2953948165
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3127089517
Short name T870
Test name
Test status
Simulation time 10043858650 ps
CPU time 13.15 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:43 PM PDT 24
Peak memory 205544 kb
Host smart-71d84cb7-fb3c-4e1b-aa57-7dafdf8ed2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31270
89517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3127089517
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.371967013
Short name T912
Test name
Test status
Simulation time 31292355912 ps
CPU time 56.99 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:43:26 PM PDT 24
Peak memory 205616 kb
Host smart-04a19e99-531e-4f6c-84bc-1f7fa936673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37196
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.371967013
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3423576416
Short name T408
Test name
Test status
Simulation time 10059946505 ps
CPU time 13.46 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:41 PM PDT 24
Peak memory 205520 kb
Host smart-fc6563f5-4e97-4ead-895c-858b59946ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
76416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3423576416
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2194640648
Short name T1713
Test name
Test status
Simulation time 10136483384 ps
CPU time 13.14 seconds
Started May 30 03:42:25 PM PDT 24
Finished May 30 03:42:40 PM PDT 24
Peak memory 205532 kb
Host smart-8b03dd34-364c-465c-a8b0-ae19874c611b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21946
40648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2194640648
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_trans.1913124504
Short name T1439
Test name
Test status
Simulation time 10063908561 ps
CPU time 13.92 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205564 kb
Host smart-37e5b175-ca05-4b20-a007-38acb4fc318d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
24504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_trans.1913124504
Directory /workspace/2.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.571053298
Short name T1735
Test name
Test status
Simulation time 10091958501 ps
CPU time 14.54 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205544 kb
Host smart-6ae6bb7c-adbe-48a5-bb92-48f475a2c84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57105
3298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.571053298
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3675155305
Short name T206
Test name
Test status
Simulation time 553473787 ps
CPU time 1.51 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:32 PM PDT 24
Peak memory 222144 kb
Host smart-d7b4f6fc-a22f-46b0-8a82-c1ee1aa8a594
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3675155305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3675155305
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2515077200
Short name T450
Test name
Test status
Simulation time 10079285167 ps
CPU time 14.62 seconds
Started May 30 03:42:27 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205492 kb
Host smart-91231607-e845-4a64-aafd-f5f794685fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25150
77200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2515077200
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.727322420
Short name T967
Test name
Test status
Simulation time 10050718077 ps
CPU time 15.6 seconds
Started May 30 03:42:24 PM PDT 24
Finished May 30 03:42:41 PM PDT 24
Peak memory 205484 kb
Host smart-64d96f3c-9e04-407a-a751-270aa5c1232c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72732
2420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.727322420
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2106597817
Short name T841
Test name
Test status
Simulation time 10165702074 ps
CPU time 13.64 seconds
Started May 30 03:42:31 PM PDT 24
Finished May 30 03:42:47 PM PDT 24
Peak memory 205560 kb
Host smart-6fe2a103-eb00-48f2-8e4e-c5da8ececb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21065
97817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2106597817
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1127446489
Short name T357
Test name
Test status
Simulation time 10119127935 ps
CPU time 13.68 seconds
Started May 30 03:42:28 PM PDT 24
Finished May 30 03:42:44 PM PDT 24
Peak memory 205516 kb
Host smart-8b0c2e69-b5d5-42e4-8fe8-0cdd88de76ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11274
46489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1127446489
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.3209204048
Short name T885
Test name
Test status
Simulation time 10061542573 ps
CPU time 13.45 seconds
Started May 30 03:42:26 PM PDT 24
Finished May 30 03:42:41 PM PDT 24
Peak memory 205544 kb
Host smart-02463657-b26d-431c-927f-44566db3e7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
04048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.3209204048
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.max_length_in_transaction.2799801641
Short name T1044
Test name
Test status
Simulation time 10239225594 ps
CPU time 13.82 seconds
Started May 30 03:44:55 PM PDT 24
Finished May 30 03:45:12 PM PDT 24
Peak memory 205600 kb
Host smart-59524d53-2ee7-4da9-ad62-7bffc77535df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2799801641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.max_length_in_transaction.2799801641
Directory /workspace/20.max_length_in_transaction/latest

Test location /workspace/coverage/default/20.min_length_in_transaction.2881895119
Short name T1868
Test name
Test status
Simulation time 10062686173 ps
CPU time 13.32 seconds
Started May 30 03:44:55 PM PDT 24
Finished May 30 03:45:12 PM PDT 24
Peak memory 205568 kb
Host smart-3087b4bc-3a46-497e-8c61-843b109afc82
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2881895119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.min_length_in_transaction.2881895119
Directory /workspace/20.min_length_in_transaction/latest

Test location /workspace/coverage/default/20.random_length_in_trans.3300015828
Short name T1765
Test name
Test status
Simulation time 10092599362 ps
CPU time 14.21 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205564 kb
Host smart-beb6c64d-91d7-4499-82b0-e73219b8187e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
15828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.random_length_in_trans.3300015828
Directory /workspace/20.random_length_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2474410333
Short name T819
Test name
Test status
Simulation time 13978475630 ps
CPU time 17.85 seconds
Started May 30 03:44:46 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205552 kb
Host smart-80ab2b72-883f-4d12-920b-98d318acbce6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2474410333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2474410333
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2701955526
Short name T905
Test name
Test status
Simulation time 13248174970 ps
CPU time 18.54 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:08 PM PDT 24
Peak memory 205560 kb
Host smart-d1cecf4f-92a6-4c72-aefc-1ea1f47d44db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2701955526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2701955526
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1792540688
Short name T977
Test name
Test status
Simulation time 13233478707 ps
CPU time 18.35 seconds
Started May 30 03:44:45 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205556 kb
Host smart-ea358242-c15a-48d5-9442-4caea97980db
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1792540688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1792540688
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2257475846
Short name T1113
Test name
Test status
Simulation time 10056071119 ps
CPU time 13.24 seconds
Started May 30 03:44:54 PM PDT 24
Finished May 30 03:45:11 PM PDT 24
Peak memory 205516 kb
Host smart-c89781ff-a1d8-4a84-8fd9-fe8c1f5a2392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
75846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2257475846
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.4291214002
Short name T561
Test name
Test status
Simulation time 10293638444 ps
CPU time 13.1 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 205636 kb
Host smart-f2881ff9-0bb3-498e-a946-2aa55434615d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42912
14002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.4291214002
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1022838027
Short name T999
Test name
Test status
Simulation time 10042049182 ps
CPU time 15.9 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205520 kb
Host smart-7d87e532-f13c-46cb-9606-769c716a990c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10228
38027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1022838027
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3790051967
Short name T542
Test name
Test status
Simulation time 10058437186 ps
CPU time 15.78 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205508 kb
Host smart-d69e7d1f-75a5-4f05-ae28-712d24f8a278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37900
51967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3790051967
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1670014180
Short name T1033
Test name
Test status
Simulation time 10754214237 ps
CPU time 14.55 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:08 PM PDT 24
Peak memory 205524 kb
Host smart-72db3498-01ec-4705-b682-fb364569f361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16700
14180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1670014180
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.78624347
Short name T1723
Test name
Test status
Simulation time 10168262612 ps
CPU time 17.19 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:13 PM PDT 24
Peak memory 205572 kb
Host smart-87be1e45-037c-47b2-ada6-4445930347e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78624
347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.78624347
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3107164507
Short name T1517
Test name
Test status
Simulation time 10054543792 ps
CPU time 14.43 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:08 PM PDT 24
Peak memory 205584 kb
Host smart-901df62b-bd56-4f63-ab12-55856c7a5cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31071
64507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3107164507
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.3340037730
Short name T1076
Test name
Test status
Simulation time 10043646117 ps
CPU time 16.39 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:11 PM PDT 24
Peak memory 205544 kb
Host smart-fc33f5f9-1c3d-44df-9c1c-3bf564068976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33400
37730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3340037730
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2025399951
Short name T705
Test name
Test status
Simulation time 10127904138 ps
CPU time 15.6 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205376 kb
Host smart-29f257fd-6471-4258-be25-51fdd90d1d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253
99951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2025399951
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2379276816
Short name T1143
Test name
Test status
Simulation time 10117032732 ps
CPU time 15.42 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205572 kb
Host smart-33e37dc8-f1a5-4ca5-a6d4-4857c2513634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
76816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2379276816
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2596618741
Short name T1050
Test name
Test status
Simulation time 13211536859 ps
CPU time 16.27 seconds
Started May 30 03:44:46 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205512 kb
Host smart-946b146c-6663-40a5-95a4-fdfafe9627e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25966
18741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2596618741
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3934451881
Short name T540
Test name
Test status
Simulation time 10103191850 ps
CPU time 14.13 seconds
Started May 30 03:44:46 PM PDT 24
Finished May 30 03:45:04 PM PDT 24
Peak memory 205552 kb
Host smart-b3b39e2b-102f-4bf8-89b2-12df87a6f7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39344
51881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3934451881
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3692563228
Short name T1296
Test name
Test status
Simulation time 10059377244 ps
CPU time 14.09 seconds
Started May 30 03:44:49 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205548 kb
Host smart-a40a61a1-7d8c-414c-b25f-2e4d2c48c67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36925
63228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3692563228
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.56062806
Short name T118
Test name
Test status
Simulation time 10115641480 ps
CPU time 13.62 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:06 PM PDT 24
Peak memory 205512 kb
Host smart-eaba74c3-84d0-4bef-b897-a77cefe2ac88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56062
806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.56062806
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.267911135
Short name T1862
Test name
Test status
Simulation time 10102783315 ps
CPU time 14.35 seconds
Started May 30 03:44:49 PM PDT 24
Finished May 30 03:45:07 PM PDT 24
Peak memory 205560 kb
Host smart-da3f64e6-dd01-4490-9dd3-3cb7c62b8ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26791
1135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.267911135
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3199535091
Short name T19
Test name
Test status
Simulation time 10098290125 ps
CPU time 13.15 seconds
Started May 30 03:44:49 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205556 kb
Host smart-cfc01a87-9bf6-4c94-bed7-e0b6169c2247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31995
35091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3199535091
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.4231031204
Short name T969
Test name
Test status
Simulation time 10065011885 ps
CPU time 15.43 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:11 PM PDT 24
Peak memory 205536 kb
Host smart-3fd08f49-b6f2-49f6-a978-8c2ee3e40554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
31204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.4231031204
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4229359507
Short name T1769
Test name
Test status
Simulation time 10153512794 ps
CPU time 12.94 seconds
Started May 30 03:44:53 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205536 kb
Host smart-6809efc9-de91-4670-8afd-d57a7f5d3e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
59507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4229359507
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.4243485409
Short name T319
Test name
Test status
Simulation time 10113278799 ps
CPU time 15.48 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205520 kb
Host smart-f6a4eaba-05ec-43e1-835b-35cc32959e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42434
85409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.4243485409
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.157727697
Short name T769
Test name
Test status
Simulation time 10035279115 ps
CPU time 14.24 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:08 PM PDT 24
Peak memory 205496 kb
Host smart-2e73e91a-d65b-4dd2-9077-f4492af356b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15772
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.157727697
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3417033097
Short name T1911
Test name
Test status
Simulation time 10050744891 ps
CPU time 15.35 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205516 kb
Host smart-8c774a21-7187-44dd-a142-5dc78b557fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
33097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3417033097
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.419596187
Short name T237
Test name
Test status
Simulation time 26812699953 ps
CPU time 48.01 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:39 PM PDT 24
Peak memory 205636 kb
Host smart-c31e545a-ee86-4717-a711-7fd29939737d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41959
6187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.419596187
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4280863838
Short name T1128
Test name
Test status
Simulation time 10094186026 ps
CPU time 13.38 seconds
Started May 30 03:44:47 PM PDT 24
Finished May 30 03:45:03 PM PDT 24
Peak memory 205536 kb
Host smart-df11c7b6-cf97-4f98-8dc3-236963873880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42808
63838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4280863838
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2128365325
Short name T1576
Test name
Test status
Simulation time 10076606775 ps
CPU time 12.65 seconds
Started May 30 03:44:55 PM PDT 24
Finished May 30 03:45:11 PM PDT 24
Peak memory 205552 kb
Host smart-5dc9dd0e-326a-444f-a867-258a2ecfa0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21283
65325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2128365325
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_trans.3347625220
Short name T1751
Test name
Test status
Simulation time 10072216840 ps
CPU time 13.06 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:04 PM PDT 24
Peak memory 205572 kb
Host smart-91dd565e-a6e3-4e67-9864-2054cbc7ba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33476
25220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_trans.3347625220
Directory /workspace/20.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1181462726
Short name T1189
Test name
Test status
Simulation time 10048169833 ps
CPU time 14.65 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205540 kb
Host smart-3dcbbaa0-5479-4ec4-88cb-f07ad9acc26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
62726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1181462726
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2924886664
Short name T134
Test name
Test status
Simulation time 10053076947 ps
CPU time 14.04 seconds
Started May 30 03:44:53 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205552 kb
Host smart-83d2f22a-0f6b-4cde-9802-fc425e634d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29248
86664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2924886664
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1059539222
Short name T1069
Test name
Test status
Simulation time 10058441942 ps
CPU time 17.15 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:12 PM PDT 24
Peak memory 205544 kb
Host smart-100aa487-a2a9-4bcd-ac89-5a8737a41252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10595
39222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1059539222
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.10642756
Short name T64
Test name
Test status
Simulation time 10106672308 ps
CPU time 13.9 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:04 PM PDT 24
Peak memory 205576 kb
Host smart-1a5d063e-686b-4d83-a09a-2683d921c46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.10642756
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2115307887
Short name T704
Test name
Test status
Simulation time 10080374911 ps
CPU time 14.56 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205580 kb
Host smart-65995167-8c2e-4352-aefe-d6889d530d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21153
07887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2115307887
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1367691214
Short name T1484
Test name
Test status
Simulation time 10062062643 ps
CPU time 13.73 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:08 PM PDT 24
Peak memory 205372 kb
Host smart-3ffc2616-431b-4ede-a4fa-5d187d64cf96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13676
91214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1367691214
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.max_length_in_transaction.3103717780
Short name T934
Test name
Test status
Simulation time 10153791501 ps
CPU time 15.34 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:17 PM PDT 24
Peak memory 205556 kb
Host smart-c94ccc42-0a58-4877-bc72-2e204414e5a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3103717780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.max_length_in_transaction.3103717780
Directory /workspace/21.max_length_in_transaction/latest

Test location /workspace/coverage/default/21.min_length_in_transaction.3497218063
Short name T1144
Test name
Test status
Simulation time 10054258792 ps
CPU time 16.01 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:17 PM PDT 24
Peak memory 205544 kb
Host smart-0d933cd0-2585-4b5e-8e57-8c16e459bff0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3497218063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.min_length_in_transaction.3497218063
Directory /workspace/21.min_length_in_transaction/latest

Test location /workspace/coverage/default/21.random_length_in_trans.3434080665
Short name T786
Test name
Test status
Simulation time 10103510245 ps
CPU time 13.33 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:20 PM PDT 24
Peak memory 205548 kb
Host smart-f39c1d8a-61cc-4851-be9f-02f07b603ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34340
80665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.random_length_in_trans.3434080665
Directory /workspace/21.random_length_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.1022290919
Short name T1746
Test name
Test status
Simulation time 13495313382 ps
CPU time 18.03 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:14 PM PDT 24
Peak memory 205560 kb
Host smart-a0129e9b-39af-49a4-8432-ca52eda9c5f1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1022290919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.1022290919
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1364997613
Short name T709
Test name
Test status
Simulation time 13319104200 ps
CPU time 17.54 seconds
Started May 30 03:44:54 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205532 kb
Host smart-0f8624b8-6dd2-4111-a83c-ef53337aa28a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1364997613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1364997613
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2144728541
Short name T604
Test name
Test status
Simulation time 10068241062 ps
CPU time 14.54 seconds
Started May 30 03:44:51 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205532 kb
Host smart-baf13082-dd4c-4c0a-a7f0-fa30691c0654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
28541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2144728541
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1129957248
Short name T1205
Test name
Test status
Simulation time 10771684320 ps
CPU time 18.48 seconds
Started May 30 03:44:49 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205544 kb
Host smart-4bcb24ce-517d-4b40-87a7-b076ae38c798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11299
57248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1129957248
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1396972590
Short name T1662
Test name
Test status
Simulation time 10034169971 ps
CPU time 12.78 seconds
Started May 30 03:45:02 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205524 kb
Host smart-a6718e20-3b68-4f0f-be89-1ecc8a42e55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13969
72590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1396972590
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.250846051
Short name T463
Test name
Test status
Simulation time 10066356332 ps
CPU time 14.95 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205564 kb
Host smart-47737375-a602-48e0-8c49-b5d688ed9453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084
6051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.250846051
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3645529501
Short name T511
Test name
Test status
Simulation time 10084856468 ps
CPU time 15.24 seconds
Started May 30 03:44:53 PM PDT 24
Finished May 30 03:45:12 PM PDT 24
Peak memory 205504 kb
Host smart-cc9762c4-f490-4dbc-b2b8-4d93a6d83aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36455
29501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3645529501
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.984358105
Short name T915
Test name
Test status
Simulation time 10121532933 ps
CPU time 14.1 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205580 kb
Host smart-8cf89669-d2bd-42e0-8093-a0e89489ea68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98435
8105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.984358105
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2949224813
Short name T747
Test name
Test status
Simulation time 10052908529 ps
CPU time 13.77 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:16 PM PDT 24
Peak memory 205532 kb
Host smart-e96002b9-df67-4612-94a1-8cb30dd7fe31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29492
24813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2949224813
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3378073730
Short name T1008
Test name
Test status
Simulation time 10071247769 ps
CPU time 15.67 seconds
Started May 30 03:44:54 PM PDT 24
Finished May 30 03:45:13 PM PDT 24
Peak memory 205564 kb
Host smart-b3750b70-3944-4730-b59c-991323657035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33780
73730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3378073730
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1987154577
Short name T14
Test name
Test status
Simulation time 10105335036 ps
CPU time 15 seconds
Started May 30 03:44:52 PM PDT 24
Finished May 30 03:45:10 PM PDT 24
Peak memory 205572 kb
Host smart-76d92f6d-db23-40a1-9172-ce63b51f6d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19871
54577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1987154577
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1623535348
Short name T737
Test name
Test status
Simulation time 13169354202 ps
CPU time 16.48 seconds
Started May 30 03:44:50 PM PDT 24
Finished May 30 03:45:09 PM PDT 24
Peak memory 205556 kb
Host smart-bd56f6f1-8643-4576-b699-6261e981596a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16235
35348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1623535348
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3502687808
Short name T1573
Test name
Test status
Simulation time 10122761758 ps
CPU time 12.94 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:20 PM PDT 24
Peak memory 205564 kb
Host smart-ba836e57-6d7e-4dde-9860-f9db414fd506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
87808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3502687808
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1903793294
Short name T1727
Test name
Test status
Simulation time 10043356803 ps
CPU time 13.88 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205548 kb
Host smart-f90f87de-0832-4079-9582-fb224c64de57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19037
93294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1903793294
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1403189369
Short name T976
Test name
Test status
Simulation time 10195910723 ps
CPU time 14.73 seconds
Started May 30 03:45:01 PM PDT 24
Finished May 30 03:45:19 PM PDT 24
Peak memory 205532 kb
Host smart-d5d77328-009f-4435-867d-ef1bca740260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14031
89369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1403189369
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2633894765
Short name T1068
Test name
Test status
Simulation time 10197656068 ps
CPU time 15.07 seconds
Started May 30 03:45:00 PM PDT 24
Finished May 30 03:45:19 PM PDT 24
Peak memory 205572 kb
Host smart-707b1366-e968-4de5-a8a3-21ece99c591b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26338
94765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2633894765
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.682712383
Short name T395
Test name
Test status
Simulation time 10087360977 ps
CPU time 16.18 seconds
Started May 30 03:45:05 PM PDT 24
Finished May 30 03:45:24 PM PDT 24
Peak memory 205556 kb
Host smart-85e2533d-6281-4d15-85c1-6f088b9da3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68271
2383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.682712383
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2289799703
Short name T1320
Test name
Test status
Simulation time 10052627747 ps
CPU time 13.3 seconds
Started May 30 03:45:02 PM PDT 24
Finished May 30 03:45:19 PM PDT 24
Peak memory 205544 kb
Host smart-4006eff2-1646-4945-9636-1dc02fcf16ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
99703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2289799703
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.487009776
Short name T798
Test name
Test status
Simulation time 10071688448 ps
CPU time 13.85 seconds
Started May 30 03:44:57 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205548 kb
Host smart-d17552a8-00bc-46e2-81fa-1427628ba758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48700
9776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.487009776
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3944333419
Short name T425
Test name
Test status
Simulation time 10053428933 ps
CPU time 15.11 seconds
Started May 30 03:45:05 PM PDT 24
Finished May 30 03:45:23 PM PDT 24
Peak memory 205540 kb
Host smart-e40a45ad-751e-4bf6-a1b8-18ffcf4d8fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443
33419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3944333419
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1931803888
Short name T953
Test name
Test status
Simulation time 10073438879 ps
CPU time 15.74 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:23 PM PDT 24
Peak memory 204876 kb
Host smart-402ae032-e2b2-42d8-909c-c9686e3589da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19318
03888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1931803888
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.587286791
Short name T863
Test name
Test status
Simulation time 17561078765 ps
CPU time 30.36 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:37 PM PDT 24
Peak memory 205596 kb
Host smart-615d460d-0ee1-4ecf-8364-d970e64525aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58728
6791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.587286791
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1303832540
Short name T1847
Test name
Test status
Simulation time 10054530777 ps
CPU time 13.63 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205608 kb
Host smart-b4b63d7e-910b-4c1a-817d-5be84064aeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13038
32540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1303832540
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1034000936
Short name T356
Test name
Test status
Simulation time 10106375754 ps
CPU time 14.58 seconds
Started May 30 03:44:56 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205544 kb
Host smart-186a908a-064e-4234-8b71-3740e5541479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10340
00936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1034000936
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_trans.264580876
Short name T875
Test name
Test status
Simulation time 10079338204 ps
CPU time 15.22 seconds
Started May 30 03:45:02 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 205524 kb
Host smart-9ec6b28a-928a-4446-b4a0-f2281e46d78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
0876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_trans.264580876
Directory /workspace/21.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3518040332
Short name T722
Test name
Test status
Simulation time 10096777691 ps
CPU time 13.89 seconds
Started May 30 03:44:56 PM PDT 24
Finished May 30 03:45:14 PM PDT 24
Peak memory 205564 kb
Host smart-7ff507e8-37c8-4494-8c25-3d19de50e587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
40332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3518040332
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.320354977
Short name T859
Test name
Test status
Simulation time 10051373387 ps
CPU time 15.85 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:22 PM PDT 24
Peak memory 205520 kb
Host smart-f844858e-9d63-4d9c-99fd-2d682305a342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32035
4977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.320354977
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2323010680
Short name T420
Test name
Test status
Simulation time 10068021522 ps
CPU time 13.38 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:20 PM PDT 24
Peak memory 205544 kb
Host smart-03f70241-6245-460d-8ae7-511892be5bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23230
10680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2323010680
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1010491030
Short name T619
Test name
Test status
Simulation time 10117694182 ps
CPU time 14.06 seconds
Started May 30 03:44:48 PM PDT 24
Finished May 30 03:45:05 PM PDT 24
Peak memory 205552 kb
Host smart-54f57daf-e853-464c-8801-7e92aac35678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
91030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1010491030
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.496396365
Short name T1101
Test name
Test status
Simulation time 10073860691 ps
CPU time 12.94 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:24 PM PDT 24
Peak memory 205620 kb
Host smart-b0db74b9-62ad-4099-a1f4-3d91b746fa45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49639
6365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.496396365
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3541975772
Short name T1699
Test name
Test status
Simulation time 10081670182 ps
CPU time 15.05 seconds
Started May 30 03:45:00 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205476 kb
Host smart-d07ac24f-091c-4a20-b7c9-00d3b20a52ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35419
75772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3541975772
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.max_length_in_transaction.650174685
Short name T1
Test name
Test status
Simulation time 10141190701 ps
CPU time 16.19 seconds
Started May 30 03:45:02 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 205548 kb
Host smart-9fa4ef05-b149-41d7-916c-0ab0caa5b0fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=650174685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.max_length_in_transaction.650174685
Directory /workspace/22.max_length_in_transaction/latest

Test location /workspace/coverage/default/22.min_length_in_transaction.4176904843
Short name T127
Test name
Test status
Simulation time 10045174300 ps
CPU time 15.12 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:16 PM PDT 24
Peak memory 205596 kb
Host smart-9f1a782e-aeb7-46e4-abf6-156e5420007e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4176904843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.min_length_in_transaction.4176904843
Directory /workspace/22.min_length_in_transaction/latest

Test location /workspace/coverage/default/22.random_length_in_trans.2427221933
Short name T577
Test name
Test status
Simulation time 10124819732 ps
CPU time 14.16 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 205536 kb
Host smart-51077d3d-fc87-4a11-8fef-45ebd68b0905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
21933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.random_length_in_trans.2427221933
Directory /workspace/22.random_length_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1171100410
Short name T1328
Test name
Test status
Simulation time 13325337439 ps
CPU time 16.48 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:23 PM PDT 24
Peak memory 205572 kb
Host smart-fbd6bd4b-f01f-489e-9a1d-4fe61b118d5c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1171100410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1171100410
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3179383032
Short name T1200
Test name
Test status
Simulation time 13320980902 ps
CPU time 16.5 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:23 PM PDT 24
Peak memory 205556 kb
Host smart-89e3c528-2b84-43d8-9a6e-995119316b69
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3179383032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3179383032
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2988450933
Short name T1800
Test name
Test status
Simulation time 13263795197 ps
CPU time 16.18 seconds
Started May 30 03:44:56 PM PDT 24
Finished May 30 03:45:16 PM PDT 24
Peak memory 205544 kb
Host smart-34c2624a-6659-4739-b337-d126ad9c37a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2988450933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.2988450933
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3111621980
Short name T648
Test name
Test status
Simulation time 10122802688 ps
CPU time 13.99 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:24 PM PDT 24
Peak memory 205612 kb
Host smart-7b8af5d4-7aa1-4fcf-b766-3fc9a89b9efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31116
21980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3111621980
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1349393376
Short name T971
Test name
Test status
Simulation time 11312601524 ps
CPU time 16.25 seconds
Started May 30 03:45:00 PM PDT 24
Finished May 30 03:45:20 PM PDT 24
Peak memory 205596 kb
Host smart-f335c2e7-8d12-4021-8cd1-60f94e56c91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493
93376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1349393376
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3142271838
Short name T1393
Test name
Test status
Simulation time 10048336328 ps
CPU time 13.59 seconds
Started May 30 03:44:57 PM PDT 24
Finished May 30 03:45:14 PM PDT 24
Peak memory 205556 kb
Host smart-3ebde4ab-4915-420c-9953-da0cda3abc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31422
71838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3142271838
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3061592484
Short name T955
Test name
Test status
Simulation time 10087309046 ps
CPU time 13.95 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 204956 kb
Host smart-bc6a9922-7487-4220-a80c-10639ff52f9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
92484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3061592484
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3290225332
Short name T69
Test name
Test status
Simulation time 10826071015 ps
CPU time 14.9 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 205532 kb
Host smart-814f88b1-96df-4edd-8eba-ce1cf30e4fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32902
25332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3290225332
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.330406078
Short name T1228
Test name
Test status
Simulation time 10111876144 ps
CPU time 14.5 seconds
Started May 30 03:45:05 PM PDT 24
Finished May 30 03:45:22 PM PDT 24
Peak memory 205540 kb
Host smart-61df8d5f-6793-434f-b765-593061f6f4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
6078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.330406078
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.268965371
Short name T1566
Test name
Test status
Simulation time 10079563147 ps
CPU time 16.55 seconds
Started May 30 03:45:07 PM PDT 24
Finished May 30 03:45:26 PM PDT 24
Peak memory 205508 kb
Host smart-58bbfcd8-20f7-45db-b3d4-c21646862d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
5371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.268965371
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1066716327
Short name T1561
Test name
Test status
Simulation time 10080568597 ps
CPU time 15.96 seconds
Started May 30 03:45:07 PM PDT 24
Finished May 30 03:45:26 PM PDT 24
Peak memory 205504 kb
Host smart-0846d80c-c728-46f5-a186-c3e7d083e1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10667
16327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1066716327
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3692885089
Short name T1618
Test name
Test status
Simulation time 10124970324 ps
CPU time 13.85 seconds
Started May 30 03:44:57 PM PDT 24
Finished May 30 03:45:15 PM PDT 24
Peak memory 205536 kb
Host smart-fa9c3d7b-9f81-46a7-a62b-a01c43971784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36928
85089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3692885089
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2710921115
Short name T1165
Test name
Test status
Simulation time 10060669142 ps
CPU time 15.75 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205524 kb
Host smart-55c006fd-c34f-40fb-a705-d102243c64b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27109
21115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2710921115
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.2513688611
Short name T1653
Test name
Test status
Simulation time 13164717105 ps
CPU time 16.38 seconds
Started May 30 03:45:04 PM PDT 24
Finished May 30 03:45:23 PM PDT 24
Peak memory 205528 kb
Host smart-6761641d-4855-4172-97a7-59e43938c104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25136
88611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2513688611
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.4279186398
Short name T560
Test name
Test status
Simulation time 10091814719 ps
CPU time 15.27 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 205580 kb
Host smart-da36fc52-b1cf-403b-b402-a1ecf2306c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
86398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.4279186398
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.485738720
Short name T1645
Test name
Test status
Simulation time 10079014950 ps
CPU time 12.97 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:24 PM PDT 24
Peak memory 205576 kb
Host smart-d2e17780-cc11-4c55-95da-eb99ff31e45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48573
8720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.485738720
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.901237911
Short name T1589
Test name
Test status
Simulation time 10120045234 ps
CPU time 16.09 seconds
Started May 30 03:44:58 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205568 kb
Host smart-b71b2863-3bac-4553-af21-55a25e880ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90123
7911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.901237911
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.4108515713
Short name T1642
Test name
Test status
Simulation time 10108804112 ps
CPU time 15.96 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:26 PM PDT 24
Peak memory 205612 kb
Host smart-5a26fdef-d9ed-4f92-9d0c-0bc1ca9cd1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085
15713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.4108515713
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2910663379
Short name T1728
Test name
Test status
Simulation time 10120562861 ps
CPU time 16.45 seconds
Started May 30 03:45:01 PM PDT 24
Finished May 30 03:45:21 PM PDT 24
Peak memory 205520 kb
Host smart-7194e492-3cff-4b46-a6aa-f73434026c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29106
63379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2910663379
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.632657473
Short name T1569
Test name
Test status
Simulation time 10142114925 ps
CPU time 13.95 seconds
Started May 30 03:45:00 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205572 kb
Host smart-66ad95b8-63d6-4c9e-850e-47e7d7124370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63265
7473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.632657473
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3063209251
Short name T1212
Test name
Test status
Simulation time 10101333144 ps
CPU time 15.73 seconds
Started May 30 03:45:03 PM PDT 24
Finished May 30 03:45:22 PM PDT 24
Peak memory 205544 kb
Host smart-496d0a81-cfea-439c-854e-8aeccc111edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632
09251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3063209251
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.322758396
Short name T516
Test name
Test status
Simulation time 10092712591 ps
CPU time 14.38 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:17 PM PDT 24
Peak memory 205544 kb
Host smart-ba7e9a7e-e940-4a0b-a914-75cd2a2dd160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32275
8396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.322758396
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2713287861
Short name T1776
Test name
Test status
Simulation time 10048964456 ps
CPU time 15.2 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:26 PM PDT 24
Peak memory 205568 kb
Host smart-0cacac8d-23b0-4e2c-8b98-d590454e7a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
87861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2713287861
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.531606803
Short name T1261
Test name
Test status
Simulation time 10046962149 ps
CPU time 13.85 seconds
Started May 30 03:45:02 PM PDT 24
Finished May 30 03:45:19 PM PDT 24
Peak memory 205540 kb
Host smart-57fa87ab-43b2-4318-b750-b4fda382f3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53160
6803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.531606803
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1563257681
Short name T1879
Test name
Test status
Simulation time 20747331647 ps
CPU time 36.28 seconds
Started May 30 03:45:05 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205608 kb
Host smart-798b4be2-989b-4e61-a208-f0438f36ebc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15632
57681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1563257681
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2965492263
Short name T728
Test name
Test status
Simulation time 10091584195 ps
CPU time 14.89 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:26 PM PDT 24
Peak memory 205540 kb
Host smart-f7f6ad66-601e-44fa-a54d-c9bb0528b4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29654
92263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2965492263
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1418664032
Short name T1341
Test name
Test status
Simulation time 10139068165 ps
CPU time 14.38 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:26 PM PDT 24
Peak memory 205580 kb
Host smart-010718bc-1883-43be-beff-29b4654eb9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14186
64032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1418664032
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_trans.1659143676
Short name T920
Test name
Test status
Simulation time 10083675565 ps
CPU time 14.14 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:25 PM PDT 24
Peak memory 205548 kb
Host smart-27be7e44-ebc0-4777-ae51-43ce50667e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
43676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_trans.1659143676
Directory /workspace/22.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.79712434
Short name T1238
Test name
Test status
Simulation time 10056090922 ps
CPU time 13.16 seconds
Started May 30 03:45:01 PM PDT 24
Finished May 30 03:45:18 PM PDT 24
Peak memory 205480 kb
Host smart-061b6d6a-b220-4742-8a52-a39808ef3db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79712
434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.79712434
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2815601757
Short name T151
Test name
Test status
Simulation time 10129783719 ps
CPU time 16.73 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:20 PM PDT 24
Peak memory 205540 kb
Host smart-6f67fb8b-600b-49a3-956a-d6ecca8e3df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
01757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2815601757
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2213023222
Short name T1072
Test name
Test status
Simulation time 10048521725 ps
CPU time 14.21 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:25 PM PDT 24
Peak memory 205508 kb
Host smart-1aa9e81e-3d6a-4c7c-b8b5-e925c5a78948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22130
23222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2213023222
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.103566187
Short name T1510
Test name
Test status
Simulation time 10114202115 ps
CPU time 13.99 seconds
Started May 30 03:44:59 PM PDT 24
Finished May 30 03:45:17 PM PDT 24
Peak memory 205572 kb
Host smart-a495fcca-23b3-4806-ab18-c36738023685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10356
6187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.103566187
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2154941794
Short name T876
Test name
Test status
Simulation time 10066171398 ps
CPU time 13.27 seconds
Started May 30 03:45:09 PM PDT 24
Finished May 30 03:45:25 PM PDT 24
Peak memory 205608 kb
Host smart-e1690836-0aa7-4ab8-997b-0ee879b6122b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
41794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2154941794
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.3452547444
Short name T1093
Test name
Test status
Simulation time 10096214841 ps
CPU time 13.35 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:24 PM PDT 24
Peak memory 205508 kb
Host smart-c9cf561f-057c-4110-a2de-aa026c150d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
47444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.3452547444
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.max_length_in_transaction.2557468690
Short name T1689
Test name
Test status
Simulation time 10206807216 ps
CPU time 14.61 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205596 kb
Host smart-cdefc118-4387-49ad-b403-a59884f557f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2557468690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.max_length_in_transaction.2557468690
Directory /workspace/23.max_length_in_transaction/latest

Test location /workspace/coverage/default/23.min_length_in_transaction.3297064454
Short name T1015
Test name
Test status
Simulation time 10061207368 ps
CPU time 13.94 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205516 kb
Host smart-8dc036f8-9e86-47c8-ab88-538eb0aaf590
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3297064454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.min_length_in_transaction.3297064454
Directory /workspace/23.min_length_in_transaction/latest

Test location /workspace/coverage/default/23.random_length_in_trans.2171729983
Short name T896
Test name
Test status
Simulation time 10080983174 ps
CPU time 15.38 seconds
Started May 30 03:45:20 PM PDT 24
Finished May 30 03:45:37 PM PDT 24
Peak memory 205504 kb
Host smart-7e3a1cfc-6f28-48d8-9983-86f469b7d96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717
29983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.random_length_in_trans.2171729983
Directory /workspace/23.random_length_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1719723955
Short name T974
Test name
Test status
Simulation time 13459507933 ps
CPU time 17.11 seconds
Started May 30 03:45:08 PM PDT 24
Finished May 30 03:45:27 PM PDT 24
Peak memory 205440 kb
Host smart-c6c253c4-7030-4d01-aa08-a0c0f3e92340
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1719723955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1719723955
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2615456839
Short name T790
Test name
Test status
Simulation time 13301541416 ps
CPU time 18.11 seconds
Started May 30 03:45:02 PM PDT 24
Finished May 30 03:45:23 PM PDT 24
Peak memory 205564 kb
Host smart-6f5cb758-4144-4b29-9203-0e391f23dfec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2615456839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2615456839
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3598675646
Short name T1853
Test name
Test status
Simulation time 13254144171 ps
CPU time 17.73 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:36 PM PDT 24
Peak memory 205564 kb
Host smart-ca251531-5756-4713-96fa-274f3dc7fa94
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3598675646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3598675646
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.898682206
Short name T1307
Test name
Test status
Simulation time 10051892067 ps
CPU time 14.6 seconds
Started May 30 03:45:12 PM PDT 24
Finished May 30 03:45:28 PM PDT 24
Peak memory 205492 kb
Host smart-55fa9f92-c0ed-441c-9f11-9e2ae1de9fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89868
2206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.898682206
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1134668146
Short name T1399
Test name
Test status
Simulation time 10725293428 ps
CPU time 14.6 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205648 kb
Host smart-504d9d5f-5ba7-4d12-8977-64dc9eca88fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11346
68146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1134668146
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1157733358
Short name T39
Test name
Test status
Simulation time 10073083939 ps
CPU time 14.58 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205500 kb
Host smart-5d2293f2-6fb5-4697-ba4b-77f2844e3650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
33358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1157733358
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.2548284504
Short name T669
Test name
Test status
Simulation time 10065134445 ps
CPU time 15.25 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205604 kb
Host smart-6f43a6af-aaab-4a6f-ba27-8cfc33d16df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
84504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2548284504
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.2160851915
Short name T679
Test name
Test status
Simulation time 10792976809 ps
CPU time 15.08 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205608 kb
Host smart-b14da292-8e2c-47f3-bce4-99c928852809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21608
51915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2160851915
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3074270231
Short name T1685
Test name
Test status
Simulation time 10180285896 ps
CPU time 15.05 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205492 kb
Host smart-84d4373a-663b-4a09-bffc-675cdafd78dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
70231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3074270231
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.2213673177
Short name T623
Test name
Test status
Simulation time 10095815112 ps
CPU time 16.72 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205572 kb
Host smart-2b8da4ab-41e6-44c9-854d-ea6363e60ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22136
73177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.2213673177
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2897342706
Short name T546
Test name
Test status
Simulation time 10129654611 ps
CPU time 13.8 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205580 kb
Host smart-4db1d0cd-89fc-4a93-a9f2-c3c7de181e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28973
42706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2897342706
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2790345640
Short name T1907
Test name
Test status
Simulation time 10222575360 ps
CPU time 13.86 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205532 kb
Host smart-edb779d6-b3f5-4405-b6fa-dbae09ec299e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27903
45640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2790345640
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3151834589
Short name T461
Test name
Test status
Simulation time 10108497998 ps
CPU time 13.9 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205508 kb
Host smart-76729e21-ece0-4c95-ba83-8c1aa3d61c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31518
34589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3151834589
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.6099805
Short name T683
Test name
Test status
Simulation time 13194313157 ps
CPU time 16.24 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205600 kb
Host smart-1503c25d-7118-4928-9233-c9e411d72ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60998
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.6099805
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3622500507
Short name T983
Test name
Test status
Simulation time 10090808982 ps
CPU time 16.04 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205528 kb
Host smart-323a343c-dacd-4bf3-be13-78eacd3bb7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36225
00507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3622500507
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.2507906822
Short name T1675
Test name
Test status
Simulation time 10050476047 ps
CPU time 13.92 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205524 kb
Host smart-3e100a6f-1b77-4234-8286-2dc23ba86608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25079
06822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.2507906822
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2916588873
Short name T117
Test name
Test status
Simulation time 10139740870 ps
CPU time 13.38 seconds
Started May 30 03:45:20 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205504 kb
Host smart-de1f7358-66b5-4fae-84e2-21ce7500c727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29165
88873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2916588873
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.292353786
Short name T1471
Test name
Test status
Simulation time 10094071064 ps
CPU time 12.79 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205584 kb
Host smart-98b19996-b5bb-4ea2-85e3-049faabbb8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29235
3786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.292353786
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1505542777
Short name T433
Test name
Test status
Simulation time 10114345473 ps
CPU time 13.48 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205524 kb
Host smart-2fd889c0-b132-47fa-82ea-c60e82252c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
42777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1505542777
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.220604130
Short name T371
Test name
Test status
Simulation time 10046138580 ps
CPU time 16.32 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205548 kb
Host smart-e6fbe55d-de98-4f9d-95c9-22753de45756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
4130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.220604130
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3833838653
Short name T171
Test name
Test status
Simulation time 10066737343 ps
CPU time 13.93 seconds
Started May 30 03:45:17 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205552 kb
Host smart-00a9ba7d-d197-4538-bf25-fb902769c951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38338
38653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3833838653
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.107371337
Short name T1045
Test name
Test status
Simulation time 10140776561 ps
CPU time 14.31 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205496 kb
Host smart-6fc8b479-7454-42af-bce4-101a20fc7eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10737
1337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.107371337
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1064711469
Short name T1295
Test name
Test status
Simulation time 10056949414 ps
CPU time 13.88 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205564 kb
Host smart-3a776f01-664d-430a-a41d-b597c5cb3a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10647
11469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1064711469
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2611025328
Short name T1052
Test name
Test status
Simulation time 10066536060 ps
CPU time 14.32 seconds
Started May 30 03:45:20 PM PDT 24
Finished May 30 03:45:36 PM PDT 24
Peak memory 205504 kb
Host smart-241c01f4-bd27-4f42-8724-f996e9910cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26110
25328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2611025328
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3582003949
Short name T991
Test name
Test status
Simulation time 25537389250 ps
CPU time 50.89 seconds
Started May 30 03:45:13 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205612 kb
Host smart-0fae37da-f6fd-4b80-9a7c-23cc896f83ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35820
03949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3582003949
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3730227814
Short name T269
Test name
Test status
Simulation time 10058482242 ps
CPU time 14.73 seconds
Started May 30 03:45:17 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205528 kb
Host smart-dc1a753c-9041-47a6-981e-ffb9df13a03a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37302
27814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3730227814
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2393942347
Short name T1878
Test name
Test status
Simulation time 10117300042 ps
CPU time 13.04 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205568 kb
Host smart-0c82dc5e-e288-4d21-8190-2c91798c80fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23939
42347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2393942347
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_trans.2071138020
Short name T1545
Test name
Test status
Simulation time 10051760341 ps
CPU time 13.41 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:30 PM PDT 24
Peak memory 205600 kb
Host smart-bdede20c-4f7a-42d2-bd97-33faf3c68513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20711
38020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_trans.2071138020
Directory /workspace/23.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1559129208
Short name T1834
Test name
Test status
Simulation time 10079342492 ps
CPU time 14.4 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205500 kb
Host smart-f7240a88-e2db-48d0-8c91-aa84211d64d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15591
29208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1559129208
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3300764217
Short name T1194
Test name
Test status
Simulation time 10051120901 ps
CPU time 13.59 seconds
Started May 30 03:45:23 PM PDT 24
Finished May 30 03:45:38 PM PDT 24
Peak memory 205544 kb
Host smart-4849a390-5eee-433a-8ee3-42dd877cc18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33007
64217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3300764217
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1403009414
Short name T1500
Test name
Test status
Simulation time 10045630703 ps
CPU time 13.53 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205552 kb
Host smart-ba5b9d2d-7335-4724-b818-72f1692550e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14030
09414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1403009414
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2532972489
Short name T1511
Test name
Test status
Simulation time 10070693430 ps
CPU time 13.7 seconds
Started May 30 03:45:23 PM PDT 24
Finished May 30 03:45:38 PM PDT 24
Peak memory 205552 kb
Host smart-78014d03-f158-4ee2-a123-f30e10ea8d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
72489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2532972489
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1998003735
Short name T1124
Test name
Test status
Simulation time 10109257121 ps
CPU time 15.33 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205532 kb
Host smart-b07eb3ee-3ecb-48d7-988d-2e9ca4877eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19980
03735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1998003735
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.max_length_in_transaction.2111894996
Short name T801
Test name
Test status
Simulation time 10145846399 ps
CPU time 12.81 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205576 kb
Host smart-b53a7b76-25cd-44b5-84fb-25b7d7a83792
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2111894996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.max_length_in_transaction.2111894996
Directory /workspace/24.max_length_in_transaction/latest

Test location /workspace/coverage/default/24.min_length_in_transaction.301088693
Short name T1914
Test name
Test status
Simulation time 10066284392 ps
CPU time 15.31 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205552 kb
Host smart-35ac2d7d-d44f-420a-ac8f-b92e73f5e788
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=301088693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.min_length_in_transaction.301088693
Directory /workspace/24.min_length_in_transaction/latest

Test location /workspace/coverage/default/24.random_length_in_trans.397363111
Short name T1385
Test name
Test status
Simulation time 10165403280 ps
CPU time 13.51 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205600 kb
Host smart-621d318a-c678-4486-b5e9-b8d17314bf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
3111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.random_length_in_trans.397363111
Directory /workspace/24.random_length_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.3379473932
Short name T1090
Test name
Test status
Simulation time 13655097556 ps
CPU time 17.56 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205584 kb
Host smart-31efc8ef-1ff9-44b3-9f6a-489a2c34f2a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3379473932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.3379473932
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1686761495
Short name T890
Test name
Test status
Simulation time 13338444804 ps
CPU time 18.82 seconds
Started May 30 03:45:13 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205548 kb
Host smart-ceaf4ab0-c5cc-423f-b8a7-6fd72abe05b1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1686761495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1686761495
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3245483457
Short name T1301
Test name
Test status
Simulation time 13270655022 ps
CPU time 17.51 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205532 kb
Host smart-9176393d-f54e-4792-a017-48496c15615a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3245483457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3245483457
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2225029622
Short name T625
Test name
Test status
Simulation time 10107041639 ps
CPU time 13.12 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205544 kb
Host smart-c2b70001-0b63-44ee-9ffe-21380691662a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22250
29622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2225029622
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.366284061
Short name T1766
Test name
Test status
Simulation time 10101275779 ps
CPU time 15.15 seconds
Started May 30 03:45:20 PM PDT 24
Finished May 30 03:45:37 PM PDT 24
Peak memory 205620 kb
Host smart-9e3e0379-af9f-4de7-8dd3-9eb2afa04956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36628
4061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.366284061
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.254615241
Short name T1827
Test name
Test status
Simulation time 10965057235 ps
CPU time 17 seconds
Started May 30 03:45:20 PM PDT 24
Finished May 30 03:45:38 PM PDT 24
Peak memory 205604 kb
Host smart-577e2545-df73-432f-ad29-9c242def5eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25461
5241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.254615241
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3492509492
Short name T496
Test name
Test status
Simulation time 10045545745 ps
CPU time 14.81 seconds
Started May 30 03:45:17 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205520 kb
Host smart-a3c25f77-9dfe-439b-89d8-585089da8e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34925
09492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3492509492
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.254368140
Short name T415
Test name
Test status
Simulation time 10059794103 ps
CPU time 13.51 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205468 kb
Host smart-14f29570-9293-43b8-9d3e-56873c28f8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25436
8140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.254368140
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.856332009
Short name T757
Test name
Test status
Simulation time 10678086333 ps
CPU time 16.83 seconds
Started May 30 03:45:15 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205488 kb
Host smart-f5ebddba-5ca9-4101-b112-e7b7d6b9b4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85633
2009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.856332009
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.616784452
Short name T363
Test name
Test status
Simulation time 10156190067 ps
CPU time 15.74 seconds
Started May 30 03:45:21 PM PDT 24
Finished May 30 03:45:38 PM PDT 24
Peak memory 205496 kb
Host smart-8874446f-e02b-4205-8c3c-4ddb4a2dead4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61678
4452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.616784452
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.299638817
Short name T780
Test name
Test status
Simulation time 10061120403 ps
CPU time 13.46 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:43 PM PDT 24
Peak memory 205380 kb
Host smart-0cabfb0a-e371-424d-a035-26273da41b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29963
8817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.299638817
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.574652417
Short name T630
Test name
Test status
Simulation time 10043158842 ps
CPU time 14.28 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:43 PM PDT 24
Peak memory 205556 kb
Host smart-c34b227c-a937-4c2b-aa4f-5219ace9d5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57465
2417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.574652417
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1298811484
Short name T585
Test name
Test status
Simulation time 10128773896 ps
CPU time 13.98 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:31 PM PDT 24
Peak memory 205568 kb
Host smart-3bb05b12-6c76-41a8-857c-c604c741b5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12988
11484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1298811484
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3998809236
Short name T1497
Test name
Test status
Simulation time 10074406677 ps
CPU time 15.41 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:35 PM PDT 24
Peak memory 205568 kb
Host smart-6e612ac9-5818-4ced-b1ab-dc6fb0859e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39988
09236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3998809236
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1286016470
Short name T1771
Test name
Test status
Simulation time 13246267505 ps
CPU time 19.36 seconds
Started May 30 03:45:17 PM PDT 24
Finished May 30 03:45:39 PM PDT 24
Peak memory 205528 kb
Host smart-941900d7-5d05-437d-a9c4-e5b37533e441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12860
16470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1286016470
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1574594141
Short name T1433
Test name
Test status
Simulation time 10089168617 ps
CPU time 14.76 seconds
Started May 30 03:45:20 PM PDT 24
Finished May 30 03:45:36 PM PDT 24
Peak memory 205600 kb
Host smart-2e1fa39f-e81c-4e54-b0c5-a9887a3a02ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
94141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1574594141
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3982211410
Short name T1369
Test name
Test status
Simulation time 10067587095 ps
CPU time 15.42 seconds
Started May 30 03:45:21 PM PDT 24
Finished May 30 03:45:38 PM PDT 24
Peak memory 205528 kb
Host smart-33509cac-6c3a-4f71-aa3f-c6129ba28084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822
11410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3982211410
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3332713309
Short name T107
Test name
Test status
Simulation time 10085880628 ps
CPU time 14.83 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205544 kb
Host smart-dcbbca20-4360-49dd-94d0-abbbabf063ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33327
13309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3332713309
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.4044022444
Short name T1435
Test name
Test status
Simulation time 10136106546 ps
CPU time 13.92 seconds
Started May 30 03:45:22 PM PDT 24
Finished May 30 03:45:37 PM PDT 24
Peak memory 205516 kb
Host smart-b76ed257-b530-4e00-8f37-0a243a5c3a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
22444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.4044022444
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1833644769
Short name T883
Test name
Test status
Simulation time 10052131775 ps
CPU time 13.81 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205624 kb
Host smart-8ee3d287-93c8-4a1f-b9f0-b9537cd64f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
44769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1833644769
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1304920360
Short name T1343
Test name
Test status
Simulation time 10082991103 ps
CPU time 13.64 seconds
Started May 30 03:45:18 PM PDT 24
Finished May 30 03:45:34 PM PDT 24
Peak memory 205544 kb
Host smart-4e11f337-ab26-4717-9b81-22d2ced61925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
20360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1304920360
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1212086868
Short name T1507
Test name
Test status
Simulation time 10087763834 ps
CPU time 14.7 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205552 kb
Host smart-d3ae2f3d-56dc-4e9b-95cc-a2e7079d2b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120
86868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1212086868
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.4196238784
Short name T373
Test name
Test status
Simulation time 10056925919 ps
CPU time 13.42 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205504 kb
Host smart-a5278644-37b2-4b6e-979e-0bbc1d7633ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41962
38784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.4196238784
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.250923479
Short name T3
Test name
Test status
Simulation time 10060450552 ps
CPU time 14.15 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:41 PM PDT 24
Peak memory 205544 kb
Host smart-70dc1dea-1704-4840-8ef9-289375f36072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
3479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.250923479
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.657853492
Short name T1388
Test name
Test status
Simulation time 10030840630 ps
CPU time 14.24 seconds
Started May 30 03:45:31 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205524 kb
Host smart-dbb58ecc-a682-46dd-921c-56d68cddd59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65785
3492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.657853492
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3447944236
Short name T1537
Test name
Test status
Simulation time 20660918352 ps
CPU time 38.96 seconds
Started May 30 03:45:17 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205580 kb
Host smart-c7c987e2-a870-4452-8b8d-04d21c15d2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34479
44236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3447944236
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2978591881
Short name T1160
Test name
Test status
Simulation time 10074607259 ps
CPU time 13.71 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205628 kb
Host smart-d2f3f01b-19aa-4606-89ff-70bbf24372c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29785
91881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2978591881
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2393753195
Short name T1829
Test name
Test status
Simulation time 10060008223 ps
CPU time 13.89 seconds
Started May 30 03:45:23 PM PDT 24
Finished May 30 03:45:38 PM PDT 24
Peak memory 205572 kb
Host smart-1386e123-2f36-4411-91f7-27204219b4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23937
53195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2393753195
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_trans.1202206314
Short name T515
Test name
Test status
Simulation time 10129492337 ps
CPU time 14.28 seconds
Started May 30 03:45:21 PM PDT 24
Finished May 30 03:45:37 PM PDT 24
Peak memory 205584 kb
Host smart-3e20e540-09b9-433a-b45b-dd5fc755cd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12022
06314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_trans.1202206314
Directory /workspace/24.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3310728617
Short name T1330
Test name
Test status
Simulation time 10057246109 ps
CPU time 13.73 seconds
Started May 30 03:45:17 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205548 kb
Host smart-58153dc4-b4a8-4280-90f1-0d413dc22c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33107
28617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3310728617
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1506829291
Short name T1051
Test name
Test status
Simulation time 10064887155 ps
CPU time 14.81 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205520 kb
Host smart-c3bec695-a910-409c-8fac-801fee81f235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15068
29291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1506829291
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2149022829
Short name T447
Test name
Test status
Simulation time 10127300495 ps
CPU time 13.4 seconds
Started May 30 03:45:13 PM PDT 24
Finished May 30 03:45:28 PM PDT 24
Peak memory 205540 kb
Host smart-1eec7c87-16f3-4221-a8bc-14575371c4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21490
22829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2149022829
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1349877071
Short name T1598
Test name
Test status
Simulation time 10163812694 ps
CPU time 13.28 seconds
Started May 30 03:45:18 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205504 kb
Host smart-1cb61473-d264-423b-9713-5922a9189be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13498
77071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1349877071
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4193643711
Short name T1756
Test name
Test status
Simulation time 10095974624 ps
CPU time 13.31 seconds
Started May 30 03:45:16 PM PDT 24
Finished May 30 03:45:32 PM PDT 24
Peak memory 205588 kb
Host smart-bebf0632-0e3e-4cd2-9417-5015b4fef2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41936
43711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4193643711
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2767536096
Short name T378
Test name
Test status
Simulation time 10063746467 ps
CPU time 16.83 seconds
Started May 30 03:45:14 PM PDT 24
Finished May 30 03:45:33 PM PDT 24
Peak memory 205536 kb
Host smart-a9c424ee-377e-43c0-aec0-5e59b73fe717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
36096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2767536096
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.max_length_in_transaction.2068057593
Short name T1851
Test name
Test status
Simulation time 10165223737 ps
CPU time 14.71 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205560 kb
Host smart-3953569e-ba9c-40f4-a586-4c0e4657fe41
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2068057593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.max_length_in_transaction.2068057593
Directory /workspace/25.max_length_in_transaction/latest

Test location /workspace/coverage/default/25.min_length_in_transaction.1015818039
Short name T1786
Test name
Test status
Simulation time 10046235881 ps
CPU time 13.55 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205516 kb
Host smart-59e64e36-f05c-4623-a7d1-4fc1d81d7367
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1015818039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.min_length_in_transaction.1015818039
Directory /workspace/25.min_length_in_transaction/latest

Test location /workspace/coverage/default/25.random_length_in_trans.429234208
Short name T1782
Test name
Test status
Simulation time 10104664366 ps
CPU time 15.06 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205560 kb
Host smart-fe6dd8ad-99a6-4d07-9d61-b30b7017adac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
4208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.random_length_in_trans.429234208
Directory /workspace/25.random_length_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1239247487
Short name T1755
Test name
Test status
Simulation time 13589358104 ps
CPU time 17.35 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205548 kb
Host smart-17851f50-48e5-4a56-826f-76d975f2e92f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1239247487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.1239247487
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.712668360
Short name T8
Test name
Test status
Simulation time 13250420561 ps
CPU time 19.13 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205580 kb
Host smart-cd3c5d0f-3ca1-4dab-a5ae-d31e26a6b95d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=712668360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.712668360
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3430688525
Short name T949
Test name
Test status
Simulation time 13248785285 ps
CPU time 16.8 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205596 kb
Host smart-64bdafc2-de9d-4539-ac71-680183c36b39
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3430688525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.3430688525
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.218935093
Short name T411
Test name
Test status
Simulation time 10051843232 ps
CPU time 13.38 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:43 PM PDT 24
Peak memory 205564 kb
Host smart-4e30ae7d-1524-469b-9a07-c94148478880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21893
5093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.218935093
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.669259621
Short name T706
Test name
Test status
Simulation time 10151551921 ps
CPU time 13.4 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:42 PM PDT 24
Peak memory 205492 kb
Host smart-420b70a2-e5b9-4ccb-8258-0611377e7a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66925
9621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.669259621
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.105303747
Short name T655
Test name
Test status
Simulation time 10061646381 ps
CPU time 15.02 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205296 kb
Host smart-95b0006a-51c7-4226-958c-546bebd4f288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530
3747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.105303747
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.1087254193
Short name T1691
Test name
Test status
Simulation time 10049756942 ps
CPU time 14.63 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205632 kb
Host smart-5d50c3c1-c5d7-4b5e-9fc1-739d4c6021ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10872
54193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.1087254193
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3174090380
Short name T858
Test name
Test status
Simulation time 10914284245 ps
CPU time 14.85 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205552 kb
Host smart-205c3fd0-ab42-44ca-ab02-c602e065de5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31740
90380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3174090380
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1273707984
Short name T1387
Test name
Test status
Simulation time 10140286362 ps
CPU time 13.96 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205556 kb
Host smart-6cfe3b08-1bfd-4367-acf8-25190daed19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12737
07984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1273707984
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3662538084
Short name T834
Test name
Test status
Simulation time 10109455239 ps
CPU time 14.87 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205520 kb
Host smart-e38f531d-9f80-4189-84a6-3fdd6746d85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36625
38084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3662538084
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1991588991
Short name T1461
Test name
Test status
Simulation time 10041284619 ps
CPU time 13.97 seconds
Started May 30 03:45:31 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205540 kb
Host smart-552b65ae-0d85-4563-8915-b3aeeeee0d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915
88991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1991588991
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3766378127
Short name T1258
Test name
Test status
Simulation time 10127006924 ps
CPU time 16.95 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205548 kb
Host smart-73a5bcfd-a69a-4d61-858a-ef64ff1e7f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37663
78127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3766378127
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3712777228
Short name T414
Test name
Test status
Simulation time 10102140328 ps
CPU time 16.67 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:49 PM PDT 24
Peak memory 205520 kb
Host smart-10b612d3-29d3-4990-a78f-9cb3ae12f97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37127
77228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3712777228
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.530361684
Short name T1767
Test name
Test status
Simulation time 13225108431 ps
CPU time 16.4 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:49 PM PDT 24
Peak memory 205532 kb
Host smart-23ccd14f-0ac5-4cee-a949-fbcd1ff9a4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53036
1684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.530361684
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1419081029
Short name T1396
Test name
Test status
Simulation time 10157178123 ps
CPU time 13.78 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205532 kb
Host smart-c9fa6f00-2a77-47ad-8b32-9d4136ce20ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14190
81029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1419081029
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2417499457
Short name T286
Test name
Test status
Simulation time 10076310368 ps
CPU time 14.41 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205496 kb
Host smart-f3fd520c-e953-430d-92a1-70ee86a32b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24174
99457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2417499457
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1114053685
Short name T1495
Test name
Test status
Simulation time 10100582894 ps
CPU time 13.73 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:42 PM PDT 24
Peak memory 205564 kb
Host smart-4452e20a-053c-4a9d-a613-a438917a2f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11140
53685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1114053685
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2630734841
Short name T79
Test name
Test status
Simulation time 10116072187 ps
CPU time 17.15 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:51 PM PDT 24
Peak memory 205656 kb
Host smart-feabfc58-c576-4ac0-94b0-51232b95b2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307
34841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2630734841
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3681796685
Short name T1337
Test name
Test status
Simulation time 10069371446 ps
CPU time 13.91 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205604 kb
Host smart-40a6636b-f14a-4159-aa80-b0d70f3aba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36817
96685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3681796685
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3717531644
Short name T335
Test name
Test status
Simulation time 10061948521 ps
CPU time 12.99 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205504 kb
Host smart-c1e2f179-e849-400e-8050-067707eef593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37175
31644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3717531644
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.468860114
Short name T1884
Test name
Test status
Simulation time 10111042969 ps
CPU time 13.6 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205544 kb
Host smart-8b2d26a4-f250-4341-a598-3061c0c7ebe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46886
0114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.468860114
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.1855804748
Short name T85
Test name
Test status
Simulation time 10078658782 ps
CPU time 15.25 seconds
Started May 30 03:45:31 PM PDT 24
Finished May 30 03:45:49 PM PDT 24
Peak memory 205532 kb
Host smart-28c7af45-b8a3-48c8-ba4e-7c7b3b434cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18558
04748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.1855804748
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2072793324
Short name T1421
Test name
Test status
Simulation time 10045671645 ps
CPU time 14.4 seconds
Started May 30 03:45:31 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205496 kb
Host smart-6b87aa37-b152-4687-bf7b-b01f31f90d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20727
93324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2072793324
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2580806218
Short name T562
Test name
Test status
Simulation time 10034950869 ps
CPU time 13.41 seconds
Started May 30 03:45:26 PM PDT 24
Finished May 30 03:45:41 PM PDT 24
Peak memory 205536 kb
Host smart-e61b9dff-4c75-44c5-8ff9-154500d770c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25808
06218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2580806218
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1562371089
Short name T236
Test name
Test status
Simulation time 28517298506 ps
CPU time 54.29 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:46:26 PM PDT 24
Peak memory 205620 kb
Host smart-cd30377c-bc5f-481f-9fd6-f3fe8575e2d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15623
71089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1562371089
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1093355895
Short name T1269
Test name
Test status
Simulation time 10090680278 ps
CPU time 14.77 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205600 kb
Host smart-1e01f92b-691f-45a4-a1ab-68924c8999b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10933
55895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1093355895
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3021761277
Short name T480
Test name
Test status
Simulation time 10121697794 ps
CPU time 15.33 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:49 PM PDT 24
Peak memory 205656 kb
Host smart-ca435c50-1f53-46e5-8210-cd72112697c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30217
61277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3021761277
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_trans.1336356262
Short name T418
Test name
Test status
Simulation time 10073763705 ps
CPU time 13.32 seconds
Started May 30 03:45:25 PM PDT 24
Finished May 30 03:45:40 PM PDT 24
Peak memory 205572 kb
Host smart-87d0e2fc-f5e3-4ddb-b621-77aa8ce98808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
56262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_trans.1336356262
Directory /workspace/25.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3384860419
Short name T1151
Test name
Test status
Simulation time 10055527860 ps
CPU time 14.79 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:43 PM PDT 24
Peak memory 205520 kb
Host smart-86b85507-6a17-4a22-9201-6672e2127a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33848
60419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3384860419
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2121308450
Short name T1863
Test name
Test status
Simulation time 10080250770 ps
CPU time 14.45 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205552 kb
Host smart-8da69c73-d24b-4431-9478-784eec9b3c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
08450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2121308450
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3122394903
Short name T1108
Test name
Test status
Simulation time 10066295704 ps
CPU time 15.36 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205580 kb
Host smart-3482541d-316b-48eb-b777-b3e37594b215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31223
94903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3122394903
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.140599854
Short name T133
Test name
Test status
Simulation time 10116873356 ps
CPU time 12.73 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205572 kb
Host smart-6599fe95-aea7-402d-b086-4f6b6c735f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
9854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.140599854
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3065587492
Short name T304
Test name
Test status
Simulation time 10085005342 ps
CPU time 13.49 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205608 kb
Host smart-0053e6e8-a44a-4ba3-9fb8-03ae729d2b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
87492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3065587492
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.415288057
Short name T1374
Test name
Test status
Simulation time 10050383610 ps
CPU time 13.88 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205480 kb
Host smart-fb2e87eb-61d2-478a-b51d-b0af7a87dfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41528
8057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.415288057
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.max_length_in_transaction.1332537554
Short name T588
Test name
Test status
Simulation time 10152300581 ps
CPU time 13.79 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205536 kb
Host smart-71819d5e-39c6-456f-9928-461b3328cd97
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1332537554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.max_length_in_transaction.1332537554
Directory /workspace/26.max_length_in_transaction/latest

Test location /workspace/coverage/default/26.min_length_in_transaction.2416450221
Short name T1795
Test name
Test status
Simulation time 10109239852 ps
CPU time 15 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205540 kb
Host smart-558543a1-bbd2-4de5-a870-6a3388195712
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2416450221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.min_length_in_transaction.2416450221
Directory /workspace/26.min_length_in_transaction/latest

Test location /workspace/coverage/default/26.random_length_in_trans.92510157
Short name T882
Test name
Test status
Simulation time 10147488647 ps
CPU time 12.85 seconds
Started May 30 03:45:37 PM PDT 24
Finished May 30 03:45:53 PM PDT 24
Peak memory 205524 kb
Host smart-576cf16a-8116-44c5-b43e-b8834210475d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92510
157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.random_length_in_trans.92510157
Directory /workspace/26.random_length_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.664494706
Short name T365
Test name
Test status
Simulation time 13935976137 ps
CPU time 21.08 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:54 PM PDT 24
Peak memory 205620 kb
Host smart-dd1a0c2d-b96e-4fe5-bc92-584ed7dd6deb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=664494706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.664494706
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.49752217
Short name T1789
Test name
Test status
Simulation time 13280949552 ps
CPU time 18.59 seconds
Started May 30 03:45:32 PM PDT 24
Finished May 30 03:45:53 PM PDT 24
Peak memory 205584 kb
Host smart-03741f96-0a15-4cb5-b9cc-c85de401e4aa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=49752217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.49752217
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1507746876
Short name T1451
Test name
Test status
Simulation time 10052939894 ps
CPU time 14.99 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205488 kb
Host smart-46471643-ff1f-4fc4-b48f-efa625c86e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15077
46876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1507746876
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1219985159
Short name T170
Test name
Test status
Simulation time 11273031468 ps
CPU time 15.21 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205632 kb
Host smart-5212bc7a-a10e-4d91-9914-5ad2f22624b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12199
85159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1219985159
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2549681984
Short name T851
Test name
Test status
Simulation time 10082916995 ps
CPU time 14.32 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205540 kb
Host smart-e7beec17-ba8d-48f2-a94c-0b57d1762c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
81984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2549681984
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2143306774
Short name T963
Test name
Test status
Simulation time 10098784628 ps
CPU time 17.46 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:50 PM PDT 24
Peak memory 205604 kb
Host smart-f4e6ced2-cd8b-4b86-89ee-e9fc46eb3d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
06774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2143306774
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1939507095
Short name T1548
Test name
Test status
Simulation time 10656032911 ps
CPU time 15.67 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205160 kb
Host smart-de5d2f51-7e13-47fc-93fe-e25bc06eba2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19395
07095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1939507095
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1906852057
Short name T1042
Test name
Test status
Simulation time 10366298760 ps
CPU time 16.09 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205552 kb
Host smart-37440683-f094-4927-b312-6bb496e45562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19068
52057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1906852057
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1968988073
Short name T401
Test name
Test status
Simulation time 10120400784 ps
CPU time 13.62 seconds
Started May 30 03:45:43 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205524 kb
Host smart-737975d3-ee4d-4027-9126-0f9fbbec0e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19689
88073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1968988073
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.4225656084
Short name T1139
Test name
Test status
Simulation time 10075670282 ps
CPU time 16.23 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:46:02 PM PDT 24
Peak memory 205568 kb
Host smart-c4e7dcef-2582-4dc1-a58a-0edb97561c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256
56084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.4225656084
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3395553370
Short name T662
Test name
Test status
Simulation time 10121522837 ps
CPU time 13.89 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205520 kb
Host smart-80ff11c0-b315-4521-a384-406525944372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33955
53370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3395553370
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1237163036
Short name T1804
Test name
Test status
Simulation time 10068024358 ps
CPU time 13.16 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205108 kb
Host smart-ef692a55-5737-471e-845d-30f04d57ecb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12371
63036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1237163036
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.507069443
Short name T574
Test name
Test status
Simulation time 13232848038 ps
CPU time 17.92 seconds
Started May 30 03:45:32 PM PDT 24
Finished May 30 03:45:53 PM PDT 24
Peak memory 205552 kb
Host smart-d155f696-1af0-4885-bc8a-3a919e92199a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50706
9443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.507069443
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.593160906
Short name T1381
Test name
Test status
Simulation time 10146022663 ps
CPU time 16.15 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:49 PM PDT 24
Peak memory 205164 kb
Host smart-694ad0cf-3dd4-4975-9183-744dde3fedf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59316
0906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.593160906
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2476050029
Short name T346
Test name
Test status
Simulation time 10049886858 ps
CPU time 13.77 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205244 kb
Host smart-686503e9-9ec2-4fb4-bca3-973856bc8941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760
50029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2476050029
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.554681203
Short name T122
Test name
Test status
Simulation time 10072376656 ps
CPU time 14.47 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:47 PM PDT 24
Peak memory 205568 kb
Host smart-9c8ec59a-ecef-466d-b47d-9c3d8cb4e90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55468
1203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.554681203
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2813779002
Short name T385
Test name
Test status
Simulation time 10100834597 ps
CPU time 14.87 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205580 kb
Host smart-a3ba5371-ed28-471e-a636-b9ce2aca87a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28137
79002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2813779002
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2984913934
Short name T1906
Test name
Test status
Simulation time 10056245478 ps
CPU time 16.96 seconds
Started May 30 03:45:31 PM PDT 24
Finished May 30 03:45:52 PM PDT 24
Peak memory 205536 kb
Host smart-847bbfde-b2dd-40a8-948b-bd93eb3479dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29849
13934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2984913934
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2331621108
Short name T911
Test name
Test status
Simulation time 10079327821 ps
CPU time 13.85 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:45:46 PM PDT 24
Peak memory 205548 kb
Host smart-379003db-d750-4541-81f3-89dc92773342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23316
21108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2331621108
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.481633952
Short name T162
Test name
Test status
Simulation time 10073126285 ps
CPU time 15.43 seconds
Started May 30 03:45:36 PM PDT 24
Finished May 30 03:45:54 PM PDT 24
Peak memory 205580 kb
Host smart-75cc90d6-7c7e-48c1-a881-00b812545b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48163
3952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.481633952
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.3377684960
Short name T323
Test name
Test status
Simulation time 10053693566 ps
CPU time 14.81 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205588 kb
Host smart-2293aec7-13b1-4800-bf84-aaf18cf4e442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33776
84960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.3377684960
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.7577411
Short name T1626
Test name
Test status
Simulation time 10086366601 ps
CPU time 16.58 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:46:02 PM PDT 24
Peak memory 205460 kb
Host smart-cab6a165-67be-4d8b-ae04-762d419f58bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75774
11 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.7577411
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1471437931
Short name T884
Test name
Test status
Simulation time 10088066633 ps
CPU time 14.08 seconds
Started May 30 03:45:37 PM PDT 24
Finished May 30 03:45:54 PM PDT 24
Peak memory 205580 kb
Host smart-a4a9e5b2-e3d6-49bd-a516-5df3579cbab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
37931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1471437931
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3137236830
Short name T235
Test name
Test status
Simulation time 28563568714 ps
CPU time 59.47 seconds
Started May 30 03:45:29 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205584 kb
Host smart-12c38d5c-593a-4db6-82be-e5f3dd8d10ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31372
36830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3137236830
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3255619616
Short name T881
Test name
Test status
Simulation time 10071819689 ps
CPU time 14.05 seconds
Started May 30 03:45:30 PM PDT 24
Finished May 30 03:45:48 PM PDT 24
Peak memory 205548 kb
Host smart-e6c007c4-6a3d-48c8-b2b8-0e49da9da63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32556
19616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3255619616
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2635124592
Short name T1787
Test name
Test status
Simulation time 10093849832 ps
CPU time 13.51 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205552 kb
Host smart-b3da38ab-231e-4c1f-ac0a-5a373230ccae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26351
24592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2635124592
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_trans.393771517
Short name T1279
Test name
Test status
Simulation time 10065252872 ps
CPU time 13.03 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:44 PM PDT 24
Peak memory 205576 kb
Host smart-27472d1e-d288-4d11-b912-08b45e4986db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39377
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_trans.393771517
Directory /workspace/26.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3976215407
Short name T1670
Test name
Test status
Simulation time 10042861794 ps
CPU time 15.28 seconds
Started May 30 03:45:25 PM PDT 24
Finished May 30 03:45:42 PM PDT 24
Peak memory 205556 kb
Host smart-4e2cb69d-451a-4f1e-a59b-a2f0466453b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39762
15407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3976215407
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.470740392
Short name T136
Test name
Test status
Simulation time 10062760433 ps
CPU time 13.74 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:56 PM PDT 24
Peak memory 205564 kb
Host smart-2821d329-8953-4b2c-b820-ca2bd7e00513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47074
0392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.470740392
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1079105524
Short name T783
Test name
Test status
Simulation time 10056037552 ps
CPU time 13.13 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205572 kb
Host smart-b8029b91-3e38-4b85-ad82-a87f21da01e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10791
05524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1079105524
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3807765922
Short name T583
Test name
Test status
Simulation time 10090762177 ps
CPU time 13.8 seconds
Started May 30 03:45:27 PM PDT 24
Finished May 30 03:45:42 PM PDT 24
Peak memory 205568 kb
Host smart-fdd4840a-8ac5-4bf9-aeea-ae98fb3808c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38077
65922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3807765922
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1363037617
Short name T1106
Test name
Test status
Simulation time 10046320894 ps
CPU time 13.47 seconds
Started May 30 03:45:37 PM PDT 24
Finished May 30 03:45:54 PM PDT 24
Peak memory 205548 kb
Host smart-b71775c1-ffe1-47c6-8684-fc58ef506696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
37617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1363037617
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2786739221
Short name T1743
Test name
Test status
Simulation time 10103845069 ps
CPU time 13.98 seconds
Started May 30 03:45:28 PM PDT 24
Finished May 30 03:45:45 PM PDT 24
Peak memory 205540 kb
Host smart-021be68b-9784-4dd9-82ea-13599b98c7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
39221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2786739221
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.max_length_in_transaction.820452044
Short name T361
Test name
Test status
Simulation time 10140823982 ps
CPU time 13.91 seconds
Started May 30 03:45:37 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205524 kb
Host smart-85bb808d-7d29-4d3f-9a2f-3a31892d32c8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=820452044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.max_length_in_transaction.820452044
Directory /workspace/27.max_length_in_transaction/latest

Test location /workspace/coverage/default/27.min_length_in_transaction.2740154361
Short name T1819
Test name
Test status
Simulation time 10131662467 ps
CPU time 14.8 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205556 kb
Host smart-9164418a-5191-450f-a37b-a9d48384b0f8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2740154361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.min_length_in_transaction.2740154361
Directory /workspace/27.min_length_in_transaction/latest

Test location /workspace/coverage/default/27.random_length_in_trans.241077090
Short name T1339
Test name
Test status
Simulation time 10138158313 ps
CPU time 14.52 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205568 kb
Host smart-ad688306-65f2-49cd-ba4c-7df36e8189f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
7090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.random_length_in_trans.241077090
Directory /workspace/27.random_length_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3308965348
Short name T390
Test name
Test status
Simulation time 13398355639 ps
CPU time 16.49 seconds
Started May 30 03:45:37 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205536 kb
Host smart-87720954-b003-4854-bbf8-50b6c0fda89b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3308965348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3308965348
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.3436588284
Short name T1707
Test name
Test status
Simulation time 13265950706 ps
CPU time 17.03 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205624 kb
Host smart-29909f3d-91cd-464b-8b4a-c6f734d563be
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3436588284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.3436588284
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2444067341
Short name T45
Test name
Test status
Simulation time 13360668724 ps
CPU time 19.87 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:46:03 PM PDT 24
Peak memory 205588 kb
Host smart-5de80c40-5d28-4d18-ae7d-b857d220422d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2444067341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.2444067341
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.417218773
Short name T1239
Test name
Test status
Simulation time 10076488205 ps
CPU time 13.45 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205560 kb
Host smart-22c9b603-f447-4bbe-a6f2-b84c9a6303b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
8773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.417218773
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1707028580
Short name T807
Test name
Test status
Simulation time 10306996657 ps
CPU time 16.5 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:46:01 PM PDT 24
Peak memory 205624 kb
Host smart-5cfb8c9d-31a8-43e8-a476-bfd32d2bf872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17070
28580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1707028580
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2724521258
Short name T670
Test name
Test status
Simulation time 10082727394 ps
CPU time 14.11 seconds
Started May 30 03:45:45 PM PDT 24
Finished May 30 03:46:03 PM PDT 24
Peak memory 205240 kb
Host smart-d7e0efee-c884-4278-b1c9-9020d6b81b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
21258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2724521258
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3833680603
Short name T1522
Test name
Test status
Simulation time 10053075997 ps
CPU time 14.23 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205604 kb
Host smart-12b7e724-7c84-472f-bbb4-f53566df8c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38336
80603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3833680603
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.2987234238
Short name T1242
Test name
Test status
Simulation time 10822811939 ps
CPU time 17.82 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:46:02 PM PDT 24
Peak memory 205524 kb
Host smart-f7bbb766-1795-45cb-b336-2aacd46eced8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29872
34238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.2987234238
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3153043012
Short name T804
Test name
Test status
Simulation time 10067091062 ps
CPU time 17.23 seconds
Started May 30 03:45:35 PM PDT 24
Finished May 30 03:45:54 PM PDT 24
Peak memory 205488 kb
Host smart-41b4d705-fa9a-4d6b-b56e-90d245b6161c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31530
43012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3153043012
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2225757727
Short name T539
Test name
Test status
Simulation time 10084240841 ps
CPU time 13.98 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:56 PM PDT 24
Peak memory 205496 kb
Host smart-90a852d9-76f4-44ed-9aee-14dfc7bcf7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257
57727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2225757727
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2060502415
Short name T959
Test name
Test status
Simulation time 10040460815 ps
CPU time 14.02 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205492 kb
Host smart-9473f3e2-117b-43f5-9fc2-3d6cff90a1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20605
02415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2060502415
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2474337682
Short name T1830
Test name
Test status
Simulation time 10133600712 ps
CPU time 13.79 seconds
Started May 30 03:45:45 PM PDT 24
Finished May 30 03:46:03 PM PDT 24
Peak memory 205272 kb
Host smart-26e5388e-58a7-42b7-b638-85aa4ce0c999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
37682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2474337682
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1356305076
Short name T1380
Test name
Test status
Simulation time 10104336202 ps
CPU time 13.39 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:56 PM PDT 24
Peak memory 205556 kb
Host smart-5340b355-a034-49d5-aa19-d78994322bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13563
05076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1356305076
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.688380287
Short name T1893
Test name
Test status
Simulation time 13233686952 ps
CPU time 17.15 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205500 kb
Host smart-d684d245-3b03-45d1-aa6c-3868e558075f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68838
0287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.688380287
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1615965817
Short name T393
Test name
Test status
Simulation time 10130900972 ps
CPU time 14.08 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205568 kb
Host smart-7c2d14d3-8ec1-43bc-8e3e-ecf8a5574457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16159
65817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1615965817
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.509695605
Short name T1002
Test name
Test status
Simulation time 10082425928 ps
CPU time 14.49 seconds
Started May 30 03:45:36 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205568 kb
Host smart-830ffa39-b54a-432a-a5e6-527eda3ba21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50969
5605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.509695605
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3942590429
Short name T121
Test name
Test status
Simulation time 10111906799 ps
CPU time 14 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205520 kb
Host smart-a4666c1b-5d72-4fb6-9b86-47b538bf623a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39425
90429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3942590429
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.527165667
Short name T1549
Test name
Test status
Simulation time 10089683033 ps
CPU time 13.42 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205568 kb
Host smart-46c56ffb-c146-4dad-a6e3-b5a027cc83ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52716
5667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.527165667
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.288588802
Short name T230
Test name
Test status
Simulation time 10147389025 ps
CPU time 15.2 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205520 kb
Host smart-40ecf647-8183-42dc-923d-8e5ca379386d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
8802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.288588802
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2587646881
Short name T1493
Test name
Test status
Simulation time 10081812090 ps
CPU time 13.87 seconds
Started May 30 03:45:37 PM PDT 24
Finished May 30 03:45:54 PM PDT 24
Peak memory 205492 kb
Host smart-8878a2f5-b951-4217-8a7a-96803694ded0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25876
46881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2587646881
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3319816381
Short name T1655
Test name
Test status
Simulation time 10085203709 ps
CPU time 13.93 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:56 PM PDT 24
Peak memory 205580 kb
Host smart-0522f99d-4a70-4e88-bd34-0e945e3e9f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
16381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3319816381
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.3845469147
Short name T729
Test name
Test status
Simulation time 10075246163 ps
CPU time 15.58 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205520 kb
Host smart-40f568ff-fb6b-41b9-8fd2-152afcfc3cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38454
69147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.3845469147
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2563981612
Short name T712
Test name
Test status
Simulation time 10047739355 ps
CPU time 13.39 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205572 kb
Host smart-4386fdaa-9ccd-49f7-91de-aac803e82cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25639
81612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2563981612
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.106907846
Short name T1857
Test name
Test status
Simulation time 10069068480 ps
CPU time 13.04 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205456 kb
Host smart-82c4ff8f-53a2-4700-99cd-5b26cc485a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
7846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.106907846
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3155002850
Short name T1217
Test name
Test status
Simulation time 10091258662 ps
CPU time 13.69 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205560 kb
Host smart-b5268f68-c36e-4ed5-b2ad-9524f3159736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31550
02850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3155002850
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3544015201
Short name T318
Test name
Test status
Simulation time 10088314116 ps
CPU time 13.45 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205504 kb
Host smart-1345266a-f41c-4337-835f-4227beee1b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35440
15201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3544015201
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_trans.2197697862
Short name T849
Test name
Test status
Simulation time 10082816131 ps
CPU time 13.94 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205536 kb
Host smart-e260970b-b8d8-40b7-90dd-20bb1e98fb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
97862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_trans.2197697862
Directory /workspace/27.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3258914102
Short name T1428
Test name
Test status
Simulation time 10037728582 ps
CPU time 14.94 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205516 kb
Host smart-0dc58c30-1b3b-438a-92e3-eed38ed53a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
14102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3258914102
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2537153799
Short name T1858
Test name
Test status
Simulation time 10052149266 ps
CPU time 14.1 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205508 kb
Host smart-5d75988c-4bca-4723-bc59-06ef1a8fc7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25371
53799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2537153799
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3917409479
Short name T1141
Test name
Test status
Simulation time 10058166156 ps
CPU time 13.22 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205512 kb
Host smart-4beab29d-ba28-4c73-a60e-b79249e007fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39174
09479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3917409479
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.3315318579
Short name T1747
Test name
Test status
Simulation time 10155197732 ps
CPU time 14.44 seconds
Started May 30 03:45:36 PM PDT 24
Finished May 30 03:45:53 PM PDT 24
Peak memory 205548 kb
Host smart-d9189d74-c24b-4c60-841c-fd108ff53ceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33153
18579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.3315318579
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.4098545191
Short name T523
Test name
Test status
Simulation time 10083190015 ps
CPU time 16.26 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:46:01 PM PDT 24
Peak memory 205492 kb
Host smart-8d956a44-b82d-40e1-ad2f-b896669962ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
45191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.4098545191
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.969998500
Short name T1856
Test name
Test status
Simulation time 10085972369 ps
CPU time 13.16 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205604 kb
Host smart-ec8037bb-8e87-4293-8e4e-def01d8045a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96999
8500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.969998500
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.max_length_in_transaction.840457695
Short name T1036
Test name
Test status
Simulation time 10141376033 ps
CPU time 13.32 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205544 kb
Host smart-3b43401d-a04d-423b-8c78-5f710e6b81f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=840457695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.max_length_in_transaction.840457695
Directory /workspace/28.max_length_in_transaction/latest

Test location /workspace/coverage/default/28.min_length_in_transaction.2158252582
Short name T1085
Test name
Test status
Simulation time 10058623720 ps
CPU time 13.99 seconds
Started May 30 03:45:47 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205556 kb
Host smart-a9b4b377-9c62-42f8-876c-ef7063bf798f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2158252582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.min_length_in_transaction.2158252582
Directory /workspace/28.min_length_in_transaction/latest

Test location /workspace/coverage/default/28.random_length_in_trans.3162075897
Short name T866
Test name
Test status
Simulation time 10138207639 ps
CPU time 13.34 seconds
Started May 30 03:45:56 PM PDT 24
Finished May 30 03:46:14 PM PDT 24
Peak memory 205480 kb
Host smart-8da17e31-b423-4a79-8bf3-ade1894950dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
75897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.random_length_in_trans.3162075897
Directory /workspace/28.random_length_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1158930755
Short name T868
Test name
Test status
Simulation time 13676532827 ps
CPU time 18.96 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:46:02 PM PDT 24
Peak memory 205592 kb
Host smart-ddcb2c57-c1f2-4230-aa02-e567b0ce86d2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1158930755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1158930755
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.898925481
Short name T873
Test name
Test status
Simulation time 13261579780 ps
CPU time 17.17 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:46:01 PM PDT 24
Peak memory 205544 kb
Host smart-a7b889e7-62e0-4b5c-94eb-dc385786bd2c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=898925481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.898925481
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3681259961
Short name T449
Test name
Test status
Simulation time 13284715529 ps
CPU time 16.84 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205544 kb
Host smart-4dc0da05-766f-4c60-a28a-e44682a1234f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3681259961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3681259961
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3536592680
Short name T1191
Test name
Test status
Simulation time 10073370322 ps
CPU time 13.34 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205564 kb
Host smart-9e86df29-4cd3-4258-94e7-95e645f4238e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
92680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3536592680
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.660408759
Short name T1159
Test name
Test status
Simulation time 10066448578 ps
CPU time 13.7 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205520 kb
Host smart-12ac3f43-1f9b-4a2e-99d2-97156f3dee3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66040
8759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.660408759
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1446346507
Short name T966
Test name
Test status
Simulation time 10655015476 ps
CPU time 14.76 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205660 kb
Host smart-78614ebb-7ae7-4677-9f87-4217c112118b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14463
46507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1446346507
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3025105203
Short name T1273
Test name
Test status
Simulation time 10054445494 ps
CPU time 14.74 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205512 kb
Host smart-6bc6d92b-a2c5-4418-91ab-fc856a6c3da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251
05203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3025105203
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3204521255
Short name T1007
Test name
Test status
Simulation time 10054567910 ps
CPU time 14.5 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205700 kb
Host smart-94b8cb3f-cdfb-4211-92e4-c903bda25bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32045
21255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3204521255
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3048904639
Short name T614
Test name
Test status
Simulation time 10926478862 ps
CPU time 14.73 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205524 kb
Host smart-b5fce07b-7705-41b9-8422-34187407c6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30489
04639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3048904639
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3023113493
Short name T928
Test name
Test status
Simulation time 10055690877 ps
CPU time 13.28 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:55 PM PDT 24
Peak memory 205544 kb
Host smart-3fff8311-81cf-44c3-b15e-8e4471a1ad63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
13493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3023113493
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.851278566
Short name T1199
Test name
Test status
Simulation time 10103491158 ps
CPU time 12.78 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205520 kb
Host smart-e23649cc-fb42-4688-b0f1-df97d881ecc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85127
8566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.851278566
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.2034287850
Short name T1585
Test name
Test status
Simulation time 10048681708 ps
CPU time 13.38 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205536 kb
Host smart-dcbec174-69f1-43ab-9f8c-327beb0907f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
87850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.2034287850
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.588540232
Short name T1043
Test name
Test status
Simulation time 10074464013 ps
CPU time 13.58 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205508 kb
Host smart-e6d89663-c964-41bd-a607-d1d3321033f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58854
0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.588540232
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1773257812
Short name T777
Test name
Test status
Simulation time 10087082034 ps
CPU time 14.7 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205564 kb
Host smart-7b998cb6-6175-424c-b457-bb997023e3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17732
57812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1773257812
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3275016745
Short name T904
Test name
Test status
Simulation time 13158897434 ps
CPU time 16.86 seconds
Started May 30 03:45:43 PM PDT 24
Finished May 30 03:46:03 PM PDT 24
Peak memory 205524 kb
Host smart-fe484b66-461d-44d3-b390-9042b5f585cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32750
16745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3275016745
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2461323562
Short name T1631
Test name
Test status
Simulation time 10087706889 ps
CPU time 13 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205548 kb
Host smart-14877a5f-e687-48b5-9847-569e2424ddb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24613
23562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2461323562
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.122814292
Short name T945
Test name
Test status
Simulation time 10046338699 ps
CPU time 14.23 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205572 kb
Host smart-b101628e-82f9-4cac-ac39-b16ea2d0efeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
4292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.122814292
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1250531152
Short name T581
Test name
Test status
Simulation time 10109865184 ps
CPU time 14.25 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205544 kb
Host smart-a39d7281-1545-40bc-90ba-01a773f2f2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
31152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1250531152
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.4182957557
Short name T474
Test name
Test status
Simulation time 10082989270 ps
CPU time 13.57 seconds
Started May 30 03:45:45 PM PDT 24
Finished May 30 03:46:02 PM PDT 24
Peak memory 205568 kb
Host smart-19d86275-8401-42c1-b992-dceaa0962e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41829
57557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.4182957557
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1534968700
Short name T306
Test name
Test status
Simulation time 10054334054 ps
CPU time 13.55 seconds
Started May 30 03:45:45 PM PDT 24
Finished May 30 03:46:02 PM PDT 24
Peak memory 205540 kb
Host smart-6272b643-ef68-448f-b492-2dfeeaecef36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15349
68700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1534968700
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3270337783
Short name T1635
Test name
Test status
Simulation time 10113545010 ps
CPU time 13.01 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205540 kb
Host smart-6fa39c30-59ff-4ee9-a437-58461a0705de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32703
37783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3270337783
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.485654217
Short name T506
Test name
Test status
Simulation time 10096151093 ps
CPU time 13.65 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205544 kb
Host smart-e614951b-97c1-4eb1-8b22-c62fd98ac54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48565
4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.485654217
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3970443061
Short name T610
Test name
Test status
Simulation time 10043656096 ps
CPU time 14.01 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205544 kb
Host smart-8dd64ae5-831e-4461-b96c-461325b5d410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39704
43061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3970443061
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1042307788
Short name T1671
Test name
Test status
Simulation time 10043946279 ps
CPU time 15.04 seconds
Started May 30 03:45:45 PM PDT 24
Finished May 30 03:46:04 PM PDT 24
Peak memory 205560 kb
Host smart-cb941b7c-772f-4b3b-8ca5-16c53a1787ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10423
07788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1042307788
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1578128221
Short name T1026
Test name
Test status
Simulation time 22965848363 ps
CPU time 41.35 seconds
Started May 30 03:45:40 PM PDT 24
Finished May 30 03:46:25 PM PDT 24
Peak memory 205604 kb
Host smart-f46d6e39-226e-4b1e-a0f7-b97094bdcac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15781
28221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1578128221
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.3428648550
Short name T343
Test name
Test status
Simulation time 10063839454 ps
CPU time 13.52 seconds
Started May 30 03:45:43 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205524 kb
Host smart-2267fd8c-3493-4880-9c6e-2a71c72f390b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34286
48550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.3428648550
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.895353736
Short name T423
Test name
Test status
Simulation time 10103804797 ps
CPU time 13.16 seconds
Started May 30 03:45:42 PM PDT 24
Finished May 30 03:45:59 PM PDT 24
Peak memory 205532 kb
Host smart-45bc4be7-7aae-44f4-ad2d-18481f5e6365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89535
3736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.895353736
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_trans.1515746276
Short name T413
Test name
Test status
Simulation time 10072947535 ps
CPU time 13.44 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205572 kb
Host smart-8f7b4406-e2c0-4d2e-a50f-561521d0584b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15157
46276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_trans.1515746276
Directory /workspace/28.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3068550662
Short name T571
Test name
Test status
Simulation time 10045755146 ps
CPU time 16.83 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:46:00 PM PDT 24
Peak memory 205504 kb
Host smart-79157326-fd4d-437c-8eba-f096b858b7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685
50662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3068550662
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1752392784
Short name T1881
Test name
Test status
Simulation time 10064892854 ps
CPU time 12.84 seconds
Started May 30 03:45:41 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205572 kb
Host smart-f31ab672-ab7c-4bcc-af64-a3da62e50ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17523
92784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1752392784
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2880811181
Short name T76
Test name
Test status
Simulation time 10049681803 ps
CPU time 14.35 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:58 PM PDT 24
Peak memory 205552 kb
Host smart-b235301a-a3b6-495c-85d5-c1973028942d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28808
11181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2880811181
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3979236815
Short name T1535
Test name
Test status
Simulation time 10122534998 ps
CPU time 13.03 seconds
Started May 30 03:45:38 PM PDT 24
Finished May 30 03:45:56 PM PDT 24
Peak memory 205548 kb
Host smart-a46e9b90-5a0c-417c-b071-2223efc3c951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39792
36815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3979236815
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1790115325
Short name T547
Test name
Test status
Simulation time 10074996684 ps
CPU time 13.7 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205576 kb
Host smart-829c186e-48f3-400a-ba4b-24fbc9997524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17901
15325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1790115325
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2068788228
Short name T1001
Test name
Test status
Simulation time 10089637206 ps
CPU time 13.77 seconds
Started May 30 03:45:39 PM PDT 24
Finished May 30 03:45:57 PM PDT 24
Peak memory 205512 kb
Host smart-8e3732e1-4203-4991-be14-fba58b2f7fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20687
88228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2068788228
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.max_length_in_transaction.1950102377
Short name T1624
Test name
Test status
Simulation time 10144227277 ps
CPU time 14 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205560 kb
Host smart-6aed721c-85e3-4bcd-95d4-eb855d4642dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1950102377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.max_length_in_transaction.1950102377
Directory /workspace/29.max_length_in_transaction/latest

Test location /workspace/coverage/default/29.min_length_in_transaction.1970901545
Short name T784
Test name
Test status
Simulation time 10051020672 ps
CPU time 15.01 seconds
Started May 30 03:45:47 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205576 kb
Host smart-e5f60b8b-d166-4210-9e3b-7060f56a6fc4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1970901545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.min_length_in_transaction.1970901545
Directory /workspace/29.min_length_in_transaction/latest

Test location /workspace/coverage/default/29.random_length_in_trans.768257125
Short name T1737
Test name
Test status
Simulation time 10118051945 ps
CPU time 14.4 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205512 kb
Host smart-02eb2faf-626a-47d3-aa6a-565e92b9f00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76825
7125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.random_length_in_trans.768257125
Directory /workspace/29.random_length_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1623648496
Short name T383
Test name
Test status
Simulation time 13758469463 ps
CPU time 19.83 seconds
Started May 30 03:45:47 PM PDT 24
Finished May 30 03:46:11 PM PDT 24
Peak memory 205544 kb
Host smart-2a163baf-9a6f-4726-bbd1-cc4fbd1e1980
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1623648496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1623648496
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1698631964
Short name T828
Test name
Test status
Simulation time 13220884673 ps
CPU time 17.54 seconds
Started May 30 03:45:46 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205560 kb
Host smart-7b13030d-43ab-4a0c-b24b-cbfedf974f56
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1698631964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1698631964
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1644063488
Short name T1275
Test name
Test status
Simulation time 13258776371 ps
CPU time 16.75 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205568 kb
Host smart-c54e3191-f33e-4f97-aeae-0bfc6cdeb0d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1644063488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.1644063488
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.3339516717
Short name T1130
Test name
Test status
Simulation time 10060243134 ps
CPU time 13.83 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205460 kb
Host smart-3795d8c4-9e88-4de0-98f9-cfc57e722840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33395
16717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.3339516717
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2391689996
Short name T74
Test name
Test status
Simulation time 10099634620 ps
CPU time 14.43 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205520 kb
Host smart-4922b6be-6418-4571-868f-92819acdd4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23916
89996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2391689996
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.4166771630
Short name T1872
Test name
Test status
Simulation time 10244998275 ps
CPU time 15.21 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:09 PM PDT 24
Peak memory 205620 kb
Host smart-c4ba5ecb-6af0-40b3-b695-ba78646f349c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
71630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.4166771630
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.42992216
Short name T960
Test name
Test status
Simulation time 10070362944 ps
CPU time 13.13 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205572 kb
Host smart-354d9a86-9153-4b06-b031-e4b6438cf909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42992
216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.42992216
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2168699864
Short name T1427
Test name
Test status
Simulation time 10063465710 ps
CPU time 15.59 seconds
Started May 30 03:45:46 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205536 kb
Host smart-abccb48f-b77e-4911-ac8e-e41d9d1de7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21686
99864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2168699864
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3489376902
Short name T1158
Test name
Test status
Simulation time 10826493921 ps
CPU time 15.36 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205604 kb
Host smart-cdfe732a-ba3e-4825-8075-85712c07d7aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
76902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3489376902
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2702409551
Short name T772
Test name
Test status
Simulation time 10098027492 ps
CPU time 13.28 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205508 kb
Host smart-4678ae51-48ff-40b9-8d52-fd801b68f8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27024
09551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2702409551
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1577052652
Short name T1536
Test name
Test status
Simulation time 10074661075 ps
CPU time 14.43 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:09 PM PDT 24
Peak memory 205556 kb
Host smart-f6ba7db3-6f75-4d43-842d-e9643e61e36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15770
52652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1577052652
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3620144315
Short name T1687
Test name
Test status
Simulation time 10058813055 ps
CPU time 13.36 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205528 kb
Host smart-e396d62b-c7b2-4a54-8797-e30bacb0ee9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36201
44315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3620144315
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.393612807
Short name T1371
Test name
Test status
Simulation time 10144069622 ps
CPU time 13.11 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205520 kb
Host smart-716e5603-d497-4fb7-928c-5899697ae5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39361
2807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.393612807
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2597330535
Short name T525
Test name
Test status
Simulation time 10125441739 ps
CPU time 14.59 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205608 kb
Host smart-06b77331-31e0-4f8d-a2df-552a859aff54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973
30535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2597330535
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1302473392
Short name T1176
Test name
Test status
Simulation time 13220286138 ps
CPU time 16.28 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:09 PM PDT 24
Peak memory 205572 kb
Host smart-f3f88a07-0f35-4431-a2ee-93ae9a2427b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13024
73392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1302473392
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.4081727222
Short name T584
Test name
Test status
Simulation time 10107343039 ps
CPU time 13.95 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:09 PM PDT 24
Peak memory 205564 kb
Host smart-ad9f7fd4-4a91-41b2-b2a4-337a2cf12839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
27222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.4081727222
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2769580054
Short name T1379
Test name
Test status
Simulation time 10053383195 ps
CPU time 13.36 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205548 kb
Host smart-5ef0ac59-e1cc-41e3-abcd-bb9fb0ac0b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27695
80054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2769580054
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2484668538
Short name T305
Test name
Test status
Simulation time 10093308351 ps
CPU time 14.48 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205528 kb
Host smart-ebe58a3b-d0e2-47c6-976a-1c839bc6a660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24846
68538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2484668538
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3298229936
Short name T1706
Test name
Test status
Simulation time 10092717460 ps
CPU time 13.12 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205568 kb
Host smart-e187b882-3915-4c09-b0be-5041bded9620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
29936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3298229936
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3857424571
Short name T1049
Test name
Test status
Simulation time 10070378872 ps
CPU time 13.64 seconds
Started May 30 03:45:47 PM PDT 24
Finished May 30 03:46:04 PM PDT 24
Peak memory 205572 kb
Host smart-46700023-913f-4706-8903-7af72ace0514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38574
24571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3857424571
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2703384282
Short name T174
Test name
Test status
Simulation time 10067127568 ps
CPU time 12.9 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205560 kb
Host smart-bc4cc0ce-23c6-41c2-a9f6-fd2b935f2d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27033
84282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2703384282
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.3545333774
Short name T1204
Test name
Test status
Simulation time 10083788772 ps
CPU time 14.46 seconds
Started May 30 03:45:47 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205528 kb
Host smart-ad2b5118-3894-4f03-a56c-80557f8ea541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35453
33774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.3545333774
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3738420057
Short name T776
Test name
Test status
Simulation time 10041612976 ps
CPU time 14.32 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205504 kb
Host smart-84c8f7cc-8004-4373-81f0-6e5d95de98e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37384
20057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3738420057
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.402274541
Short name T1772
Test name
Test status
Simulation time 10059337518 ps
CPU time 13.8 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205356 kb
Host smart-774e533a-9d70-4954-8977-713ee4bf7ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40227
4541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.402274541
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1737158489
Short name T167
Test name
Test status
Simulation time 29941378284 ps
CPU time 54.74 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:48 PM PDT 24
Peak memory 205552 kb
Host smart-9aea40d0-5763-4ad0-97cd-9b36df56300b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17371
58489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1737158489
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1598215964
Short name T386
Test name
Test status
Simulation time 10081567471 ps
CPU time 14.37 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205496 kb
Host smart-9af84b11-80f2-4460-b686-05e317b22af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15982
15964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1598215964
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3153629251
Short name T922
Test name
Test status
Simulation time 10105594086 ps
CPU time 13.55 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205568 kb
Host smart-542863b6-47d6-480b-ba4d-9b8134fecb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
29251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3153629251
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_trans.2625374166
Short name T827
Test name
Test status
Simulation time 10071229608 ps
CPU time 14.96 seconds
Started May 30 03:45:46 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205508 kb
Host smart-8ff67678-d927-40bd-97cc-3e6936153a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253
74166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_trans.2625374166
Directory /workspace/29.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3161086289
Short name T758
Test name
Test status
Simulation time 10069336090 ps
CPU time 14.53 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205460 kb
Host smart-7d751639-255a-43de-98e9-4075b2c9a6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
86289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3161086289
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.922693279
Short name T456
Test name
Test status
Simulation time 10054598804 ps
CPU time 15.45 seconds
Started May 30 03:45:46 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205532 kb
Host smart-ec6bce43-1b6d-427a-b287-1ca7332ec9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92269
3279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.922693279
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1978971363
Short name T1405
Test name
Test status
Simulation time 10061884829 ps
CPU time 15.17 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205576 kb
Host smart-bcd9e9e5-22eb-4cbe-91ff-aca7af2f7726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19789
71363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1978971363
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.472898181
Short name T1541
Test name
Test status
Simulation time 10109353613 ps
CPU time 15.38 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205464 kb
Host smart-404d009a-db5b-416d-bd35-d3647a3d7add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47289
8181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.472898181
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3022031648
Short name T536
Test name
Test status
Simulation time 10108805325 ps
CPU time 12.99 seconds
Started May 30 03:45:47 PM PDT 24
Finished May 30 03:46:04 PM PDT 24
Peak memory 205588 kb
Host smart-f557a0a9-3ba7-4869-9be5-bf02649fc221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30220
31648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3022031648
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.903594242
Short name T1683
Test name
Test status
Simulation time 10096039056 ps
CPU time 13.97 seconds
Started May 30 03:45:48 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205524 kb
Host smart-c68c07de-00fe-4e8e-8f91-ecc6160603b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90359
4242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.903594242
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.max_length_in_transaction.980995828
Short name T1912
Test name
Test status
Simulation time 10142123392 ps
CPU time 14.08 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:43:00 PM PDT 24
Peak memory 205564 kb
Host smart-86e6d139-adb0-41fa-a078-87a0471ae1ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=980995828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.max_length_in_transaction.980995828
Directory /workspace/3.max_length_in_transaction/latest

Test location /workspace/coverage/default/3.min_length_in_transaction.3564262131
Short name T1762
Test name
Test status
Simulation time 10056850881 ps
CPU time 15.88 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205520 kb
Host smart-688658f3-4cdb-4115-a8a4-86e4c647870b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3564262131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.min_length_in_transaction.3564262131
Directory /workspace/3.min_length_in_transaction/latest

Test location /workspace/coverage/default/3.random_length_in_trans.2560836640
Short name T1516
Test name
Test status
Simulation time 10073902433 ps
CPU time 13.32 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205512 kb
Host smart-eed85f79-ec3d-4cfd-bba3-3d4275dc1d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
36640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.random_length_in_trans.2560836640
Directory /workspace/3.random_length_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3700384333
Short name T498
Test name
Test status
Simulation time 14184607232 ps
CPU time 17.93 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:43:01 PM PDT 24
Peak memory 205528 kb
Host smart-07620bf7-c858-4c11-a46e-c06215fafade
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3700384333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3700384333
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2197881389
Short name T1152
Test name
Test status
Simulation time 13241748677 ps
CPU time 21.58 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:43:03 PM PDT 24
Peak memory 205556 kb
Host smart-7aba4500-b512-4eb2-bd25-4c99d55eeae3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2197881389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2197881389
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2953645890
Short name T1652
Test name
Test status
Simulation time 10076686522 ps
CPU time 14.61 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205472 kb
Host smart-91ffcc16-097e-4a8f-9da9-dc4506129278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29536
45890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2953645890
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2750930828
Short name T1695
Test name
Test status
Simulation time 11008157707 ps
CPU time 14.38 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:56 PM PDT 24
Peak memory 205576 kb
Host smart-fcbbcab5-3b14-4e88-872d-b0bbd6635ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27509
30828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2750930828
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.838643564
Short name T1098
Test name
Test status
Simulation time 10040392584 ps
CPU time 16.76 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205508 kb
Host smart-0b53f4f8-1530-4d5d-9c91-ed15cc4d6d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83864
3564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.838643564
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.90015057
Short name T1524
Test name
Test status
Simulation time 10099954419 ps
CPU time 14.19 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205516 kb
Host smart-1c143b2b-bb35-4521-85e2-a184b7016de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90015
057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.90015057
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3945636209
Short name T1206
Test name
Test status
Simulation time 11007582481 ps
CPU time 14.82 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205588 kb
Host smart-1e6da2e3-5a79-4b26-b9b0-83611e6bec94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39456
36209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3945636209
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1779758718
Short name T500
Test name
Test status
Simulation time 10071420657 ps
CPU time 13.48 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:55 PM PDT 24
Peak memory 205596 kb
Host smart-783dce0d-183e-4260-8a5c-e39bd20f12d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
58718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1779758718
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1013357127
Short name T453
Test name
Test status
Simulation time 10161975763 ps
CPU time 13.57 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:56 PM PDT 24
Peak memory 205520 kb
Host smart-aa1ddd03-d40a-4fa4-892a-d499169fd39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10133
57127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1013357127
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2929864708
Short name T1854
Test name
Test status
Simulation time 10082089296 ps
CPU time 13.32 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:55 PM PDT 24
Peak memory 205572 kb
Host smart-6429ef7c-e45d-409c-98ef-2fc94dc50a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29298
64708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2929864708
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2713252064
Short name T944
Test name
Test status
Simulation time 10106453389 ps
CPU time 14.33 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205528 kb
Host smart-1b5f6b8e-857a-42c1-b9e8-54a1f3b8d516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
52064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2713252064
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1244274855
Short name T808
Test name
Test status
Simulation time 10055936800 ps
CPU time 15.45 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205564 kb
Host smart-8b68a080-87e0-43a1-97d3-104013cf383c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12442
74855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1244274855
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.263329970
Short name T407
Test name
Test status
Simulation time 13195895917 ps
CPU time 17.01 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205504 kb
Host smart-92f356d6-4a27-4ebd-ab8f-b32277926cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
9970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.263329970
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2761595415
Short name T1440
Test name
Test status
Simulation time 10094202667 ps
CPU time 13.21 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:54 PM PDT 24
Peak memory 205548 kb
Host smart-646c4820-44af-47b4-88c9-cf12af1b3ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27615
95415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2761595415
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.503746195
Short name T1660
Test name
Test status
Simulation time 10110468288 ps
CPU time 13.59 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205528 kb
Host smart-fc38b038-e6d1-41d5-b721-8b536a9eadac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50374
6195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.503746195
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.910813453
Short name T120
Test name
Test status
Simulation time 10147145532 ps
CPU time 13.2 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:56 PM PDT 24
Peak memory 205520 kb
Host smart-15cc3c24-9c09-474f-8e17-b373ebe05607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91081
3453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.910813453
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3796756169
Short name T1047
Test name
Test status
Simulation time 10105185162 ps
CPU time 16.76 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205572 kb
Host smart-dd76081e-b9a6-4989-ac8a-57dcb362114f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37967
56169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3796756169
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.364732915
Short name T1774
Test name
Test status
Simulation time 10079060550 ps
CPU time 13.12 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205208 kb
Host smart-7ae00880-ed07-441f-bf10-932aa23ad6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36473
2915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.364732915
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2450780569
Short name T1567
Test name
Test status
Simulation time 10096043855 ps
CPU time 14.31 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:56 PM PDT 24
Peak memory 205552 kb
Host smart-659a9158-df89-4c3c-a6a8-03f4101708b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24507
80569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2450780569
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.872198960
Short name T137
Test name
Test status
Simulation time 10088794765 ps
CPU time 13.31 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205552 kb
Host smart-fd32478e-71da-4823-abe5-f45628a017e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87219
8960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.872198960
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.544733438
Short name T1603
Test name
Test status
Simulation time 10079833007 ps
CPU time 13.92 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:56 PM PDT 24
Peak memory 205576 kb
Host smart-bbba83f5-ffc4-47c8-9300-9ed9c867f86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54473
3438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.544733438
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2507843512
Short name T1345
Test name
Test status
Simulation time 10044893285 ps
CPU time 15.21 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205572 kb
Host smart-34e37a2e-c60e-4e90-9b69-0308878f33ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25078
43512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2507843512
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3452569761
Short name T457
Test name
Test status
Simulation time 10059531509 ps
CPU time 14.71 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205592 kb
Host smart-5d914c27-1d8a-4299-86e6-81c921669b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34525
69761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3452569761
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2833102538
Short name T1513
Test name
Test status
Simulation time 30916333056 ps
CPU time 65.44 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205624 kb
Host smart-6ea1646a-db80-44b2-a066-fda9f726c5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28331
02538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2833102538
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2558581747
Short name T486
Test name
Test status
Simulation time 10092364196 ps
CPU time 13.68 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205524 kb
Host smart-736f7093-7ea2-49b1-86f9-992a6a2319d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25585
81747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2558581747
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.918751904
Short name T1710
Test name
Test status
Simulation time 10181509544 ps
CPU time 16 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:43:02 PM PDT 24
Peak memory 205048 kb
Host smart-d82a8a0d-8d09-49c6-871d-8d25a5661066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91875
1904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.918751904
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_trans.3196496652
Short name T1096
Test name
Test status
Simulation time 10084982857 ps
CPU time 16.42 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205528 kb
Host smart-452fe4fe-147d-4097-ba27-7e4d12c371fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964
96652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_trans.3196496652
Directory /workspace/3.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1018754138
Short name T228
Test name
Test status
Simulation time 10034485464 ps
CPU time 14.03 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:55 PM PDT 24
Peak memory 205528 kb
Host smart-5279bc05-24c8-41d1-9929-8b04218412fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
54138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1018754138
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.2211697609
Short name T207
Test name
Test status
Simulation time 1199623379 ps
CPU time 2.03 seconds
Started May 30 03:42:42 PM PDT 24
Finished May 30 03:42:47 PM PDT 24
Peak memory 222772 kb
Host smart-b050393a-9a55-4449-b9f8-02688058531b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2211697609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2211697609
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.358418899
Short name T1127
Test name
Test status
Simulation time 10057322811 ps
CPU time 12.81 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:55 PM PDT 24
Peak memory 205500 kb
Host smart-90fa9803-52a1-4c13-832d-21cb475e0328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35841
8899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.358418899
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3750254594
Short name T1664
Test name
Test status
Simulation time 10056012546 ps
CPU time 16.06 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:43:00 PM PDT 24
Peak memory 205528 kb
Host smart-7398ccf1-2e2a-442e-a0af-4cb408709f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
54594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3750254594
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.959515730
Short name T154
Test name
Test status
Simulation time 10165733791 ps
CPU time 13.34 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205556 kb
Host smart-24ef8ad6-1807-41ea-ba99-84756e743499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95951
5730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.959515730
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.999073472
Short name T360
Test name
Test status
Simulation time 10071814603 ps
CPU time 14.04 seconds
Started May 30 03:42:45 PM PDT 24
Finished May 30 03:43:01 PM PDT 24
Peak memory 205556 kb
Host smart-8688edad-3e7c-47ef-acbe-525edbde89f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99907
3472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.999073472
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.491422880
Short name T1734
Test name
Test status
Simulation time 10074644402 ps
CPU time 16.45 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205544 kb
Host smart-bf1a20ca-9132-424d-a3a4-a500b98fbbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49142
2880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.491422880
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.max_length_in_transaction.203352026
Short name T28
Test name
Test status
Simulation time 10162915644 ps
CPU time 14.57 seconds
Started May 30 03:45:57 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205620 kb
Host smart-aa982dc9-8707-4c74-a99c-930c239f4d3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=203352026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.max_length_in_transaction.203352026
Directory /workspace/30.max_length_in_transaction/latest

Test location /workspace/coverage/default/30.min_length_in_transaction.1378354784
Short name T1203
Test name
Test status
Simulation time 10063005395 ps
CPU time 13.93 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:18 PM PDT 24
Peak memory 205616 kb
Host smart-7cdd2685-c075-4e74-9426-dc1c46bd142d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1378354784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.min_length_in_transaction.1378354784
Directory /workspace/30.min_length_in_transaction/latest

Test location /workspace/coverage/default/30.random_length_in_trans.388075584
Short name T1178
Test name
Test status
Simulation time 10149471666 ps
CPU time 13.26 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:18 PM PDT 24
Peak memory 205540 kb
Host smart-64006f37-eea7-42d9-a45b-fabe4256b2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38807
5584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.random_length_in_trans.388075584
Directory /workspace/30.random_length_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3421630711
Short name T1081
Test name
Test status
Simulation time 13490692244 ps
CPU time 17.01 seconds
Started May 30 03:45:54 PM PDT 24
Finished May 30 03:46:14 PM PDT 24
Peak memory 205596 kb
Host smart-1987254a-6585-48b5-a6bc-d7cc8b060dd4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3421630711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3421630711
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.442200051
Short name T713
Test name
Test status
Simulation time 13249886868 ps
CPU time 17.43 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:11 PM PDT 24
Peak memory 205580 kb
Host smart-1afd9221-da9e-4cb7-b31b-7a8087192f24
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=442200051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.442200051
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.1285979335
Short name T775
Test name
Test status
Simulation time 13281041867 ps
CPU time 18.12 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:11 PM PDT 24
Peak memory 205528 kb
Host smart-daadc4d1-979e-425c-998a-fce35fb30bbc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1285979335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.1285979335
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3755850806
Short name T1712
Test name
Test status
Simulation time 10052761494 ps
CPU time 14.23 seconds
Started May 30 03:45:53 PM PDT 24
Finished May 30 03:46:10 PM PDT 24
Peak memory 205548 kb
Host smart-0e1bc691-477b-4b46-90dc-142eacd76b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37558
50806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3755850806
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3289906385
Short name T1584
Test name
Test status
Simulation time 10242626635 ps
CPU time 14.48 seconds
Started May 30 03:45:52 PM PDT 24
Finished May 30 03:46:10 PM PDT 24
Peak memory 205608 kb
Host smart-9c81a118-d7d6-44cc-bd90-e592b1ccb5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32899
06385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3289906385
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2049547233
Short name T794
Test name
Test status
Simulation time 10093950075 ps
CPU time 15.26 seconds
Started May 30 03:45:55 PM PDT 24
Finished May 30 03:46:15 PM PDT 24
Peak memory 205536 kb
Host smart-6b32b76a-ea1b-49cd-8155-f364e8ac826d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20495
47233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2049547233
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1147706655
Short name T675
Test name
Test status
Simulation time 10122002988 ps
CPU time 13.15 seconds
Started May 30 03:45:56 PM PDT 24
Finished May 30 03:46:14 PM PDT 24
Peak memory 205596 kb
Host smart-cd417b3f-d780-48ef-a2bd-42b7238f42e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
06655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1147706655
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2930492946
Short name T1885
Test name
Test status
Simulation time 10923192627 ps
CPU time 15.8 seconds
Started May 30 03:45:54 PM PDT 24
Finished May 30 03:46:13 PM PDT 24
Peak memory 205544 kb
Host smart-0bb94b82-8ab7-49a7-828a-e3f770a19fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304
92946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2930492946
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2813312529
Short name T84
Test name
Test status
Simulation time 10172817848 ps
CPU time 14.1 seconds
Started May 30 03:45:49 PM PDT 24
Finished May 30 03:46:07 PM PDT 24
Peak memory 205568 kb
Host smart-a684c9ff-bd97-433b-8f85-74ac64adb794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28133
12529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2813312529
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.2015756404
Short name T1476
Test name
Test status
Simulation time 10155531480 ps
CPU time 14.08 seconds
Started May 30 03:46:03 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205532 kb
Host smart-92374e05-5357-43e6-bf14-9ca3745df774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20157
56404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.2015756404
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.4209639219
Short name T1777
Test name
Test status
Simulation time 10055091775 ps
CPU time 13.89 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205564 kb
Host smart-63ebc78f-f140-4069-ac89-384360f26f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
39219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.4209639219
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1260506865
Short name T1486
Test name
Test status
Simulation time 10096681213 ps
CPU time 13.32 seconds
Started May 30 03:45:51 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205528 kb
Host smart-11606bc7-1b91-4789-a464-fa72455bd862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12605
06865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1260506865
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.469036117
Short name T431
Test name
Test status
Simulation time 10079978194 ps
CPU time 15.66 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:09 PM PDT 24
Peak memory 205564 kb
Host smart-4f6137f5-8597-43e6-a953-bcdd0e86b9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46903
6117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.469036117
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1427003362
Short name T1534
Test name
Test status
Simulation time 13275522741 ps
CPU time 16.52 seconds
Started May 30 03:45:56 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205512 kb
Host smart-b84804af-b039-4526-93a9-19b32a5e8442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14270
03362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1427003362
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3111884693
Short name T878
Test name
Test status
Simulation time 10087614250 ps
CPU time 13.32 seconds
Started May 30 03:45:56 PM PDT 24
Finished May 30 03:46:15 PM PDT 24
Peak memory 205520 kb
Host smart-8c56e9b4-840d-4df5-9323-b4e22b26c042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31118
84693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3111884693
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3031616741
Short name T743
Test name
Test status
Simulation time 10052295916 ps
CPU time 14.27 seconds
Started May 30 03:45:46 PM PDT 24
Finished May 30 03:46:05 PM PDT 24
Peak memory 205572 kb
Host smart-965503e0-77e6-4604-9c79-dbe37e62fb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30316
16741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3031616741
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.12242632
Short name T18
Test name
Test status
Simulation time 10104527097 ps
CPU time 16.35 seconds
Started May 30 03:45:52 PM PDT 24
Finished May 30 03:46:12 PM PDT 24
Peak memory 205540 kb
Host smart-1960a915-5e0e-4706-ac31-1d746088437a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12242
632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.12242632
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3968759446
Short name T1353
Test name
Test status
Simulation time 10114621530 ps
CPU time 13.18 seconds
Started May 30 03:45:55 PM PDT 24
Finished May 30 03:46:12 PM PDT 24
Peak memory 205588 kb
Host smart-fd8c8e93-ce56-4f67-9669-35a22ffdc65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
59446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3968759446
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1497020768
Short name T1314
Test name
Test status
Simulation time 10075455578 ps
CPU time 15.14 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205536 kb
Host smart-d8c8e342-bc05-42b5-b75c-7d20adeb1573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14970
20768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1497020768
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3740424025
Short name T1456
Test name
Test status
Simulation time 10080739713 ps
CPU time 12.78 seconds
Started May 30 03:45:52 PM PDT 24
Finished May 30 03:46:08 PM PDT 24
Peak memory 205576 kb
Host smart-71bef0cc-ec98-4018-ad68-42e64d7dd58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37404
24025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3740424025
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.1816560599
Short name T295
Test name
Test status
Simulation time 10064422297 ps
CPU time 15.11 seconds
Started May 30 03:46:04 PM PDT 24
Finished May 30 03:46:24 PM PDT 24
Peak memory 205560 kb
Host smart-49fb6b72-7084-4b57-bfcf-a82b42add9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18165
60599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.1816560599
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.458834114
Short name T34
Test name
Test status
Simulation time 10053781424 ps
CPU time 13.09 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205576 kb
Host smart-e6e094f7-6336-49d3-b7ba-d48a674f660a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45883
4114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.458834114
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.362507101
Short name T1218
Test name
Test status
Simulation time 10059289057 ps
CPU time 14.47 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:19 PM PDT 24
Peak memory 205488 kb
Host smart-4f1b6d79-57fb-45f3-8e7f-ec540d4827e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36250
7101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.362507101
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3522271502
Short name T1167
Test name
Test status
Simulation time 10081022048 ps
CPU time 12.89 seconds
Started May 30 03:45:53 PM PDT 24
Finished May 30 03:46:09 PM PDT 24
Peak memory 205496 kb
Host smart-5e03dd7f-33aa-414f-a9df-9fc02376d9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
71502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3522271502
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3814252745
Short name T803
Test name
Test status
Simulation time 10055442451 ps
CPU time 14.02 seconds
Started May 30 03:45:55 PM PDT 24
Finished May 30 03:46:13 PM PDT 24
Peak memory 205564 kb
Host smart-a8309fae-9952-469d-adda-bc2967061923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38142
52745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3814252745
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_trans.2122137403
Short name T1104
Test name
Test status
Simulation time 10076858702 ps
CPU time 15.22 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:19 PM PDT 24
Peak memory 205572 kb
Host smart-031c0784-ef7f-464a-9c65-6d354c26c1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21221
37403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_trans.2122137403
Directory /workspace/30.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3591724062
Short name T1084
Test name
Test status
Simulation time 10063890454 ps
CPU time 13.59 seconds
Started May 30 03:45:57 PM PDT 24
Finished May 30 03:46:16 PM PDT 24
Peak memory 205520 kb
Host smart-8cf78d9e-2879-4ea3-8c23-b375d7ee582c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
24062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3591724062
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.4149763313
Short name T1272
Test name
Test status
Simulation time 10064261337 ps
CPU time 16.88 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205552 kb
Host smart-ed6b538c-4f96-4b52-bf3e-da6f389f197f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41497
63313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.4149763313
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3184784593
Short name T872
Test name
Test status
Simulation time 10062533146 ps
CPU time 14.63 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205544 kb
Host smart-5fdb5693-5379-4c79-bc81-6ca730487b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31847
84593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3184784593
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.805539630
Short name T156
Test name
Test status
Simulation time 10118767314 ps
CPU time 13.12 seconds
Started May 30 03:45:50 PM PDT 24
Finished May 30 03:46:06 PM PDT 24
Peak memory 205544 kb
Host smart-960267cb-ffd9-41ee-b02c-e5b5ce97da30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80553
9630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.805539630
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3149104198
Short name T403
Test name
Test status
Simulation time 10088469599 ps
CPU time 17 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205508 kb
Host smart-69bc1da3-0216-4699-848d-ec7dbfe7e8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31491
04198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3149104198
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2015376935
Short name T568
Test name
Test status
Simulation time 10100152944 ps
CPU time 15.25 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205396 kb
Host smart-3849770a-eaa8-4e3e-aab0-4665d5eec5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
76935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2015376935
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.max_length_in_transaction.851933046
Short name T740
Test name
Test status
Simulation time 10141620836 ps
CPU time 14.37 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205456 kb
Host smart-ba2d5c86-58f3-45df-8e06-bebf750413cc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=851933046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.max_length_in_transaction.851933046
Directory /workspace/31.max_length_in_transaction/latest

Test location /workspace/coverage/default/31.min_length_in_transaction.2235948931
Short name T1909
Test name
Test status
Simulation time 10088921936 ps
CPU time 13.18 seconds
Started May 30 03:46:05 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205544 kb
Host smart-3b0dcd97-9104-4393-ad6a-ec89d697f1ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2235948931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.min_length_in_transaction.2235948931
Directory /workspace/31.min_length_in_transaction/latest

Test location /workspace/coverage/default/31.random_length_in_trans.2231480580
Short name T1499
Test name
Test status
Simulation time 10144806252 ps
CPU time 15.46 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:20 PM PDT 24
Peak memory 205540 kb
Host smart-15277ff8-9016-4e2d-9ade-dfac73b1a54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22314
80580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.random_length_in_trans.2231480580
Directory /workspace/31.random_length_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.865280558
Short name T428
Test name
Test status
Simulation time 13278058837 ps
CPU time 16.19 seconds
Started May 30 03:46:01 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205584 kb
Host smart-4ee7981f-edef-48c6-82f9-1e5f24bf0cd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=865280558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.865280558
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3927221196
Short name T1821
Test name
Test status
Simulation time 13210036053 ps
CPU time 19.01 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205564 kb
Host smart-33f9f90d-18e4-48b9-9bc0-f115a8a55320
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3927221196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3927221196
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2337272130
Short name T1918
Test name
Test status
Simulation time 10058200340 ps
CPU time 14.37 seconds
Started May 30 03:45:57 PM PDT 24
Finished May 30 03:46:16 PM PDT 24
Peak memory 205620 kb
Host smart-10b1878c-d3d0-4edf-9370-4e5939b6e4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23372
72130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2337272130
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2966455478
Short name T1347
Test name
Test status
Simulation time 10044382939 ps
CPU time 16.59 seconds
Started May 30 03:46:01 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205528 kb
Host smart-2561c617-f78d-42aa-98a9-b0df7d4ef47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29664
55478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2966455478
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3629627862
Short name T61
Test name
Test status
Simulation time 10537884235 ps
CPU time 15.03 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205560 kb
Host smart-fbb82c96-d46c-4de9-8a91-c03e952d94dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36296
27862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3629627862
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2832510992
Short name T1551
Test name
Test status
Simulation time 10094426662 ps
CPU time 13.74 seconds
Started May 30 03:45:57 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205536 kb
Host smart-ffb318f0-5e1f-4402-ae9c-4f21e7841845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28325
10992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2832510992
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2074442862
Short name T762
Test name
Test status
Simulation time 10071142849 ps
CPU time 13.6 seconds
Started May 30 03:46:00 PM PDT 24
Finished May 30 03:46:19 PM PDT 24
Peak memory 204840 kb
Host smart-ce4c884e-035c-4a0c-b0c7-c3b40a5f6d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20744
42862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2074442862
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.1470829171
Short name T521
Test name
Test status
Simulation time 10857104169 ps
CPU time 14.96 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:18 PM PDT 24
Peak memory 205572 kb
Host smart-f44077fe-8b39-49d2-b16c-5f8fb3280bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14708
29171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.1470829171
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2216193851
Short name T1900
Test name
Test status
Simulation time 10085154644 ps
CPU time 18.31 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205564 kb
Host smart-8c0580a4-294d-4df1-9a03-9550914fbbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22161
93851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2216193851
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.284835296
Short name T1324
Test name
Test status
Simulation time 10091030021 ps
CPU time 13.19 seconds
Started May 30 03:46:04 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205536 kb
Host smart-61854c9e-a766-4f71-8b86-86e27bf81978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28483
5296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.284835296
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.39823789
Short name T1837
Test name
Test status
Simulation time 10039540123 ps
CPU time 13.52 seconds
Started May 30 03:46:04 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205592 kb
Host smart-82f30137-9749-4788-a21e-34e0adc89a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39823
789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.39823789
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3068855608
Short name T394
Test name
Test status
Simulation time 10095964844 ps
CPU time 12.63 seconds
Started May 30 03:45:57 PM PDT 24
Finished May 30 03:46:15 PM PDT 24
Peak memory 205576 kb
Host smart-74fc566b-10ef-4c4a-8f60-39be9e7bded0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
55608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3068855608
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.355056644
Short name T367
Test name
Test status
Simulation time 10067058718 ps
CPU time 14.3 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:22 PM PDT 24
Peak memory 205548 kb
Host smart-08757ee4-2d99-4646-a805-bd923a13d77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
6644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.355056644
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.470491841
Short name T997
Test name
Test status
Simulation time 13224136336 ps
CPU time 16.17 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205560 kb
Host smart-a63be7d2-a331-412a-87d6-108b31ac6e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47049
1841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.470491841
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.4206201827
Short name T322
Test name
Test status
Simulation time 10111829080 ps
CPU time 14.54 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:19 PM PDT 24
Peak memory 205528 kb
Host smart-23c1aebb-bd43-4ddc-93f9-ec8b0f8b7e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42062
01827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.4206201827
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1631870714
Short name T1711
Test name
Test status
Simulation time 10134713237 ps
CPU time 16.1 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:19 PM PDT 24
Peak memory 205492 kb
Host smart-fdab9bbc-f441-476e-9b24-3dadfec77ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16318
70714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1631870714
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.4025910904
Short name T104
Test name
Test status
Simulation time 10075613258 ps
CPU time 16.76 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205496 kb
Host smart-6ab7dfa1-5ffa-4e78-b955-aa1d8d5b8367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40259
10904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.4025910904
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3053063242
Short name T530
Test name
Test status
Simulation time 10097070077 ps
CPU time 14.57 seconds
Started May 30 03:45:56 PM PDT 24
Finished May 30 03:46:16 PM PDT 24
Peak memory 205568 kb
Host smart-79257646-e985-44a8-ac67-f29b9ade339f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30530
63242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3053063242
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3574670914
Short name T80
Test name
Test status
Simulation time 10084424635 ps
CPU time 14.51 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205580 kb
Host smart-1ffd53ec-1c3f-4805-9ec6-62edda3c831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35746
70914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3574670914
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2996427547
Short name T339
Test name
Test status
Simulation time 10084731507 ps
CPU time 13.38 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:18 PM PDT 24
Peak memory 205524 kb
Host smart-5c089abe-05ef-4318-a586-32304987ea53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29964
27547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2996427547
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1553977843
Short name T169
Test name
Test status
Simulation time 10080981525 ps
CPU time 13.64 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205560 kb
Host smart-57f2b835-4cd3-4d8e-9b98-c2455eb8e8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15539
77843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1553977843
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.1096819823
Short name T649
Test name
Test status
Simulation time 10058410006 ps
CPU time 14.35 seconds
Started May 30 03:46:00 PM PDT 24
Finished May 30 03:46:20 PM PDT 24
Peak memory 205528 kb
Host smart-719c5089-f9b2-4684-ab8c-809d84c71096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
19823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.1096819823
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1625853678
Short name T640
Test name
Test status
Simulation time 10065296997 ps
CPU time 12.53 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:17 PM PDT 24
Peak memory 205576 kb
Host smart-c2849e6f-adb6-4403-b461-3018c5353ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16258
53678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1625853678
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.981747684
Short name T869
Test name
Test status
Simulation time 10031712168 ps
CPU time 13.55 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:18 PM PDT 24
Peak memory 205524 kb
Host smart-344c8110-32cc-4b0c-9cc7-be7c98e946c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98174
7684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.981747684
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1372882331
Short name T1533
Test name
Test status
Simulation time 27762591701 ps
CPU time 50.85 seconds
Started May 30 03:45:59 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205580 kb
Host smart-b5bab777-898d-4e09-a6e0-b06df66bb573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13728
82331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1372882331
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.162575606
Short name T549
Test name
Test status
Simulation time 10106756986 ps
CPU time 13.86 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205568 kb
Host smart-d3be241b-286b-4803-b26d-87d9f7342bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16257
5606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.162575606
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.824666188
Short name T860
Test name
Test status
Simulation time 10064100125 ps
CPU time 15.12 seconds
Started May 30 03:46:03 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205552 kb
Host smart-6652d219-b859-4f5b-96f4-098e4a8294c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82466
6188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.824666188
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_trans.3588402198
Short name T312
Test name
Test status
Simulation time 10071972011 ps
CPU time 13.99 seconds
Started May 30 03:46:03 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205568 kb
Host smart-46a15ec4-7ced-486c-b657-eef5c978cfbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35884
02198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_trans.3588402198
Directory /workspace/31.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2764098771
Short name T986
Test name
Test status
Simulation time 10059381010 ps
CPU time 15.37 seconds
Started May 30 03:46:00 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 204740 kb
Host smart-900c2958-84a3-443d-a507-604199b89e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27640
98771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2764098771
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1950967744
Short name T1438
Test name
Test status
Simulation time 10158511903 ps
CPU time 14.51 seconds
Started May 30 03:46:01 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205536 kb
Host smart-a655e61a-5e97-46c5-bc5b-71e24aa65c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
67744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1950967744
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4241628845
Short name T1596
Test name
Test status
Simulation time 10094471572 ps
CPU time 14.61 seconds
Started May 30 03:46:04 PM PDT 24
Finished May 30 03:46:24 PM PDT 24
Peak memory 205552 kb
Host smart-97584125-0d5e-4281-98f3-2e341f7555ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42416
28845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4241628845
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.118931526
Short name T1826
Test name
Test status
Simulation time 10113853562 ps
CPU time 15.16 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:23 PM PDT 24
Peak memory 205568 kb
Host smart-4af04531-3208-431d-935d-3f134c78197a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11893
1526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.118931526
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.734106202
Short name T990
Test name
Test status
Simulation time 10115629763 ps
CPU time 17.31 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205508 kb
Host smart-3d420e92-0acf-4bf4-8da5-a1a38b291015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73410
6202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.734106202
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1381277429
Short name T677
Test name
Test status
Simulation time 10054609233 ps
CPU time 13.71 seconds
Started May 30 03:46:01 PM PDT 24
Finished May 30 03:46:20 PM PDT 24
Peak memory 205560 kb
Host smart-e2ca5347-cc83-4b55-b618-d86e6d4a1b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13812
77429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1381277429
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.max_length_in_transaction.3706443518
Short name T1836
Test name
Test status
Simulation time 10151652869 ps
CPU time 15.72 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205596 kb
Host smart-5f07ca49-655e-40c4-92ab-82aa91b99742
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3706443518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.max_length_in_transaction.3706443518
Directory /workspace/32.max_length_in_transaction/latest

Test location /workspace/coverage/default/32.min_length_in_transaction.1139860339
Short name T836
Test name
Test status
Simulation time 10067180258 ps
CPU time 13.25 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205528 kb
Host smart-05fec652-1041-49ef-9f45-6a88a03f08a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1139860339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.min_length_in_transaction.1139860339
Directory /workspace/32.min_length_in_transaction/latest

Test location /workspace/coverage/default/32.random_length_in_trans.1076054205
Short name T716
Test name
Test status
Simulation time 10149081723 ps
CPU time 14.76 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205524 kb
Host smart-3ad89d53-ba05-4d06-87b7-f3e8b37909c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10760
54205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.random_length_in_trans.1076054205
Directory /workspace/32.random_length_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.371714376
Short name T1692
Test name
Test status
Simulation time 13896660951 ps
CPU time 17.76 seconds
Started May 30 03:45:58 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205600 kb
Host smart-ec9abe7a-5a63-4d9f-b1cf-ed2ed0331571
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=371714376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.371714376
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.599564568
Short name T1181
Test name
Test status
Simulation time 13307939298 ps
CPU time 19.18 seconds
Started May 30 03:46:00 PM PDT 24
Finished May 30 03:46:25 PM PDT 24
Peak memory 205560 kb
Host smart-2deff82f-10c0-44a1-a4d9-9d3e495fcda3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=599564568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.599564568
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1107692794
Short name T1188
Test name
Test status
Simulation time 13232716889 ps
CPU time 18.74 seconds
Started May 30 03:46:05 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205592 kb
Host smart-75a24f7b-0d3f-4099-bf42-801862d700de
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1107692794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.1107692794
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.1246818656
Short name T1525
Test name
Test status
Simulation time 10051323241 ps
CPU time 13.19 seconds
Started May 30 03:46:02 PM PDT 24
Finished May 30 03:46:21 PM PDT 24
Peak memory 205520 kb
Host smart-16feb97f-05dc-4c94-91ec-848426c19991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12468
18656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.1246818656
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.435959242
Short name T1197
Test name
Test status
Simulation time 10061401229 ps
CPU time 15.74 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:31 PM PDT 24
Peak memory 205508 kb
Host smart-a8fc4930-f4b4-47c5-a39a-9902779f24c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43595
9242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.435959242
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1552340003
Short name T1844
Test name
Test status
Simulation time 10903733242 ps
CPU time 16.94 seconds
Started May 30 03:46:13 PM PDT 24
Finished May 30 03:46:33 PM PDT 24
Peak memory 205612 kb
Host smart-b6a3455e-6a1a-4677-9b41-b98f019de6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
40003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1552340003
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.511848962
Short name T1931
Test name
Test status
Simulation time 10055776513 ps
CPU time 13.3 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205464 kb
Host smart-f9166719-f615-4284-820f-1e66378ebc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51184
8962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.511848962
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.470387930
Short name T602
Test name
Test status
Simulation time 10052713345 ps
CPU time 17.07 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:33 PM PDT 24
Peak memory 205484 kb
Host smart-c6eba99d-3838-4ec6-a8f4-c4c1a48fe580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47038
7930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.470387930
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.727297043
Short name T1133
Test name
Test status
Simulation time 10735620475 ps
CPU time 13.69 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205548 kb
Host smart-5efb35e8-2a93-4575-b6a1-6e3e588db4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72729
7043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.727297043
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1081952144
Short name T1186
Test name
Test status
Simulation time 10174576794 ps
CPU time 16.75 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:31 PM PDT 24
Peak memory 205568 kb
Host smart-68863a71-77c2-4cac-8210-14d18847f0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
52144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1081952144
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1042303285
Short name T686
Test name
Test status
Simulation time 10070692250 ps
CPU time 14.53 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:31 PM PDT 24
Peak memory 205460 kb
Host smart-e4125a7a-2d85-4dde-8d95-ced5934a8747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10423
03285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1042303285
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3292614637
Short name T1475
Test name
Test status
Simulation time 10041811609 ps
CPU time 14.54 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205512 kb
Host smart-4e369376-231c-47c9-b535-54884c7367ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32926
14637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3292614637
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.880365422
Short name T1135
Test name
Test status
Simulation time 10138092730 ps
CPU time 13.97 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205512 kb
Host smart-babf8cc4-0c33-4b72-b864-f85510aac91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88036
5422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.880365422
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2128215007
Short name T435
Test name
Test status
Simulation time 10091417095 ps
CPU time 13.25 seconds
Started May 30 03:46:14 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205568 kb
Host smart-06659cf6-e674-4eae-a8b9-cfe688768643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21282
15007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2128215007
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1442447370
Short name T822
Test name
Test status
Simulation time 13175248157 ps
CPU time 17.32 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205540 kb
Host smart-c981301e-ace3-464d-8cc8-427ecea3f1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
47370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1442447370
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3345548305
Short name T1409
Test name
Test status
Simulation time 10135913030 ps
CPU time 13.61 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205528 kb
Host smart-1a80268d-76db-4632-9237-892503d85739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33455
48305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3345548305
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3298191279
Short name T1155
Test name
Test status
Simulation time 10068048460 ps
CPU time 17.02 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205532 kb
Host smart-f6c42c97-3701-4313-aad6-698f57b329ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32981
91279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3298191279
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1558672095
Short name T99
Test name
Test status
Simulation time 10079088978 ps
CPU time 12.92 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205544 kb
Host smart-208cac8a-f6da-4658-b7e5-8d628389f031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15586
72095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1558672095
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2970733833
Short name T1926
Test name
Test status
Simulation time 10107424479 ps
CPU time 14.82 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205588 kb
Host smart-91b9e68f-d385-4992-88d5-bea8dc651533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29707
33833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2970733833
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3745904305
Short name T1211
Test name
Test status
Simulation time 10055898091 ps
CPU time 13.63 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:26 PM PDT 24
Peak memory 205524 kb
Host smart-5440f39a-8de1-40a0-8a0d-5e41554ea9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
04305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3745904305
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.177717076
Short name T70
Test name
Test status
Simulation time 10076673176 ps
CPU time 13.59 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205612 kb
Host smart-c3a956e1-abfb-4a83-8e36-c7e459756802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
7076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.177717076
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3429387560
Short name T166
Test name
Test status
Simulation time 10077558945 ps
CPU time 13.73 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205572 kb
Host smart-b3996e49-0ede-4328-b4bc-e194375cf110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34293
87560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3429387560
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.3942452423
Short name T1468
Test name
Test status
Simulation time 10065498180 ps
CPU time 13.72 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:26 PM PDT 24
Peak memory 205544 kb
Host smart-32d0277f-3aa8-4b3b-b6ef-9f94a195c6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
52423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.3942452423
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2260264888
Short name T1375
Test name
Test status
Simulation time 10044706093 ps
CPU time 13.77 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205516 kb
Host smart-c41e930e-f122-46c7-ae86-f636b81ba044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22602
64888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2260264888
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3771408100
Short name T1563
Test name
Test status
Simulation time 10036662374 ps
CPU time 13.12 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205532 kb
Host smart-731e90f5-6b7f-4058-8775-7f8749a746cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
08100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3771408100
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1835862034
Short name T1759
Test name
Test status
Simulation time 30859352494 ps
CPU time 62.19 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205588 kb
Host smart-fb20bfb8-8cee-4e80-843d-6e6e8e09f71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358
62034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1835862034
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1586121012
Short name T1157
Test name
Test status
Simulation time 10055103407 ps
CPU time 15.31 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205540 kb
Host smart-587f0577-074b-4054-ae23-e69605f895f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
21012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1586121012
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.789922346
Short name T1207
Test name
Test status
Simulation time 10077855509 ps
CPU time 13.97 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205564 kb
Host smart-7c3dc9f1-91fa-4ee6-8533-b59cff6f95c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78992
2346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.789922346
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_trans.2837491342
Short name T1182
Test name
Test status
Simulation time 10067071185 ps
CPU time 13.76 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205548 kb
Host smart-d2c96f22-279b-4963-bc01-b3251f9e1b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374
91342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_trans.2837491342
Directory /workspace/32.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3852527111
Short name T1058
Test name
Test status
Simulation time 10031357882 ps
CPU time 14.94 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205520 kb
Host smart-7c1b5ed4-2f42-4f77-8d14-272a765372d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
27111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3852527111
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.4077834399
Short name T1908
Test name
Test status
Simulation time 10058274129 ps
CPU time 14.97 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205560 kb
Host smart-8d733cc7-cffb-494c-b0c8-811f836f8ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40778
34399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.4077834399
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1317360919
Short name T1600
Test name
Test status
Simulation time 10051467457 ps
CPU time 16.13 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205504 kb
Host smart-dba0840e-f12d-4390-bb8c-f6f41e258e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13173
60919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1317360919
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.1598868184
Short name T455
Test name
Test status
Simulation time 10115233656 ps
CPU time 13.75 seconds
Started May 30 03:46:00 PM PDT 24
Finished May 30 03:46:19 PM PDT 24
Peak memory 205560 kb
Host smart-ff21ed0d-76af-439a-ab7d-57c1fc91f656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15988
68184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.1598868184
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1697191840
Short name T1464
Test name
Test status
Simulation time 10071499460 ps
CPU time 13.65 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205536 kb
Host smart-cfc47630-0ced-43c5-94b2-d8ca77b014a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16971
91840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1697191840
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.2103968061
Short name T338
Test name
Test status
Simulation time 10065683096 ps
CPU time 13.55 seconds
Started May 30 03:46:13 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205524 kb
Host smart-0bd41bcd-f06c-42d7-9d80-a46e82a2140e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
68061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2103968061
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.max_length_in_transaction.3518336766
Short name T1193
Test name
Test status
Simulation time 10157579257 ps
CPU time 14.94 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205608 kb
Host smart-c91474ad-e727-4074-804a-c263bc74b564
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3518336766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.max_length_in_transaction.3518336766
Directory /workspace/33.max_length_in_transaction/latest

Test location /workspace/coverage/default/33.min_length_in_transaction.208680200
Short name T404
Test name
Test status
Simulation time 10060631735 ps
CPU time 15.58 seconds
Started May 30 03:46:20 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205568 kb
Host smart-a785daf4-6d9e-4e10-ae2f-2b7c356cda78
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=208680200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.min_length_in_transaction.208680200
Directory /workspace/33.min_length_in_transaction/latest

Test location /workspace/coverage/default/33.random_length_in_trans.2505046938
Short name T1562
Test name
Test status
Simulation time 10073227788 ps
CPU time 13.05 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205572 kb
Host smart-51f26490-e53e-4df8-8cca-1ac98f11a779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25050
46938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.random_length_in_trans.2505046938
Directory /workspace/33.random_length_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1194637626
Short name T1594
Test name
Test status
Simulation time 13203184902 ps
CPU time 16.95 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205524 kb
Host smart-4903439b-002f-45e0-a995-17016635ce19
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1194637626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1194637626
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1526087136
Short name T464
Test name
Test status
Simulation time 13304515739 ps
CPU time 16.56 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205556 kb
Host smart-f86f640d-803a-4018-8f59-e156632fc634
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1526087136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1526087136
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1872845187
Short name T1508
Test name
Test status
Simulation time 10101115805 ps
CPU time 13.2 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205544 kb
Host smart-ffc3a489-cc47-4c5e-aa85-5b9fa0ab7956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
45187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1872845187
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.1699066777
Short name T1888
Test name
Test status
Simulation time 10903360684 ps
CPU time 16.06 seconds
Started May 30 03:46:08 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205704 kb
Host smart-4961fb72-08be-4a83-a1f7-61231a6ff2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16990
66777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1699066777
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.4258526062
Short name T1057
Test name
Test status
Simulation time 10037586533 ps
CPU time 13.6 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205624 kb
Host smart-a59a5dab-53e1-4095-977a-a59c6f6addfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42585
26062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.4258526062
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3459187556
Short name T1611
Test name
Test status
Simulation time 10089884125 ps
CPU time 15.96 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:32 PM PDT 24
Peak memory 205536 kb
Host smart-78a538b3-aa7f-4f5f-a87f-1483b9b1a2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34591
87556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3459187556
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.505502282
Short name T1686
Test name
Test status
Simulation time 10920740245 ps
CPU time 15.03 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:30 PM PDT 24
Peak memory 205544 kb
Host smart-fcb2ca8a-0949-46cb-95cd-c0da1704bfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50550
2282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.505502282
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1672178479
Short name T814
Test name
Test status
Simulation time 10058178662 ps
CPU time 14.56 seconds
Started May 30 03:46:12 PM PDT 24
Finished May 30 03:46:31 PM PDT 24
Peak memory 205596 kb
Host smart-9a349100-4b41-44f1-a2a9-7bf861cb62e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16721
78479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1672178479
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2940936542
Short name T1693
Test name
Test status
Simulation time 10108494294 ps
CPU time 14.37 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205572 kb
Host smart-45d14548-4a25-4722-a7ab-73ff4d84c254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
36542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2940936542
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.916260404
Short name T899
Test name
Test status
Simulation time 10050683203 ps
CPU time 13.1 seconds
Started May 30 03:46:26 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205552 kb
Host smart-ef39179a-c348-4add-83fe-ce6d122ceb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91626
0404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.916260404
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2122775973
Short name T1336
Test name
Test status
Simulation time 10074905536 ps
CPU time 13.91 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205512 kb
Host smart-e58335f5-f6d7-4aa6-95a6-f71270c58765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
75973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2122775973
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2921162883
Short name T1602
Test name
Test status
Simulation time 10071092077 ps
CPU time 12.96 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205552 kb
Host smart-cee6409b-6135-4a28-8c5d-d2ffb1a2e68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29211
62883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2921162883
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.166930413
Short name T1243
Test name
Test status
Simulation time 13236655068 ps
CPU time 17.44 seconds
Started May 30 03:46:13 PM PDT 24
Finished May 30 03:46:34 PM PDT 24
Peak memory 205548 kb
Host smart-fc7099c9-0d2d-4632-8a87-287c4106bb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16693
0413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.166930413
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.4006853098
Short name T374
Test name
Test status
Simulation time 10137800320 ps
CPU time 17.02 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:31 PM PDT 24
Peak memory 205528 kb
Host smart-8f91166b-ce15-4f1b-a9b3-34a6e26141f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40068
53098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.4006853098
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.1827023471
Short name T907
Test name
Test status
Simulation time 10046872009 ps
CPU time 12.8 seconds
Started May 30 03:46:10 PM PDT 24
Finished May 30 03:46:27 PM PDT 24
Peak memory 205512 kb
Host smart-08866b55-4850-45e0-8f2b-d42e28ab5129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18270
23471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1827023471
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.3501749272
Short name T1429
Test name
Test status
Simulation time 10103857315 ps
CPU time 13.12 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205560 kb
Host smart-d22ccb11-eb57-498f-9a2d-68e16f8a3907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35017
49272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.3501749272
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2626702764
Short name T78
Test name
Test status
Simulation time 10102355766 ps
CPU time 14.69 seconds
Started May 30 03:46:09 PM PDT 24
Finished May 30 03:46:28 PM PDT 24
Peak memory 205592 kb
Host smart-ab983dda-e7af-4885-a1c3-f1957825bd77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
02764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2626702764
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.190185744
Short name T1891
Test name
Test status
Simulation time 10065923013 ps
CPU time 14.37 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205552 kb
Host smart-402fa41f-a9ac-4b18-b2d4-1ccaa96a1dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19018
5744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.190185744
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1654496653
Short name T748
Test name
Test status
Simulation time 10088091005 ps
CPU time 13.48 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205548 kb
Host smart-6542b2cc-3479-4c12-8f65-6ea68cb0e2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16544
96653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1654496653
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.4205110615
Short name T186
Test name
Test status
Simulation time 10087468403 ps
CPU time 14.58 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205540 kb
Host smart-9810d38b-c8d9-4b60-abde-b12c3fdd3e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
10615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.4205110615
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.535601584
Short name T927
Test name
Test status
Simulation time 10065251558 ps
CPU time 13.92 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205504 kb
Host smart-7c17edf0-6c81-4323-9a32-dc8891dfe733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53560
1584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.535601584
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.348641952
Short name T587
Test name
Test status
Simulation time 10056724413 ps
CPU time 12.79 seconds
Started May 30 03:46:27 PM PDT 24
Finished May 30 03:46:43 PM PDT 24
Peak memory 205564 kb
Host smart-d1788de2-87f8-49d6-b35d-3f23c95e0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34864
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.348641952
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.847221247
Short name T1753
Test name
Test status
Simulation time 10048973844 ps
CPU time 15.17 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205540 kb
Host smart-dd3dee83-7987-47d7-8fd8-8442e748f9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84722
1247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.847221247
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3182608010
Short name T1164
Test name
Test status
Simulation time 16621923658 ps
CPU time 28.14 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:53 PM PDT 24
Peak memory 205584 kb
Host smart-d8edc8ac-3c5f-4b4d-b43c-007c6721e3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826
08010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3182608010
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.4065945240
Short name T681
Test name
Test status
Simulation time 10145593926 ps
CPU time 13.79 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205596 kb
Host smart-0cea7ff9-3ec1-4e10-81c6-ff67c25c2ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40659
45240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.4065945240
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3925389362
Short name T1422
Test name
Test status
Simulation time 10131177066 ps
CPU time 13.52 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205508 kb
Host smart-52aa662c-a757-41cf-85f4-49af97d5faae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39253
89362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3925389362
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_trans.2950285331
Short name T1278
Test name
Test status
Simulation time 10068509601 ps
CPU time 13.59 seconds
Started May 30 03:46:18 PM PDT 24
Finished May 30 03:46:34 PM PDT 24
Peak memory 205572 kb
Host smart-bd2693ad-ab6b-4eeb-98d0-c932c6c4f1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29502
85331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_trans.2950285331
Directory /workspace/33.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2985978724
Short name T939
Test name
Test status
Simulation time 10048828490 ps
CPU time 12.62 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205524 kb
Host smart-25636ab7-24ae-4df2-8fdb-7edd12377eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29859
78724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2985978724
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3071873895
Short name T1890
Test name
Test status
Simulation time 10049420813 ps
CPU time 13.98 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205532 kb
Host smart-10305df2-ab7c-4203-8512-a0b8f2dc515e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30718
73895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3071873895
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2079705010
Short name T1022
Test name
Test status
Simulation time 10085784342 ps
CPU time 13.39 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205568 kb
Host smart-93169235-ff35-4780-866f-ed49a7afc4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
05010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2079705010
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1406264636
Short name T1355
Test name
Test status
Simulation time 10095980243 ps
CPU time 14.58 seconds
Started May 30 03:46:11 PM PDT 24
Finished May 30 03:46:29 PM PDT 24
Peak memory 205552 kb
Host smart-66d40a59-789b-4a35-a3e3-b86cdfe11a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14062
64636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1406264636
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2938047351
Short name T291
Test name
Test status
Simulation time 10092818508 ps
CPU time 13.31 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205532 kb
Host smart-6e61e9e9-fbf0-4b29-a394-ba4248198fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29380
47351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2938047351
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3821817721
Short name T303
Test name
Test status
Simulation time 10081884728 ps
CPU time 13.05 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205516 kb
Host smart-452b1863-bfcf-4c59-86f3-dce6a1fa1142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38218
17721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3821817721
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.max_length_in_transaction.2936152735
Short name T17
Test name
Test status
Simulation time 10173493826 ps
CPU time 14.62 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205380 kb
Host smart-aeb9398f-da60-4be1-b942-a7f9dd6b97ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2936152735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.max_length_in_transaction.2936152735
Directory /workspace/34.max_length_in_transaction/latest

Test location /workspace/coverage/default/34.min_length_in_transaction.3221367251
Short name T1021
Test name
Test status
Simulation time 10055129930 ps
CPU time 15.67 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205592 kb
Host smart-6e7dc5ba-b29c-4039-bad1-8e41848a3d84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3221367251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.min_length_in_transaction.3221367251
Directory /workspace/34.min_length_in_transaction/latest

Test location /workspace/coverage/default/34.random_length_in_trans.1597141722
Short name T429
Test name
Test status
Simulation time 10148230996 ps
CPU time 15.44 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205100 kb
Host smart-ccbab82b-446d-49ad-8c1f-bb84b3c3d205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15971
41722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.random_length_in_trans.1597141722
Directory /workspace/34.random_length_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1305735030
Short name T337
Test name
Test status
Simulation time 13739975734 ps
CPU time 18.45 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:43 PM PDT 24
Peak memory 205556 kb
Host smart-a8f0f784-1a96-403d-8bed-d12ac7e3b64b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1305735030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1305735030
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.1095191095
Short name T190
Test name
Test status
Simulation time 13282895607 ps
CPU time 16.34 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205508 kb
Host smart-c3bccffb-7c33-412c-a82d-3ad6f1bad41f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1095191095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.1095191095
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.808294838
Short name T1192
Test name
Test status
Simulation time 13263893974 ps
CPU time 17.14 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205580 kb
Host smart-c8de1763-28ef-43a5-8e59-97e790b41c7d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=808294838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.808294838
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2274886704
Short name T1280
Test name
Test status
Simulation time 10058861191 ps
CPU time 16.1 seconds
Started May 30 03:46:20 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205560 kb
Host smart-5059d098-44b8-4921-bcf8-b52a354a73ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22748
86704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2274886704
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.656287122
Short name T725
Test name
Test status
Simulation time 10535452700 ps
CPU time 14.66 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205572 kb
Host smart-27f71d3d-84aa-45e9-9b82-cd03d1cd5405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65628
7122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.656287122
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.846659226
Short name T871
Test name
Test status
Simulation time 10068549083 ps
CPU time 16.72 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:45 PM PDT 24
Peak memory 205532 kb
Host smart-748f6461-6cc7-4109-b950-88e440a534ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84665
9226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.846659226
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2427544909
Short name T1420
Test name
Test status
Simulation time 10058150317 ps
CPU time 15.48 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205092 kb
Host smart-4b4630a9-6be6-4d4e-8158-28beb0274e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
44909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2427544909
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2593193520
Short name T475
Test name
Test status
Simulation time 10779259916 ps
CPU time 15.2 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205592 kb
Host smart-f386cabf-a14a-41e9-927b-213077078895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25931
93520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2593193520
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2799294250
Short name T532
Test name
Test status
Simulation time 10101084204 ps
CPU time 14.47 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205536 kb
Host smart-108f84d2-6746-430d-bfb6-181a7f35f51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27992
94250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2799294250
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.142530102
Short name T27
Test name
Test status
Simulation time 10129035048 ps
CPU time 13.66 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205296 kb
Host smart-e3252db7-5b61-42f3-9a11-276027fe58e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14253
0102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.142530102
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1984256
Short name T1032
Test name
Test status
Simulation time 10050219803 ps
CPU time 15.27 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205496 kb
Host smart-71deaa18-0746-4610-bbac-0c0b97c9453a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19842
56 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1984256
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1995370908
Short name T702
Test name
Test status
Simulation time 10088345381 ps
CPU time 13.27 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205588 kb
Host smart-02179da7-c76f-40e2-8cec-a491ced845c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19953
70908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1995370908
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3260796879
Short name T1325
Test name
Test status
Simulation time 10160812894 ps
CPU time 14.43 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205224 kb
Host smart-3fb136fa-bf99-4e27-9005-364adbdbf7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32607
96879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3260796879
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1045798926
Short name T1060
Test name
Test status
Simulation time 13269973574 ps
CPU time 20.08 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:47 PM PDT 24
Peak memory 205528 kb
Host smart-2c3c3081-2e68-4731-9c82-fbf4ba600bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
98926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1045798926
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2249055859
Short name T1166
Test name
Test status
Simulation time 10102566540 ps
CPU time 13.34 seconds
Started May 30 03:46:20 PM PDT 24
Finished May 30 03:46:36 PM PDT 24
Peak memory 205548 kb
Host smart-1527f901-9b29-43b2-9921-eb59e914012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
55859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2249055859
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.466762957
Short name T528
Test name
Test status
Simulation time 10044520506 ps
CPU time 13.81 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205532 kb
Host smart-247262ce-5444-4b87-91af-be379042718f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46676
2957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.466762957
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.2501384794
Short name T109
Test name
Test status
Simulation time 10132303055 ps
CPU time 14.31 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205548 kb
Host smart-b4bbb6b5-f798-4e6c-bade-3f862e884ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
84794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2501384794
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.276159216
Short name T1568
Test name
Test status
Simulation time 10131484021 ps
CPU time 13.56 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205572 kb
Host smart-439df31b-146e-424a-bc58-bcff14068014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27615
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.276159216
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2889601408
Short name T1063
Test name
Test status
Simulation time 10083028220 ps
CPU time 15.79 seconds
Started May 30 03:46:27 PM PDT 24
Finished May 30 03:46:45 PM PDT 24
Peak memory 205576 kb
Host smart-7cb996c4-de1d-4714-9d8e-9149d9b47fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28896
01408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2889601408
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.701814158
Short name T1150
Test name
Test status
Simulation time 10088266472 ps
CPU time 12.9 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205540 kb
Host smart-14492001-6b5c-4422-a6a1-d1c88defdeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70181
4158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.701814158
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3189340978
Short name T149
Test name
Test status
Simulation time 10084812134 ps
CPU time 14.31 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205604 kb
Host smart-e351b8bc-ffb7-4323-ad61-7926f6752adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31893
40978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3189340978
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.1143134889
Short name T996
Test name
Test status
Simulation time 10084122418 ps
CPU time 13.48 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:38 PM PDT 24
Peak memory 205532 kb
Host smart-62860d97-689f-456a-8f1c-04a8be40e3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11431
34889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.1143134889
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3132148691
Short name T437
Test name
Test status
Simulation time 10116934129 ps
CPU time 14.92 seconds
Started May 30 03:46:22 PM PDT 24
Finished May 30 03:46:39 PM PDT 24
Peak memory 205544 kb
Host smart-b435f7bd-a905-40c2-b158-f4c971e48302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31321
48691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3132148691
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3336972317
Short name T693
Test name
Test status
Simulation time 10071075574 ps
CPU time 15.12 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205320 kb
Host smart-52268777-4974-4642-964a-a951f0b83317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33369
72317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3336972317
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.634084114
Short name T791
Test name
Test status
Simulation time 29859188358 ps
CPU time 63.28 seconds
Started May 30 03:46:20 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205624 kb
Host smart-e438feae-7f07-4013-82a9-80e951fb4c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63408
4114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.634084114
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3261949673
Short name T1526
Test name
Test status
Simulation time 10091857815 ps
CPU time 13.92 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205572 kb
Host smart-790c91b6-3b41-4c66-8e3f-d6f78d980dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32619
49673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3261949673
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3938807116
Short name T1730
Test name
Test status
Simulation time 10076584858 ps
CPU time 16.21 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:40 PM PDT 24
Peak memory 205584 kb
Host smart-bf097a36-2c0d-4817-b1ac-8b6d42cc6bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39388
07116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3938807116
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_trans.2224714289
Short name T1841
Test name
Test status
Simulation time 10134541992 ps
CPU time 15.37 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205576 kb
Host smart-fe7dfb73-fb3f-4b5e-bfd4-79921bc5ab91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22247
14289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_trans.2224714289
Directory /workspace/34.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1767271489
Short name T1363
Test name
Test status
Simulation time 10057914421 ps
CPU time 13.33 seconds
Started May 30 03:46:27 PM PDT 24
Finished May 30 03:46:43 PM PDT 24
Peak memory 205524 kb
Host smart-766dc5a8-6526-4202-802e-f057c93f80ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17672
71489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1767271489
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1165547054
Short name T1454
Test name
Test status
Simulation time 10057005103 ps
CPU time 13.23 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205508 kb
Host smart-aaa2da61-4937-4418-a407-4acc152d35c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
47054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1165547054
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.3095684363
Short name T380
Test name
Test status
Simulation time 10055779157 ps
CPU time 13.8 seconds
Started May 30 03:46:20 PM PDT 24
Finished May 30 03:46:36 PM PDT 24
Peak memory 205524 kb
Host smart-fed38711-1b9d-42c2-a9bd-9ae91dfa6f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
84363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.3095684363
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2773396387
Short name T724
Test name
Test status
Simulation time 10074164474 ps
CPU time 13.37 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205544 kb
Host smart-aebf7f21-6e7f-4bbf-8f18-385457131d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27733
96387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2773396387
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1567600368
Short name T1792
Test name
Test status
Simulation time 10055423628 ps
CPU time 13.23 seconds
Started May 30 03:46:21 PM PDT 24
Finished May 30 03:46:37 PM PDT 24
Peak memory 205572 kb
Host smart-2fc5d9de-a36b-4df3-8189-9db2e5d0cecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15676
00368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1567600368
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.823956062
Short name T368
Test name
Test status
Simulation time 10083564394 ps
CPU time 12.98 seconds
Started May 30 03:46:27 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205592 kb
Host smart-93c20bda-b334-4649-a981-4fc2cd32002b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82395
6062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.823956062
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.max_length_in_transaction.2983876850
Short name T362
Test name
Test status
Simulation time 10143181749 ps
CPU time 14.03 seconds
Started May 30 03:46:36 PM PDT 24
Finished May 30 03:46:56 PM PDT 24
Peak memory 205540 kb
Host smart-c8cebfb8-c260-477b-b861-ba94ad9b1f3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2983876850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.max_length_in_transaction.2983876850
Directory /workspace/35.max_length_in_transaction/latest

Test location /workspace/coverage/default/35.min_length_in_transaction.143066904
Short name T1070
Test name
Test status
Simulation time 10074671679 ps
CPU time 15 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205524 kb
Host smart-88b74fde-1601-4368-b944-e2865eeb6671
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=143066904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.min_length_in_transaction.143066904
Directory /workspace/35.min_length_in_transaction/latest

Test location /workspace/coverage/default/35.random_length_in_trans.3621915016
Short name T1041
Test name
Test status
Simulation time 10105466092 ps
CPU time 13.54 seconds
Started May 30 03:46:30 PM PDT 24
Finished May 30 03:46:46 PM PDT 24
Peak memory 205560 kb
Host smart-8ce19a82-02fe-4bb5-bb0d-656e597f4c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36219
15016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.random_length_in_trans.3621915016
Directory /workspace/35.random_length_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.603027008
Short name T1145
Test name
Test status
Simulation time 14314932509 ps
CPU time 19.51 seconds
Started May 30 03:46:23 PM PDT 24
Finished May 30 03:46:45 PM PDT 24
Peak memory 205540 kb
Host smart-5df25d6a-7ca2-4ffe-af3d-dce4ad471c1d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=603027008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.603027008
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.915048127
Short name T226
Test name
Test status
Simulation time 13294311490 ps
CPU time 17.46 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:45 PM PDT 24
Peak memory 205580 kb
Host smart-2bd52b89-4372-4460-8333-ce862b4689a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=915048127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.915048127
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.546721925
Short name T1504
Test name
Test status
Simulation time 10097357737 ps
CPU time 13.95 seconds
Started May 30 03:46:28 PM PDT 24
Finished May 30 03:46:44 PM PDT 24
Peak memory 205536 kb
Host smart-56bb0f90-ca66-49a9-85cf-945664587211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54672
1925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.546721925
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2730162961
Short name T947
Test name
Test status
Simulation time 10203240895 ps
CPU time 14.33 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205616 kb
Host smart-04489a22-8140-48fb-aeed-849d58515e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
62961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2730162961
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.926230718
Short name T41
Test name
Test status
Simulation time 10097938158 ps
CPU time 13.75 seconds
Started May 30 03:46:37 PM PDT 24
Finished May 30 03:46:57 PM PDT 24
Peak memory 205544 kb
Host smart-50cda678-636b-4850-bbdb-1d4408532035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92623
0718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.926230718
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3052063068
Short name T1154
Test name
Test status
Simulation time 10074062466 ps
CPU time 13.87 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:42 PM PDT 24
Peak memory 205360 kb
Host smart-3d8f647b-cbfc-4d24-9dbb-7d8cf1027188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30520
63068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3052063068
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3698594560
Short name T573
Test name
Test status
Simulation time 10965735272 ps
CPU time 14.64 seconds
Started May 30 03:46:24 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205580 kb
Host smart-02c5b08b-7c2e-4d3b-8fec-c6276d823f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36985
94560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3698594560
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3514592624
Short name T1832
Test name
Test status
Simulation time 10272213859 ps
CPU time 15.76 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205588 kb
Host smart-08956514-52fd-4599-860b-8d5795b38d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35145
92624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3514592624
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.817494639
Short name T1629
Test name
Test status
Simulation time 10119469585 ps
CPU time 15.69 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205496 kb
Host smart-b85468e3-e198-462c-8c39-abf962c08952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81749
4639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.817494639
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.807055945
Short name T409
Test name
Test status
Simulation time 10051770486 ps
CPU time 12.77 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 205508 kb
Host smart-4d6fe9c5-d757-40cf-955d-a113747642d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80705
5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.807055945
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.882833431
Short name T965
Test name
Test status
Simulation time 10106765323 ps
CPU time 15.23 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:54 PM PDT 24
Peak memory 205596 kb
Host smart-594bea9c-4b50-4dbf-8643-59a8866b549f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88283
3431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.882833431
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3794814610
Short name T1066
Test name
Test status
Simulation time 10082180924 ps
CPU time 13.15 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:49 PM PDT 24
Peak memory 205500 kb
Host smart-ddcb2ab7-7751-403f-a2ac-0ae7a0dd8739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37948
14610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3794814610
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2275115851
Short name T601
Test name
Test status
Simulation time 13232150991 ps
CPU time 15.94 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:57 PM PDT 24
Peak memory 204872 kb
Host smart-4be6f23d-5f75-4e77-a7fd-e4996ab6b09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22751
15851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2275115851
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2401483011
Short name T501
Test name
Test status
Simulation time 10093998494 ps
CPU time 14.76 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205556 kb
Host smart-ecb433ac-1791-4213-86a9-0c457a5e8a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
83011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2401483011
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2458760867
Short name T576
Test name
Test status
Simulation time 10058658075 ps
CPU time 13.27 seconds
Started May 30 03:46:38 PM PDT 24
Finished May 30 03:46:57 PM PDT 24
Peak memory 205504 kb
Host smart-08888bc7-7c73-4ac9-a9f6-0468c5536a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587
60867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2458760867
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3115359509
Short name T1599
Test name
Test status
Simulation time 10074501309 ps
CPU time 13.33 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205520 kb
Host smart-e5b47002-f963-42e6-a009-4c456729c1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31153
59509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3115359509
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1122097090
Short name T1257
Test name
Test status
Simulation time 10114336329 ps
CPU time 15.05 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:53 PM PDT 24
Peak memory 204860 kb
Host smart-4f1bf1c1-fef4-44fa-9b95-959426c824e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
97090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1122097090
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1413708842
Short name T517
Test name
Test status
Simulation time 10089558633 ps
CPU time 14.45 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205580 kb
Host smart-c7438f5d-e85b-47a3-ba49-7d12ffb7857c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14137
08842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1413708842
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.1032393519
Short name T1338
Test name
Test status
Simulation time 10069779213 ps
CPU time 14.68 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205632 kb
Host smart-cc166069-4a49-49f6-ac8e-1304f568a214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10323
93519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.1032393519
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3859895066
Short name T163
Test name
Test status
Simulation time 10100701203 ps
CPU time 14.88 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205564 kb
Host smart-e1d85c65-89dc-4845-b4d9-c75365cb74f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38598
95066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3859895066
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.2400322848
Short name T505
Test name
Test status
Simulation time 10159550780 ps
CPU time 13.01 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205492 kb
Host smart-5b1c69f7-5bcb-42f4-a174-d88c0b2860cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24003
22848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.2400322848
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.459357924
Short name T579
Test name
Test status
Simulation time 10056923799 ps
CPU time 13.17 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205556 kb
Host smart-971c55be-3dc9-4b02-b960-47cedd570edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45935
7924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.459357924
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1549415674
Short name T1928
Test name
Test status
Simulation time 10040661829 ps
CPU time 12.97 seconds
Started May 30 03:46:30 PM PDT 24
Finished May 30 03:46:46 PM PDT 24
Peak memory 205520 kb
Host smart-e011dd5e-dbe2-4c5f-96e3-69fc22a1b061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15494
15674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1549415674
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.604017580
Short name T1237
Test name
Test status
Simulation time 20412416012 ps
CPU time 41.08 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205600 kb
Host smart-2db21b04-345f-42ac-8b53-835075419d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60401
7580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.604017580
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.860945375
Short name T1556
Test name
Test status
Simulation time 10072279582 ps
CPU time 13.77 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:47 PM PDT 24
Peak memory 205524 kb
Host smart-c722db01-3513-481a-bd9e-44a223f96925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86094
5375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.860945375
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1887110533
Short name T489
Test name
Test status
Simulation time 10058029992 ps
CPU time 16.22 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 205492 kb
Host smart-e8b54766-395f-4cdb-89a8-16ac44705912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18871
10533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1887110533
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_trans.2714518832
Short name T982
Test name
Test status
Simulation time 10074201876 ps
CPU time 14.31 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205532 kb
Host smart-b85c5f5a-1569-4baa-bfaa-32665013c311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27145
18832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_trans.2714518832
Directory /workspace/35.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2594741793
Short name T1571
Test name
Test status
Simulation time 10063532638 ps
CPU time 15.3 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:48 PM PDT 24
Peak memory 205500 kb
Host smart-f34f3b78-0685-4d0c-8f89-fa52bdec24a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25947
41793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2594741793
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1547168214
Short name T1801
Test name
Test status
Simulation time 10047378836 ps
CPU time 14.65 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205532 kb
Host smart-c635d159-a527-4bcb-8e88-cde474205fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
68214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1547168214
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3156914929
Short name T1323
Test name
Test status
Simulation time 10068879564 ps
CPU time 12.87 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:53 PM PDT 24
Peak memory 205576 kb
Host smart-83fe835e-455d-41be-88d6-54bbe435f02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31569
14929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3156914929
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.113762566
Short name T30
Test name
Test status
Simulation time 10114555653 ps
CPU time 13.2 seconds
Started May 30 03:46:25 PM PDT 24
Finished May 30 03:46:41 PM PDT 24
Peak memory 205548 kb
Host smart-5cd0d5b1-2726-48f2-a6f9-055926429135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11376
2566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.113762566
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2580131521
Short name T1011
Test name
Test status
Simulation time 10081673922 ps
CPU time 15.36 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205560 kb
Host smart-27498244-7034-4750-841a-2f766b3d9ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25801
31521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2580131521
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.781792243
Short name T1595
Test name
Test status
Simulation time 10091144368 ps
CPU time 14 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205516 kb
Host smart-49719075-60d9-45b1-b6aa-cdde1a5f6702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78179
2243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.781792243
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.max_length_in_transaction.4016091019
Short name T214
Test name
Test status
Simulation time 10135467721 ps
CPU time 13.83 seconds
Started May 30 03:46:37 PM PDT 24
Finished May 30 03:46:57 PM PDT 24
Peak memory 205540 kb
Host smart-c2a11a9e-54eb-401b-9a45-f8193839c9f6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4016091019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.max_length_in_transaction.4016091019
Directory /workspace/36.max_length_in_transaction/latest

Test location /workspace/coverage/default/36.min_length_in_transaction.2553740435
Short name T485
Test name
Test status
Simulation time 10108872226 ps
CPU time 17.44 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205552 kb
Host smart-b445ab5d-7963-4158-a776-936de8fa5c02
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2553740435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.min_length_in_transaction.2553740435
Directory /workspace/36.min_length_in_transaction/latest

Test location /workspace/coverage/default/36.random_length_in_trans.152869906
Short name T641
Test name
Test status
Simulation time 10065910467 ps
CPU time 17.87 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:59 PM PDT 24
Peak memory 205540 kb
Host smart-574d89a2-c924-439a-a9a9-452747d4ee50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15286
9906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.random_length_in_trans.152869906
Directory /workspace/36.random_length_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1219828352
Short name T211
Test name
Test status
Simulation time 13454918100 ps
CPU time 17.43 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:56 PM PDT 24
Peak memory 205540 kb
Host smart-58dccf64-5c35-4473-a56c-7a4993763dc1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1219828352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1219828352
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3611427425
Short name T47
Test name
Test status
Simulation time 13299779852 ps
CPU time 16.07 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:53 PM PDT 24
Peak memory 205548 kb
Host smart-aaff0fea-24fc-425b-962a-a70d14a615c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3611427425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3611427425
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2785980971
Short name T210
Test name
Test status
Simulation time 13201927758 ps
CPU time 17.07 seconds
Started May 30 03:46:29 PM PDT 24
Finished May 30 03:46:48 PM PDT 24
Peak memory 205572 kb
Host smart-7870c194-bf9f-497b-b2e0-4816b554b941
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2785980971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2785980971
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3064531093
Short name T1813
Test name
Test status
Simulation time 10046740242 ps
CPU time 15.82 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205508 kb
Host smart-34830da8-11df-4ecd-8d8f-6927a661d863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30645
31093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3064531093
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2741972230
Short name T175
Test name
Test status
Simulation time 10316509839 ps
CPU time 13.58 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205528 kb
Host smart-0c8d2107-885e-4b54-bd30-cd316a8fa095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27419
72230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2741972230
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2441955791
Short name T1855
Test name
Test status
Simulation time 10038277160 ps
CPU time 13.82 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 205564 kb
Host smart-53d3c0eb-5b86-4401-abea-17c177659470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
55791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2441955791
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.920967869
Short name T432
Test name
Test status
Simulation time 10052496074 ps
CPU time 16.19 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205716 kb
Host smart-150efe38-e60a-4d9d-9b1b-323ee4c5c96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92096
7869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.920967869
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.101318108
Short name T370
Test name
Test status
Simulation time 10708825867 ps
CPU time 14.14 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 205548 kb
Host smart-00155536-2064-42d1-b4fa-68de1289ebf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10131
8108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.101318108
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4118171447
Short name T1732
Test name
Test status
Simulation time 10199874022 ps
CPU time 15.19 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205488 kb
Host smart-f227c07e-f117-4b12-a561-7701394114bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181
71447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4118171447
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1497204269
Short name T1377
Test name
Test status
Simulation time 10079925243 ps
CPU time 16.17 seconds
Started May 30 03:46:37 PM PDT 24
Finished May 30 03:46:59 PM PDT 24
Peak memory 205492 kb
Host smart-f471cc31-30e2-4ffb-b0d6-ddac8d474dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14972
04269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1497204269
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3007456903
Short name T67
Test name
Test status
Simulation time 10088995790 ps
CPU time 12.97 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:54 PM PDT 24
Peak memory 205560 kb
Host smart-e4e410d4-4036-4b38-9fc2-e0777b28f87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30074
56903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3007456903
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.757633882
Short name T847
Test name
Test status
Simulation time 10110759802 ps
CPU time 13.04 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:00 PM PDT 24
Peak memory 205556 kb
Host smart-7801380e-18ed-4058-9c0b-ba3a414452e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75763
3882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.757633882
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1369492890
Short name T1657
Test name
Test status
Simulation time 10056907800 ps
CPU time 15.4 seconds
Started May 30 03:46:37 PM PDT 24
Finished May 30 03:46:59 PM PDT 24
Peak memory 205416 kb
Host smart-6b555e6b-3126-4ee6-af0c-c9d03bd8eec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
92890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1369492890
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1327095964
Short name T1646
Test name
Test status
Simulation time 13287238787 ps
CPU time 17.82 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:56 PM PDT 24
Peak memory 204848 kb
Host smart-0d2ddeff-6d96-4cd9-a329-5706600806ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13270
95964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1327095964
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1501499789
Short name T288
Test name
Test status
Simulation time 10087559494 ps
CPU time 13.46 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205524 kb
Host smart-b032e8a7-07a1-407d-8ea7-9b7ccc042c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014
99789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1501499789
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2676197745
Short name T1259
Test name
Test status
Simulation time 10058002861 ps
CPU time 13.67 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205516 kb
Host smart-4b7f9287-7d32-4803-9063-559b345a59a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26761
97745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2676197745
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1192485010
Short name T1873
Test name
Test status
Simulation time 10123364542 ps
CPU time 13.86 seconds
Started May 30 03:46:38 PM PDT 24
Finished May 30 03:46:58 PM PDT 24
Peak memory 205460 kb
Host smart-e51a9577-ef26-4877-84d8-29d4c6587bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
85010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1192485010
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3505814685
Short name T923
Test name
Test status
Simulation time 10104390470 ps
CPU time 13.68 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205564 kb
Host smart-09750332-1b71-4dc1-a07d-f40e511e8c58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
14685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3505814685
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2229067743
Short name T717
Test name
Test status
Simulation time 10056672785 ps
CPU time 15.54 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:49 PM PDT 24
Peak memory 205504 kb
Host smart-b91d23d5-e1c5-4269-8157-921d8a079ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22290
67743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2229067743
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2623447304
Short name T773
Test name
Test status
Simulation time 10095315054 ps
CPU time 14.98 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205552 kb
Host smart-caeb3e6b-c6dd-4e06-a992-c1b28ae5f427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26234
47304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2623447304
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3960830326
Short name T810
Test name
Test status
Simulation time 10133540179 ps
CPU time 14.27 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 205580 kb
Host smart-89a7e558-0ab6-4214-b913-787d2a3df49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
30326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3960830326
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.1943000965
Short name T430
Test name
Test status
Simulation time 10075769692 ps
CPU time 14.65 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:54 PM PDT 24
Peak memory 205548 kb
Host smart-6eb1355b-844f-4e0f-970d-a7db50aed6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19430
00965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.1943000965
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2212181266
Short name T942
Test name
Test status
Simulation time 10049184103 ps
CPU time 12.52 seconds
Started May 30 03:46:37 PM PDT 24
Finished May 30 03:46:56 PM PDT 24
Peak memory 205560 kb
Host smart-86e6e4d0-a971-4755-98ca-c45d058adbb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22121
81266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2212181266
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.683858327
Short name T908
Test name
Test status
Simulation time 10047180062 ps
CPU time 15.85 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205540 kb
Host smart-a0963141-449e-418c-9a1f-3b3d7a4c054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68385
8327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.683858327
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3934287306
Short name T239
Test name
Test status
Simulation time 19737271651 ps
CPU time 33.36 seconds
Started May 30 03:46:38 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205576 kb
Host smart-605559b3-a76c-4c3e-ab43-137aea49c4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39342
87306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3934287306
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3401372555
Short name T1053
Test name
Test status
Simulation time 10152993979 ps
CPU time 14.04 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205572 kb
Host smart-abd926d8-5d82-4e91-9c4e-0a1a2a13a74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34013
72555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3401372555
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.4238040350
Short name T1386
Test name
Test status
Simulation time 10186620505 ps
CPU time 15.04 seconds
Started May 30 03:46:34 PM PDT 24
Finished May 30 03:46:54 PM PDT 24
Peak memory 205568 kb
Host smart-d9dcce22-ce2d-4b04-9645-3725ba762e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
40350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.4238040350
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_trans.3054624538
Short name T570
Test name
Test status
Simulation time 10079330732 ps
CPU time 13.72 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:54 PM PDT 24
Peak memory 204880 kb
Host smart-46f2d121-aec6-452d-9e4f-b3b2b314a614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30546
24538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_trans.3054624538
Directory /workspace/36.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3963314526
Short name T597
Test name
Test status
Simulation time 10045369662 ps
CPU time 14.53 seconds
Started May 30 03:46:37 PM PDT 24
Finished May 30 03:46:58 PM PDT 24
Peak memory 205516 kb
Host smart-e803e79f-1fa3-48f4-8635-89c3c95d8037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
14526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3963314526
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1181219251
Short name T1514
Test name
Test status
Simulation time 10052620412 ps
CPU time 14.39 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:49 PM PDT 24
Peak memory 205556 kb
Host smart-5910c6a2-89dc-41e8-848c-4ac7c1125119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11812
19251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1181219251
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.4204012114
Short name T494
Test name
Test status
Simulation time 10053064875 ps
CPU time 14.46 seconds
Started May 30 03:46:35 PM PDT 24
Finished May 30 03:46:56 PM PDT 24
Peak memory 205524 kb
Host smart-a6574911-7ab7-401e-81d3-ca29b6b09854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42040
12114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.4204012114
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1981156918
Short name T1506
Test name
Test status
Simulation time 10160489719 ps
CPU time 15.72 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:50 PM PDT 24
Peak memory 205512 kb
Host smart-8b4ef641-59bd-4811-9d3d-659623d91fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
56918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1981156918
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3220942198
Short name T410
Test name
Test status
Simulation time 10058566755 ps
CPU time 13.65 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205572 kb
Host smart-a9dfd959-36ed-48b6-895e-7bef11b47f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32209
42198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3220942198
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.1434881523
Short name T813
Test name
Test status
Simulation time 10095486718 ps
CPU time 15.88 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:02 PM PDT 24
Peak memory 205588 kb
Host smart-e5ea4b43-30a8-4da8-a234-1b5bd2d3553d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14348
81523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1434881523
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.max_length_in_transaction.3149136291
Short name T512
Test name
Test status
Simulation time 10145003296 ps
CPU time 12.97 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205536 kb
Host smart-7f911325-743a-4f27-bf9c-1c6723d9703a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3149136291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.max_length_in_transaction.3149136291
Directory /workspace/37.max_length_in_transaction/latest

Test location /workspace/coverage/default/37.min_length_in_transaction.3834801633
Short name T657
Test name
Test status
Simulation time 10075171174 ps
CPU time 13.8 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:00 PM PDT 24
Peak memory 205568 kb
Host smart-b1aafa76-31f6-45d1-9d61-2bd9b6c509ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3834801633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.min_length_in_transaction.3834801633
Directory /workspace/37.min_length_in_transaction/latest

Test location /workspace/coverage/default/37.random_length_in_trans.2519184071
Short name T313
Test name
Test status
Simulation time 10057711250 ps
CPU time 13.33 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:02 PM PDT 24
Peak memory 205496 kb
Host smart-2ff61124-8f6c-4d01-b914-b6df931c8da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25191
84071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.random_length_in_trans.2519184071
Directory /workspace/37.random_length_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1440911012
Short name T13
Test name
Test status
Simulation time 13571758613 ps
CPU time 17.23 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:04 PM PDT 24
Peak memory 205548 kb
Host smart-860fd465-1815-46ee-8da3-36003b325ef3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1440911012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1440911012
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2734976373
Short name T925
Test name
Test status
Simulation time 13297244405 ps
CPU time 18.51 seconds
Started May 30 03:46:31 PM PDT 24
Finished May 30 03:46:52 PM PDT 24
Peak memory 205584 kb
Host smart-b5ad057a-be85-41c9-8026-b9323e71ed74
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2734976373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2734976373
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1519254031
Short name T1406
Test name
Test status
Simulation time 13270444452 ps
CPU time 19.55 seconds
Started May 30 03:46:32 PM PDT 24
Finished May 30 03:46:55 PM PDT 24
Peak memory 205544 kb
Host smart-8d4336fe-8e7b-4692-87ac-d4f0754b190f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1519254031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1519254031
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1609857446
Short name T826
Test name
Test status
Simulation time 10075945282 ps
CPU time 14.98 seconds
Started May 30 03:46:33 PM PDT 24
Finished May 30 03:46:51 PM PDT 24
Peak memory 205552 kb
Host smart-0cbaf480-8202-4c22-819a-ea6d1b983d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098
57446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1609857446
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3176014038
Short name T1690
Test name
Test status
Simulation time 10156899032 ps
CPU time 13.37 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205648 kb
Host smart-fe6ec45f-d040-4977-878b-f11319fdeb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31760
14038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3176014038
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.4148046594
Short name T478
Test name
Test status
Simulation time 10046993093 ps
CPU time 17.29 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205540 kb
Host smart-7c0dbb40-2f09-4f7e-9974-ef97bfa4f064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480
46594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.4148046594
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.4054177664
Short name T781
Test name
Test status
Simulation time 10074205396 ps
CPU time 13.11 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205508 kb
Host smart-5497a29d-58a1-4a62-a413-22493ad04c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40541
77664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.4054177664
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3174402540
Short name T1391
Test name
Test status
Simulation time 10688412999 ps
CPU time 15.38 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:03 PM PDT 24
Peak memory 205592 kb
Host smart-4e8cebac-6811-49be-9cc5-afa638ebee4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744
02540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3174402540
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.319718966
Short name T958
Test name
Test status
Simulation time 10139852652 ps
CPU time 14.01 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:04 PM PDT 24
Peak memory 205508 kb
Host smart-db7b7a9c-31bc-4d23-85a9-1f84bd7b6fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31971
8966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.319718966
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3044960650
Short name T1709
Test name
Test status
Simulation time 10054363699 ps
CPU time 12.66 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205540 kb
Host smart-f98aaa8a-259e-46cb-9ecc-f39cc8c06f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30449
60650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3044960650
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.878529669
Short name T1088
Test name
Test status
Simulation time 10081624560 ps
CPU time 13.48 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:02 PM PDT 24
Peak memory 205508 kb
Host smart-4fbd79a6-78ee-4721-838b-41df1ec0492e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87852
9669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.878529669
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.810881779
Short name T629
Test name
Test status
Simulation time 10101262106 ps
CPU time 15.64 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205544 kb
Host smart-1758683f-3047-45a4-bc72-dcb8edafec54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81088
1779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.810881779
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3387026293
Short name T1031
Test name
Test status
Simulation time 10054457229 ps
CPU time 13.66 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205540 kb
Host smart-06f38628-c25f-477c-8663-c3adebc5e4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33870
26293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3387026293
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3452930014
Short name T558
Test name
Test status
Simulation time 13188162600 ps
CPU time 15.86 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205548 kb
Host smart-452abe9c-d3c2-4dd7-ad91-f46a69b77d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
30014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3452930014
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2026027540
Short name T889
Test name
Test status
Simulation time 10111697062 ps
CPU time 14.74 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205544 kb
Host smart-95932710-cb48-41a1-9b66-e948110d32ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20260
27540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2026027540
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3888505212
Short name T1018
Test name
Test status
Simulation time 10080327156 ps
CPU time 16.65 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:04 PM PDT 24
Peak memory 205604 kb
Host smart-35443f39-e09e-43e7-a83e-a37ea40f0fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38885
05212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3888505212
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4009636917
Short name T113
Test name
Test status
Simulation time 10119242182 ps
CPU time 15.04 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205636 kb
Host smart-f24b005a-cd66-4812-b8ae-cc75ca03c8ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40096
36917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4009636917
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.959736560
Short name T1131
Test name
Test status
Simulation time 10095523850 ps
CPU time 14.31 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:02 PM PDT 24
Peak memory 205560 kb
Host smart-b28c5281-25b9-4376-98c4-00fa0223504b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95973
6560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.959736560
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.328490034
Short name T1557
Test name
Test status
Simulation time 10075326763 ps
CPU time 13.27 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205548 kb
Host smart-7dea1e06-33b8-44cb-a977-a5940a6be37a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
0034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.328490034
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2152937874
Short name T895
Test name
Test status
Simulation time 10074028039 ps
CPU time 13.99 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205536 kb
Host smart-ccdf4783-677d-4c19-bae9-56a8d215e8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21529
37874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2152937874
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1725513632
Short name T89
Test name
Test status
Simulation time 10078788789 ps
CPU time 13.11 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205496 kb
Host smart-8b3eec6e-dcb7-4c9f-91a3-e742ed327c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17255
13632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1725513632
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.479801709
Short name T1887
Test name
Test status
Simulation time 10042257359 ps
CPU time 13.46 seconds
Started May 30 03:46:48 PM PDT 24
Finished May 30 03:47:08 PM PDT 24
Peak memory 205524 kb
Host smart-ee5cecdc-c634-4333-aa52-7a89d55ed171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47980
1709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.479801709
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4205160033
Short name T60
Test name
Test status
Simulation time 10046705673 ps
CPU time 13.91 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:03 PM PDT 24
Peak memory 205548 kb
Host smart-316a4c97-026d-4c1b-bc45-2fe2a75fc13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
60033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4205160033
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.796424787
Short name T1174
Test name
Test status
Simulation time 10080141576 ps
CPU time 13.01 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:00 PM PDT 24
Peak memory 205552 kb
Host smart-7ff08365-bcd1-4703-bdac-ff0c69541d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79642
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.796424787
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3332293006
Short name T1299
Test name
Test status
Simulation time 20221292999 ps
CPU time 38.35 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205556 kb
Host smart-690f2c3b-9748-4eeb-a0dc-80195d0e7ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
93006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3332293006
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3335770346
Short name T1485
Test name
Test status
Simulation time 10070687833 ps
CPU time 15.26 seconds
Started May 30 03:46:41 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205580 kb
Host smart-8dc45056-9a40-4c68-9ae5-05f781bd2fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
70346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3335770346
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1468005136
Short name T1231
Test name
Test status
Simulation time 10139227425 ps
CPU time 13.18 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205580 kb
Host smart-c495a248-a8a5-46de-aa26-59fdf246dfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14680
05136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1468005136
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_trans.42084706
Short name T715
Test name
Test status
Simulation time 10089022657 ps
CPU time 13.32 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205544 kb
Host smart-5fc501b3-6b90-468f-ae4e-92db21b1d7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42084
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_trans.42084706
Directory /workspace/37.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.927939804
Short name T1253
Test name
Test status
Simulation time 10040795041 ps
CPU time 16.21 seconds
Started May 30 03:46:45 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205540 kb
Host smart-008272d9-416b-4f4f-9ff9-f0a65f031c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92793
9804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.927939804
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2222146068
Short name T1215
Test name
Test status
Simulation time 10048307284 ps
CPU time 13.65 seconds
Started May 30 03:46:45 PM PDT 24
Finished May 30 03:47:04 PM PDT 24
Peak memory 205520 kb
Host smart-6b238e08-e777-4c87-8d8a-dbae2cbaf611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
46068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2222146068
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.833771252
Short name T1010
Test name
Test status
Simulation time 10052567573 ps
CPU time 16.51 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205496 kb
Host smart-69fa336c-0b77-4f2e-82b1-ad9d667a25c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83377
1252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.833771252
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2866543818
Short name T1714
Test name
Test status
Simulation time 10185636549 ps
CPU time 13.24 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:00 PM PDT 24
Peak memory 205612 kb
Host smart-f1ceb523-5592-4ec4-878a-8a165a8728db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
43818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2866543818
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.551510060
Short name T1123
Test name
Test status
Simulation time 10104867709 ps
CPU time 12.87 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205520 kb
Host smart-020a0ffc-6dbb-4baa-97d4-bb737f65acae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55151
0060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.551510060
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.954309755
Short name T1038
Test name
Test status
Simulation time 10086622836 ps
CPU time 13.93 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205540 kb
Host smart-5a0ecc2a-ed02-4794-8d81-fce142cfe9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95430
9755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.954309755
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.max_length_in_transaction.3506203495
Short name T1059
Test name
Test status
Simulation time 10145235292 ps
CPU time 14.8 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205584 kb
Host smart-b66278ee-28d7-476d-b383-002dcd1aa9a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3506203495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.max_length_in_transaction.3506203495
Directory /workspace/38.max_length_in_transaction/latest

Test location /workspace/coverage/default/38.min_length_in_transaction.1374189608
Short name T1501
Test name
Test status
Simulation time 10073120467 ps
CPU time 13.93 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205588 kb
Host smart-91b50201-fd75-4186-b042-20a6ddb1ccef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1374189608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.min_length_in_transaction.1374189608
Directory /workspace/38.min_length_in_transaction/latest

Test location /workspace/coverage/default/38.random_length_in_trans.2375432527
Short name T1896
Test name
Test status
Simulation time 10074931934 ps
CPU time 16.19 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205544 kb
Host smart-42dbb46e-a33c-4c25-801c-d41f88f60c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23754
32527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.random_length_in_trans.2375432527
Directory /workspace/38.random_length_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.598765051
Short name T1702
Test name
Test status
Simulation time 13688933661 ps
CPU time 22.26 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205548 kb
Host smart-3cefab3f-24e0-4e56-9e44-b87c9ba38872
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=598765051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.598765051
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.676080522
Short name T624
Test name
Test status
Simulation time 13389368155 ps
CPU time 19.28 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205484 kb
Host smart-9974386c-dcfc-4edb-be59-2b9f6532027d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=676080522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.676080522
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1597525942
Short name T1366
Test name
Test status
Simulation time 13224463077 ps
CPU time 20.8 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205652 kb
Host smart-9c07a6b2-b08f-4d4b-93f1-c3bc690589ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1597525942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1597525942
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2734492995
Short name T946
Test name
Test status
Simulation time 10067172178 ps
CPU time 13.99 seconds
Started May 30 03:46:41 PM PDT 24
Finished May 30 03:46:59 PM PDT 24
Peak memory 205560 kb
Host smart-501bed53-0c75-420e-8d83-bf647bfc4f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27344
92995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2734492995
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1309472143
Short name T1902
Test name
Test status
Simulation time 11068029894 ps
CPU time 16.8 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205520 kb
Host smart-a797a3d8-5c69-4b75-bd98-5e4c9729a343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094
72143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1309472143
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1158573600
Short name T664
Test name
Test status
Simulation time 10044176320 ps
CPU time 13.62 seconds
Started May 30 03:46:45 PM PDT 24
Finished May 30 03:47:04 PM PDT 24
Peak memory 205576 kb
Host smart-8a882a14-784a-481f-8f56-d758507e49a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11585
73600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1158573600
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.603352279
Short name T400
Test name
Test status
Simulation time 10050824602 ps
CPU time 16.27 seconds
Started May 30 03:46:41 PM PDT 24
Finished May 30 03:47:02 PM PDT 24
Peak memory 205636 kb
Host smart-165f9095-676d-486f-b082-9283846f1bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60335
2279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.603352279
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2925975022
Short name T1246
Test name
Test status
Simulation time 10833044523 ps
CPU time 15.26 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:08 PM PDT 24
Peak memory 205528 kb
Host smart-1a80703b-aadc-4f06-b925-ddafd9bfe9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29259
75022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2925975022
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3826437996
Short name T726
Test name
Test status
Simulation time 10091328378 ps
CPU time 15.23 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205508 kb
Host smart-7269cb71-0369-4e7f-a277-585ca62dcfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38264
37996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3826437996
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.430363743
Short name T1570
Test name
Test status
Simulation time 10140876883 ps
CPU time 13.87 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205548 kb
Host smart-f569de61-09d1-49dd-8e4b-dfae0250e634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43036
3743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.430363743
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3417282317
Short name T699
Test name
Test status
Simulation time 10045868787 ps
CPU time 13.36 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205560 kb
Host smart-43aed47a-2c6c-4b3e-883d-bfc96e69dff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
82317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3417282317
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3826046289
Short name T887
Test name
Test status
Simulation time 10196526172 ps
CPU time 14.51 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205528 kb
Host smart-fd1dcf31-d25a-4526-aa9b-1eaf90c716a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38260
46289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3826046289
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1621948432
Short name T1520
Test name
Test status
Simulation time 10118250219 ps
CPU time 16.28 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205532 kb
Host smart-868a675b-dd2d-4d2b-a7fb-740213ac4289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16219
48432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1621948432
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1522106149
Short name T1180
Test name
Test status
Simulation time 13173408521 ps
CPU time 15.97 seconds
Started May 30 03:46:42 PM PDT 24
Finished May 30 03:47:03 PM PDT 24
Peak memory 205556 kb
Host smart-49d34327-bb79-4bc9-8e68-8e77ef20a4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15221
06149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1522106149
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3915688593
Short name T1726
Test name
Test status
Simulation time 10089899013 ps
CPU time 13.18 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205596 kb
Host smart-2bb2bba9-d398-4a9b-b71f-79c380f082a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
88593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3915688593
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2775088238
Short name T749
Test name
Test status
Simulation time 10050043466 ps
CPU time 14.49 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205556 kb
Host smart-8ded669b-9689-4ce5-936b-3f03592a716c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27750
88238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2775088238
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3081027922
Short name T105
Test name
Test status
Simulation time 10092575149 ps
CPU time 14.98 seconds
Started May 30 03:46:48 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205564 kb
Host smart-72edf396-9311-40e5-968f-7c2c2fb8ad6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30810
27922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3081027922
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2419421709
Short name T1023
Test name
Test status
Simulation time 10094407359 ps
CPU time 14.2 seconds
Started May 30 03:46:48 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205532 kb
Host smart-b1d90902-e9f6-4e14-ba63-9b418e146be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
21709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2419421709
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2398203085
Short name T551
Test name
Test status
Simulation time 10059490878 ps
CPU time 13.11 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:03 PM PDT 24
Peak memory 205496 kb
Host smart-21f8d816-5c2f-4238-993d-4a0c8327193c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23982
03085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2398203085
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1696941536
Short name T1235
Test name
Test status
Simulation time 10085012614 ps
CPU time 14.26 seconds
Started May 30 03:46:49 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205536 kb
Host smart-a846ccb2-d01d-4ed6-a635-24bc5351df65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
41536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1696941536
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2689378881
Short name T1793
Test name
Test status
Simulation time 10055943713 ps
CPU time 13.75 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205572 kb
Host smart-2fe97564-3f07-47be-aca2-a4f01ed1ad74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893
78881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2689378881
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.1372231568
Short name T554
Test name
Test status
Simulation time 10076167032 ps
CPU time 13.45 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:03 PM PDT 24
Peak memory 205524 kb
Host smart-e2167ab1-f456-4ce0-9052-1ac83d186153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13722
31568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.1372231568
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3850685859
Short name T833
Test name
Test status
Simulation time 10086954687 ps
CPU time 13.97 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205572 kb
Host smart-bc19ca16-bee9-4903-9436-314a3e33c816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38506
85859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3850685859
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1137627146
Short name T935
Test name
Test status
Simulation time 10027766780 ps
CPU time 13.28 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205552 kb
Host smart-a444be25-f7f4-47ba-97f0-e755ec85061f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11376
27146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1137627146
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.970041175
Short name T1925
Test name
Test status
Simulation time 31457542234 ps
CPU time 56.86 seconds
Started May 30 03:46:49 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205604 kb
Host smart-ff6aadfc-d863-42af-b3ae-d65a61ac3a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97004
1175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.970041175
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1125166918
Short name T1781
Test name
Test status
Simulation time 10057896025 ps
CPU time 15.34 seconds
Started May 30 03:46:51 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205544 kb
Host smart-58b3480b-814b-4eba-93ca-86c31f11277d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11251
66918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1125166918
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2268045204
Short name T750
Test name
Test status
Simulation time 10097805841 ps
CPU time 16.44 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205540 kb
Host smart-1ff74bce-076a-4bdd-803a-4dbbdb15b259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22680
45204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2268045204
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_trans.3089106120
Short name T613
Test name
Test status
Simulation time 10065955869 ps
CPU time 13.36 seconds
Started May 30 03:46:45 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205580 kb
Host smart-a27df46b-7532-42f7-a852-34570b354b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30891
06120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_trans.3089106120
Directory /workspace/38.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.825786623
Short name T1140
Test name
Test status
Simulation time 10069550891 ps
CPU time 12.93 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205520 kb
Host smart-9354927a-659d-41e9-b066-260f1f4d7fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82578
6623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.825786623
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3367977145
Short name T853
Test name
Test status
Simulation time 10083880300 ps
CPU time 12.62 seconds
Started May 30 03:46:43 PM PDT 24
Finished May 30 03:47:01 PM PDT 24
Peak memory 205480 kb
Host smart-1af01fdc-6746-4815-914a-97f86560681a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33679
77145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3367977145
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.23068076
Short name T376
Test name
Test status
Simulation time 10055933341 ps
CPU time 13.65 seconds
Started May 30 03:46:51 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205548 kb
Host smart-ca4e03ba-19e4-4916-bd9f-0b0ba6dbba70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23068
076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.23068076
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.528092801
Short name T1216
Test name
Test status
Simulation time 10152031134 ps
CPU time 13.28 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:05 PM PDT 24
Peak memory 205548 kb
Host smart-d3d39d92-b86f-4b6b-a300-13b29ad00c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52809
2801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.528092801
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3696186619
Short name T375
Test name
Test status
Simulation time 10082426284 ps
CPU time 14.01 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205580 kb
Host smart-c1d47a37-ec9d-4d74-8cde-2ead80b3f36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
86619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3696186619
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1625514220
Short name T1122
Test name
Test status
Simulation time 10095792865 ps
CPU time 14.12 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205596 kb
Host smart-083cc529-aaec-49d1-8d94-d85c5094c0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16255
14220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1625514220
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.max_length_in_transaction.2125870135
Short name T1785
Test name
Test status
Simulation time 10139761041 ps
CPU time 12.64 seconds
Started May 30 03:46:53 PM PDT 24
Finished May 30 03:47:11 PM PDT 24
Peak memory 205580 kb
Host smart-c3eca486-b224-44d6-a0a4-773a5b0bbcaf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2125870135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.max_length_in_transaction.2125870135
Directory /workspace/39.max_length_in_transaction/latest

Test location /workspace/coverage/default/39.min_length_in_transaction.461064927
Short name T287
Test name
Test status
Simulation time 10065149486 ps
CPU time 13.41 seconds
Started May 30 03:46:57 PM PDT 24
Finished May 30 03:47:15 PM PDT 24
Peak memory 205544 kb
Host smart-2ceb489c-ba29-41d4-afdf-83d10c093e8a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=461064927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.min_length_in_transaction.461064927
Directory /workspace/39.min_length_in_transaction/latest

Test location /workspace/coverage/default/39.random_length_in_trans.2233160441
Short name T1305
Test name
Test status
Simulation time 10100298918 ps
CPU time 15.16 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205500 kb
Host smart-94469a3f-84fc-4f28-8be3-04fde4af1eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22331
60441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.random_length_in_trans.2233160441
Directory /workspace/39.random_length_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1402793973
Short name T1656
Test name
Test status
Simulation time 14009525913 ps
CPU time 18.12 seconds
Started May 30 03:46:50 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205596 kb
Host smart-28786174-ab7b-4b0c-84b7-52023700cb69
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1402793973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1402793973
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3703617397
Short name T874
Test name
Test status
Simulation time 13264594790 ps
CPU time 19.41 seconds
Started May 30 03:46:44 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205536 kb
Host smart-c8a0535d-d01f-4974-af3c-3e29be4a377a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3703617397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3703617397
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1051581582
Short name T1447
Test name
Test status
Simulation time 13248898455 ps
CPU time 16.7 seconds
Started May 30 03:46:49 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205588 kb
Host smart-7a045c79-b541-4ba7-ad7b-e1841d43d0cf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1051581582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1051581582
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3095474788
Short name T1620
Test name
Test status
Simulation time 10111264628 ps
CPU time 13.1 seconds
Started May 30 03:46:49 PM PDT 24
Finished May 30 03:47:08 PM PDT 24
Peak memory 205492 kb
Host smart-cf02d2c4-1b12-4cb9-b3de-13208f4ca192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954
74788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3095474788
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1534761516
Short name T671
Test name
Test status
Simulation time 10053942927 ps
CPU time 16.01 seconds
Started May 30 03:46:48 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205568 kb
Host smart-c0410f00-256f-4f25-8c6d-3e7ff404977c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
61516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1534761516
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2569568098
Short name T812
Test name
Test status
Simulation time 10600488405 ps
CPU time 13.81 seconds
Started May 30 03:46:49 PM PDT 24
Finished May 30 03:47:08 PM PDT 24
Peak memory 205616 kb
Host smart-d731bc9a-6c96-4bd7-b4e1-00b738991f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
68098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2569568098
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.966702606
Short name T1293
Test name
Test status
Simulation time 10085482870 ps
CPU time 13.17 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205512 kb
Host smart-480cbe1a-6be5-4ebe-bf47-10454f56efa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96670
2606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.966702606
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.4030208003
Short name T628
Test name
Test status
Simulation time 10070449285 ps
CPU time 13.8 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205544 kb
Host smart-5fc522ec-c6c0-4212-9f3b-1e1ad302e4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40302
08003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.4030208003
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.2280635643
Short name T1450
Test name
Test status
Simulation time 10282637132 ps
CPU time 14.63 seconds
Started May 30 03:46:49 PM PDT 24
Finished May 30 03:47:09 PM PDT 24
Peak memory 205520 kb
Host smart-e7e76569-7acb-49a7-b182-af1471cd05f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22806
35643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2280635643
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.154900521
Short name T129
Test name
Test status
Simulation time 10109679616 ps
CPU time 13.41 seconds
Started May 30 03:46:52 PM PDT 24
Finished May 30 03:47:11 PM PDT 24
Peak memory 205544 kb
Host smart-0c49fe22-f0ae-47af-aceb-8a1536077be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490
0521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.154900521
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3257483521
Short name T1927
Test name
Test status
Simulation time 10056074114 ps
CPU time 13.58 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205516 kb
Host smart-09daa78c-b6f8-471b-b891-bb3eef9798dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32574
83521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3257483521
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.144121472
Short name T381
Test name
Test status
Simulation time 10141220345 ps
CPU time 13.65 seconds
Started May 30 03:46:46 PM PDT 24
Finished May 30 03:47:06 PM PDT 24
Peak memory 205532 kb
Host smart-b497d56e-9170-4ee7-8edc-a8917f0b7f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
1472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.144121472
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.988249148
Short name T1245
Test name
Test status
Simulation time 10130942127 ps
CPU time 14.32 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205540 kb
Host smart-09c3a86d-8b1a-422b-9f63-d21f61736c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98824
9148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.988249148
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1562667142
Short name T1790
Test name
Test status
Simulation time 13219737014 ps
CPU time 15.86 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205508 kb
Host smart-6d3a02c5-31e1-4167-b141-dabfdf93ceae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
67142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1562667142
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2138435517
Short name T529
Test name
Test status
Simulation time 10111179234 ps
CPU time 14.51 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205568 kb
Host smart-412e9c00-62a4-4aa1-b41e-1e862078845a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21384
35517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2138435517
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1121639750
Short name T739
Test name
Test status
Simulation time 10099116545 ps
CPU time 13.76 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205504 kb
Host smart-8a7f9631-ea8c-466b-83de-3ac523a088ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11216
39750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1121639750
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2207481361
Short name T93
Test name
Test status
Simulation time 10123181286 ps
CPU time 14.02 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:22 PM PDT 24
Peak memory 205540 kb
Host smart-a474871d-10c9-4898-a4d0-014b835e9b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22074
81361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2207481361
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.4279386749
Short name T328
Test name
Test status
Simulation time 10084405413 ps
CPU time 13.97 seconds
Started May 30 03:47:00 PM PDT 24
Finished May 30 03:47:18 PM PDT 24
Peak memory 205532 kb
Host smart-e19d7814-5627-4cb0-ad57-5774785158ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42793
86749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.4279386749
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2845171728
Short name T497
Test name
Test status
Simulation time 10059031898 ps
CPU time 13.14 seconds
Started May 30 03:46:52 PM PDT 24
Finished May 30 03:47:10 PM PDT 24
Peak memory 205572 kb
Host smart-567ff477-2450-43f8-a82b-21fe353ad375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28451
71728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2845171728
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1885191728
Short name T1876
Test name
Test status
Simulation time 10163855682 ps
CPU time 14.15 seconds
Started May 30 03:46:56 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205552 kb
Host smart-6fb0dee4-d407-4485-925f-d8a47d487325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18851
91728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1885191728
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.2385912753
Short name T1233
Test name
Test status
Simulation time 10108117824 ps
CPU time 14.77 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:23 PM PDT 24
Peak memory 205480 kb
Host smart-0f337fbe-ec73-4b90-95b8-c44963225243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23859
12753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.2385912753
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1866741042
Short name T1866
Test name
Test status
Simulation time 10039688072 ps
CPU time 14.65 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205492 kb
Host smart-1a367429-e04a-4158-8ee8-bbd68a8219ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
41042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1866741042
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2682629829
Short name T1419
Test name
Test status
Simulation time 10031917165 ps
CPU time 15.22 seconds
Started May 30 03:46:53 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205516 kb
Host smart-8a5f526b-3346-4f6f-8d79-35e230a4742e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26826
29829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2682629829
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1438521113
Short name T1327
Test name
Test status
Simulation time 24504738816 ps
CPU time 44.17 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205608 kb
Host smart-d0234e15-9ba9-4825-8259-07e73fb2d145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14385
21113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1438521113
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.264489289
Short name T795
Test name
Test status
Simulation time 10130081057 ps
CPU time 15.28 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205536 kb
Host smart-92292186-f7bc-420e-bb4e-2cc3bb9d6405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448
9289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.264489289
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1736535502
Short name T302
Test name
Test status
Simulation time 10128029701 ps
CPU time 14.58 seconds
Started May 30 03:46:57 PM PDT 24
Finished May 30 03:47:15 PM PDT 24
Peak memory 205588 kb
Host smart-2c0ce308-2b93-4d8e-adb8-13a09888d8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17365
35502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1736535502
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_trans.796443150
Short name T308
Test name
Test status
Simulation time 10055619487 ps
CPU time 16.63 seconds
Started May 30 03:46:57 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205540 kb
Host smart-6ebeceae-650b-4983-84d2-fd075ec184e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79644
3150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_trans.796443150
Directory /workspace/39.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2870111122
Short name T850
Test name
Test status
Simulation time 10059577094 ps
CPU time 13.7 seconds
Started May 30 03:46:57 PM PDT 24
Finished May 30 03:47:15 PM PDT 24
Peak memory 205528 kb
Host smart-a612e5a2-874f-4806-a383-e05b72f0dcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
11122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2870111122
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.712764878
Short name T1161
Test name
Test status
Simulation time 10065829367 ps
CPU time 13.53 seconds
Started May 30 03:47:00 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205536 kb
Host smart-4b01bdab-f302-4549-9719-eaf6b9485361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71276
4878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.712764878
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.626199443
Short name T518
Test name
Test status
Simulation time 10063069815 ps
CPU time 14.58 seconds
Started May 30 03:47:01 PM PDT 24
Finished May 30 03:47:20 PM PDT 24
Peak memory 204712 kb
Host smart-47ee86ee-f394-4372-b7e6-f3b4fe559b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62619
9443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.626199443
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1591666562
Short name T1037
Test name
Test status
Simulation time 10125718866 ps
CPU time 13.76 seconds
Started May 30 03:46:47 PM PDT 24
Finished May 30 03:47:07 PM PDT 24
Peak memory 205348 kb
Host smart-c8211b59-ec17-4b1d-94c6-e0a2034d15f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15916
66562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1591666562
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1828923717
Short name T1046
Test name
Test status
Simulation time 10106573599 ps
CPU time 16.51 seconds
Started May 30 03:46:57 PM PDT 24
Finished May 30 03:47:18 PM PDT 24
Peak memory 205568 kb
Host smart-6b38fe7d-6357-4420-839c-d4702164ca52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
23717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1828923717
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.434425985
Short name T424
Test name
Test status
Simulation time 10081556097 ps
CPU time 13.64 seconds
Started May 30 03:46:56 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205616 kb
Host smart-5f56c53a-74a9-43f2-9001-678d47c3c60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43442
5985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.434425985
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.max_length_in_transaction.3992933192
Short name T788
Test name
Test status
Simulation time 10143375432 ps
CPU time 13.66 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205632 kb
Host smart-0fae187b-ca42-467c-af05-543303b92347
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3992933192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.max_length_in_transaction.3992933192
Directory /workspace/4.max_length_in_transaction/latest

Test location /workspace/coverage/default/4.min_length_in_transaction.745687829
Short name T802
Test name
Test status
Simulation time 10050152257 ps
CPU time 14.86 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205516 kb
Host smart-d14a0d98-452a-416a-bc42-9b686fa8f831
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=745687829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.min_length_in_transaction.745687829
Directory /workspace/4.min_length_in_transaction/latest

Test location /workspace/coverage/default/4.random_length_in_trans.2699123958
Short name T1361
Test name
Test status
Simulation time 10065007960 ps
CPU time 14.04 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205548 kb
Host smart-e7150c21-f52e-49cb-a49c-19be0899edaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26991
23958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.random_length_in_trans.2699123958
Directory /workspace/4.random_length_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.998289686
Short name T1254
Test name
Test status
Simulation time 13345065659 ps
CPU time 18.24 seconds
Started May 30 03:42:44 PM PDT 24
Finished May 30 03:43:04 PM PDT 24
Peak memory 205568 kb
Host smart-9f7a9ea3-36a1-4c8c-a9e5-293ef176249b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=998289686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.998289686
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.4178837052
Short name T667
Test name
Test status
Simulation time 13286007124 ps
CPU time 15.58 seconds
Started May 30 03:42:42 PM PDT 24
Finished May 30 03:43:00 PM PDT 24
Peak memory 205540 kb
Host smart-8f8d16a6-0f7f-47e5-9ecc-2de4b21af16c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4178837052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.4178837052
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.4161195298
Short name T800
Test name
Test status
Simulation time 13241303091 ps
CPU time 18.04 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:43:00 PM PDT 24
Peak memory 205556 kb
Host smart-90227511-c24c-489a-9bb3-7aa470bc9b5a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4161195298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.4161195298
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2462922726
Short name T676
Test name
Test status
Simulation time 10055064616 ps
CPU time 13.73 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205528 kb
Host smart-3a90ac1f-d63c-4beb-a511-f32a4d57c6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
22726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2462922726
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3661387845
Short name T179
Test name
Test status
Simulation time 11257039448 ps
CPU time 15.97 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205560 kb
Host smart-2a737974-2365-42c8-9f5c-35ae5a7b68b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36613
87845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3661387845
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2083416182
Short name T1448
Test name
Test status
Simulation time 10046082941 ps
CPU time 13.16 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205576 kb
Host smart-6fd383bd-4bce-426c-9c8b-b2a5fef7e25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20834
16182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2083416182
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1358377653
Short name T989
Test name
Test status
Simulation time 10090234545 ps
CPU time 13.93 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205540 kb
Host smart-1566ab05-5354-42a6-b270-67dec849c035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13583
77653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1358377653
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2175274203
Short name T130
Test name
Test status
Simulation time 10622303364 ps
CPU time 15.08 seconds
Started May 30 03:42:40 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205476 kb
Host smart-ed5aa68c-d260-472e-88fd-a8e843b301e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21752
74203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2175274203
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2805702581
Short name T1736
Test name
Test status
Simulation time 10079501374 ps
CPU time 14.34 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:55 PM PDT 24
Peak memory 205564 kb
Host smart-4733ea6d-f718-4760-8a00-5c89993f60f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28057
02581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2805702581
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3422213744
Short name T1591
Test name
Test status
Simulation time 10094916821 ps
CPU time 13.05 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:05 PM PDT 24
Peak memory 205572 kb
Host smart-790c9e27-8e61-42a9-bb58-99d7ad2dc81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34222
13744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3422213744
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1591975777
Short name T1825
Test name
Test status
Simulation time 10048823267 ps
CPU time 15.14 seconds
Started May 30 03:42:52 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205572 kb
Host smart-99639cb4-be60-4da3-8b60-4667a27f5777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15919
75777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1591975777
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.683761137
Short name T980
Test name
Test status
Simulation time 10100964732 ps
CPU time 14.25 seconds
Started May 30 03:42:39 PM PDT 24
Finished May 30 03:42:55 PM PDT 24
Peak memory 205512 kb
Host smart-746bd954-282b-4934-8bc4-2d36a93e03c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68376
1137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.683761137
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.460810715
Short name T379
Test name
Test status
Simulation time 10085157844 ps
CPU time 13.8 seconds
Started May 30 03:42:42 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205512 kb
Host smart-3e0b8638-b9fa-4956-afd1-17c40ca5cc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46081
0715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.460810715
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.102704173
Short name T1382
Test name
Test status
Simulation time 13182742377 ps
CPU time 16.21 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:43:02 PM PDT 24
Peak memory 205516 kb
Host smart-3f644484-f6fe-4a98-bd31-00e2b9cf894f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10270
4173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.102704173
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1084018013
Short name T1586
Test name
Test status
Simulation time 10120555625 ps
CPU time 17.38 seconds
Started May 30 03:42:45 PM PDT 24
Finished May 30 03:43:04 PM PDT 24
Peak memory 205580 kb
Host smart-f5f5127c-d3a4-4a48-bbca-9f93bcf38c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
18013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1084018013
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3596566104
Short name T1187
Test name
Test status
Simulation time 10061162726 ps
CPU time 16.92 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:43:02 PM PDT 24
Peak memory 205548 kb
Host smart-145ce529-035c-45bd-a8f3-65a8c5d76789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
66104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3596566104
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.4151787563
Short name T112
Test name
Test status
Simulation time 10115832113 ps
CPU time 13.52 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:57 PM PDT 24
Peak memory 205516 kb
Host smart-db20f0e0-bd49-4158-a3b0-16f1506b342f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41517
87563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.4151787563
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3766383848
Short name T479
Test name
Test status
Simulation time 10106105525 ps
CPU time 14.68 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205484 kb
Host smart-cda1c5dd-dc2a-458c-9a54-b3595351ca3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37663
83848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3766383848
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3984104804
Short name T674
Test name
Test status
Simulation time 10068831479 ps
CPU time 13.05 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205572 kb
Host smart-88d59b61-059f-409b-9a18-9b546c832935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39841
04804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3984104804
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.603563138
Short name T1729
Test name
Test status
Simulation time 10093117422 ps
CPU time 14.52 seconds
Started May 30 03:42:42 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205572 kb
Host smart-6108dd4e-c8b4-4888-a58a-9c7840e347e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60356
3138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.603563138
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.534685544
Short name T157
Test name
Test status
Simulation time 10109696223 ps
CPU time 14.08 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205536 kb
Host smart-417493f8-57ea-461e-a8b8-6f4d60c448ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53468
5544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.534685544
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.780904877
Short name T544
Test name
Test status
Simulation time 10060648800 ps
CPU time 14.44 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:07 PM PDT 24
Peak memory 205580 kb
Host smart-9260dcda-c76a-4d29-b571-00bc534f5727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78090
4877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.780904877
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4060528903
Short name T524
Test name
Test status
Simulation time 10049912559 ps
CPU time 13.23 seconds
Started May 30 03:42:54 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205556 kb
Host smart-7bdc7471-a648-4e0d-8143-953e5e2cf877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40605
28903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4060528903
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3427704680
Short name T1527
Test name
Test status
Simulation time 10051642104 ps
CPU time 13.5 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205520 kb
Host smart-06deb941-75de-4c02-bf27-1b211f00e706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34277
04680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3427704680
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.341876134
Short name T1498
Test name
Test status
Simulation time 31181136072 ps
CPU time 63.33 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:43:47 PM PDT 24
Peak memory 205600 kb
Host smart-ff4fbbb6-2754-426f-82d5-9b41643c0f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34187
6134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.341876134
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1242130523
Short name T68
Test name
Test status
Simulation time 10076716016 ps
CPU time 16.7 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:43:03 PM PDT 24
Peak memory 205572 kb
Host smart-3d5861fd-629a-44a0-bfad-178233a0c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12421
30523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1242130523
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1706388408
Short name T1542
Test name
Test status
Simulation time 10131991950 ps
CPU time 14.47 seconds
Started May 30 03:42:44 PM PDT 24
Finished May 30 03:43:00 PM PDT 24
Peak memory 205576 kb
Host smart-b8fe49db-b4cf-4412-80ac-7a2de9753018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17063
88408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1706388408
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_trans.2619466938
Short name T799
Test name
Test status
Simulation time 10088560515 ps
CPU time 14.04 seconds
Started May 30 03:42:43 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205572 kb
Host smart-9e3f1f6c-b1a4-427a-a764-f38dca199518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26194
66938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_trans.2619466938
Directory /workspace/4.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.4152673553
Short name T1006
Test name
Test status
Simulation time 10047819666 ps
CPU time 12.56 seconds
Started May 30 03:42:45 PM PDT 24
Finished May 30 03:42:59 PM PDT 24
Peak memory 205544 kb
Host smart-3207a9e4-5c96-4771-9bc4-a8ceb5a96fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41526
73553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.4152673553
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.650998928
Short name T193
Test name
Test status
Simulation time 248272498 ps
CPU time 1.11 seconds
Started May 30 03:42:56 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 221564 kb
Host smart-72c2232a-ddde-4707-b8c1-16fd728c1b23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=650998928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.650998928
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2415678638
Short name T147
Test name
Test status
Simulation time 10078399387 ps
CPU time 14.15 seconds
Started May 30 03:42:54 PM PDT 24
Finished May 30 03:43:10 PM PDT 24
Peak memory 205548 kb
Host smart-06e33881-c6d9-470e-b033-45c61b2f94c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24156
78638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2415678638
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3925680851
Short name T1311
Test name
Test status
Simulation time 10089547645 ps
CPU time 13.02 seconds
Started May 30 03:42:42 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205584 kb
Host smart-6ccdd5a6-0319-4879-8a86-80d72f628305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39256
80851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3925680851
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2393712479
Short name T759
Test name
Test status
Simulation time 10118402941 ps
CPU time 14.14 seconds
Started May 30 03:42:41 PM PDT 24
Finished May 30 03:42:58 PM PDT 24
Peak memory 205564 kb
Host smart-de51e29e-be2c-43e0-8ed2-4d98846db74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23937
12479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2393712479
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1876508127
Short name T1065
Test name
Test status
Simulation time 10111982539 ps
CPU time 16.01 seconds
Started May 30 03:42:42 PM PDT 24
Finished May 30 03:43:01 PM PDT 24
Peak memory 205604 kb
Host smart-746dbc8b-73b9-4011-b1e6-bc62d3b5bc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18765
08127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1876508127
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3355829246
Short name T1703
Test name
Test status
Simulation time 10092337012 ps
CPU time 15.34 seconds
Started May 30 03:42:44 PM PDT 24
Finished May 30 03:43:01 PM PDT 24
Peak memory 205576 kb
Host smart-2229c9d4-942d-4506-ac7d-f3f4b4fa1c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33558
29246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3355829246
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.max_length_in_transaction.1099632055
Short name T616
Test name
Test status
Simulation time 10135649862 ps
CPU time 15.64 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205528 kb
Host smart-40154e8c-7c69-4661-a1c2-33ab7c5e79f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1099632055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.max_length_in_transaction.1099632055
Directory /workspace/40.max_length_in_transaction/latest

Test location /workspace/coverage/default/40.min_length_in_transaction.3699297488
Short name T1477
Test name
Test status
Simulation time 10059741959 ps
CPU time 12.91 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205572 kb
Host smart-9f256c72-3659-448d-bc28-4a55848cec81
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3699297488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.min_length_in_transaction.3699297488
Directory /workspace/40.min_length_in_transaction/latest

Test location /workspace/coverage/default/40.random_length_in_trans.618940890
Short name T767
Test name
Test status
Simulation time 10135177183 ps
CPU time 13.97 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205492 kb
Host smart-c423143c-71b9-4cd3-8706-a382fe23c8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61894
0890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.random_length_in_trans.618940890
Directory /workspace/40.random_length_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1868561731
Short name T1794
Test name
Test status
Simulation time 13324520144 ps
CPU time 16.46 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:15 PM PDT 24
Peak memory 205568 kb
Host smart-7660ff2d-16d6-40ab-902b-b31799fe256f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1868561731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1868561731
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3525520073
Short name T191
Test name
Test status
Simulation time 13228556202 ps
CPU time 17.97 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205560 kb
Host smart-c0d10d5b-eccf-40e1-b18a-e8901f8120f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3525520073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3525520073
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1532407714
Short name T1431
Test name
Test status
Simulation time 13379637088 ps
CPU time 21.18 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:23 PM PDT 24
Peak memory 205516 kb
Host smart-4414b687-e3a4-47cf-9e88-9a42e3091753
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1532407714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.1532407714
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3052757561
Short name T1025
Test name
Test status
Simulation time 10073730151 ps
CPU time 14.43 seconds
Started May 30 03:46:53 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205544 kb
Host smart-1a964c66-81d3-4d4e-bd30-16c27150ecd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
57561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3052757561
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3813954963
Short name T1553
Test name
Test status
Simulation time 10118380658 ps
CPU time 16.71 seconds
Started May 30 03:47:01 PM PDT 24
Finished May 30 03:47:22 PM PDT 24
Peak memory 205584 kb
Host smart-e8f0a1ab-53b1-46db-a586-255739eac94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38139
54963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3813954963
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.4173747482
Short name T1376
Test name
Test status
Simulation time 10056458226 ps
CPU time 14.68 seconds
Started May 30 03:47:00 PM PDT 24
Finished May 30 03:47:18 PM PDT 24
Peak memory 205560 kb
Host smart-51d87332-7af5-46df-a5dc-3ff301629a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41737
47482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.4173747482
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1130859173
Short name T1658
Test name
Test status
Simulation time 10063818470 ps
CPU time 13.57 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205648 kb
Host smart-832e5404-4fe7-4504-81e7-cbf2b48ac7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
59173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1130859173
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2023827248
Short name T1095
Test name
Test status
Simulation time 10113123385 ps
CPU time 14.34 seconds
Started May 30 03:46:56 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205520 kb
Host smart-8b3e1e30-5e9c-4060-87f0-4496aa77f334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
27248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2023827248
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3342594603
Short name T843
Test name
Test status
Simulation time 10125930254 ps
CPU time 14.17 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205556 kb
Host smart-41278eee-807d-492b-86bb-7b12c231179c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
94603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3342594603
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2289039588
Short name T352
Test name
Test status
Simulation time 10053194690 ps
CPU time 15.87 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:28 PM PDT 24
Peak memory 205448 kb
Host smart-d568624e-d614-427a-bf8b-308c17ced204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22890
39588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2289039588
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1554131714
Short name T580
Test name
Test status
Simulation time 10074883106 ps
CPU time 14.04 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:13 PM PDT 24
Peak memory 205592 kb
Host smart-8d270dac-aef5-46ef-b4ac-b430f59fa107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
31714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1554131714
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.3810450648
Short name T1308
Test name
Test status
Simulation time 10070474007 ps
CPU time 15.19 seconds
Started May 30 03:46:59 PM PDT 24
Finished May 30 03:47:19 PM PDT 24
Peak memory 205556 kb
Host smart-0c7dafcd-cf07-4406-a549-05f9780c2922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38104
50648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.3810450648
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3183127388
Short name T1867
Test name
Test status
Simulation time 13180136359 ps
CPU time 17.45 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205520 kb
Host smart-7f5f5ed0-9e87-416a-8820-a8231da615b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
27388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3183127388
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2784095767
Short name T1138
Test name
Test status
Simulation time 10091369288 ps
CPU time 13.62 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205532 kb
Host smart-ed1ff744-d967-4014-8682-b4126918f3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27840
95767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2784095767
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1677718235
Short name T732
Test name
Test status
Simulation time 10049460378 ps
CPU time 13.81 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205484 kb
Host smart-46ce98c2-b112-44f7-b784-880b6a6df015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16777
18235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1677718235
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.378023791
Short name T111
Test name
Test status
Simulation time 10065660704 ps
CPU time 16.56 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:15 PM PDT 24
Peak memory 205492 kb
Host smart-9d120a1e-0e8c-4019-85b4-19b16a8d6eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37802
3791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.378023791
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1269897990
Short name T1572
Test name
Test status
Simulation time 10090857333 ps
CPU time 13.45 seconds
Started May 30 03:46:59 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205552 kb
Host smart-f2bfa206-ba30-4cd3-b6cd-9adcf473aa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
97990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1269897990
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3524125916
Short name T1137
Test name
Test status
Simulation time 10039301317 ps
CPU time 13.8 seconds
Started May 30 03:46:57 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205588 kb
Host smart-fea61303-1ef6-4fa5-888b-47b92d6ffa6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35241
25916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3524125916
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.4159763287
Short name T340
Test name
Test status
Simulation time 10077810159 ps
CPU time 13.19 seconds
Started May 30 03:46:59 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205560 kb
Host smart-d4e22894-c665-4142-ad00-3f7fad725903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41597
63287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.4159763287
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3465720539
Short name T1587
Test name
Test status
Simulation time 10079944522 ps
CPU time 13.71 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:12 PM PDT 24
Peak memory 205580 kb
Host smart-2ee6ae16-6e49-4c1d-95cf-16f9abb481bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34657
20539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3465720539
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.599633701
Short name T1760
Test name
Test status
Simulation time 10101351558 ps
CPU time 14.9 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205508 kb
Host smart-6b5310e4-97d4-4065-aa0c-74d61f7443c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59963
3701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.599633701
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3957606532
Short name T1263
Test name
Test status
Simulation time 10043435824 ps
CPU time 13.68 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:22 PM PDT 24
Peak memory 205492 kb
Host smart-d77e1e90-c480-45e7-b41d-bea8369fbd15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39576
06532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3957606532
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2156055758
Short name T1244
Test name
Test status
Simulation time 10036505722 ps
CPU time 12.96 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:24 PM PDT 24
Peak memory 205548 kb
Host smart-6ab87bbd-4f83-47b9-b3c9-e85cfaa09c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21560
55758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2156055758
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1688268250
Short name T1577
Test name
Test status
Simulation time 27325771727 ps
CPU time 55.25 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205608 kb
Host smart-346c02bd-21d8-459d-b03f-e613af6bbcbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
68250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1688268250
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1893902477
Short name T763
Test name
Test status
Simulation time 10066282085 ps
CPU time 16.5 seconds
Started May 30 03:47:00 PM PDT 24
Finished May 30 03:47:20 PM PDT 24
Peak memory 205480 kb
Host smart-22403b8f-25b5-4604-b7a7-8e841dd70542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18939
02477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1893902477
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1951191004
Short name T565
Test name
Test status
Simulation time 10072375141 ps
CPU time 13.71 seconds
Started May 30 03:46:59 PM PDT 24
Finished May 30 03:47:17 PM PDT 24
Peak memory 205544 kb
Host smart-d2d18ca1-111f-466a-9880-68fd8e2198b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19511
91004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1951191004
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_trans.2160469473
Short name T483
Test name
Test status
Simulation time 10063377026 ps
CPU time 15.35 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:24 PM PDT 24
Peak memory 205532 kb
Host smart-035fcca0-8fea-488c-9536-da575973c5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21604
69473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_trans.2160469473
Directory /workspace/40.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.6318021
Short name T1232
Test name
Test status
Simulation time 10085470231 ps
CPU time 14.45 seconds
Started May 30 03:46:55 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205588 kb
Host smart-fc18c6ae-2710-417e-a58d-2090a686ae01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63180
21 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.6318021
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2401804441
Short name T1805
Test name
Test status
Simulation time 10053981856 ps
CPU time 16.43 seconds
Started May 30 03:47:01 PM PDT 24
Finished May 30 03:47:22 PM PDT 24
Peak memory 205240 kb
Host smart-62850e19-0d2a-4c13-8f66-3dcd207fa47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24018
04441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2401804441
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4090299080
Short name T741
Test name
Test status
Simulation time 10083019870 ps
CPU time 15.65 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:18 PM PDT 24
Peak memory 205528 kb
Host smart-028fb980-1e19-4531-b127-7799ad85547f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40902
99080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4090299080
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.683662277
Short name T522
Test name
Test status
Simulation time 10119338513 ps
CPU time 15.77 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205568 kb
Host smart-7fe992d6-0754-4573-a23a-5026a6f4eb0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68366
2277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.683662277
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1328094457
Short name T452
Test name
Test status
Simulation time 10081980732 ps
CPU time 14 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205564 kb
Host smart-2468932f-e597-4e2d-b68b-798d5b85c79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13280
94457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1328094457
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3943148874
Short name T388
Test name
Test status
Simulation time 10060210970 ps
CPU time 13.95 seconds
Started May 30 03:46:58 PM PDT 24
Finished May 30 03:47:16 PM PDT 24
Peak memory 205524 kb
Host smart-4bd5775b-9f65-4577-9b8d-504fbeb6ce31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
48874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3943148874
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.max_length_in_transaction.438652037
Short name T1171
Test name
Test status
Simulation time 10185200155 ps
CPU time 16.4 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205616 kb
Host smart-ba632c03-8da3-4b94-87d6-c60c0ec818cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=438652037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.max_length_in_transaction.438652037
Directory /workspace/41.max_length_in_transaction/latest

Test location /workspace/coverage/default/41.min_length_in_transaction.1029949895
Short name T1722
Test name
Test status
Simulation time 10051224589 ps
CPU time 15.43 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205616 kb
Host smart-f0c0f112-b34a-43bc-9138-62f862bdc73f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1029949895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.min_length_in_transaction.1029949895
Directory /workspace/41.min_length_in_transaction/latest

Test location /workspace/coverage/default/41.random_length_in_trans.2685947784
Short name T412
Test name
Test status
Simulation time 10184374938 ps
CPU time 13.45 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205560 kb
Host smart-5550e860-13c8-406d-9b2f-ac2e3c2530eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26859
47784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.random_length_in_trans.2685947784
Directory /workspace/41.random_length_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.769132725
Short name T1831
Test name
Test status
Simulation time 13583466181 ps
CPU time 16.55 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:28 PM PDT 24
Peak memory 205580 kb
Host smart-4d248c35-352c-4de7-9bab-bb4d2fa51750
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=769132725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.769132725
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1015840223
Short name T1221
Test name
Test status
Simulation time 13279415830 ps
CPU time 16.56 seconds
Started May 30 03:46:53 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205560 kb
Host smart-2990cb81-97ba-4607-9007-020b19ad837d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1015840223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1015840223
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.4087710879
Short name T1604
Test name
Test status
Simulation time 13292195426 ps
CPU time 20.79 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:19 PM PDT 24
Peak memory 205568 kb
Host smart-eca257fa-c27d-4982-b2ea-9cdb904168ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4087710879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.4087710879
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3435273810
Short name T902
Test name
Test status
Simulation time 10046425053 ps
CPU time 15.24 seconds
Started May 30 03:46:54 PM PDT 24
Finished May 30 03:47:14 PM PDT 24
Peak memory 205504 kb
Host smart-195d6e14-5e3c-48f8-bbe6-244fc9c8a0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34352
73810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3435273810
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.187183724
Short name T1147
Test name
Test status
Simulation time 10286096364 ps
CPU time 14.15 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205596 kb
Host smart-6fe856ec-5763-4732-996f-c848b91c1f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18718
3724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.187183724
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.46161965
Short name T770
Test name
Test status
Simulation time 10049668762 ps
CPU time 13.57 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205548 kb
Host smart-be5e78e2-5304-4560-9b95-ba35136bcb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46161
965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.46161965
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3321324778
Short name T219
Test name
Test status
Simulation time 10072583827 ps
CPU time 13.3 seconds
Started May 30 03:47:09 PM PDT 24
Finished May 30 03:47:29 PM PDT 24
Peak memory 205560 kb
Host smart-a8c8c615-5175-4641-9084-d74e6260f812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33213
24778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3321324778
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3430987916
Short name T778
Test name
Test status
Simulation time 10668504848 ps
CPU time 14.92 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205524 kb
Host smart-ddd7c340-44e7-42d5-b326-633a4d1a0ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
87916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3430987916
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.500211929
Short name T954
Test name
Test status
Simulation time 10246492726 ps
CPU time 16.34 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:30 PM PDT 24
Peak memory 205524 kb
Host smart-92d602e5-a8eb-49a2-b424-8aab6f8e254a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50021
1929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.500211929
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1992824116
Short name T1609
Test name
Test status
Simulation time 10096772075 ps
CPU time 14.77 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:24 PM PDT 24
Peak memory 205540 kb
Host smart-5b7130e4-871f-4392-9319-ec8bb022962a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19928
24116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1992824116
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2333959460
Short name T1368
Test name
Test status
Simulation time 10056446979 ps
CPU time 14.69 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205536 kb
Host smart-e606ec88-94e5-4e5e-b975-7b6ad8338da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23339
59460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2333959460
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3189669514
Short name T1168
Test name
Test status
Simulation time 10083252073 ps
CPU time 13.99 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205608 kb
Host smart-34eaadd0-d548-42d1-93dc-2ea017a64f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
69514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3189669514
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2908161112
Short name T840
Test name
Test status
Simulation time 10082148852 ps
CPU time 13.4 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205576 kb
Host smart-e4216c48-51bc-4e6f-b092-1e486eeddf58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081
61112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2908161112
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1003691106
Short name T421
Test name
Test status
Simulation time 13229012807 ps
CPU time 15.89 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205552 kb
Host smart-ae453266-7e73-4aeb-bc22-cca83563debd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10036
91106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1003691106
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1907527173
Short name T326
Test name
Test status
Simulation time 10128259743 ps
CPU time 14.72 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:23 PM PDT 24
Peak memory 205592 kb
Host smart-9fc233bf-bbb6-432d-a1db-b9c8d5ab0bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19075
27173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1907527173
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.4064129390
Short name T754
Test name
Test status
Simulation time 10089896885 ps
CPU time 13.53 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:24 PM PDT 24
Peak memory 205532 kb
Host smart-06f00be6-206b-407d-b52c-aa62e13a7db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40641
29390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.4064129390
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2570150910
Short name T20
Test name
Test status
Simulation time 10090333195 ps
CPU time 13.53 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205532 kb
Host smart-e196c137-9e3d-4458-bbac-486ae90c46c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25701
50910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2570150910
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.3661563474
Short name T1110
Test name
Test status
Simulation time 10153271890 ps
CPU time 13.89 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205548 kb
Host smart-b3012f1f-41d7-4931-b597-1ac1cf8ecd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
63474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.3661563474
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3853541305
Short name T519
Test name
Test status
Simulation time 10076925560 ps
CPU time 13.91 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205636 kb
Host smart-bed46e2b-756b-4783-a45f-785aa88dfc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38535
41305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3853541305
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2961824895
Short name T1605
Test name
Test status
Simulation time 10052678054 ps
CPU time 13.55 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:24 PM PDT 24
Peak memory 205520 kb
Host smart-a8223783-f342-415f-8243-9abb0a7cd832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
24895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2961824895
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3975287303
Short name T181
Test name
Test status
Simulation time 10089334272 ps
CPU time 15.52 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:29 PM PDT 24
Peak memory 205472 kb
Host smart-f57c4693-e9f8-4da8-b4bb-4be2ffb0ccd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752
87303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3975287303
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.1386214712
Short name T331
Test name
Test status
Simulation time 10114271354 ps
CPU time 13.86 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205536 kb
Host smart-625030dd-3a7d-4872-bda7-2c5f27f1c388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862
14712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.1386214712
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2859341455
Short name T620
Test name
Test status
Simulation time 10048313980 ps
CPU time 13.13 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205508 kb
Host smart-3142676c-092f-4639-924b-8c0310660eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28593
41455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2859341455
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.286659546
Short name T1898
Test name
Test status
Simulation time 10045802393 ps
CPU time 16.21 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205516 kb
Host smart-8298c01d-ca6f-40c0-ba1f-5b712cf78a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
9546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.286659546
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3249642649
Short name T42
Test name
Test status
Simulation time 19541233751 ps
CPU time 35.96 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205572 kb
Host smart-1fcabd55-6095-4c43-ad44-949554d5f8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32496
42649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3249642649
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1547870871
Short name T440
Test name
Test status
Simulation time 10066526656 ps
CPU time 15.25 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205540 kb
Host smart-70800d18-1b6b-4240-a3f7-91ff81b3aa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15478
70871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1547870871
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2992679911
Short name T1472
Test name
Test status
Simulation time 10146811999 ps
CPU time 14.8 seconds
Started May 30 03:47:09 PM PDT 24
Finished May 30 03:47:30 PM PDT 24
Peak memory 205540 kb
Host smart-50e248ab-d0d1-42d2-9326-6dced5365002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29926
79911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2992679911
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_trans.1256651825
Short name T1087
Test name
Test status
Simulation time 10067031894 ps
CPU time 14.56 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205604 kb
Host smart-c171f092-115f-4b46-a8d1-aef6a54d7d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
51825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_trans.1256651825
Directory /workspace/41.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.618161553
Short name T1744
Test name
Test status
Simulation time 10064300645 ps
CPU time 12.99 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205536 kb
Host smart-1cd19d42-9e43-4f97-b9dc-5b8d21ba0a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61816
1553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.618161553
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.860462115
Short name T1255
Test name
Test status
Simulation time 10067105130 ps
CPU time 13.61 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205536 kb
Host smart-34985c9b-d9f6-49ae-9849-8b5900d363cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86046
2115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.860462115
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.4278147819
Short name T1134
Test name
Test status
Simulation time 10097705268 ps
CPU time 13.56 seconds
Started May 30 03:47:07 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205540 kb
Host smart-cbbfb381-8520-4fcd-a35d-32ac8a89af9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42781
47819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.4278147819
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1479912697
Short name T1784
Test name
Test status
Simulation time 10113755467 ps
CPU time 16.27 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:28 PM PDT 24
Peak memory 205576 kb
Host smart-a6c8faa7-c9d9-4bc6-a4a4-9ded2f9e7a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14799
12697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1479912697
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1718494783
Short name T897
Test name
Test status
Simulation time 10093707671 ps
CPU time 13.34 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205588 kb
Host smart-ea4f0239-368e-4ab2-b0a6-4fc80796f35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17184
94783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1718494783
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.293237465
Short name T324
Test name
Test status
Simulation time 10046031328 ps
CPU time 13.62 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:28 PM PDT 24
Peak memory 205516 kb
Host smart-ef74a44b-c191-4b4b-bd2c-7e9b425cc608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29323
7465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.293237465
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.max_length_in_transaction.2820430203
Short name T1803
Test name
Test status
Simulation time 10177756462 ps
CPU time 13.78 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:37 PM PDT 24
Peak memory 205584 kb
Host smart-ea1c8244-f295-484f-a46a-4c55166293b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2820430203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.max_length_in_transaction.2820430203
Directory /workspace/42.max_length_in_transaction/latest

Test location /workspace/coverage/default/42.min_length_in_transaction.849346979
Short name T1466
Test name
Test status
Simulation time 10068736573 ps
CPU time 13.72 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205576 kb
Host smart-b890dde7-a435-4c3e-ae90-8514ec103b74
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=849346979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.min_length_in_transaction.849346979
Directory /workspace/42.min_length_in_transaction/latest

Test location /workspace/coverage/default/42.random_length_in_trans.2361937455
Short name T1352
Test name
Test status
Simulation time 10110149110 ps
CPU time 15.15 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205536 kb
Host smart-ecde6a5f-e1a5-4f66-a726-deffab86412a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23619
37455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.random_length_in_trans.2361937455
Directory /workspace/42.random_length_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3520250799
Short name T1632
Test name
Test status
Simulation time 13894597977 ps
CPU time 17.46 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205504 kb
Host smart-46ef1add-c947-4a62-babc-ee9ab4e0c7cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3520250799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3520250799
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3538551885
Short name T877
Test name
Test status
Simulation time 13357402438 ps
CPU time 17.61 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:32 PM PDT 24
Peak memory 205544 kb
Host smart-7737effe-12a8-4d0d-ae34-da35e929fb35
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3538551885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3538551885
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1488617400
Short name T229
Test name
Test status
Simulation time 13241459873 ps
CPU time 19.18 seconds
Started May 30 03:47:07 PM PDT 24
Finished May 30 03:47:32 PM PDT 24
Peak memory 205556 kb
Host smart-5667bc81-d073-4897-96e0-719176f7d030
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1488617400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1488617400
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2283564898
Short name T714
Test name
Test status
Simulation time 10054367405 ps
CPU time 14.21 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205524 kb
Host smart-290a0105-0d0c-4bf5-8883-4983fbe44c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22835
64898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2283564898
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3555995985
Short name T213
Test name
Test status
Simulation time 10063152603 ps
CPU time 15.5 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205544 kb
Host smart-e2b97d3b-3f1e-4a82-8d32-542e3e080bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559
95985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3555995985
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.1127236845
Short name T59
Test name
Test status
Simulation time 10190582491 ps
CPU time 14.87 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205656 kb
Host smart-d57a17ab-77a1-4028-9315-7f3df9598340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11272
36845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1127236845
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1326375972
Short name T755
Test name
Test status
Simulation time 10059054818 ps
CPU time 14.29 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:24 PM PDT 24
Peak memory 205516 kb
Host smart-50e93011-bb49-459d-86bc-8ffc60ec2fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13263
75972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1326375972
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1849339697
Short name T327
Test name
Test status
Simulation time 10065734709 ps
CPU time 13.96 seconds
Started May 30 03:47:06 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205560 kb
Host smart-f9d43b63-ec8f-4121-95e9-c3342e80e3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18493
39697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1849339697
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3625927458
Short name T687
Test name
Test status
Simulation time 10677767229 ps
CPU time 15.54 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205504 kb
Host smart-1ca42a2e-b6df-4c88-90f5-7b3b0450b7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36259
27458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3625927458
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1901096629
Short name T654
Test name
Test status
Simulation time 10118523079 ps
CPU time 15.97 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205556 kb
Host smart-56df2494-76a8-49a0-a53f-1987b6686007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010
96629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1901096629
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.196541892
Short name T1426
Test name
Test status
Simulation time 10100054737 ps
CPU time 13.91 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 205520 kb
Host smart-74db71ad-5a44-4e0c-8977-6d0cd8554b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19654
1892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.196541892
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1526482659
Short name T1266
Test name
Test status
Simulation time 10104861506 ps
CPU time 13.7 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205532 kb
Host smart-43d5d0d0-4154-46ec-8576-d3786af647bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15264
82659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1526482659
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.74251412
Short name T1103
Test name
Test status
Simulation time 10104295719 ps
CPU time 13.31 seconds
Started May 30 03:47:07 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205576 kb
Host smart-19ab3c2a-2618-4aa9-ae3b-232f38d8b26b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74251
412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.74251412
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.2156329605
Short name T513
Test name
Test status
Simulation time 10061932492 ps
CPU time 13.26 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:23 PM PDT 24
Peak memory 205508 kb
Host smart-48bb8fc2-6786-483e-a0ca-ff2c2320e19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21563
29605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.2156329605
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.100045447
Short name T1802
Test name
Test status
Simulation time 13251664186 ps
CPU time 18.76 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:33 PM PDT 24
Peak memory 204768 kb
Host smart-63881322-c3ea-4e26-8e44-3bb370519f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10004
5447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.100045447
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1621329096
Short name T765
Test name
Test status
Simulation time 10087781573 ps
CPU time 14.52 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205532 kb
Host smart-30ba3f38-3086-499a-9778-e6eeeec48173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
29096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1621329096
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3634228766
Short name T1329
Test name
Test status
Simulation time 10050037067 ps
CPU time 13.58 seconds
Started May 30 03:47:10 PM PDT 24
Finished May 30 03:47:30 PM PDT 24
Peak memory 205568 kb
Host smart-c80244b8-8739-46f6-b99d-963d51eef267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36342
28766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3634228766
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3035543687
Short name T1839
Test name
Test status
Simulation time 10106100147 ps
CPU time 15.99 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:30 PM PDT 24
Peak memory 204852 kb
Host smart-d9903043-e965-4624-beb6-1d8a2887e69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355
43687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3035543687
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2256935753
Short name T438
Test name
Test status
Simulation time 10106260508 ps
CPU time 14.93 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205576 kb
Host smart-45889335-f4a3-403f-a37b-8d27bb0f939e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
35753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2256935753
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.826810687
Short name T543
Test name
Test status
Simulation time 10134692833 ps
CPU time 13.53 seconds
Started May 30 03:47:16 PM PDT 24
Finished May 30 03:47:33 PM PDT 24
Peak memory 205496 kb
Host smart-920abe1a-c7d5-42f1-8677-662a7cc0b91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82681
0687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.826810687
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2230074097
Short name T950
Test name
Test status
Simulation time 10048494798 ps
CPU time 16.4 seconds
Started May 30 03:47:13 PM PDT 24
Finished May 30 03:47:34 PM PDT 24
Peak memory 205592 kb
Host smart-1485f7bc-2ba1-48e8-8dbf-f626f23723b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
74097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2230074097
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1564846554
Short name T1770
Test name
Test status
Simulation time 10079395799 ps
CPU time 14.26 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205644 kb
Host smart-2e45e7a2-a449-4577-8cb7-e58ebf4dc757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15648
46554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1564846554
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.911563488
Short name T293
Test name
Test status
Simulation time 10054332464 ps
CPU time 12.97 seconds
Started May 30 03:47:03 PM PDT 24
Finished May 30 03:47:21 PM PDT 24
Peak memory 205520 kb
Host smart-59570377-0c2e-43f0-959d-785542b9b1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91156
3488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.911563488
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.359939041
Short name T1091
Test name
Test status
Simulation time 10069004396 ps
CPU time 14.49 seconds
Started May 30 03:47:05 PM PDT 24
Finished May 30 03:47:26 PM PDT 24
Peak memory 205528 kb
Host smart-324a7555-dd66-4217-a3f8-14a7339ba7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35993
9041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.359939041
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.227353705
Short name T36
Test name
Test status
Simulation time 10039824574 ps
CPU time 13.09 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:36 PM PDT 24
Peak memory 205512 kb
Host smart-df01f995-8782-47be-9a07-b82a5fa0be9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22735
3705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.227353705
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1981184724
Short name T256
Test name
Test status
Simulation time 16619247070 ps
CPU time 28.27 seconds
Started May 30 03:47:09 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205684 kb
Host smart-ee1d3858-095b-4a44-a85b-88500c4e24de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
84724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1981184724
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.682838605
Short name T865
Test name
Test status
Simulation time 10080096244 ps
CPU time 14.21 seconds
Started May 30 03:47:16 PM PDT 24
Finished May 30 03:47:34 PM PDT 24
Peak memory 205560 kb
Host smart-67228cb9-7299-405f-be63-f7ff9f39ab53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68283
8605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.682838605
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3777893134
Short name T894
Test name
Test status
Simulation time 10072969770 ps
CPU time 12.95 seconds
Started May 30 03:47:13 PM PDT 24
Finished May 30 03:47:31 PM PDT 24
Peak memory 205556 kb
Host smart-5c6d417b-c366-4bfb-acb5-fcd284688602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37778
93134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3777893134
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_trans.3293614946
Short name T900
Test name
Test status
Simulation time 10083454958 ps
CPU time 14.28 seconds
Started May 30 03:47:07 PM PDT 24
Finished May 30 03:47:28 PM PDT 24
Peak memory 205524 kb
Host smart-c0507361-d7a6-45b7-a8d9-ef6d258df1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32936
14946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_trans.3293614946
Directory /workspace/42.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1213927167
Short name T1356
Test name
Test status
Simulation time 10066581017 ps
CPU time 14.27 seconds
Started May 30 03:47:09 PM PDT 24
Finished May 30 03:47:30 PM PDT 24
Peak memory 205600 kb
Host smart-7619d36d-77b3-4af9-9510-1bc05d4f7783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12139
27167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1213927167
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.739291975
Short name T1288
Test name
Test status
Simulation time 10050311827 ps
CPU time 13.41 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:36 PM PDT 24
Peak memory 205496 kb
Host smart-3e7915ba-b250-481c-85af-0057f952cec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73929
1975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.739291975
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2388598182
Short name T1240
Test name
Test status
Simulation time 10084758561 ps
CPU time 16.3 seconds
Started May 30 03:47:16 PM PDT 24
Finished May 30 03:47:36 PM PDT 24
Peak memory 205480 kb
Host smart-9fa272a9-4923-4eae-8984-ba9b593f28f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
98182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2388598182
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2937174418
Short name T138
Test name
Test status
Simulation time 10120621788 ps
CPU time 14.8 seconds
Started May 30 03:47:04 PM PDT 24
Finished May 30 03:47:25 PM PDT 24
Peak memory 205572 kb
Host smart-5cbad105-d352-4a74-a273-6f587dc7b7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
74418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2937174418
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1776972578
Short name T1764
Test name
Test status
Simulation time 10083443079 ps
CPU time 12.93 seconds
Started May 30 03:47:08 PM PDT 24
Finished May 30 03:47:27 PM PDT 24
Peak memory 205504 kb
Host smart-84610fe2-8c50-40b4-b2f0-794c60a86fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
72578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1776972578
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2974534890
Short name T1416
Test name
Test status
Simulation time 10045755682 ps
CPU time 13.67 seconds
Started May 30 03:47:09 PM PDT 24
Finished May 30 03:47:29 PM PDT 24
Peak memory 205628 kb
Host smart-8d77fe14-b686-4fe2-8cca-42e36733c091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
34890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2974534890
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.max_length_in_transaction.170966067
Short name T330
Test name
Test status
Simulation time 10161648887 ps
CPU time 14.39 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205608 kb
Host smart-91c6f373-9594-4563-8087-602d86d80e7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=170966067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.max_length_in_transaction.170966067
Directory /workspace/43.max_length_in_transaction/latest

Test location /workspace/coverage/default/43.min_length_in_transaction.1922721281
Short name T1806
Test name
Test status
Simulation time 10126515081 ps
CPU time 14.38 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205596 kb
Host smart-20005e46-5c8d-41e8-a2df-27c1a0e96233
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1922721281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.min_length_in_transaction.1922721281
Directory /workspace/43.min_length_in_transaction/latest

Test location /workspace/coverage/default/43.random_length_in_trans.3777410504
Short name T1306
Test name
Test status
Simulation time 10149381881 ps
CPU time 13.87 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205572 kb
Host smart-f6060496-0dc5-457b-8474-de3f6d93d699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37774
10504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.random_length_in_trans.3777410504
Directory /workspace/43.random_length_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.77018124
Short name T344
Test name
Test status
Simulation time 13659505404 ps
CPU time 17.82 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:45 PM PDT 24
Peak memory 205580 kb
Host smart-8ac1b21a-0082-44b6-b138-954a312064ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=77018124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.77018124
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3859735160
Short name T49
Test name
Test status
Simulation time 13270471488 ps
CPU time 18.3 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205584 kb
Host smart-83b32c56-5612-41a1-86dd-be3a8c214a67
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3859735160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3859735160
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3472470258
Short name T1415
Test name
Test status
Simulation time 13357192241 ps
CPU time 17.57 seconds
Started May 30 03:47:19 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205552 kb
Host smart-b3dc6355-166a-4c90-90f5-eef2b494e00d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3472470258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3472470258
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1048092724
Short name T1395
Test name
Test status
Simulation time 10097928612 ps
CPU time 13.24 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205528 kb
Host smart-299230b2-1ea6-4258-81e5-0477497c0fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10480
92724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1048092724
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.271308223
Short name T1075
Test name
Test status
Simulation time 10203743801 ps
CPU time 13.5 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:36 PM PDT 24
Peak memory 205560 kb
Host smart-3624787b-a52a-4d6b-bd66-25abd1f60280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27130
8223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.271308223
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.110428602
Short name T1359
Test name
Test status
Simulation time 10061748301 ps
CPU time 14.06 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205500 kb
Host smart-c667072a-2531-4112-96ae-61a6686ec626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
8602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.110428602
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3068869876
Short name T940
Test name
Test status
Simulation time 10050872144 ps
CPU time 13.92 seconds
Started May 30 03:47:19 PM PDT 24
Finished May 30 03:47:36 PM PDT 24
Peak memory 205656 kb
Host smart-c12ef671-261e-4ba9-8265-3e0593c7a672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
69876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3068869876
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1145823466
Short name T753
Test name
Test status
Simulation time 10701131381 ps
CPU time 14.51 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205536 kb
Host smart-db5fc9e4-fe1e-4294-a266-98fdf40986ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11458
23466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1145823466
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1724911992
Short name T1544
Test name
Test status
Simulation time 10191248499 ps
CPU time 14.44 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:37 PM PDT 24
Peak memory 205520 kb
Host smart-2f5e4bc7-0688-4d7a-ad95-85ab89b911a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
11992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1724911992
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2777368744
Short name T283
Test name
Test status
Simulation time 10126589656 ps
CPU time 13.14 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205564 kb
Host smart-792bc194-568a-4cc5-801c-a272187eba35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27773
68744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2777368744
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.572216499
Short name T844
Test name
Test status
Simulation time 10042200988 ps
CPU time 14.09 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205532 kb
Host smart-3c1b1614-6f5a-43b5-92f5-0ee1a745ef04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57221
6499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.572216499
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3571282362
Short name T487
Test name
Test status
Simulation time 10065998940 ps
CPU time 13.59 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 205560 kb
Host smart-b8e49542-ae1f-4982-ad55-31234c8e6326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
82362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3571282362
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3156965731
Short name T297
Test name
Test status
Simulation time 10102656284 ps
CPU time 14.26 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205500 kb
Host smart-0558cbe4-3578-4275-a941-069821385f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31569
65731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3156965731
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3284064507
Short name T658
Test name
Test status
Simulation time 13213452967 ps
CPU time 17.08 seconds
Started May 30 03:47:19 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205512 kb
Host smart-3477ffe8-c34c-428a-ab88-6fa65e00669f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32840
64507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3284064507
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2289730070
Short name T482
Test name
Test status
Simulation time 10126582893 ps
CPU time 13.95 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205576 kb
Host smart-65ac1246-2b71-4a5d-aa23-475af462df5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
30070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2289730070
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2066838304
Short name T771
Test name
Test status
Simulation time 10040072086 ps
CPU time 13.09 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205548 kb
Host smart-6a171415-5792-48f6-9093-6add84905831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20668
38304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2066838304
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2865959295
Short name T115
Test name
Test status
Simulation time 10089082615 ps
CPU time 14.15 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205388 kb
Host smart-a5c1dd5f-4c0f-4106-a00c-a22f86d5dc6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28659
59295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2865959295
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.4085458961
Short name T426
Test name
Test status
Simulation time 10124209506 ps
CPU time 15.09 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 205508 kb
Host smart-b8c3e794-8526-41ff-b619-3d42fa5caaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40854
58961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.4085458961
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3382095226
Short name T1648
Test name
Test status
Simulation time 10083007285 ps
CPU time 14.51 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205528 kb
Host smart-10984bd0-435c-4648-a27e-91435991c114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33820
95226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3382095226
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1329499562
Short name T621
Test name
Test status
Simulation time 10123508883 ps
CPU time 15.82 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205572 kb
Host smart-e4e7949d-f968-448e-986a-3fc0bbded378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13294
99562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1329499562
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1898596840
Short name T131
Test name
Test status
Simulation time 10067405610 ps
CPU time 13.82 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205560 kb
Host smart-4507dff6-ddb4-40b8-a614-2ffc7871f3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18985
96840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1898596840
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.1516043172
Short name T1441
Test name
Test status
Simulation time 10087770163 ps
CPU time 13.84 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:36 PM PDT 24
Peak memory 205540 kb
Host smart-ce44cc95-8ca7-4d55-bcbb-111f980c0665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160
43172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.1516043172
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.538674573
Short name T38
Test name
Test status
Simulation time 10044595367 ps
CPU time 13.97 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205576 kb
Host smart-d116b201-173e-4909-98c4-79fff9a9e08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53867
4573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.538674573
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2247335252
Short name T1214
Test name
Test status
Simulation time 10052539158 ps
CPU time 14.01 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 205604 kb
Host smart-c9fda277-f1ac-42e4-90e6-aec65cd70b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22473
35252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2247335252
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2521542404
Short name T1132
Test name
Test status
Simulation time 10074926989 ps
CPU time 13.57 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:37 PM PDT 24
Peak memory 205548 kb
Host smart-551b38f5-0af2-4ad4-aba7-048368282eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25215
42404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2521542404
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.281722605
Short name T1669
Test name
Test status
Simulation time 10070629998 ps
CPU time 12.86 seconds
Started May 30 03:47:24 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205556 kb
Host smart-f72292d2-4465-4c10-9964-d3d436d4b3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28172
2605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.281722605
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_trans.1498028338
Short name T1322
Test name
Test status
Simulation time 10093662457 ps
CPU time 13.35 seconds
Started May 30 03:47:20 PM PDT 24
Finished May 30 03:47:37 PM PDT 24
Peak memory 205524 kb
Host smart-618bf243-b408-4592-bb85-36e1d940d3d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
28338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_trans.1498028338
Directory /workspace/43.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1394356519
Short name T1332
Test name
Test status
Simulation time 10055648399 ps
CPU time 15.86 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:44 PM PDT 24
Peak memory 205524 kb
Host smart-f3fa0087-3e7a-4ebf-b27a-2d4f9b548b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13943
56519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1394356519
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.287921754
Short name T607
Test name
Test status
Simulation time 10093752890 ps
CPU time 12.58 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205568 kb
Host smart-9fffeda1-aa97-4210-9708-1422bbf0207f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28792
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.287921754
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.183190153
Short name T839
Test name
Test status
Simulation time 10094843254 ps
CPU time 13.71 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205576 kb
Host smart-e6825242-015d-4d81-a8f4-a4c274c2dc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18319
0153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.183190153
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3799816603
Short name T1247
Test name
Test status
Simulation time 10153634273 ps
CPU time 13.36 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:39 PM PDT 24
Peak memory 205548 kb
Host smart-40a93b7d-d49c-4912-ac31-d2b315c4fa28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
16603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3799816603
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3169339292
Short name T345
Test name
Test status
Simulation time 10076031212 ps
CPU time 14.36 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 205556 kb
Host smart-86c39026-7631-4778-94ee-9f4d7b44a4d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31693
39292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3169339292
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1567563437
Short name T1815
Test name
Test status
Simulation time 10048488148 ps
CPU time 15.21 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205576 kb
Host smart-85890cd6-88e2-491f-9190-ff82f4e74af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15675
63437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1567563437
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.max_length_in_transaction.1743765225
Short name T1334
Test name
Test status
Simulation time 10190706392 ps
CPU time 13.51 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:48 PM PDT 24
Peak memory 205560 kb
Host smart-2f7a9996-0939-413b-bd35-f07ebc4c839b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1743765225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.max_length_in_transaction.1743765225
Directory /workspace/44.max_length_in_transaction/latest

Test location /workspace/coverage/default/44.min_length_in_transaction.3198243044
Short name T1651
Test name
Test status
Simulation time 10142011524 ps
CPU time 14.42 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205584 kb
Host smart-78aee9d3-29eb-44ae-b7ec-e5c4f3f32a6b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3198243044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.min_length_in_transaction.3198243044
Directory /workspace/44.min_length_in_transaction/latest

Test location /workspace/coverage/default/44.random_length_in_trans.694476348
Short name T1251
Test name
Test status
Simulation time 10121811830 ps
CPU time 15.08 seconds
Started May 30 03:47:44 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205512 kb
Host smart-c142d019-34c3-4c81-ab77-48fc9c7a7b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69447
6348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.random_length_in_trans.694476348
Directory /workspace/44.random_length_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1744388951
Short name T349
Test name
Test status
Simulation time 14112115866 ps
CPU time 17.42 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205588 kb
Host smart-af39b66e-4fb3-49d2-9bd3-fb694b690a6f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1744388951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.1744388951
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2389806323
Short name T1779
Test name
Test status
Simulation time 13326458050 ps
CPU time 17.7 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:45 PM PDT 24
Peak memory 205524 kb
Host smart-269d910e-6432-4927-89e1-f380ef9103ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2389806323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2389806323
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1830922607
Short name T594
Test name
Test status
Simulation time 13260790073 ps
CPU time 17.34 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205544 kb
Host smart-efd4cedc-46dd-4125-87bb-494b2039ae05
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1830922607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.1830922607
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.944191681
Short name T1389
Test name
Test status
Simulation time 10050297945 ps
CPU time 13.32 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205456 kb
Host smart-467ac0a9-95fc-4ee2-bcf4-4a223f1efeab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94419
1681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.944191681
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2652034485
Short name T1823
Test name
Test status
Simulation time 11020672935 ps
CPU time 15.34 seconds
Started May 30 03:47:25 PM PDT 24
Finished May 30 03:47:44 PM PDT 24
Peak memory 205568 kb
Host smart-c0a24696-2de9-4685-9ae4-80de1f74306c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
34485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2652034485
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2188777998
Short name T1248
Test name
Test status
Simulation time 10043896367 ps
CPU time 12.83 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:40 PM PDT 24
Peak memory 205476 kb
Host smart-4def2551-7261-4fa1-9b5d-d66cf39543ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887
77998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2188777998
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2408108673
Short name T1478
Test name
Test status
Simulation time 10063153542 ps
CPU time 14.79 seconds
Started May 30 03:47:24 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205576 kb
Host smart-9009fae4-8b3e-428c-838a-863c46837787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24081
08673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2408108673
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3706019333
Short name T351
Test name
Test status
Simulation time 10947776747 ps
CPU time 16.18 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205572 kb
Host smart-2b347d75-fcb8-4e53-b7b7-b63b9cbb1b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
19333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3706019333
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1823625654
Short name T535
Test name
Test status
Simulation time 10281025365 ps
CPU time 15.05 seconds
Started May 30 03:47:24 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205552 kb
Host smart-8abe82ac-e175-4f22-b9ab-2808abb6938f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
25654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1823625654
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3957276283
Short name T1079
Test name
Test status
Simulation time 10102440732 ps
CPU time 13.84 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205552 kb
Host smart-b0ba31fe-f811-4781-b42b-bb32a22a5740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39572
76283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3957276283
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3301843703
Short name T1005
Test name
Test status
Simulation time 10058991344 ps
CPU time 15.92 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205536 kb
Host smart-1e6b6d33-5e27-4dca-85fe-ba4cd750e4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
43703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3301843703
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3757102100
Short name T1390
Test name
Test status
Simulation time 10063400707 ps
CPU time 13.44 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:38 PM PDT 24
Peak memory 205544 kb
Host smart-68bc9bb9-1d98-4be0-b47e-d185d14ec426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
02100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3757102100
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1975417597
Short name T1538
Test name
Test status
Simulation time 10057927307 ps
CPU time 15.34 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:43 PM PDT 24
Peak memory 205508 kb
Host smart-eebd0a9f-6273-4fa7-a04f-b7d7c6fcd6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
17597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1975417597
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.505245546
Short name T1644
Test name
Test status
Simulation time 13246573799 ps
CPU time 17.11 seconds
Started May 30 03:47:21 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205520 kb
Host smart-428b686f-9c4e-4293-a864-9adda1ae3af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50524
5546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.505245546
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2281430667
Short name T1016
Test name
Test status
Simulation time 10097613357 ps
CPU time 14.97 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205508 kb
Host smart-53c676e0-37b8-4609-96c4-737ee1ea84d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22814
30667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2281430667
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1150375966
Short name T1373
Test name
Test status
Simulation time 10054895383 ps
CPU time 15.37 seconds
Started May 30 03:47:23 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205584 kb
Host smart-202c9465-3b7e-4a39-aa57-5f029c227cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
75966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1150375966
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.560395492
Short name T124
Test name
Test status
Simulation time 10096885251 ps
CPU time 14.25 seconds
Started May 30 03:47:24 PM PDT 24
Finished May 30 03:47:42 PM PDT 24
Peak memory 205472 kb
Host smart-37bc8285-2eec-4e7a-aa06-3bc319f3e195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56039
5492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.560395492
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.4087340868
Short name T1445
Test name
Test status
Simulation time 10090961188 ps
CPU time 13.29 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:49 PM PDT 24
Peak memory 205536 kb
Host smart-8bff0096-55e6-448c-88c4-3689405de63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873
40868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.4087340868
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.232051229
Short name T913
Test name
Test status
Simulation time 10059072556 ps
CPU time 16.38 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205544 kb
Host smart-31a56727-ebdb-42d8-b4fc-e89bf6484ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
1229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.232051229
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2288866528
Short name T442
Test name
Test status
Simulation time 10064464481 ps
CPU time 13.29 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205544 kb
Host smart-676351e5-d352-43ab-bfb6-8a136964bb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888
66528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2288866528
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.3382648021
Short name T81
Test name
Test status
Simulation time 10091660782 ps
CPU time 14.35 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205544 kb
Host smart-6c7f6e5d-28f2-4710-88bc-bdd6aa0dcddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33826
48021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.3382648021
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1542410418
Short name T359
Test name
Test status
Simulation time 10113187574 ps
CPU time 14.73 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205528 kb
Host smart-752656b7-fb37-4c25-8413-22dc5c7997bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
10418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1542410418
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2988941045
Short name T1074
Test name
Test status
Simulation time 10033555337 ps
CPU time 12.33 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205528 kb
Host smart-62e7ebea-16c3-49d2-849f-0546355f30a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29889
41045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2988941045
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1077917950
Short name T1067
Test name
Test status
Simulation time 26661311405 ps
CPU time 53.39 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:48:28 PM PDT 24
Peak memory 205596 kb
Host smart-41a1121e-fbea-46f7-bff0-a14074963aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10779
17950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1077917950
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.455340143
Short name T1530
Test name
Test status
Simulation time 10161812510 ps
CPU time 15.48 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205464 kb
Host smart-9a205a49-dbb1-4154-8b72-7a96ec72f8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45534
0143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.455340143
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1055028052
Short name T502
Test name
Test status
Simulation time 10143063976 ps
CPU time 13.59 seconds
Started May 30 03:47:30 PM PDT 24
Finished May 30 03:47:45 PM PDT 24
Peak memory 205516 kb
Host smart-52bd2a5d-2973-4b40-b904-d6ac700b6e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
28052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1055028052
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_trans.490291748
Short name T952
Test name
Test status
Simulation time 10085562214 ps
CPU time 13.23 seconds
Started May 30 03:47:31 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205548 kb
Host smart-6d850a70-b683-43d0-b595-284363271f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49029
1748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_trans.490291748
Directory /workspace/44.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.4177133267
Short name T647
Test name
Test status
Simulation time 10038854843 ps
CPU time 12.58 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:47 PM PDT 24
Peak memory 205528 kb
Host smart-55f21443-1e88-4778-8916-45f8ef002a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41771
33267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.4177133267
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2230473826
Short name T140
Test name
Test status
Simulation time 10095820190 ps
CPU time 14.54 seconds
Started May 30 03:47:32 PM PDT 24
Finished May 30 03:47:48 PM PDT 24
Peak memory 205580 kb
Host smart-843a3680-1973-4211-8009-c569c5cd954c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304
73826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2230473826
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2847631515
Short name T1313
Test name
Test status
Simulation time 10064989421 ps
CPU time 13.12 seconds
Started May 30 03:47:39 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205592 kb
Host smart-6e4e18b7-fe21-4f16-810b-e12ad52d50d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28476
31515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2847631515
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2444331954
Short name T153
Test name
Test status
Simulation time 10128746554 ps
CPU time 14.45 seconds
Started May 30 03:47:22 PM PDT 24
Finished May 30 03:47:41 PM PDT 24
Peak memory 205596 kb
Host smart-6624fe68-8c99-4e36-8f08-396140501bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443
31954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2444331954
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.2314131213
Short name T1210
Test name
Test status
Simulation time 10072471405 ps
CPU time 13.54 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205564 kb
Host smart-8a709ce8-ce97-4588-a065-bcf3d805eb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23141
31213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.2314131213
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3841098806
Short name T701
Test name
Test status
Simulation time 10060122972 ps
CPU time 14.75 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205632 kb
Host smart-d81ef5c9-8c21-46c9-b7bf-4f8a6c67ac9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38410
98806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3841098806
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.max_length_in_transaction.3698879492
Short name T981
Test name
Test status
Simulation time 10188771922 ps
CPU time 15.19 seconds
Started May 30 03:47:32 PM PDT 24
Finished May 30 03:47:48 PM PDT 24
Peak memory 205608 kb
Host smart-40acd46c-cfda-4fa8-8078-0e2eab1c6efc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3698879492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.max_length_in_transaction.3698879492
Directory /workspace/45.max_length_in_transaction/latest

Test location /workspace/coverage/default/45.min_length_in_transaction.3952692477
Short name T1250
Test name
Test status
Simulation time 10056968171 ps
CPU time 14.03 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205532 kb
Host smart-33b843b6-ec91-41ef-92e4-adf6a84d86cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3952692477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.min_length_in_transaction.3952692477
Directory /workspace/45.min_length_in_transaction/latest

Test location /workspace/coverage/default/45.random_length_in_trans.258414979
Short name T830
Test name
Test status
Simulation time 10068560699 ps
CPU time 14.28 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205516 kb
Host smart-622ed3ce-e223-4d19-9fe4-168e287ca5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25841
4979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.random_length_in_trans.258414979
Directory /workspace/45.random_length_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.457441505
Short name T1460
Test name
Test status
Simulation time 14182275180 ps
CPU time 16.56 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:56 PM PDT 24
Peak memory 205544 kb
Host smart-727440da-d00a-4186-86d8-bfb43c8359ca
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=457441505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.457441505
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.664416610
Short name T1874
Test name
Test status
Simulation time 13316203202 ps
CPU time 16.99 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205552 kb
Host smart-16b83263-15bf-4424-8a28-ac8a4e7828d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=664416610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.664416610
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3676600964
Short name T829
Test name
Test status
Simulation time 13321313089 ps
CPU time 19.11 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205604 kb
Host smart-b9d8a2a0-cfe0-47ad-bafe-5a80f92bea57
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3676600964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3676600964
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3408418221
Short name T1252
Test name
Test status
Simulation time 10054737413 ps
CPU time 17.2 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205516 kb
Host smart-fb54b580-125b-4d81-bd65-9a5ee9edb256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
18221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3408418221
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.600658088
Short name T1913
Test name
Test status
Simulation time 10069441425 ps
CPU time 16.45 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205540 kb
Host smart-852057b2-4e51-46d5-811e-b93a17838bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60065
8088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.600658088
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3777106467
Short name T58
Test name
Test status
Simulation time 10932756918 ps
CPU time 15.37 seconds
Started May 30 03:47:32 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205520 kb
Host smart-208a9e35-197c-4d6c-aac9-a3ff6988e0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37771
06467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3777106467
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3786064921
Short name T708
Test name
Test status
Simulation time 10040802540 ps
CPU time 13.01 seconds
Started May 30 03:47:31 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205596 kb
Host smart-a4bdaab2-09df-4ff9-83b5-aaac53e06ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37860
64921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3786064921
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3862231727
Short name T1733
Test name
Test status
Simulation time 10055737109 ps
CPU time 13.14 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:48 PM PDT 24
Peak memory 205620 kb
Host smart-144552bc-4461-45c8-80e4-0608f8ac44db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
31727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3862231727
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2254729435
Short name T857
Test name
Test status
Simulation time 10661572238 ps
CPU time 16.06 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205552 kb
Host smart-95d43367-682b-4e6b-ba10-96cd373bc61c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22547
29435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2254729435
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3268437311
Short name T1845
Test name
Test status
Simulation time 10173123896 ps
CPU time 15.57 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205536 kb
Host smart-569acb02-7bca-45c4-af49-3f49c10b4d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
37311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3268437311
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2000820780
Short name T1859
Test name
Test status
Simulation time 10177605567 ps
CPU time 13.73 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205564 kb
Host smart-762d4942-f21a-4f46-b51a-b62661ad877f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20008
20780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2000820780
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3652300692
Short name T1482
Test name
Test status
Simulation time 10065856395 ps
CPU time 15.69 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205572 kb
Host smart-9864142b-0862-468c-bb1f-aa0067506bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36523
00692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3652300692
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2777565554
Short name T387
Test name
Test status
Simulation time 10122662617 ps
CPU time 15.44 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205508 kb
Host smart-8c90b7ef-161b-4dd3-9e08-89afc9343f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
65554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2777565554
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3111529249
Short name T1920
Test name
Test status
Simulation time 10077643936 ps
CPU time 15.68 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205584 kb
Host smart-e4edbfae-e400-4955-90bc-d3c73ba8305f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31115
29249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3111529249
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3965519948
Short name T451
Test name
Test status
Simulation time 13184979164 ps
CPU time 16.78 seconds
Started May 30 03:47:31 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205520 kb
Host smart-7a2ca3ec-6145-4d0a-81f4-76b89b26f000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39655
19948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3965519948
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2277781865
Short name T86
Test name
Test status
Simulation time 10102490105 ps
CPU time 13.82 seconds
Started May 30 03:47:32 PM PDT 24
Finished May 30 03:47:47 PM PDT 24
Peak memory 205620 kb
Host smart-f49541d9-6580-471d-a172-40e6e25b8e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22777
81865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2277781865
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2756922180
Short name T893
Test name
Test status
Simulation time 10053057066 ps
CPU time 16.66 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205548 kb
Host smart-c68becaf-8c3f-4e25-9c97-50037be32754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27569
22180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2756922180
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2181103034
Short name T1479
Test name
Test status
Simulation time 10074989715 ps
CPU time 13.53 seconds
Started May 30 03:47:31 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205516 kb
Host smart-4919cdc7-d45f-4473-bd3f-f5a6e1a7faf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811
03034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2181103034
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3580288506
Short name T315
Test name
Test status
Simulation time 10100746296 ps
CPU time 13.16 seconds
Started May 30 03:47:32 PM PDT 24
Finished May 30 03:47:47 PM PDT 24
Peak memory 205520 kb
Host smart-42ddd8f3-ca81-4519-9321-27c2cae8db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35802
88506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3580288506
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1747986455
Short name T1340
Test name
Test status
Simulation time 10057710889 ps
CPU time 13.3 seconds
Started May 30 03:47:31 PM PDT 24
Finished May 30 03:47:46 PM PDT 24
Peak memory 205568 kb
Host smart-8a591f6b-5864-4beb-88b8-7e2a9a44adb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17479
86455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1747986455
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1608290247
Short name T533
Test name
Test status
Simulation time 10047906682 ps
CPU time 13.58 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205512 kb
Host smart-c4ea31c7-9340-45a9-a4dd-a27238c005b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16082
90247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1608290247
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1463735178
Short name T177
Test name
Test status
Simulation time 10083012099 ps
CPU time 13.84 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205580 kb
Host smart-a2ce8bd7-2d1e-4168-9055-d395336358f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14637
35178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1463735178
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.2896342930
Short name T599
Test name
Test status
Simulation time 10071796506 ps
CPU time 16.4 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205516 kb
Host smart-94b976a1-9baf-40d8-840c-c4d82a3d21cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28963
42930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.2896342930
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2366551184
Short name T582
Test name
Test status
Simulation time 10096198730 ps
CPU time 12.84 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205536 kb
Host smart-93c0099e-b2fa-44c8-be90-e0d3013eda32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
51184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2366551184
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2538224321
Short name T1579
Test name
Test status
Simulation time 10041825498 ps
CPU time 13.82 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205548 kb
Host smart-eee28ab9-8126-4ae7-a6cd-ba1a9843ebfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25382
24321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2538224321
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1093856717
Short name T1555
Test name
Test status
Simulation time 22684049209 ps
CPU time 40.44 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:48:20 PM PDT 24
Peak memory 205580 kb
Host smart-f8895c0d-76d0-4455-9912-45b5fe2079df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10938
56717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1093856717
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.169884489
Short name T1797
Test name
Test status
Simulation time 10136555513 ps
CPU time 13.99 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205524 kb
Host smart-f403a163-1305-48d3-b6d8-b67250190c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16988
4489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.169884489
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3033740843
Short name T1904
Test name
Test status
Simulation time 10130966145 ps
CPU time 14.03 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:49 PM PDT 24
Peak memory 205528 kb
Host smart-9d52cfed-c412-4d0d-a5c9-3e3bd5143a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30337
40843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3033740843
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_trans.2746533077
Short name T392
Test name
Test status
Simulation time 10119079092 ps
CPU time 13.69 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205580 kb
Host smart-fa3bb570-035c-4ff8-b72a-71966f012bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
33077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_trans.2746533077
Directory /workspace/45.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2564448964
Short name T1384
Test name
Test status
Simulation time 10075202849 ps
CPU time 14.3 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205512 kb
Host smart-32d6f48b-4f0c-41c7-97fe-1232e3bde092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25644
48964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2564448964
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2600045770
Short name T1400
Test name
Test status
Simulation time 10053341624 ps
CPU time 14.98 seconds
Started May 30 03:47:31 PM PDT 24
Finished May 30 03:47:48 PM PDT 24
Peak memory 205512 kb
Host smart-bd0aa3b7-c85c-4037-be71-a493e12aa938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26000
45770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2600045770
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.476082752
Short name T978
Test name
Test status
Simulation time 10114716700 ps
CPU time 14.54 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205568 kb
Host smart-67201c8f-52f8-457b-8c67-d32e3f6ce2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47608
2752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.476082752
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2757888426
Short name T1198
Test name
Test status
Simulation time 10142114481 ps
CPU time 17.03 seconds
Started May 30 03:47:32 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205560 kb
Host smart-39031ce1-31b4-4094-a452-b832aebd2a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578
88426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2757888426
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2922217714
Short name T917
Test name
Test status
Simulation time 10084589016 ps
CPU time 13.97 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205536 kb
Host smart-1db73eb5-414b-4475-92a0-ebbb1f3baab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29222
17714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2922217714
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3294798195
Short name T1877
Test name
Test status
Simulation time 10062025747 ps
CPU time 17.18 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205496 kb
Host smart-19b94011-0a6f-495b-8632-881638c91d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
98195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3294798195
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.max_length_in_transaction.2891444972
Short name T951
Test name
Test status
Simulation time 10149753386 ps
CPU time 15.21 seconds
Started May 30 03:47:39 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205492 kb
Host smart-c3a5fbf9-f55b-4321-aaa7-c421a9bb3610
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2891444972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.max_length_in_transaction.2891444972
Directory /workspace/46.max_length_in_transaction/latest

Test location /workspace/coverage/default/46.min_length_in_transaction.132947007
Short name T617
Test name
Test status
Simulation time 10058489438 ps
CPU time 14.32 seconds
Started May 30 03:47:38 PM PDT 24
Finished May 30 03:47:56 PM PDT 24
Peak memory 205472 kb
Host smart-f7a9d107-c349-4222-9851-25f6b9fd74f1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=132947007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.min_length_in_transaction.132947007
Directory /workspace/46.min_length_in_transaction/latest

Test location /workspace/coverage/default/46.random_length_in_trans.832701616
Short name T973
Test name
Test status
Simulation time 10167039750 ps
CPU time 13.18 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:53 PM PDT 24
Peak memory 205496 kb
Host smart-c30e937e-0cbd-49b0-ab75-2bffd71deb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83270
1616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.random_length_in_trans.832701616
Directory /workspace/46.random_length_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2501700448
Short name T797
Test name
Test status
Simulation time 14192204034 ps
CPU time 19.6 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:56 PM PDT 24
Peak memory 205540 kb
Host smart-0b5f07e2-913b-4a90-b326-3ddeb7c22449
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2501700448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2501700448
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.969220655
Short name T1835
Test name
Test status
Simulation time 13239521230 ps
CPU time 16.58 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:54 PM PDT 24
Peak memory 205580 kb
Host smart-de42a7de-f354-4513-8c13-713195c0f8a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=969220655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.969220655
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1153395269
Short name T631
Test name
Test status
Simulation time 13374773856 ps
CPU time 16.62 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205528 kb
Host smart-530c8095-39e4-4f2d-bf25-1df627f32dc5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1153395269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.1153395269
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.206355200
Short name T1749
Test name
Test status
Simulation time 10075538737 ps
CPU time 13.97 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:51 PM PDT 24
Peak memory 205584 kb
Host smart-30191ac1-7b10-4693-8f6e-dce8c0cb30ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20635
5200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.206355200
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1356886606
Short name T509
Test name
Test status
Simulation time 10048604006 ps
CPU time 13.85 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205520 kb
Host smart-8a2e5100-3324-45ca-932b-a1f798bd0e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13568
86606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1356886606
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1162240712
Short name T1398
Test name
Test status
Simulation time 10530746258 ps
CPU time 14.27 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:54 PM PDT 24
Peak memory 205652 kb
Host smart-b7b5f77e-f295-498c-9e04-2a9800a27dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11622
40712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1162240712
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.74325069
Short name T1608
Test name
Test status
Simulation time 10062241107 ps
CPU time 16.17 seconds
Started May 30 03:47:39 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205544 kb
Host smart-53928338-6056-4422-9f0a-80d982d0b597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74325
069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.74325069
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3522195113
Short name T1864
Test name
Test status
Simulation time 10054678419 ps
CPU time 17.34 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205616 kb
Host smart-a27abf91-6c1a-4493-9bcb-a3366e3982b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35221
95113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3522195113
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.586734462
Short name T1700
Test name
Test status
Simulation time 10669129218 ps
CPU time 17.81 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205564 kb
Host smart-13ba2e9d-7dd3-4c47-b6e8-d4fb33d14ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58673
4462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.586734462
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2237071043
Short name T1029
Test name
Test status
Simulation time 10148040418 ps
CPU time 14.33 seconds
Started May 30 03:47:40 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205540 kb
Host smart-18845b5e-cfdc-4c13-beba-fb2cc27ebf7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22370
71043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2237071043
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2176338632
Short name T1694
Test name
Test status
Simulation time 10129623209 ps
CPU time 15.78 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205520 kb
Host smart-0ed5b54b-8270-414b-a269-1a03f5c299ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21763
38632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2176338632
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3114542536
Short name T632
Test name
Test status
Simulation time 10073931746 ps
CPU time 15.16 seconds
Started May 30 03:47:38 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205524 kb
Host smart-6452ccb6-0e4a-4d19-99bd-0fff502907b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31145
42536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3114542536
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1723672258
Short name T643
Test name
Test status
Simulation time 10130248255 ps
CPU time 15.55 seconds
Started May 30 03:47:40 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205576 kb
Host smart-62019e9c-709e-4583-a36e-d756dd49ba5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17236
72258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1723672258
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3689556671
Short name T918
Test name
Test status
Simulation time 10084998587 ps
CPU time 13.38 seconds
Started May 30 03:47:40 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205580 kb
Host smart-36675020-918a-4c0f-9908-cd947be9747b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36895
56671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3689556671
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.903441723
Short name T1698
Test name
Test status
Simulation time 13179313431 ps
CPU time 17.86 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205532 kb
Host smart-723a4641-6fe7-497b-8f85-f10c1c0bbfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90344
1723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.903441723
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3122633702
Short name T756
Test name
Test status
Simulation time 10087326819 ps
CPU time 13.34 seconds
Started May 30 03:47:39 PM PDT 24
Finished May 30 03:47:56 PM PDT 24
Peak memory 205576 kb
Host smart-fa8b6646-0ffc-48c9-ad78-150a73e20730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31226
33702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3122633702
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1439119034
Short name T1716
Test name
Test status
Simulation time 10054737509 ps
CPU time 13.72 seconds
Started May 30 03:47:40 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205532 kb
Host smart-622abeda-8ede-4185-b9b8-20e362737f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14391
19034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1439119034
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.440677859
Short name T100
Test name
Test status
Simulation time 10113771777 ps
CPU time 13.79 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205536 kb
Host smart-f38d7729-e929-4057-a2d9-6bad9337ba92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44067
7859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.440677859
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.143150900
Short name T1004
Test name
Test status
Simulation time 10139611203 ps
CPU time 14.51 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205588 kb
Host smart-dbb8b5a2-e1f5-4d5e-9802-d0c93f064b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
0900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.143150900
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2225555891
Short name T1532
Test name
Test status
Simulation time 10053720409 ps
CPU time 13.19 seconds
Started May 30 03:47:39 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205568 kb
Host smart-de906828-e0ce-4104-a86a-3e6a04e84f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255
55891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2225555891
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.708326814
Short name T805
Test name
Test status
Simulation time 10060746245 ps
CPU time 13.03 seconds
Started May 30 03:47:40 PM PDT 24
Finished May 30 03:47:56 PM PDT 24
Peak memory 205548 kb
Host smart-87328b48-cc3b-448b-844c-34b500014021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70832
6814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.708326814
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1147371276
Short name T1175
Test name
Test status
Simulation time 10067414240 ps
CPU time 13.63 seconds
Started May 30 03:47:38 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205472 kb
Host smart-5959a30e-5f9a-42c2-a5cc-7678cc7304c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11473
71276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1147371276
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.3618329709
Short name T1304
Test name
Test status
Simulation time 10100889740 ps
CPU time 13.19 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205520 kb
Host smart-1f457ea0-33cf-460a-8b59-38cb7a535c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
29709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.3618329709
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1162405916
Short name T984
Test name
Test status
Simulation time 10052790883 ps
CPU time 13.72 seconds
Started May 30 03:47:35 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205592 kb
Host smart-60ecaf3d-069e-4b1c-87e6-eae30423da81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11624
05916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1162405916
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.366205079
Short name T1661
Test name
Test status
Simulation time 10036032876 ps
CPU time 12.72 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205548 kb
Host smart-e04ac1a6-ba60-4efb-a476-8c76f235b446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36620
5079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.366205079
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1367405843
Short name T43
Test name
Test status
Simulation time 28876285668 ps
CPU time 55.4 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:48:39 PM PDT 24
Peak memory 205596 kb
Host smart-03cc8899-302d-442c-91c7-5808386d8084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674
05843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1367405843
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.729000754
Short name T626
Test name
Test status
Simulation time 10111032491 ps
CPU time 15.83 seconds
Started May 30 03:47:38 PM PDT 24
Finished May 30 03:47:57 PM PDT 24
Peak memory 205548 kb
Host smart-088c93f0-fd60-4cb3-865b-51aba4683220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72900
0754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.729000754
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1671257826
Short name T33
Test name
Test status
Simulation time 10196041363 ps
CPU time 15.71 seconds
Started May 30 03:47:40 PM PDT 24
Finished May 30 03:47:59 PM PDT 24
Peak memory 205492 kb
Host smart-7810365e-cbb2-41e2-a64e-4efa1969bce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16712
57826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1671257826
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_trans.1327993696
Short name T964
Test name
Test status
Simulation time 10085058950 ps
CPU time 14.03 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:50 PM PDT 24
Peak memory 205528 kb
Host smart-3579c79f-0e8b-49cc-94cb-5b7acd051185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13279
93696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_trans.1327993696
Directory /workspace/46.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3003546735
Short name T608
Test name
Test status
Simulation time 10038158465 ps
CPU time 14.47 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205540 kb
Host smart-e14015b3-87bf-492a-91af-58b24898e806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30035
46735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3003546735
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2621543996
Short name T146
Test name
Test status
Simulation time 10049713979 ps
CPU time 14.39 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205580 kb
Host smart-67908c61-bfda-4ecb-9b66-d9193baa8fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26215
43996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2621543996
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.3974472253
Short name T1267
Test name
Test status
Simulation time 10056933645 ps
CPU time 16 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:48:00 PM PDT 24
Peak memory 205572 kb
Host smart-30dcf8ce-065b-4e33-96f3-354a005602f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39744
72253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.3974472253
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.4133474292
Short name T1886
Test name
Test status
Simulation time 10124431074 ps
CPU time 13.86 seconds
Started May 30 03:47:33 PM PDT 24
Finished May 30 03:47:49 PM PDT 24
Peak memory 205528 kb
Host smart-de37523f-9073-47d1-9260-9c604c203333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41334
74292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.4133474292
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3424549524
Short name T1213
Test name
Test status
Simulation time 10101482085 ps
CPU time 13.19 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:47:59 PM PDT 24
Peak memory 205580 kb
Host smart-59bfa6e8-5f63-454d-ac90-5177528c075d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34245
49524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3424549524
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.1405888425
Short name T1298
Test name
Test status
Simulation time 10085317140 ps
CPU time 15.42 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205520 kb
Host smart-43258b0a-79b1-42b5-b390-3b4c575914e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058
88425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1405888425
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.max_length_in_transaction.3285938118
Short name T1704
Test name
Test status
Simulation time 10145022883 ps
CPU time 14.3 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205552 kb
Host smart-1d7c2de5-7990-4be4-91a6-18d0dc1dc418
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3285938118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.max_length_in_transaction.3285938118
Directory /workspace/47.max_length_in_transaction/latest

Test location /workspace/coverage/default/47.min_length_in_transaction.215945711
Short name T703
Test name
Test status
Simulation time 10054467641 ps
CPU time 14.45 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205508 kb
Host smart-2425536f-e248-434a-9c0b-b37c38432158
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=215945711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.min_length_in_transaction.215945711
Directory /workspace/47.min_length_in_transaction/latest

Test location /workspace/coverage/default/47.random_length_in_trans.1901741785
Short name T735
Test name
Test status
Simulation time 10146227406 ps
CPU time 13.6 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205512 kb
Host smart-057b5d2e-222d-4a16-96a8-ae5f18abc073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19017
41785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.random_length_in_trans.1901741785
Directory /workspace/47.random_length_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1571477815
Short name T1292
Test name
Test status
Simulation time 13664519295 ps
CPU time 17.28 seconds
Started May 30 03:47:37 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205664 kb
Host smart-479a2b22-866b-49b8-9362-1574aaaaeade
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1571477815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1571477815
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.685285836
Short name T660
Test name
Test status
Simulation time 13193623623 ps
CPU time 18.16 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205532 kb
Host smart-4f38ef5d-0486-4de9-8ba5-9339eea1ad5e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=685285836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.685285836
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.3636625738
Short name T1676
Test name
Test status
Simulation time 13241110357 ps
CPU time 17.66 seconds
Started May 30 03:47:34 PM PDT 24
Finished May 30 03:47:55 PM PDT 24
Peak memory 205580 kb
Host smart-7b5c5e24-bf5e-4653-83d8-36ab96cbbfe2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3636625738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.3636625738
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1229629240
Short name T684
Test name
Test status
Simulation time 10068149286 ps
CPU time 12.98 seconds
Started May 30 03:47:36 PM PDT 24
Finished May 30 03:47:52 PM PDT 24
Peak memory 205548 kb
Host smart-04e0a14e-9e4e-45d1-9410-3ae90d8daf9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12296
29240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1229629240
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.351806684
Short name T710
Test name
Test status
Simulation time 11023764135 ps
CPU time 17.64 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205524 kb
Host smart-8dc8d7b7-4e68-4aa8-a9b0-0ba527c8ecb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
6684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.351806684
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3867427462
Short name T1358
Test name
Test status
Simulation time 10061635883 ps
CPU time 15.3 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:04 PM PDT 24
Peak memory 205516 kb
Host smart-680caf35-fe94-4f76-bb23-79ad86ebad86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38674
27462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3867427462
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2903137765
Short name T550
Test name
Test status
Simulation time 10085829826 ps
CPU time 17.38 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205508 kb
Host smart-1718fe73-0589-424f-bf05-fc03b7beac59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031
37765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2903137765
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.372589866
Short name T1229
Test name
Test status
Simulation time 10890827668 ps
CPU time 17.71 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205564 kb
Host smart-c0611630-bd0a-401b-a15f-1b8a9189a6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37258
9866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.372589866
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.656063790
Short name T846
Test name
Test status
Simulation time 10193425527 ps
CPU time 13.92 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:05 PM PDT 24
Peak memory 205608 kb
Host smart-9ae7561e-a0b1-469b-bdd4-048532a4d1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65606
3790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.656063790
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.522062447
Short name T575
Test name
Test status
Simulation time 10099298022 ps
CPU time 13.29 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205328 kb
Host smart-e3c0d629-27f3-49b0-859c-a1b92096b39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52206
2447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.522062447
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1597296952
Short name T1583
Test name
Test status
Simulation time 10042809613 ps
CPU time 14.96 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:59 PM PDT 24
Peak memory 205532 kb
Host smart-37188fac-9875-4482-8917-6c611ae61f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15972
96952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1597296952
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.3255430336
Short name T541
Test name
Test status
Simulation time 10085909799 ps
CPU time 13.03 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:04 PM PDT 24
Peak memory 205556 kb
Host smart-807c2ddb-dbdc-4456-a17f-18111f9ed4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
30336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.3255430336
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2727683181
Short name T1404
Test name
Test status
Simulation time 10069624412 ps
CPU time 13.26 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205608 kb
Host smart-1d35207f-f41e-4f66-979d-38d44a0587cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
83181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2727683181
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3799091245
Short name T1768
Test name
Test status
Simulation time 13185914873 ps
CPU time 15.59 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:48:00 PM PDT 24
Peak memory 205476 kb
Host smart-5e15f743-36fe-40dd-87ed-f32c64ebf549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37990
91245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3799091245
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2282318696
Short name T391
Test name
Test status
Simulation time 10128942546 ps
CPU time 16.53 seconds
Started May 30 03:47:48 PM PDT 24
Finished May 30 03:48:09 PM PDT 24
Peak memory 205504 kb
Host smart-ed263ee8-95f7-4e93-8d78-e882c345cb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22823
18696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2282318696
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4021750133
Short name T1643
Test name
Test status
Simulation time 10053456580 ps
CPU time 14.93 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:59 PM PDT 24
Peak memory 205568 kb
Host smart-c65792a8-b610-42ac-a9ba-367603aae7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40217
50133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4021750133
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2500046495
Short name T101
Test name
Test status
Simulation time 10100774211 ps
CPU time 13.64 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:05 PM PDT 24
Peak memory 205580 kb
Host smart-88b8789d-0986-4b04-b722-6f91513a79c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25000
46495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2500046495
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2366373180
Short name T1149
Test name
Test status
Simulation time 10101458973 ps
CPU time 13.8 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:47:59 PM PDT 24
Peak memory 205512 kb
Host smart-2ab70abf-4c50-4483-92d9-e5acf142e35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
73180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2366373180
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2729362693
Short name T988
Test name
Test status
Simulation time 10150289971 ps
CPU time 16.43 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205568 kb
Host smart-3f881544-8048-4ce0-a6a8-1792102d5798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27293
62693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2729362693
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.1523847708
Short name T1364
Test name
Test status
Simulation time 10071475052 ps
CPU time 14.46 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:48:00 PM PDT 24
Peak memory 205556 kb
Host smart-d9aa9b9d-dea9-4718-ac48-a15dcfd87419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15238
47708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.1523847708
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1153159154
Short name T182
Test name
Test status
Simulation time 10068696481 ps
CPU time 16.13 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205584 kb
Host smart-250611de-924f-41dd-b280-8e52a90d8e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11531
59154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1153159154
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.1099832487
Short name T1843
Test name
Test status
Simulation time 10091892190 ps
CPU time 13.97 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:05 PM PDT 24
Peak memory 205600 kb
Host smart-3f55291f-24ec-4ac1-b934-782764276620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998
32487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.1099832487
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2273198782
Short name T634
Test name
Test status
Simulation time 10048401445 ps
CPU time 13.87 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205516 kb
Host smart-478d6202-52a5-4eb5-8bb1-c6b58a4c947c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22731
98782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2273198782
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3944433779
Short name T37
Test name
Test status
Simulation time 10045194543 ps
CPU time 13.64 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205508 kb
Host smart-64d5a184-3923-4a93-b961-094bbccb83a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39444
33779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3944433779
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.247733372
Short name T1773
Test name
Test status
Simulation time 16879714142 ps
CPU time 31.73 seconds
Started May 30 03:47:42 PM PDT 24
Finished May 30 03:48:16 PM PDT 24
Peak memory 205600 kb
Host smart-c73ec6f1-f9cb-4908-87d9-2aba498f4781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
3372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.247733372
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1665931126
Short name T970
Test name
Test status
Simulation time 10087173394 ps
CPU time 13.15 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205560 kb
Host smart-8468e7a8-5b7e-4749-96e0-d2e03055ef68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659
31126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1665931126
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.880672575
Short name T1443
Test name
Test status
Simulation time 10137773852 ps
CPU time 16.16 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205452 kb
Host smart-761e65b3-dfb2-4861-b54f-918acfbb9de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88067
2575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.880672575
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_trans.1756136981
Short name T1302
Test name
Test status
Simulation time 10097625325 ps
CPU time 14.34 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205504 kb
Host smart-e6f0e0e4-9407-4e61-a690-e1bbf4103e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17561
36981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_trans.1756136981
Directory /workspace/47.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1761451888
Short name T593
Test name
Test status
Simulation time 10117609578 ps
CPU time 13.89 seconds
Started May 30 03:47:41 PM PDT 24
Finished May 30 03:47:58 PM PDT 24
Peak memory 205552 kb
Host smart-f4195006-3496-4b7b-8993-fc7234052fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17614
51888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1761451888
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2012818938
Short name T723
Test name
Test status
Simulation time 10045354704 ps
CPU time 13.82 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205308 kb
Host smart-6d08d82a-dd07-4be9-8b4f-bd4f0c319de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20128
18938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2012818938
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.732624598
Short name T62
Test name
Test status
Simulation time 10047061651 ps
CPU time 17.82 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:48:04 PM PDT 24
Peak memory 205500 kb
Host smart-e84479ac-78f4-43b6-b644-16950eebafc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73262
4598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.732624598
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.523085129
Short name T855
Test name
Test status
Simulation time 10142343613 ps
CPU time 13.75 seconds
Started May 30 03:47:39 PM PDT 24
Finished May 30 03:47:56 PM PDT 24
Peak memory 205536 kb
Host smart-5d39a033-6e28-4037-ad61-b4fad3bb02a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52308
5129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.523085129
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3078291595
Short name T1846
Test name
Test status
Simulation time 10052094439 ps
CPU time 12.92 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:47:59 PM PDT 24
Peak memory 204912 kb
Host smart-45f1c67c-c72a-4c5d-8af3-04825b18b2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
91595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3078291595
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2648424871
Short name T731
Test name
Test status
Simulation time 10085114582 ps
CPU time 15.54 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 204900 kb
Host smart-f482180c-e27f-4990-8240-9affc29e0423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26484
24871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2648424871
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.max_length_in_transaction.1474379675
Short name T1111
Test name
Test status
Simulation time 10139520466 ps
CPU time 15.44 seconds
Started May 30 03:47:52 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205532 kb
Host smart-290753d2-635b-480e-9c27-275653f1f438
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1474379675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.max_length_in_transaction.1474379675
Directory /workspace/48.max_length_in_transaction/latest

Test location /workspace/coverage/default/48.min_length_in_transaction.3306142565
Short name T1672
Test name
Test status
Simulation time 10049188024 ps
CPU time 13.58 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205580 kb
Host smart-451398e6-6296-4da9-8587-008249114e8d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3306142565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.min_length_in_transaction.3306142565
Directory /workspace/48.min_length_in_transaction/latest

Test location /workspace/coverage/default/48.random_length_in_trans.1842228616
Short name T1297
Test name
Test status
Simulation time 10145112917 ps
CPU time 15 seconds
Started May 30 03:47:55 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205524 kb
Host smart-40be5028-9f5a-4233-bc3f-af13da21873a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
28616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.random_length_in_trans.1842228616
Directory /workspace/48.random_length_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.141164063
Short name T1094
Test name
Test status
Simulation time 13741349192 ps
CPU time 16.49 seconds
Started May 30 03:47:49 PM PDT 24
Finished May 30 03:48:10 PM PDT 24
Peak memory 205600 kb
Host smart-262a6ede-2840-4841-8807-ad1fd58eaca0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=141164063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.141164063
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.667535082
Short name T689
Test name
Test status
Simulation time 13235910793 ps
CPU time 20.28 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:10 PM PDT 24
Peak memory 205588 kb
Host smart-52d3018d-6748-485b-be73-b78a4f30fb5b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=667535082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.667535082
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2813564437
Short name T837
Test name
Test status
Simulation time 13396468759 ps
CPU time 16.8 seconds
Started May 30 03:47:49 PM PDT 24
Finished May 30 03:48:11 PM PDT 24
Peak memory 205584 kb
Host smart-864d10be-10b1-4853-88cf-725b1fd45966
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2813564437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2813564437
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3635336893
Short name T816
Test name
Test status
Simulation time 10068173154 ps
CPU time 13.26 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205548 kb
Host smart-cee790dd-7f34-4914-b372-118d96866c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36353
36893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3635336893
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.589514235
Short name T507
Test name
Test status
Simulation time 10050393959 ps
CPU time 13.97 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:04 PM PDT 24
Peak memory 205552 kb
Host smart-e2dce700-a708-426f-aa7d-4f23c9d49cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58951
4235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.589514235
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.823048511
Short name T1539
Test name
Test status
Simulation time 10623147762 ps
CPU time 16.24 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:17 PM PDT 24
Peak memory 205452 kb
Host smart-0647fbe8-6493-45f5-8ce2-154fefd03714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82304
8511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.823048511
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3511635007
Short name T1614
Test name
Test status
Simulation time 10041388620 ps
CPU time 13.85 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205508 kb
Host smart-247c5180-3ef4-4258-9343-b3e465abda32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35116
35007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3511635007
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1921548498
Short name T1850
Test name
Test status
Simulation time 10104249641 ps
CPU time 13.62 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205596 kb
Host smart-9ba7faff-92e7-43fe-bba6-680bb2dd8415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
48498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1921548498
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1554842057
Short name T1842
Test name
Test status
Simulation time 10649100094 ps
CPU time 14.39 seconds
Started May 30 03:47:48 PM PDT 24
Finished May 30 03:48:07 PM PDT 24
Peak memory 205564 kb
Host smart-1f75261c-808d-476e-a708-e65882cf421a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548
42057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1554842057
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3841989667
Short name T1613
Test name
Test status
Simulation time 10296432974 ps
CPU time 16.11 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:04 PM PDT 24
Peak memory 205512 kb
Host smart-16bebca9-8f97-458e-9017-fea648e15acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38419
89667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3841989667
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.4084191348
Short name T1294
Test name
Test status
Simulation time 10075153574 ps
CPU time 15.32 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:16 PM PDT 24
Peak memory 205560 kb
Host smart-df5d7f37-b988-456d-b7a4-82d502509c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
91348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.4084191348
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1367492619
Short name T1899
Test name
Test status
Simulation time 10043157351 ps
CPU time 13.14 seconds
Started May 30 03:47:57 PM PDT 24
Finished May 30 03:48:15 PM PDT 24
Peak memory 205536 kb
Host smart-c69dc291-7891-4d36-88d3-2a2e3026d222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674
92619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1367492619
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.3493494826
Short name T1861
Test name
Test status
Simulation time 10105111277 ps
CPU time 14.2 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:15 PM PDT 24
Peak memory 205460 kb
Host smart-24b2d2c9-b1ce-4cad-ac11-8f0cb62ae7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934
94826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3493494826
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2711594164
Short name T1588
Test name
Test status
Simulation time 10074004412 ps
CPU time 14.97 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205544 kb
Host smart-5edeeb9b-cd40-4568-935b-8b997b7ecf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27115
94164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2711594164
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3263784405
Short name T1092
Test name
Test status
Simulation time 13249096082 ps
CPU time 17.2 seconds
Started May 30 03:47:43 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205572 kb
Host smart-d9087e15-e525-4b60-b183-ee5bdf0c16b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32637
84405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3263784405
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.341614292
Short name T341
Test name
Test status
Simulation time 10123037652 ps
CPU time 14.48 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205504 kb
Host smart-5f2ba4eb-4b4c-464e-a3b2-4dca1fcba757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34161
4292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.341614292
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3888500353
Short name T416
Test name
Test status
Simulation time 10046826441 ps
CPU time 14.18 seconds
Started May 30 03:47:47 PM PDT 24
Finished May 30 03:48:05 PM PDT 24
Peak memory 205564 kb
Host smart-dfb78f83-bc3f-46a9-b811-2cd7deed1d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38885
00353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3888500353
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3858867437
Short name T94
Test name
Test status
Simulation time 10094187504 ps
CPU time 17.84 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:07 PM PDT 24
Peak memory 205536 kb
Host smart-1cb6cdb4-b512-4ee6-ac69-babb09b4cbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
67437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3858867437
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.54599153
Short name T1222
Test name
Test status
Simulation time 10104367315 ps
CPU time 15.66 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:16 PM PDT 24
Peak memory 205516 kb
Host smart-eba033ad-5f84-427a-8c31-2f17e37afaae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54599
153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.54599153
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1588244688
Short name T1630
Test name
Test status
Simulation time 10051794947 ps
CPU time 14.3 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205536 kb
Host smart-9a64cdc6-41de-4b1f-b372-fde6deca0321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15882
44688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1588244688
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2690883240
Short name T299
Test name
Test status
Simulation time 10132344062 ps
CPU time 15.17 seconds
Started May 30 03:47:48 PM PDT 24
Finished May 30 03:48:07 PM PDT 24
Peak memory 205464 kb
Host smart-ddb26f00-a5d5-4803-b200-9be8cf2b7bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26908
83240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2690883240
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1911536804
Short name T142
Test name
Test status
Simulation time 10085757812 ps
CPU time 12.99 seconds
Started May 30 03:47:52 PM PDT 24
Finished May 30 03:48:10 PM PDT 24
Peak memory 205564 kb
Host smart-c6663518-77aa-4207-bec0-bb5ec7551d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19115
36804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1911536804
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.4245568407
Short name T504
Test name
Test status
Simulation time 10066543058 ps
CPU time 14.08 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:11 PM PDT 24
Peak memory 205536 kb
Host smart-90e6d2e2-040b-4f8f-95b6-e667523abda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42455
68407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.4245568407
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4182410753
Short name T355
Test name
Test status
Simulation time 10047752157 ps
CPU time 13.71 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:15 PM PDT 24
Peak memory 205468 kb
Host smart-be2d55a6-cb3b-462f-ac4b-80e07b8c9af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41824
10753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4182410753
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.69433623
Short name T1372
Test name
Test status
Simulation time 10037087651 ps
CPU time 14.27 seconds
Started May 30 03:48:03 PM PDT 24
Finished May 30 03:48:21 PM PDT 24
Peak memory 205564 kb
Host smart-b92725c3-5e2a-478c-be55-e6c04caa25b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69433
623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.69433623
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3226507005
Short name T1550
Test name
Test status
Simulation time 17551461327 ps
CPU time 31.56 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:21 PM PDT 24
Peak memory 205548 kb
Host smart-479c4e42-4db4-4d2c-a75b-d8426e52c8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32265
07005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3226507005
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2249469844
Short name T314
Test name
Test status
Simulation time 10128958937 ps
CPU time 13.94 seconds
Started May 30 03:47:48 PM PDT 24
Finished May 30 03:48:06 PM PDT 24
Peak memory 205464 kb
Host smart-322e466b-c9fc-48aa-b253-f4618d2e1082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22494
69844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2249469844
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2659966518
Short name T1462
Test name
Test status
Simulation time 10083090937 ps
CPU time 14.36 seconds
Started May 30 03:47:48 PM PDT 24
Finished May 30 03:48:06 PM PDT 24
Peak memory 205524 kb
Host smart-a3ba6c3d-2014-4e5e-b6ba-976b5db02108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599
66518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2659966518
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_trans.3278795784
Short name T916
Test name
Test status
Simulation time 10097609306 ps
CPU time 13.51 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:02 PM PDT 24
Peak memory 205580 kb
Host smart-c202abdf-d5b1-4144-9b1c-e5b711e82292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32787
95784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_trans.3278795784
Directory /workspace/48.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.223262622
Short name T1720
Test name
Test status
Simulation time 10052364481 ps
CPU time 13.48 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:01 PM PDT 24
Peak memory 205508 kb
Host smart-f29e8bb4-b1db-47c9-9ba9-c1ea4fc45ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
2622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.223262622
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2507432825
Short name T465
Test name
Test status
Simulation time 10052090666 ps
CPU time 14.35 seconds
Started May 30 03:47:55 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205576 kb
Host smart-e1c6116b-a09d-480d-b2a3-fff5dcf2da2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25074
32825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2507432825
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3366983787
Short name T1402
Test name
Test status
Simulation time 10101799644 ps
CPU time 13.71 seconds
Started May 30 03:47:46 PM PDT 24
Finished May 30 03:48:03 PM PDT 24
Peak memory 205548 kb
Host smart-867a5637-e250-4e2e-bdbd-488ef4e995c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33669
83787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3366983787
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2241344609
Short name T1129
Test name
Test status
Simulation time 10142186982 ps
CPU time 14.52 seconds
Started May 30 03:47:49 PM PDT 24
Finished May 30 03:48:08 PM PDT 24
Peak memory 205504 kb
Host smart-cf265b33-0632-478e-a48a-4c522411c4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22413
44609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2241344609
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.344243922
Short name T490
Test name
Test status
Simulation time 10074946498 ps
CPU time 13.43 seconds
Started May 30 03:47:44 PM PDT 24
Finished May 30 03:48:00 PM PDT 24
Peak memory 205548 kb
Host smart-3c262bcd-9410-422d-86b7-3ee03a890e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34424
3922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.344243922
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.3424729593
Short name T1333
Test name
Test status
Simulation time 10112012234 ps
CPU time 16.77 seconds
Started May 30 03:47:45 PM PDT 24
Finished May 30 03:48:05 PM PDT 24
Peak memory 205560 kb
Host smart-e7f8947f-61ab-4b53-9151-9294d60a9d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34247
29593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.3424729593
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.max_length_in_transaction.3814061722
Short name T26
Test name
Test status
Simulation time 10144602671 ps
CPU time 17.09 seconds
Started May 30 03:47:55 PM PDT 24
Finished May 30 03:48:17 PM PDT 24
Peak memory 205496 kb
Host smart-bece0dbe-7c77-4e43-aeec-7b32dbcbd2a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3814061722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.max_length_in_transaction.3814061722
Directory /workspace/49.max_length_in_transaction/latest

Test location /workspace/coverage/default/49.min_length_in_transaction.3632687054
Short name T476
Test name
Test status
Simulation time 10076726485 ps
CPU time 13.45 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:11 PM PDT 24
Peak memory 205160 kb
Host smart-d3c5d566-2d26-406c-b610-0e117453c6d8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3632687054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.min_length_in_transaction.3632687054
Directory /workspace/49.min_length_in_transaction/latest

Test location /workspace/coverage/default/49.random_length_in_trans.4094458941
Short name T336
Test name
Test status
Simulation time 10094031353 ps
CPU time 14.25 seconds
Started May 30 03:47:58 PM PDT 24
Finished May 30 03:48:18 PM PDT 24
Peak memory 205504 kb
Host smart-2cf7b595-7ee6-40f2-944f-dfe7f69cbbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40944
58941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.random_length_in_trans.4094458941
Directory /workspace/49.random_length_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.4107553917
Short name T736
Test name
Test status
Simulation time 14043227103 ps
CPU time 17.07 seconds
Started May 30 03:48:01 PM PDT 24
Finished May 30 03:48:22 PM PDT 24
Peak memory 205600 kb
Host smart-503674f1-50ad-4b13-a713-d0259be2aca7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4107553917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.4107553917
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3179592091
Short name T1411
Test name
Test status
Simulation time 13239442316 ps
CPU time 15.96 seconds
Started May 30 03:48:09 PM PDT 24
Finished May 30 03:48:26 PM PDT 24
Peak memory 205540 kb
Host smart-57dbdc36-2ed3-40c2-a7f3-3c72a42f72ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3179592091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3179592091
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3714071177
Short name T398
Test name
Test status
Simulation time 13276410262 ps
CPU time 18.05 seconds
Started May 30 03:47:52 PM PDT 24
Finished May 30 03:48:15 PM PDT 24
Peak memory 205540 kb
Host smart-2dfbddfa-c0ba-4dec-a0ef-4c9bf0a00514
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3714071177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3714071177
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2652106225
Short name T1838
Test name
Test status
Simulation time 10070585750 ps
CPU time 13.71 seconds
Started May 30 03:48:00 PM PDT 24
Finished May 30 03:48:18 PM PDT 24
Peak memory 205540 kb
Host smart-1bc21da6-c157-47ae-a672-d9b1b43f8293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26521
06225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2652106225
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_enable.1155327333
Short name T1758
Test name
Test status
Simulation time 10062796933 ps
CPU time 13.24 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205524 kb
Host smart-476e1923-3767-4369-806c-af3e3a4b1296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11553
27333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1155327333
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3696781182
Short name T459
Test name
Test status
Simulation time 10862019220 ps
CPU time 17.73 seconds
Started May 30 03:48:08 PM PDT 24
Finished May 30 03:48:27 PM PDT 24
Peak memory 205556 kb
Host smart-5a7edeaf-1db9-4278-adc0-68687d57de79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36967
81182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3696781182
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2189347649
Short name T1170
Test name
Test status
Simulation time 10181155200 ps
CPU time 15.06 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205604 kb
Host smart-0cdc652e-22f7-4e91-987d-8d78f903136b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21893
47649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2189347649
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.3925741049
Short name T556
Test name
Test status
Simulation time 10092148192 ps
CPU time 13.73 seconds
Started May 30 03:48:02 PM PDT 24
Finished May 30 03:48:20 PM PDT 24
Peak memory 205516 kb
Host smart-8a572f5a-f8f4-441b-8b0d-766289b525df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39257
41049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3925741049
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.597952584
Short name T1360
Test name
Test status
Simulation time 10041846236 ps
CPU time 13.63 seconds
Started May 30 03:47:57 PM PDT 24
Finished May 30 03:48:16 PM PDT 24
Peak memory 205488 kb
Host smart-0f30f6cc-799e-467b-9bdc-de307da38039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59795
2584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.597952584
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.744849355
Short name T1470
Test name
Test status
Simulation time 10125435146 ps
CPU time 13.23 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:10 PM PDT 24
Peak memory 205576 kb
Host smart-79d19de6-4a51-45af-8746-10d88291e0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74484
9355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.744849355
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3754278729
Short name T1270
Test name
Test status
Simulation time 10053500956 ps
CPU time 15.22 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205536 kb
Host smart-ab271a11-5145-403e-a03d-52e494779eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37542
78729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3754278729
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.3635287429
Short name T292
Test name
Test status
Simulation time 13166658453 ps
CPU time 17.79 seconds
Started May 30 03:47:58 PM PDT 24
Finished May 30 03:48:21 PM PDT 24
Peak memory 205528 kb
Host smart-f2d8228c-d6bf-4ee9-9379-fe24587c04ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36352
87429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.3635287429
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3915473062
Short name T592
Test name
Test status
Simulation time 10085823813 ps
CPU time 13.9 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205536 kb
Host smart-911950e4-5c23-468c-9ef9-15c0144f42e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
73062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3915473062
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2872551716
Short name T1414
Test name
Test status
Simulation time 10066376186 ps
CPU time 13.49 seconds
Started May 30 03:47:58 PM PDT 24
Finished May 30 03:48:16 PM PDT 24
Peak memory 205504 kb
Host smart-e2c202de-1446-4bb4-b3d9-60ade8a5cfeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
51716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2872551716
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1229333959
Short name T116
Test name
Test status
Simulation time 10114574016 ps
CPU time 14.69 seconds
Started May 30 03:47:55 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205552 kb
Host smart-0d30c506-2966-4ced-a4c7-33e5eea0bc74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293
33959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1229333959
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.778751310
Short name T774
Test name
Test status
Simulation time 10130133850 ps
CPU time 13.17 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:11 PM PDT 24
Peak memory 205188 kb
Host smart-591ee4f1-6d79-49b3-99ab-31d9991b10cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77875
1310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.778751310
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1047137335
Short name T835
Test name
Test status
Simulation time 10060288177 ps
CPU time 14.4 seconds
Started May 30 03:47:53 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205552 kb
Host smart-1e47e2fe-5a0d-41c3-ab39-69f571fcb462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10471
37335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1047137335
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.1416354960
Short name T1117
Test name
Test status
Simulation time 10068086604 ps
CPU time 15.3 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:13 PM PDT 24
Peak memory 205524 kb
Host smart-0649f7c3-2935-4d95-b3cb-b9d0508b9d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14163
54960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.1416354960
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.662711721
Short name T1491
Test name
Test status
Simulation time 10096770142 ps
CPU time 15.11 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205580 kb
Host smart-c71f0bb3-0dd8-4495-97e3-fed0b0c8b227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66271
1721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.662711721
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.1098959174
Short name T1310
Test name
Test status
Simulation time 10070129060 ps
CPU time 14.45 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:13 PM PDT 24
Peak memory 205572 kb
Host smart-7814abd9-451c-4536-be24-b3fd76cf188e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10989
59174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.1098959174
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.4209837210
Short name T591
Test name
Test status
Simulation time 10069595904 ps
CPU time 13.87 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205600 kb
Host smart-9913476f-87b2-4865-8ccf-bd4e9ef20edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
37210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.4209837210
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1091686702
Short name T35
Test name
Test status
Simulation time 10062230925 ps
CPU time 13.9 seconds
Started May 30 03:48:10 PM PDT 24
Finished May 30 03:48:25 PM PDT 24
Peak memory 205540 kb
Host smart-fd9dfd94-dbf4-4f62-b40b-96762e398d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10916
86702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1091686702
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3576425511
Short name T90
Test name
Test status
Simulation time 25694003453 ps
CPU time 49.71 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:49 PM PDT 24
Peak memory 205600 kb
Host smart-474edc27-0b64-40f4-bc51-ad1a8a6e53f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35764
25511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3576425511
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.4266888540
Short name T1082
Test name
Test status
Simulation time 10053760679 ps
CPU time 13.69 seconds
Started May 30 03:47:57 PM PDT 24
Finished May 30 03:48:16 PM PDT 24
Peak memory 205508 kb
Host smart-ecc5ad6f-0037-4b87-8f7d-0b2ce595f9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
88540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.4266888540
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.15944751
Short name T1637
Test name
Test status
Simulation time 10142649210 ps
CPU time 14.39 seconds
Started May 30 03:47:56 PM PDT 24
Finished May 30 03:48:15 PM PDT 24
Peak memory 205576 kb
Host smart-f357ce3c-8f50-4ad3-a8de-64fcf3d760ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.15944751
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_trans.3609343509
Short name T321
Test name
Test status
Simulation time 10045575888 ps
CPU time 14.08 seconds
Started May 30 03:48:08 PM PDT 24
Finished May 30 03:48:23 PM PDT 24
Peak memory 205580 kb
Host smart-f2367cad-5599-4914-9485-e5a2bbf5cb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36093
43509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_trans.3609343509
Directory /workspace/49.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2347998355
Short name T1126
Test name
Test status
Simulation time 10084309289 ps
CPU time 13.32 seconds
Started May 30 03:48:11 PM PDT 24
Finished May 30 03:48:26 PM PDT 24
Peak memory 205496 kb
Host smart-ea16e23a-947c-406f-bc04-65d4a26acee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23479
98355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2347998355
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3935510659
Short name T825
Test name
Test status
Simulation time 10042844651 ps
CPU time 13.03 seconds
Started May 30 03:48:12 PM PDT 24
Finished May 30 03:48:26 PM PDT 24
Peak memory 205520 kb
Host smart-f372e5c0-42c3-4cad-8d14-23f16ad1fb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39355
10659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3935510659
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.375022086
Short name T1316
Test name
Test status
Simulation time 10047193833 ps
CPU time 14.83 seconds
Started May 30 03:47:55 PM PDT 24
Finished May 30 03:48:14 PM PDT 24
Peak memory 205520 kb
Host smart-0e005404-ec54-46d2-95fe-2c9356bb7cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
2086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.375022086
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1829731842
Short name T668
Test name
Test status
Simulation time 10098871637 ps
CPU time 13.77 seconds
Started May 30 03:48:11 PM PDT 24
Finished May 30 03:48:26 PM PDT 24
Peak memory 205540 kb
Host smart-7bf95b52-7347-4b11-ace4-79aa85e87e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18297
31842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1829731842
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1518844219
Short name T824
Test name
Test status
Simulation time 10091066293 ps
CPU time 13.83 seconds
Started May 30 03:48:01 PM PDT 24
Finished May 30 03:48:19 PM PDT 24
Peak memory 205596 kb
Host smart-cbbc9d01-8e2d-4f41-8804-cfe93188189c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15188
44219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1518844219
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1545897847
Short name T1271
Test name
Test status
Simulation time 10078005823 ps
CPU time 13.02 seconds
Started May 30 03:47:54 PM PDT 24
Finished May 30 03:48:12 PM PDT 24
Peak memory 205560 kb
Host smart-807efdc2-e153-401d-8b60-6d552b490b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15458
97847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1545897847
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.max_length_in_transaction.1117239700
Short name T590
Test name
Test status
Simulation time 10171577529 ps
CPU time 16.56 seconds
Started May 30 03:42:56 PM PDT 24
Finished May 30 03:43:14 PM PDT 24
Peak memory 205524 kb
Host smart-b7020771-fa5e-49c7-942f-b30ee92f07e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1117239700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.max_length_in_transaction.1117239700
Directory /workspace/5.max_length_in_transaction/latest

Test location /workspace/coverage/default/5.min_length_in_transaction.1922126960
Short name T979
Test name
Test status
Simulation time 10054429511 ps
CPU time 13.47 seconds
Started May 30 03:42:55 PM PDT 24
Finished May 30 03:43:10 PM PDT 24
Peak memory 205604 kb
Host smart-1c5ebc41-34a6-4bd8-a4a1-88a33a5c8f78
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1922126960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.min_length_in_transaction.1922126960
Directory /workspace/5.min_length_in_transaction/latest

Test location /workspace/coverage/default/5.random_length_in_trans.2030518090
Short name T1640
Test name
Test status
Simulation time 10120805298 ps
CPU time 13.29 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205528 kb
Host smart-d3e4ea5f-87bf-4e8c-8bc9-c571a8449aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20305
18090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.random_length_in_trans.2030518090
Directory /workspace/5.random_length_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.104072997
Short name T1442
Test name
Test status
Simulation time 13664532328 ps
CPU time 17.58 seconds
Started May 30 03:42:54 PM PDT 24
Finished May 30 03:43:13 PM PDT 24
Peak memory 205544 kb
Host smart-089c5b1b-fa1f-43f2-aad6-f553ecd89788
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=104072997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.104072997
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2107188063
Short name T1303
Test name
Test status
Simulation time 13300921033 ps
CPU time 16.74 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205532 kb
Host smart-e190b21b-ca8c-4570-a57c-d1aebaf97ea2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2107188063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2107188063
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.4166874956
Short name T817
Test name
Test status
Simulation time 13249071802 ps
CPU time 16.98 seconds
Started May 30 03:42:52 PM PDT 24
Finished May 30 03:43:10 PM PDT 24
Peak memory 205580 kb
Host smart-70a5e08e-6367-4a6c-8955-c75bca05f6fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4166874956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.4166874956
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1452910146
Short name T377
Test name
Test status
Simulation time 10055595258 ps
CPU time 17.13 seconds
Started May 30 03:42:52 PM PDT 24
Finished May 30 03:43:11 PM PDT 24
Peak memory 205500 kb
Host smart-31840ec7-fc97-4059-bf37-4902b7ed069e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14529
10146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1452910146
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1795492719
Short name T160
Test name
Test status
Simulation time 11257737280 ps
CPU time 14.57 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205580 kb
Host smart-50aa3e4a-d2a6-45fa-a85e-206825357697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
92719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1795492719
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2363189570
Short name T531
Test name
Test status
Simulation time 10055947980 ps
CPU time 16.86 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205580 kb
Host smart-c4a49f05-ba1c-44a7-a21d-2964d34395c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
89570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2363189570
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3946460024
Short name T1265
Test name
Test status
Simulation time 10141676843 ps
CPU time 13.43 seconds
Started May 30 03:42:55 PM PDT 24
Finished May 30 03:43:10 PM PDT 24
Peak memory 205580 kb
Host smart-4b94846f-b8fb-4534-97e3-d12914f0e6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39464
60024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3946460024
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.4099255579
Short name T470
Test name
Test status
Simulation time 10868431419 ps
CPU time 15.21 seconds
Started May 30 03:42:55 PM PDT 24
Finished May 30 03:43:12 PM PDT 24
Peak memory 205532 kb
Host smart-c5049d24-8200-4173-b38a-8feb54e9bbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992
55579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.4099255579
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3519163852
Short name T1840
Test name
Test status
Simulation time 10206077074 ps
CPU time 13.59 seconds
Started May 30 03:42:49 PM PDT 24
Finished May 30 03:43:04 PM PDT 24
Peak memory 205532 kb
Host smart-8824b991-99c6-4bac-a60d-1525f07180c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
63852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3519163852
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.1456670066
Short name T1312
Test name
Test status
Simulation time 10114753215 ps
CPU time 16.15 seconds
Started May 30 03:42:55 PM PDT 24
Finished May 30 03:43:12 PM PDT 24
Peak memory 205524 kb
Host smart-aacacabc-9b4b-4ec9-bac5-a0438dc2c9bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14566
70066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1456670066
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.72527148
Short name T589
Test name
Test status
Simulation time 10052138251 ps
CPU time 13.84 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205596 kb
Host smart-70db79a8-72aa-49d8-abcf-0003835d35f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72527
148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.72527148
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3649591531
Short name T698
Test name
Test status
Simulation time 10172279677 ps
CPU time 14.81 seconds
Started May 30 03:42:52 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205524 kb
Host smart-a5a40c6a-3d74-4d75-a585-73aeff31c4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
91531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3649591531
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.729357687
Short name T1169
Test name
Test status
Simulation time 10067256639 ps
CPU time 13.95 seconds
Started May 30 03:42:54 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205556 kb
Host smart-134b3096-3780-44f9-ad45-9d7e0724ae0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72935
7687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.729357687
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.3565006639
Short name T1673
Test name
Test status
Simulation time 13166558422 ps
CPU time 18.54 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:12 PM PDT 24
Peak memory 205540 kb
Host smart-4e0bfacc-4400-4f4b-a465-26b4116bd3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35650
06639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3565006639
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.985148323
Short name T1894
Test name
Test status
Simulation time 10102213856 ps
CPU time 14.19 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205516 kb
Host smart-c12219c7-8a4c-4c39-9632-2459594d7fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98514
8323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.985148323
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.3519196018
Short name T1636
Test name
Test status
Simulation time 10038513049 ps
CPU time 14.9 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:07 PM PDT 24
Peak memory 205500 kb
Host smart-d8ef943e-3a08-46c9-88bb-39fb60b8e64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
96018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.3519196018
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2407432893
Short name T1674
Test name
Test status
Simulation time 10112074424 ps
CPU time 16.2 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205536 kb
Host smart-c119bc10-fee3-402f-8aff-6c2ce05a8961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24074
32893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2407432893
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4115391670
Short name T1860
Test name
Test status
Simulation time 10094620277 ps
CPU time 14.05 seconds
Started May 30 03:42:49 PM PDT 24
Finished May 30 03:43:04 PM PDT 24
Peak memory 205572 kb
Host smart-53edde6c-1ab8-488d-a638-017e767de9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
91670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4115391670
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2496177584
Short name T300
Test name
Test status
Simulation time 10047871801 ps
CPU time 15.3 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:08 PM PDT 24
Peak memory 205568 kb
Host smart-b022203c-c8f5-4653-8213-c9068e7902fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
77584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2496177584
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4084060038
Short name T1503
Test name
Test status
Simulation time 10068303070 ps
CPU time 14.44 seconds
Started May 30 03:42:56 PM PDT 24
Finished May 30 03:43:12 PM PDT 24
Peak memory 205576 kb
Host smart-0b370e42-378b-4dac-baa4-289735a6f063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40840
60038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4084060038
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3656287880
Short name T1467
Test name
Test status
Simulation time 10096569394 ps
CPU time 14.18 seconds
Started May 30 03:42:54 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205580 kb
Host smart-0e05a90c-f39d-4691-96cd-d8a775ba8b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
87880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3656287880
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.494821352
Short name T642
Test name
Test status
Simulation time 10079413379 ps
CPU time 13.81 seconds
Started May 30 03:42:49 PM PDT 24
Finished May 30 03:43:03 PM PDT 24
Peak memory 205528 kb
Host smart-37dd5d85-09e3-4c6a-9532-98d2289e7eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49482
1352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.494821352
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3610099136
Short name T1606
Test name
Test status
Simulation time 10049134443 ps
CPU time 14.15 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:06 PM PDT 24
Peak memory 205548 kb
Host smart-32de28ae-c01a-47b2-93e4-451024e30195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36100
99136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3610099136
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2934400024
Short name T22
Test name
Test status
Simulation time 10075321663 ps
CPU time 14.13 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205556 kb
Host smart-640ee3e3-2137-4e98-b761-545227946c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
00024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2934400024
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4168877142
Short name T92
Test name
Test status
Simulation time 31434805911 ps
CPU time 65.48 seconds
Started May 30 03:42:49 PM PDT 24
Finished May 30 03:43:56 PM PDT 24
Peak memory 205624 kb
Host smart-af27f609-f9fb-4c57-928d-ac664a6cef55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41688
77142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4168877142
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2686585864
Short name T1558
Test name
Test status
Simulation time 10079682283 ps
CPU time 14.37 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205564 kb
Host smart-3ff21ca8-391c-479d-aece-22db09471c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26865
85864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2686585864
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1920058921
Short name T1798
Test name
Test status
Simulation time 10082305496 ps
CPU time 15.89 seconds
Started May 30 03:42:55 PM PDT 24
Finished May 30 03:43:13 PM PDT 24
Peak memory 205544 kb
Host smart-63784c4d-9ec7-4318-ba3e-a171dd86dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19200
58921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1920058921
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_trans.3291424219
Short name T720
Test name
Test status
Simulation time 10074467235 ps
CPU time 16.72 seconds
Started May 30 03:42:56 PM PDT 24
Finished May 30 03:43:15 PM PDT 24
Peak memory 205556 kb
Host smart-1e587104-ce9e-4697-b6c2-d41ba3d00552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
24219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_trans.3291424219
Directory /workspace/5.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2644882146
Short name T820
Test name
Test status
Simulation time 10044472978 ps
CPU time 14.52 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:07 PM PDT 24
Peak memory 205612 kb
Host smart-79d10ceb-aec0-4102-b7d8-b342173eae42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448
82146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2644882146
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.791743255
Short name T155
Test name
Test status
Simulation time 10071479034 ps
CPU time 12.57 seconds
Started May 30 03:42:51 PM PDT 24
Finished May 30 03:43:05 PM PDT 24
Peak memory 205616 kb
Host smart-5d6a6918-3eaa-4839-85d9-4c6822185ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79174
3255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.791743255
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3786249228
Short name T77
Test name
Test status
Simulation time 10101278649 ps
CPU time 13.69 seconds
Started May 30 03:42:55 PM PDT 24
Finished May 30 03:43:10 PM PDT 24
Peak memory 205548 kb
Host smart-6f212d02-8be0-490f-bacb-4c52df8cd092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37862
49228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3786249228
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1884549095
Short name T1268
Test name
Test status
Simulation time 10121534063 ps
CPU time 14.18 seconds
Started May 30 03:42:53 PM PDT 24
Finished May 30 03:43:09 PM PDT 24
Peak memory 205560 kb
Host smart-5637d9ad-8707-45bb-88f7-85e3012c1670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845
49095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1884549095
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3043529914
Short name T553
Test name
Test status
Simulation time 10094000471 ps
CPU time 12.76 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:04 PM PDT 24
Peak memory 205576 kb
Host smart-897ad26c-fe67-48b9-ada1-5b6ec672d582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30435
29914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3043529914
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1559366391
Short name T1619
Test name
Test status
Simulation time 10067713449 ps
CPU time 13.73 seconds
Started May 30 03:42:50 PM PDT 24
Finished May 30 03:43:04 PM PDT 24
Peak memory 205552 kb
Host smart-96aa56f4-38ac-46fa-8632-acf4082a7f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15593
66391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1559366391
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.max_length_in_transaction.1888220778
Short name T317
Test name
Test status
Simulation time 10149123256 ps
CPU time 14.49 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205540 kb
Host smart-cc54e792-eace-4539-9359-72fecba3fe83
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1888220778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.max_length_in_transaction.1888220778
Directory /workspace/6.max_length_in_transaction/latest

Test location /workspace/coverage/default/6.min_length_in_transaction.3096978298
Short name T961
Test name
Test status
Simulation time 10055223224 ps
CPU time 15.44 seconds
Started May 30 03:43:21 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205560 kb
Host smart-28d77680-cb52-4202-bad4-68faa156029a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3096978298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.min_length_in_transaction.3096978298
Directory /workspace/6.min_length_in_transaction/latest

Test location /workspace/coverage/default/6.random_length_in_trans.470444580
Short name T1828
Test name
Test status
Simulation time 10060683733 ps
CPU time 14.02 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205524 kb
Host smart-3000a476-6ef2-47a3-9e77-82c56083c409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47044
4580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.random_length_in_trans.470444580
Directory /workspace/6.random_length_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1814385143
Short name T901
Test name
Test status
Simulation time 13915557155 ps
CPU time 17.55 seconds
Started May 30 03:43:16 PM PDT 24
Finished May 30 03:43:34 PM PDT 24
Peak memory 205504 kb
Host smart-0f2ffbd0-5927-4af2-a8f9-1f285c637d5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1814385143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1814385143
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.3053573301
Short name T690
Test name
Test status
Simulation time 13272369379 ps
CPU time 17.21 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:29 PM PDT 24
Peak memory 205500 kb
Host smart-20c9866d-ee6d-43e5-946f-1832920cf861
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3053573301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.3053573301
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.25878133
Short name T656
Test name
Test status
Simulation time 13291616190 ps
CPU time 19.28 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:32 PM PDT 24
Peak memory 205500 kb
Host smart-0ee461b5-42c8-4238-a223-fe0040c926b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=25878133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.25878133
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2837391791
Short name T1523
Test name
Test status
Simulation time 10054136397 ps
CPU time 13.53 seconds
Started May 30 03:43:13 PM PDT 24
Finished May 30 03:43:28 PM PDT 24
Peak memory 205564 kb
Host smart-263c50c6-3398-4e59-b34b-4399d2d00cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28373
91791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2837391791
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1233323612
Short name T1286
Test name
Test status
Simulation time 10927699863 ps
CPU time 15.78 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:28 PM PDT 24
Peak memory 205652 kb
Host smart-1dc8821f-f072-427a-bdcc-cf47edd1690d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
23612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1233323612
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2196264971
Short name T1708
Test name
Test status
Simulation time 10043587697 ps
CPU time 13.63 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205612 kb
Host smart-39fadfc7-22de-47e8-bd40-aa34ea6564a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21962
64971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2196264971
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.270613519
Short name T557
Test name
Test status
Simulation time 10065198210 ps
CPU time 16.48 seconds
Started May 30 03:43:13 PM PDT 24
Finished May 30 03:43:31 PM PDT 24
Peak memory 205520 kb
Host smart-1d44cc2f-f91a-4def-9754-6db526be6902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27061
3519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.270613519
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.750068315
Short name T921
Test name
Test status
Simulation time 10934395235 ps
CPU time 15.81 seconds
Started May 30 03:43:13 PM PDT 24
Finished May 30 03:43:30 PM PDT 24
Peak memory 205548 kb
Host smart-15fb3b9d-c308-4f08-89b7-9f4162b3d66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75006
8315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.750068315
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1126763802
Short name T1519
Test name
Test status
Simulation time 10102732118 ps
CPU time 15.06 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205544 kb
Host smart-89adecb9-c8f6-40f2-a8ee-2ab3cfe45003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11267
63802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1126763802
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1116028640
Short name T1678
Test name
Test status
Simulation time 10123458245 ps
CPU time 16.6 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205528 kb
Host smart-bcf8c945-8de8-4bfa-9bf6-73765c397989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11160
28640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1116028640
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3296128662
Short name T1921
Test name
Test status
Simulation time 10080250579 ps
CPU time 15.1 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205496 kb
Host smart-9e233493-b3c9-49a0-a7a4-050b413164a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32961
28662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3296128662
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2898960515
Short name T1241
Test name
Test status
Simulation time 10115143226 ps
CPU time 14.09 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:26 PM PDT 24
Peak memory 205556 kb
Host smart-3ff84f5d-fb07-4ee6-ba8c-16083fdba62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28989
60515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2898960515
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.3456542501
Short name T1473
Test name
Test status
Simulation time 10096919458 ps
CPU time 16.14 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:29 PM PDT 24
Peak memory 205476 kb
Host smart-77cdaf88-17aa-4a88-8589-1008ee4ebda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
42501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.3456542501
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1126937562
Short name T1739
Test name
Test status
Simulation time 13151735137 ps
CPU time 19.86 seconds
Started May 30 03:43:13 PM PDT 24
Finished May 30 03:43:34 PM PDT 24
Peak memory 205512 kb
Host smart-ec4cd6f9-f363-41fe-a8c5-9cba4009bf95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11269
37562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1126937562
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1089336559
Short name T1597
Test name
Test status
Simulation time 10136805308 ps
CPU time 15.03 seconds
Started May 30 03:43:09 PM PDT 24
Finished May 30 03:43:25 PM PDT 24
Peak memory 205592 kb
Host smart-a962fd6a-7123-434b-be69-d1df9afd7cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10893
36559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1089336559
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1564794676
Short name T436
Test name
Test status
Simulation time 10062087148 ps
CPU time 13.75 seconds
Started May 30 03:43:10 PM PDT 24
Finished May 30 03:43:25 PM PDT 24
Peak memory 205568 kb
Host smart-b01d4721-f009-4251-be90-f8d53dfd32cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15647
94676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1564794676
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3745620409
Short name T1321
Test name
Test status
Simulation time 10087880708 ps
CPU time 14.89 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:28 PM PDT 24
Peak memory 205604 kb
Host smart-4c7b432c-e760-46ea-8213-9f49a0ff1b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37456
20409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3745620409
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1919230010
Short name T332
Test name
Test status
Simulation time 10127900934 ps
CPU time 15.56 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:29 PM PDT 24
Peak memory 205588 kb
Host smart-78fce6be-761a-4f52-b083-1694700a3c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19192
30010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1919230010
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.390017774
Short name T1452
Test name
Test status
Simulation time 10063901174 ps
CPU time 16.42 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:30 PM PDT 24
Peak memory 205612 kb
Host smart-74b179af-43f6-484f-9d10-daa6ad38ba83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39001
7774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.390017774
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2466075396
Short name T471
Test name
Test status
Simulation time 10096009401 ps
CPU time 14.44 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205544 kb
Host smart-69e380ed-b3e5-4f87-8864-fb669757939d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24660
75396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2466075396
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1488224097
Short name T1638
Test name
Test status
Simulation time 10063849989 ps
CPU time 14.46 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:26 PM PDT 24
Peak memory 205604 kb
Host smart-bd30f152-b384-4a68-bbb2-a5b93a7a1b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14882
24097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1488224097
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.3732362396
Short name T848
Test name
Test status
Simulation time 10098916740 ps
CPU time 17.51 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:30 PM PDT 24
Peak memory 205564 kb
Host smart-275cc21c-0998-4f2c-a7d1-c874185d5821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
62396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.3732362396
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1159339737
Short name T1146
Test name
Test status
Simulation time 10081075559 ps
CPU time 13.7 seconds
Started May 30 03:43:18 PM PDT 24
Finished May 30 03:43:32 PM PDT 24
Peak memory 205508 kb
Host smart-3ab6b2f8-18ab-4f2d-b9e1-2815e4f05376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11593
39737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1159339737
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4207593786
Short name T1505
Test name
Test status
Simulation time 10052037055 ps
CPU time 16.4 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:44 PM PDT 24
Peak memory 205496 kb
Host smart-f4afbc9f-1f3d-4ec9-9b1a-36cf509b534a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42075
93786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4207593786
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3414818362
Short name T1173
Test name
Test status
Simulation time 26899621097 ps
CPU time 50.84 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:44:03 PM PDT 24
Peak memory 205584 kb
Host smart-1cf99f8f-ed68-4f90-9050-ff308219f3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
18362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3414818362
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2210252996
Short name T682
Test name
Test status
Simulation time 10096279585 ps
CPU time 13.3 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205500 kb
Host smart-4a8aced1-a8ac-4a9a-97c7-748edf20b070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22102
52996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2210252996
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2097061663
Short name T1903
Test name
Test status
Simulation time 10125706692 ps
CPU time 14.39 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205584 kb
Host smart-352dd069-26d6-4bdf-980b-4e9ad84fea61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20970
61663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2097061663
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_trans.4115245930
Short name T734
Test name
Test status
Simulation time 10083113601 ps
CPU time 13.57 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205556 kb
Host smart-47ef149d-b76d-4d9b-bd47-75e938cfca82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41152
45930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_trans.4115245930
Directory /workspace/6.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2276280095
Short name T1521
Test name
Test status
Simulation time 10040761806 ps
CPU time 14.14 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205632 kb
Host smart-c398be4a-3ef2-49c0-bdd8-40311d3b2ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22762
80095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2276280095
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1550029429
Short name T1190
Test name
Test status
Simulation time 10053111513 ps
CPU time 16.04 seconds
Started May 30 03:43:10 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205520 kb
Host smart-d849b8dd-9160-4a4c-b211-2250fd7dfe55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15500
29429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1550029429
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3202964098
Short name T1916
Test name
Test status
Simulation time 10054181410 ps
CPU time 14.09 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:28 PM PDT 24
Peak memory 205516 kb
Host smart-7c6323c1-cd8a-4036-8e7e-919b233334e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32029
64098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3202964098
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1935492877
Short name T975
Test name
Test status
Simulation time 10150298931 ps
CPU time 13.41 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:27 PM PDT 24
Peak memory 205540 kb
Host smart-1961aff2-a5db-48af-acb9-260992ced48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
92877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1935492877
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3388633915
Short name T1219
Test name
Test status
Simulation time 10061905799 ps
CPU time 13.57 seconds
Started May 30 03:43:11 PM PDT 24
Finished May 30 03:43:25 PM PDT 24
Peak memory 205548 kb
Host smart-b8b94415-28d9-4697-8738-774dd2e0a102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33886
33915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3388633915
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2332510604
Short name T1578
Test name
Test status
Simulation time 10139788839 ps
CPU time 15.73 seconds
Started May 30 03:43:12 PM PDT 24
Finished May 30 03:43:29 PM PDT 24
Peak memory 205540 kb
Host smart-3a002942-b7e8-46f0-b5c4-99f9aabd354d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325
10604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2332510604
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.max_length_in_transaction.4292914238
Short name T1543
Test name
Test status
Simulation time 10137759879 ps
CPU time 15.46 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205604 kb
Host smart-67b37733-7b76-4d85-a4b0-20a1911c9306
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4292914238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.max_length_in_transaction.4292914238
Directory /workspace/7.max_length_in_transaction/latest

Test location /workspace/coverage/default/7.min_length_in_transaction.2125327827
Short name T1810
Test name
Test status
Simulation time 10084231743 ps
CPU time 14.95 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205604 kb
Host smart-4dd446dc-bb3e-4efa-b00c-b1ebf25c95a3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2125327827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.min_length_in_transaction.2125327827
Directory /workspace/7.min_length_in_transaction/latest

Test location /workspace/coverage/default/7.random_length_in_trans.1630753758
Short name T1808
Test name
Test status
Simulation time 10119211975 ps
CPU time 13.84 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205476 kb
Host smart-23f5853a-3eb7-4361-8b5e-73db51715137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
53758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.random_length_in_trans.1630753758
Directory /workspace/7.random_length_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1273216899
Short name T198
Test name
Test status
Simulation time 14131302135 ps
CPU time 19.9 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205528 kb
Host smart-03f31b84-2f55-4ef1-b231-8b164fa23e7d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1273216899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1273216899
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3257781959
Short name T1919
Test name
Test status
Simulation time 13314055477 ps
CPU time 18.99 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:45 PM PDT 24
Peak memory 205488 kb
Host smart-06255a18-3212-46cf-a0ef-d7cd4d63c067
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3257781959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3257781959
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.1809350025
Short name T46
Test name
Test status
Simulation time 13359860893 ps
CPU time 20.1 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205552 kb
Host smart-3812b2ae-d29e-480f-8915-f503d5778859
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1809350025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.1809350025
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3702941812
Short name T1291
Test name
Test status
Simulation time 10092678021 ps
CPU time 14.5 seconds
Started May 30 03:43:21 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205628 kb
Host smart-23776bd8-abef-40a5-858b-ef9fa9a0a494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
41812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3702941812
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.4138888983
Short name T1663
Test name
Test status
Simulation time 10717900886 ps
CPU time 14.82 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:36 PM PDT 24
Peak memory 205540 kb
Host smart-9f5fcd55-617d-4d66-b7d2-b93252719aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
88983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.4138888983
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2818289022
Short name T605
Test name
Test status
Simulation time 10046923842 ps
CPU time 12.69 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205580 kb
Host smart-0446fba9-b58d-4da9-8480-441dee975dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28182
89022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2818289022
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2450844723
Short name T929
Test name
Test status
Simulation time 10113640621 ps
CPU time 15.14 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205636 kb
Host smart-45a0cf52-4b71-4c1f-b908-edeb8ee00851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
44723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2450844723
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3165815109
Short name T1054
Test name
Test status
Simulation time 10816656426 ps
CPU time 15.14 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205568 kb
Host smart-b2e00127-4e51-431f-a0d3-255202c88588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31658
15109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3165815109
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1336439002
Short name T1177
Test name
Test status
Simulation time 10052069979 ps
CPU time 14.21 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205508 kb
Host smart-5d007c5f-d5a0-445d-bb3e-628e462b5024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13364
39002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1336439002
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1623019555
Short name T369
Test name
Test status
Simulation time 10098089348 ps
CPU time 14.08 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205524 kb
Host smart-30bd3fee-d5aa-4971-a743-a71270df78be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16230
19555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1623019555
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2147441957
Short name T595
Test name
Test status
Simulation time 10043573256 ps
CPU time 16.91 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205592 kb
Host smart-f92a3767-653f-455b-87cf-89773bd414bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21474
41957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2147441957
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2615122613
Short name T1348
Test name
Test status
Simulation time 10146319724 ps
CPU time 13.89 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:35 PM PDT 24
Peak memory 205548 kb
Host smart-e3796613-86ed-4b8a-b5b1-0224bb92c941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26151
22613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2615122613
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3138542569
Short name T852
Test name
Test status
Simulation time 10076982792 ps
CPU time 13.01 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205540 kb
Host smart-4710a033-71b4-4e87-b976-758c24aab92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31385
42569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3138542569
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3402381000
Short name T1457
Test name
Test status
Simulation time 13182733571 ps
CPU time 17.31 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205500 kb
Host smart-0c6a52d2-aff2-4da5-a6e9-641f746953f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34023
81000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3402381000
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.723715602
Short name T473
Test name
Test status
Simulation time 10089996252 ps
CPU time 13.07 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:35 PM PDT 24
Peak memory 205560 kb
Host smart-7f183ce7-edcd-441f-822a-e3f1f16b64b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72371
5602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.723715602
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.795328757
Short name T1865
Test name
Test status
Simulation time 10046007353 ps
CPU time 13.79 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205564 kb
Host smart-c73e456f-94e2-4101-9278-a81502332c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79532
8757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.795328757
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3494845336
Short name T815
Test name
Test status
Simulation time 10078616120 ps
CPU time 15.17 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205496 kb
Host smart-b0307ee2-aad2-42bd-b9ce-d1ad7c38d921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948
45336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3494845336
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2966333617
Short name T1383
Test name
Test status
Simulation time 10104762481 ps
CPU time 16.5 seconds
Started May 30 03:43:21 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205540 kb
Host smart-d4d27637-f6d6-4a78-9efd-a1d92b3fd95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
33617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2966333617
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.3305240855
Short name T1582
Test name
Test status
Simulation time 10091983071 ps
CPU time 13.68 seconds
Started May 30 03:43:21 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205548 kb
Host smart-1e5c7024-dd9e-40dd-b5e1-305241bb2425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052
40855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.3305240855
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.163614582
Short name T443
Test name
Test status
Simulation time 10079683852 ps
CPU time 13.52 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205572 kb
Host smart-c5c7688a-4f33-4f75-b153-75cf5559bef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16361
4582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.163614582
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1389345970
Short name T185
Test name
Test status
Simulation time 10062440593 ps
CPU time 14.73 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205544 kb
Host smart-e5a79f68-8274-4ba9-9c8a-2057a9eaeec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13893
45970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1389345970
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.3713314586
Short name T937
Test name
Test status
Simulation time 10147306312 ps
CPU time 13.44 seconds
Started May 30 03:43:21 PM PDT 24
Finished May 30 03:43:36 PM PDT 24
Peak memory 205520 kb
Host smart-c3561ad0-0e60-46a1-b422-146b17b6b351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37133
14586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.3713314586
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2065313509
Short name T290
Test name
Test status
Simulation time 10057719552 ps
CPU time 13.51 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205548 kb
Host smart-d9bf6306-db8d-4c88-a093-0a22a3b617bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20653
13509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2065313509
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2553504202
Short name T919
Test name
Test status
Simulation time 10066738909 ps
CPU time 14.05 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:35 PM PDT 24
Peak memory 205516 kb
Host smart-bb8f5b0c-723b-499d-a224-7a244f78e0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25535
04202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2553504202
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2035917789
Short name T1185
Test name
Test status
Simulation time 30362337501 ps
CPU time 59.97 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:44:23 PM PDT 24
Peak memory 205624 kb
Host smart-ca01c30e-d523-404d-9da2-99b75e1414d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359
17789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2035917789
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3917671527
Short name T615
Test name
Test status
Simulation time 10096186171 ps
CPU time 14.68 seconds
Started May 30 03:43:27 PM PDT 24
Finished May 30 03:43:43 PM PDT 24
Peak memory 205544 kb
Host smart-cb71d25f-d565-46b8-a068-5f618ae85c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39176
71527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3917671527
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1477189721
Short name T1754
Test name
Test status
Simulation time 10132896252 ps
CPU time 16.72 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205560 kb
Host smart-23aa53ac-d672-488c-8f53-46b701f36e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771
89721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1477189721
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_trans.1868962269
Short name T957
Test name
Test status
Simulation time 10085866231 ps
CPU time 13.89 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205572 kb
Host smart-bb75c291-bcf0-4aaf-a040-6be66fb7b154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18689
62269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_trans.1868962269
Directory /workspace/7.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1196624833
Short name T1430
Test name
Test status
Simulation time 10077085173 ps
CPU time 14.77 seconds
Started May 30 03:43:20 PM PDT 24
Finished May 30 03:43:36 PM PDT 24
Peak memory 205576 kb
Host smart-c4c130de-14b9-4c5c-aa02-fbbdb054ea74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11966
24833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1196624833
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1386151278
Short name T158
Test name
Test status
Simulation time 10074385750 ps
CPU time 15.61 seconds
Started May 30 03:43:21 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205608 kb
Host smart-10e88c6d-4a34-4972-981b-83c37caf20b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13861
51278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1386151278
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.4082974330
Short name T793
Test name
Test status
Simulation time 10056405591 ps
CPU time 13.31 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205516 kb
Host smart-68d1560b-36f3-40d7-8a9f-3933ef1019be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40829
74330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.4082974330
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.926297251
Short name T1869
Test name
Test status
Simulation time 10078517732 ps
CPU time 13.12 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205528 kb
Host smart-5e07b475-f770-45a3-9805-854928c62c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92629
7251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.926297251
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.375392296
Short name T1455
Test name
Test status
Simulation time 10100586021 ps
CPU time 13.12 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205560 kb
Host smart-71acb8c9-030a-4eaa-8688-020d5d1e2690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37539
2296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.375392296
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4237252887
Short name T1679
Test name
Test status
Simulation time 10073093487 ps
CPU time 13.12 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205508 kb
Host smart-1e1c6625-2ead-42d9-81b8-f716e4bb1cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
52887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4237252887
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.max_length_in_transaction.4165884305
Short name T1408
Test name
Test status
Simulation time 10195874505 ps
CPU time 14.25 seconds
Started May 30 03:43:30 PM PDT 24
Finished May 30 03:43:45 PM PDT 24
Peak memory 205548 kb
Host smart-fac3294e-1fb5-426e-a87b-f2fb5f919838
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4165884305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.max_length_in_transaction.4165884305
Directory /workspace/8.max_length_in_transaction/latest

Test location /workspace/coverage/default/8.min_length_in_transaction.904672451
Short name T888
Test name
Test status
Simulation time 10070729004 ps
CPU time 15.26 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:44 PM PDT 24
Peak memory 205560 kb
Host smart-308e4539-a8ea-431c-90c7-90730903fb35
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=904672451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.min_length_in_transaction.904672451
Directory /workspace/8.min_length_in_transaction/latest

Test location /workspace/coverage/default/8.random_length_in_trans.3355092468
Short name T688
Test name
Test status
Simulation time 10120247368 ps
CPU time 14.31 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205512 kb
Host smart-0fa9525a-2e7a-41ab-aa49-f0cb7ab9789a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33550
92468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.random_length_in_trans.3355092468
Directory /workspace/8.random_length_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1645608102
Short name T1719
Test name
Test status
Simulation time 13957728860 ps
CPU time 21.04 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:47 PM PDT 24
Peak memory 205536 kb
Host smart-a80a1531-331c-4fef-be7e-b6f3183adf90
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1645608102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1645608102
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3656441491
Short name T906
Test name
Test status
Simulation time 13247962767 ps
CPU time 16.35 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205524 kb
Host smart-e0b168a3-691d-4cc4-81f6-3bb7c35d7a71
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3656441491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3656441491
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2153561773
Short name T1236
Test name
Test status
Simulation time 13235090314 ps
CPU time 17.51 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:43 PM PDT 24
Peak memory 205524 kb
Host smart-d409c49c-7490-4897-9be5-a4b02a55be27
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2153561773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2153561773
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2462984540
Short name T752
Test name
Test status
Simulation time 10120086945 ps
CPU time 14.31 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:38 PM PDT 24
Peak memory 205572 kb
Host smart-7a91d835-6529-4546-947c-67a038503a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
84540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2462984540
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.1006059905
Short name T1649
Test name
Test status
Simulation time 11196120381 ps
CPU time 15.52 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205544 kb
Host smart-44e946c0-9ee1-446f-8cf4-c96035bc455f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10060
59905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.1006059905
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.56294003
Short name T454
Test name
Test status
Simulation time 10066942759 ps
CPU time 16.96 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205572 kb
Host smart-4694dcc7-f8d0-4fd9-9fa2-1ab297ccd9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56294
003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.56294003
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3619740638
Short name T1682
Test name
Test status
Simulation time 10060862655 ps
CPU time 14.92 seconds
Started May 30 03:44:03 PM PDT 24
Finished May 30 03:44:20 PM PDT 24
Peak memory 205584 kb
Host smart-138ae3c5-e19c-479b-a8bc-02b5301e61b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
40638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3619740638
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3439290015
Short name T1115
Test name
Test status
Simulation time 10177052932 ps
CPU time 15.16 seconds
Started May 30 03:43:25 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205516 kb
Host smart-1b26d6df-a382-46f8-8022-6d0c9b207246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
90015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3439290015
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.524271441
Short name T534
Test name
Test status
Simulation time 10091532164 ps
CPU time 14.45 seconds
Started May 30 03:43:27 PM PDT 24
Finished May 30 03:43:43 PM PDT 24
Peak memory 205524 kb
Host smart-665f661c-98bd-4173-9be9-4e660d9bfd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52427
1441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.524271441
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3595194579
Short name T65
Test name
Test status
Simulation time 10042244535 ps
CPU time 12.57 seconds
Started May 30 03:43:27 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205524 kb
Host smart-42ece221-d775-48d7-b307-b3558ad43a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35951
94579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3595194579
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2421177583
Short name T1289
Test name
Test status
Simulation time 10061618143 ps
CPU time 13.62 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205476 kb
Host smart-f5fbbbf5-9b17-4e28-b4c7-3036743c67bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24211
77583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2421177583
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1945492806
Short name T310
Test name
Test status
Simulation time 10101708048 ps
CPU time 15.92 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205588 kb
Host smart-5fd63b21-e6d8-4502-ac5e-1f979805a7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19454
92806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1945492806
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3209371379
Short name T1064
Test name
Test status
Simulation time 13248969517 ps
CPU time 18.53 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:47 PM PDT 24
Peak memory 205552 kb
Host smart-b23be5db-e2f2-4b61-9b7b-60d3440844ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32093
71379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3209371379
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.509879470
Short name T862
Test name
Test status
Simulation time 10111146782 ps
CPU time 15.92 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205560 kb
Host smart-8f8ea6b8-dc26-4b5e-836b-3854cf42c193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50987
9470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.509879470
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3082803104
Short name T301
Test name
Test status
Simulation time 10091664230 ps
CPU time 14.58 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205548 kb
Host smart-be73a415-8ce6-4b94-b3b9-be045ca64ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
03104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3082803104
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3492039396
Short name T114
Test name
Test status
Simulation time 10109504684 ps
CPU time 16.75 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205572 kb
Host smart-fbfb8474-fdee-4326-999e-0038acf01519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34920
39396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3492039396
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2487891577
Short name T1796
Test name
Test status
Simulation time 10077634828 ps
CPU time 14.62 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:48 PM PDT 24
Peak memory 205552 kb
Host smart-19ca0b2e-ec87-43da-ad8b-e2f91bd7152e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
91577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2487891577
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.382542784
Short name T358
Test name
Test status
Simulation time 10077027229 ps
CPU time 14.33 seconds
Started May 30 03:43:25 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205528 kb
Host smart-3683195e-517e-4f90-94d0-7809b1fbd20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38254
2784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.382542784
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3864425162
Short name T1883
Test name
Test status
Simulation time 10093804540 ps
CPU time 16 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205596 kb
Host smart-43a10e27-3677-4612-ae3a-9819f7a24e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
25162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3864425162
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1552601762
Short name T161
Test name
Test status
Simulation time 10075550093 ps
CPU time 14.06 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205548 kb
Host smart-0d953e23-1874-421c-a32f-9f4b769e62c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15526
01762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1552601762
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.1579084507
Short name T1027
Test name
Test status
Simulation time 10091175919 ps
CPU time 13.54 seconds
Started May 30 03:43:25 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205524 kb
Host smart-5611d44b-cef3-4dff-9cf7-303cc101b376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15790
84507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.1579084507
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3805912092
Short name T1119
Test name
Test status
Simulation time 10116216282 ps
CPU time 13.92 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:42 PM PDT 24
Peak memory 205504 kb
Host smart-69ad9c7e-b9bb-4bfe-ab0f-5abc2a6a3d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38059
12092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3805912092
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1409747024
Short name T1114
Test name
Test status
Simulation time 10054973163 ps
CPU time 14.91 seconds
Started May 30 03:43:30 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205504 kb
Host smart-6fa1826e-cc48-4106-b47b-f080bb8ce801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14097
47024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1409747024
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3126153132
Short name T1625
Test name
Test status
Simulation time 33384083729 ps
CPU time 68.42 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:44:34 PM PDT 24
Peak memory 205588 kb
Host smart-aba4f04d-fa1c-4ce5-9236-d0de69a97ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31261
53132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3126153132
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.537403736
Short name T864
Test name
Test status
Simulation time 10069526496 ps
CPU time 13.51 seconds
Started May 30 03:43:24 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205540 kb
Host smart-e7d06130-bfb7-4487-99b8-1bee6b079b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53740
3736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.537403736
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1927724231
Short name T1107
Test name
Test status
Simulation time 10131633061 ps
CPU time 13.56 seconds
Started May 30 03:43:25 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205552 kb
Host smart-14cb73ed-ac8e-44c1-a6e5-af683dcd5ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19277
24231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1927724231
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_trans.1068631293
Short name T1701
Test name
Test status
Simulation time 10088198139 ps
CPU time 14.72 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:47 PM PDT 24
Peak memory 205552 kb
Host smart-b665a917-7a05-4f1d-a9b5-e5a5e7f7b8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10686
31293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_trans.1068631293
Directory /workspace/8.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1598151253
Short name T718
Test name
Test status
Simulation time 10050697813 ps
CPU time 16.15 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:44 PM PDT 24
Peak memory 205492 kb
Host smart-ea525c35-95e2-4bf8-b6a8-e2987051927d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
51253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1598151253
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.782142051
Short name T1650
Test name
Test status
Simulation time 10096908631 ps
CPU time 13.31 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:37 PM PDT 24
Peak memory 205564 kb
Host smart-b6e4921b-4573-4ab1-991c-473254db9c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78214
2051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.782142051
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.938976208
Short name T586
Test name
Test status
Simulation time 10059544160 ps
CPU time 13.55 seconds
Started May 30 03:43:25 PM PDT 24
Finished May 30 03:43:41 PM PDT 24
Peak memory 205516 kb
Host smart-fc8f8535-5102-4b34-9ed2-2d291e66e415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93897
6208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.938976208
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.4250913661
Short name T730
Test name
Test status
Simulation time 10175194711 ps
CPU time 14.06 seconds
Started May 30 03:43:23 PM PDT 24
Finished May 30 03:43:39 PM PDT 24
Peak memory 205592 kb
Host smart-f5224184-31b9-4b81-8e3a-01cea9671ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42509
13661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4250913661
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1622744481
Short name T503
Test name
Test status
Simulation time 10068371078 ps
CPU time 16.54 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205552 kb
Host smart-228e5ef0-4490-41fe-b155-bd4d761f596d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16227
44481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1622744481
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1284961798
Short name T618
Test name
Test status
Simulation time 10056116952 ps
CPU time 13.82 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205520 kb
Host smart-af25f34c-0cc3-4b75-83e5-2de0143b3929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
61798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1284961798
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.max_length_in_transaction.3778010201
Short name T787
Test name
Test status
Simulation time 10196842703 ps
CPU time 13.35 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205528 kb
Host smart-2a0e3611-a688-497b-838a-1adb97e8fb5e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3778010201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.max_length_in_transaction.3778010201
Directory /workspace/9.max_length_in_transaction/latest

Test location /workspace/coverage/default/9.min_length_in_transaction.1162763715
Short name T462
Test name
Test status
Simulation time 10069484111 ps
CPU time 13.22 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205580 kb
Host smart-b2f10dcd-786a-43a3-b218-aaa8eb5c7fd3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1162763715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.min_length_in_transaction.1162763715
Directory /workspace/9.min_length_in_transaction/latest

Test location /workspace/coverage/default/9.random_length_in_trans.2646282546
Short name T1565
Test name
Test status
Simulation time 10093972391 ps
CPU time 13.58 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205528 kb
Host smart-b24afc68-4d51-4550-82ef-b8f4c083f224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26462
82546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.random_length_in_trans.2646282546
Directory /workspace/9.random_length_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1447726538
Short name T678
Test name
Test status
Simulation time 14189529881 ps
CPU time 22.08 seconds
Started May 30 03:43:26 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205564 kb
Host smart-af97ab05-c733-4f44-b232-8e0024278c08
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1447726538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1447726538
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1682300722
Short name T1490
Test name
Test status
Simulation time 13262260487 ps
CPU time 16.51 seconds
Started May 30 03:43:27 PM PDT 24
Finished May 30 03:43:45 PM PDT 24
Peak memory 205540 kb
Host smart-796a67c9-7493-47ff-aaef-ed68e885a80e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1682300722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1682300722
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3706567574
Short name T444
Test name
Test status
Simulation time 13294781567 ps
CPU time 16.89 seconds
Started May 30 03:43:22 PM PDT 24
Finished May 30 03:43:40 PM PDT 24
Peak memory 205580 kb
Host smart-edb38ef5-a150-4311-a444-da69313d8e8f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3706567574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3706567574
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1541637113
Short name T1226
Test name
Test status
Simulation time 10104156096 ps
CPU time 13.8 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205560 kb
Host smart-3a5ff5cc-6417-4687-b9e0-92ba8e1fa73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
37113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1541637113
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.603060425
Short name T54
Test name
Test status
Simulation time 10088795552 ps
CPU time 16.03 seconds
Started May 30 03:43:27 PM PDT 24
Finished May 30 03:43:45 PM PDT 24
Peak memory 205568 kb
Host smart-de19e7ef-a404-472d-97ee-dedcfb32754a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60306
0425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.603060425
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1771064365
Short name T1080
Test name
Test status
Simulation time 10914443287 ps
CPU time 14.54 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:47 PM PDT 24
Peak memory 205580 kb
Host smart-8d354f2e-d5e3-48a8-b37f-62d541fbdc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17710
64365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1771064365
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.490949790
Short name T227
Test name
Test status
Simulation time 10045458138 ps
CPU time 14.96 seconds
Started May 30 03:43:33 PM PDT 24
Finished May 30 03:43:49 PM PDT 24
Peak memory 205540 kb
Host smart-ea94af93-87aa-4bfc-9f8a-8e8ad47ceb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49094
9790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.490949790
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1331987264
Short name T1434
Test name
Test status
Simulation time 10068143743 ps
CPU time 13.62 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205620 kb
Host smart-fedc3fb2-ae06-481b-8ab1-e29573d6ad20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
87264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1331987264
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2206286547
Short name T1184
Test name
Test status
Simulation time 10709748353 ps
CPU time 16.26 seconds
Started May 30 03:43:31 PM PDT 24
Finished May 30 03:43:49 PM PDT 24
Peak memory 205540 kb
Host smart-481f36f3-fe31-4ad5-9e9e-6eb2d96dbbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22062
86547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2206286547
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.919100244
Short name T806
Test name
Test status
Simulation time 10082530714 ps
CPU time 14.66 seconds
Started May 30 03:43:30 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205532 kb
Host smart-405c63b5-3cf0-4a2d-acde-2af2f527b3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91910
0244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.919100244
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3299087424
Short name T1622
Test name
Test status
Simulation time 10080318218 ps
CPU time 16.19 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205548 kb
Host smart-d276cc50-a43f-4ce3-9560-2a002e81a53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32990
87424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3299087424
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3364330750
Short name T733
Test name
Test status
Simulation time 10052093678 ps
CPU time 15.84 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205584 kb
Host smart-113807b5-6982-463f-a4f2-1fad99bf06cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33643
30750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3364330750
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.308789160
Short name T126
Test name
Test status
Simulation time 10138863888 ps
CPU time 15.15 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205520 kb
Host smart-223a5359-779c-4ec4-89a8-105574419a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30878
9160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.308789160
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2205999931
Short name T638
Test name
Test status
Simulation time 10051778690 ps
CPU time 13.47 seconds
Started May 30 03:43:33 PM PDT 24
Finished May 30 03:43:48 PM PDT 24
Peak memory 205532 kb
Host smart-55ae92f5-2c24-4cec-8c03-86b43e4de92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22059
99931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2205999931
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3815093408
Short name T1717
Test name
Test status
Simulation time 13171369816 ps
CPU time 16.84 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:57 PM PDT 24
Peak memory 205516 kb
Host smart-4a618178-eb5a-4cca-9274-da28487b04eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38150
93408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3815093408
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.682514343
Short name T1889
Test name
Test status
Simulation time 10162491432 ps
CPU time 12.89 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205536 kb
Host smart-6c94d544-a7e9-498b-8361-1498060046d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68251
4343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.682514343
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3228272590
Short name T779
Test name
Test status
Simulation time 10044868122 ps
CPU time 15.44 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205576 kb
Host smart-406b1c31-2206-46a0-8293-f409174bd720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32282
72590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3228272590
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.4208651917
Short name T936
Test name
Test status
Simulation time 10087510477 ps
CPU time 14.6 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205540 kb
Host smart-3d168cb4-3d07-4dec-bb86-b2e2c106f5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42086
51917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.4208651917
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.1191342342
Short name T289
Test name
Test status
Simulation time 10091406718 ps
CPU time 13.71 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:53 PM PDT 24
Peak memory 205556 kb
Host smart-bf169c87-5d64-411d-a441-18b9f64bb853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11913
42342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.1191342342
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1054377157
Short name T1223
Test name
Test status
Simulation time 10057735741 ps
CPU time 16.54 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205636 kb
Host smart-5ba2d4d4-17ad-420f-a92d-3c9af4d37771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
77157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1054377157
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4012418105
Short name T1281
Test name
Test status
Simulation time 10050515245 ps
CPU time 13.11 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:49 PM PDT 24
Peak memory 205520 kb
Host smart-8d58c51a-7753-49d4-9f27-b85031fe7a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40124
18105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4012418105
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.4173354718
Short name T87
Test name
Test status
Simulation time 10126465627 ps
CPU time 13.31 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205572 kb
Host smart-6a40866c-d805-438c-9db0-028dfbcb767a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
54718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.4173354718
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.1566752001
Short name T1077
Test name
Test status
Simulation time 10066238066 ps
CPU time 15.19 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205564 kb
Host smart-ff1ee3bd-84d8-4c42-826a-1d3de205f516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15667
52001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.1566752001
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3269448520
Short name T751
Test name
Test status
Simulation time 10053950785 ps
CPU time 13.18 seconds
Started May 30 03:43:37 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205500 kb
Host smart-85f700be-23d4-4821-832f-55f21410e20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
48520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3269448520
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3136960376
Short name T548
Test name
Test status
Simulation time 10041548260 ps
CPU time 15.93 seconds
Started May 30 03:43:33 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205576 kb
Host smart-f7772514-1a30-4cb1-94fe-450172960c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
60376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3136960376
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2499090835
Short name T1697
Test name
Test status
Simulation time 20444403479 ps
CPU time 35.39 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:44:11 PM PDT 24
Peak memory 205616 kb
Host smart-5ce018f0-e5e1-4f37-abf2-c8a5337f69b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24990
90835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2499090835
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3754199521
Short name T1546
Test name
Test status
Simulation time 10142087280 ps
CPU time 14.86 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205504 kb
Host smart-69a0a7c4-178d-428d-8ff3-a3efaa884c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541
99521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3754199521
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.876363092
Short name T596
Test name
Test status
Simulation time 10125607086 ps
CPU time 14.92 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:52 PM PDT 24
Peak memory 205544 kb
Host smart-9570bd62-2d44-4251-b854-402d3d3e4985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87636
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.876363092
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_trans.683131754
Short name T1593
Test name
Test status
Simulation time 10079487289 ps
CPU time 13.93 seconds
Started May 30 03:43:39 PM PDT 24
Finished May 30 03:43:55 PM PDT 24
Peak memory 205572 kb
Host smart-f335e94c-faf5-4350-a734-b19ba2f3ed92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68313
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_trans.683131754
Directory /workspace/9.usbdev_random_length_out_trans/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1376222531
Short name T1436
Test name
Test status
Simulation time 10055392623 ps
CPU time 14.31 seconds
Started May 30 03:43:34 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205568 kb
Host smart-8036b36c-8fa0-49e4-8eee-c962a8a03da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762
22531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1376222531
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.457022471
Short name T63
Test name
Test status
Simulation time 10117524481 ps
CPU time 12.62 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205560 kb
Host smart-aa1b88ba-b712-45a6-8cab-9b3cd3004ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45702
2471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.457022471
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2347939076
Short name T1628
Test name
Test status
Simulation time 10077125981 ps
CPU time 12.73 seconds
Started May 30 03:43:36 PM PDT 24
Finished May 30 03:43:51 PM PDT 24
Peak memory 205520 kb
Host smart-7f7fc7f4-2f80-458a-bb7f-c197a3967e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23479
39076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2347939076
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3662663471
Short name T1459
Test name
Test status
Simulation time 10140494470 ps
CPU time 15.38 seconds
Started May 30 03:43:30 PM PDT 24
Finished May 30 03:43:46 PM PDT 24
Peak memory 205560 kb
Host smart-4cb0c64e-504c-41eb-9e2c-b03362addac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626
63471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3662663471
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.144694703
Short name T1287
Test name
Test status
Simulation time 10095165319 ps
CPU time 13.11 seconds
Started May 30 03:43:38 PM PDT 24
Finished May 30 03:43:54 PM PDT 24
Peak memory 205524 kb
Host smart-65c3ed39-f691-4e22-9179-98831eeaafb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14469
4703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.144694703
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2759653978
Short name T1822
Test name
Test status
Simulation time 10053570890 ps
CPU time 13.13 seconds
Started May 30 03:43:35 PM PDT 24
Finished May 30 03:43:50 PM PDT 24
Peak memory 205468 kb
Host smart-b46dec07-0205-438a-aace-3882375f31ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27596
53978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2759653978
Directory /workspace/9.usbdev_stall_trans/latest
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