Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16458459	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9815856	1		T1	5		T2	8		T3	35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25907918	1		T1	3700		T2	3510		T3	3708
values[0x0]	182680	1		T1	3		T2	3		T3	15
values[0x1]	183717	1		T1	5		T2	4		T3	15

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12800443	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	13473872	1		T1	927		T2	890		T3	908

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	81996	1		T1	7		T2	15		T3	13
valid_sources[0x01]	81934	1		T1	9		T2	18		T3	22
valid_sources[0x02]	86657	1		T1	17		T3	13		T29	16
valid_sources[0x03]	83180	1		T1	13		T2	20		T3	20
valid_sources[0x04]	81047	1		T1	14		T2	9		T3	21
valid_sources[0x05]	82870	1		T1	17		T2	6		T3	19
valid_sources[0x06]	89916	1		T1	9		T2	20		T3	18
valid_sources[0x07]	87259	1		T1	12		T2	18		T3	11
valid_sources[0x08]	83504	1		T1	7		T2	7		T3	14
valid_sources[0x09]	294684	1		T1	12		T3	19		T29	12
valid_sources[0x0a]	81655	1		T1	13		T2	50		T3	5
valid_sources[0x0b]	191488	1		T1	19		T2	25		T3	17
valid_sources[0x0c]	81942	1		T1	15		T3	18		T29	11
valid_sources[0x0d]	128360	1		T1	4		T2	5		T3	14
valid_sources[0x0e]	90078	1		T1	17		T2	7		T3	6
valid_sources[0x0f]	89119	1		T1	19		T2	14		T3	10
valid_sources[0x10]	79221	1		T1	20		T2	5		T3	14
valid_sources[0x11]	89777	1		T1	18		T2	24		T3	17
valid_sources[0x12]	77419	1		T1	15		T2	13		T3	21
valid_sources[0x13]	83619	1		T1	22		T2	21		T3	20
valid_sources[0x14]	196850	1		T1	16		T2	13		T3	18
valid_sources[0x15]	112246	1		T1	13		T2	8		T3	17
valid_sources[0x16]	89457	1		T1	12		T2	12		T3	22
valid_sources[0x17]	86505	1		T1	7		T2	16		T3	17
valid_sources[0x18]	81865	1		T1	10		T2	11		T3	12
valid_sources[0x19]	143940	1		T1	13		T2	17		T3	7
valid_sources[0x1a]	142040	1		T1	11		T2	18		T3	10
valid_sources[0x1b]	85248	1		T1	19		T2	13		T3	14
valid_sources[0x1c]	86777	1		T1	15		T2	19		T3	9
valid_sources[0x1d]	79030	1		T1	19		T2	19		T3	6
valid_sources[0x1e]	89427	1		T1	20		T2	12		T3	13
valid_sources[0x1f]	84501	1		T1	18		T2	18		T3	18
valid_sources[0x20]	79845	1		T1	13		T2	12		T3	7
valid_sources[0x21]	725070	1		T1	20		T2	30		T3	5
valid_sources[0x22]	92680	1		T1	17		T2	5		T3	18
valid_sources[0x23]	95875	1		T1	19		T2	4		T3	12
valid_sources[0x24]	81938	1		T1	14		T2	8		T3	15
valid_sources[0x25]	79607	1		T1	6		T2	10		T3	18
valid_sources[0x26]	83849	1		T1	10		T2	2		T3	23
valid_sources[0x27]	93330	1		T1	7		T2	4		T3	12
valid_sources[0x28]	88841	1		T1	10		T2	8		T3	17
valid_sources[0x29]	82094	1		T1	14		T2	29		T3	7
valid_sources[0x2a]	90394	1		T1	7		T2	41		T3	24
valid_sources[0x2b]	86948	1		T1	16		T2	17		T3	6
valid_sources[0x2c]	81872	1		T1	14		T2	10		T3	15
valid_sources[0x2d]	87087	1		T1	15		T2	39		T3	13
valid_sources[0x2e]	82517	1		T1	10		T2	22		T3	12
valid_sources[0x2f]	85791	1		T1	16		T2	22		T3	24
valid_sources[0x30]	82371	1		T1	13		T2	21		T3	13
valid_sources[0x31]	85839	1		T1	21		T2	6		T3	11
valid_sources[0x32]	80193	1		T1	24		T2	11		T3	18
valid_sources[0x33]	81795	1		T1	14		T2	15		T3	18
valid_sources[0x34]	382151	1		T1	16		T2	12		T3	12
valid_sources[0x35]	84750	1		T1	30		T3	18		T29	19
valid_sources[0x36]	84881	1		T1	14		T2	3		T3	16
valid_sources[0x37]	78288	1		T1	18		T2	16		T3	9
valid_sources[0x38]	83337	1		T1	20		T2	14		T3	13
valid_sources[0x39]	88935	1		T1	14		T2	3		T3	6
valid_sources[0x3a]	82471	1		T1	13		T2	1		T3	13
valid_sources[0x3b]	86929	1		T1	16		T2	9		T3	17
valid_sources[0x3c]	86453	1		T1	32		T2	3		T3	11
valid_sources[0x3d]	90339	1		T1	11		T2	17		T3	13
valid_sources[0x3e]	89795	1		T1	19		T2	2		T3	15
valid_sources[0x3f]	90268	1		T1	4		T2	17		T3	13
valid_sources[0x40]	84075	1		T1	9		T2	6		T3	20
valid_sources[0x41]	82862	1		T1	19		T2	25		T3	22
valid_sources[0x42]	86498	1		T1	13		T2	4		T3	8
valid_sources[0x43]	79169	1		T1	12		T2	16		T3	18
valid_sources[0x44]	86670	1		T1	16		T2	8		T3	19
valid_sources[0x45]	82419	1		T1	17		T2	18		T3	10
valid_sources[0x46]	180038	1		T1	20		T2	23		T3	22
valid_sources[0x47]	88955	1		T1	6		T2	9		T3	7
valid_sources[0x48]	82582	1		T1	11		T2	25		T3	18
valid_sources[0x49]	82173	1		T1	11		T2	31		T3	10
valid_sources[0x4a]	78125	1		T1	14		T2	38		T3	9
valid_sources[0x4b]	88288	1		T1	7		T2	4		T3	13
valid_sources[0x4c]	87733	1		T1	15		T2	5		T3	8
valid_sources[0x4d]	83679	1		T1	8		T2	9		T3	16
valid_sources[0x4e]	78524	1		T1	27		T2	4		T3	18
valid_sources[0x4f]	200688	1		T1	18		T2	9		T3	11
valid_sources[0x50]	91105	1		T1	25		T2	15		T3	18
valid_sources[0x51]	83675	1		T1	22		T2	30		T3	11
valid_sources[0x52]	88092	1		T1	23		T2	15		T3	13
valid_sources[0x53]	82989	1		T1	19		T2	1		T3	13
valid_sources[0x54]	95097	1		T1	17		T2	22		T3	14
valid_sources[0x55]	83200	1		T1	15		T2	14		T3	16
valid_sources[0x56]	82251	1		T1	15		T2	13		T3	16
valid_sources[0x57]	86752	1		T1	18		T2	15		T3	19
valid_sources[0x58]	90288	1		T1	20		T2	3		T3	12
valid_sources[0x59]	176267	1		T1	17		T2	10		T3	16
valid_sources[0x5a]	170943	1		T1	9		T2	5		T3	9
valid_sources[0x5b]	156873	1		T1	8		T2	6		T3	11
valid_sources[0x5c]	84052	1		T1	7		T2	3		T3	10
valid_sources[0x5d]	92388	1		T1	13		T2	27		T3	15
valid_sources[0x5e]	87148	1		T1	15		T2	14		T3	20
valid_sources[0x5f]	83199	1		T1	16		T2	13		T3	22
valid_sources[0x60]	82300	1		T1	16		T2	7		T3	17
valid_sources[0x61]	83305	1		T1	15		T2	17		T3	9
valid_sources[0x62]	78516	1		T1	24		T2	29		T3	15
valid_sources[0x63]	86220	1		T1	21		T2	7		T3	10
valid_sources[0x64]	90229	1		T1	4		T2	2		T3	19
valid_sources[0x65]	87199	1		T1	23		T2	18		T3	8
valid_sources[0x66]	85577	1		T1	14		T2	20		T3	17
valid_sources[0x67]	81804	1		T1	5		T2	5		T3	10
valid_sources[0x68]	82574	1		T1	8		T2	13		T3	17
valid_sources[0x69]	378164	1		T1	15		T2	29		T3	34
valid_sources[0x6a]	82608	1		T1	9		T2	29		T3	12
valid_sources[0x6b]	82598	1		T1	9		T2	14		T3	4
valid_sources[0x6c]	91875	1		T1	21		T2	7		T3	13
valid_sources[0x6d]	85984	1		T1	11		T2	17		T3	15
valid_sources[0x6e]	85135	1		T1	11		T2	28		T3	17
valid_sources[0x6f]	81521	1		T1	9		T2	8		T3	16
valid_sources[0x70]	89551	1		T1	9		T2	8		T3	9
valid_sources[0x71]	82598	1		T1	12		T2	11		T3	11
valid_sources[0x72]	93318	1		T1	15		T2	5		T3	15
valid_sources[0x73]	79894	1		T1	16		T2	29		T3	12
valid_sources[0x74]	149714	1		T1	12		T2	28		T3	13
valid_sources[0x75]	83418	1		T1	15		T2	19		T3	11
valid_sources[0x76]	86315	1		T1	13		T2	5		T3	23
valid_sources[0x77]	78981	1		T1	7		T2	19		T3	29
valid_sources[0x78]	86063	1		T1	7		T2	11		T3	23
valid_sources[0x79]	80545	1		T1	16		T2	7		T3	16
valid_sources[0x7a]	78865	1		T1	21		T2	7		T3	22
valid_sources[0x7b]	81861	1		T1	23		T2	5		T3	17
valid_sources[0x7c]	81536	1		T1	12		T2	31		T3	15
valid_sources[0x7d]	78816	1		T1	24		T2	23		T3	16
valid_sources[0x7e]	85757	1		T1	11		T2	7		T3	21
valid_sources[0x7f]	82355	1		T1	11		T2	42		T3	15
valid_sources[0x80]	78776	1		T1	20		T2	24		T3	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9531436

1

T1

3

T2

4

T3

12

values[0x0]

all_enables

biggest_size

147346

1

T1

2

T2

3

T3

13

values[0x1]

all_enables

biggest_size

137074

1

T2

1

T3

10

T29

13