Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16470823	1		T1	3703		T2	3509		T3	3703
full_word	9816719	1		T1	5		T2	8		T3	35

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	26287222	1		T1	3708		T2	3517		T3	3738
auto[TlIntgErrCmd]	105	1		T199	2		T200	6		T201	5
auto[TlIntgErrData]	116	1		T199	6		T200	1		T201	11
auto[TlIntgErrBoth]	99	1		T199	2		T200	3		T201	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25909500	1		T1	3700		T2	3510		T3	3708
auto[1]	378042	1		T1	8		T2	7		T3	30

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16377784	1		T1	3697		T2	3506		T3	3696
auto[TlIntgErrNone]	partial	auto[1]	92751	1		T1	6		T2	3		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	9531587	1		T1	3		T2	4		T3	12
auto[TlIntgErrNone]	full_word	auto[1]	285100	1		T1	2		T2	4		T3	23
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T200	3		T219	4		T223	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T199	2		T200	3		T201	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T223	1		T238	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T201	1		T284	2		T282	1
auto[TlIntgErrData]	partial	auto[0]	51	1		T199	2		T201	7		T219	1
auto[TlIntgErrData]	partial	auto[1]	55	1		T199	4		T200	1		T201	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T223	1		T280	1		T285	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T286	1		T287	1		T282	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T200	1		T223	2		T238	6
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T199	2		T200	2		T201	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T201	1		T284	1		T282	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T219	1		T223	1		T286	1