Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1110212793	10355	0	0
ep_in_enable_rd_A	1110212793	2119	0	0
ep_out_enable_rd_A	1110212793	2513	0	0
in_iso_rd_A	1110212793	2095	0	0
intr_enable_rd_A	1110212793	3514	0	0
out_iso_rd_A	1110212793	2009	0	0
phy_config_rd_A	1110212793	1585	0	0
phy_pins_drive_rd_A	1110212793	2012	0	0
rxenable_setup_rd_A	1110212793	2226	0	0
set_nak_out_rd_A	1110212793	2125	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	10355	0	0
T199	14006	3	0	0
T200	18100	3	0	0
T201	44257	3	0	0
T220	12686	14	0	0
T221	7649	169	0	0
T222	4454	21	0	0
T223	58849	7	0	0
T225	12246	493	0	0
T236	4908	17	0	0
T238	38333	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2119	0	0
T227	8481	57	0	0
T237	8649	11	0	0
T240	8542	72	0	0
T252	4417	79	0	0
T253	4974	1	0	0
T254	16596	118	0	0
T259	10683	41	0	0
T260	13374	60	0	0
T263	5766	29	0	0
T264	3418	14	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2513	0	0
T227	8481	39	0	0
T237	8649	28	0	0
T240	8542	112	0	0
T252	4417	51	0	0
T254	16596	149	0	0
T259	10683	24	0	0
T260	13374	67	0	0
T263	5766	40	0	0
T265	7528	61	0	0
T266	5234	59	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2095	0	0
T227	8481	7	0	0
T237	8649	8	0	0
T240	8542	85	0	0
T252	4417	45	0	0
T253	4974	6	0	0
T254	16596	87	0	0
T259	10683	59	0	0
T260	13374	36	0	0
T263	5766	14	0	0
T265	7528	66	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	3514	0	0
T99	5410	15	0	0
T237	8649	24	0	0
T240	8542	91	0	0
T252	4417	3	0	0
T254	16596	77	0	0
T259	10683	39	0	0
T260	13374	57	0	0
T263	5766	2	0	0
T267	2742	16	0	0
T268	1738	14	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2009	0	0
T227	8481	54	0	0
T237	8649	43	0	0
T240	8542	18	0	0
T252	4417	44	0	0
T254	16596	85	0	0
T259	10683	24	0	0
T260	13374	48	0	0
T263	5766	15	0	0
T264	3418	5	0	0
T265	7528	67	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	1585	0	0
T227	8481	40	0	0
T237	8649	20	0	0
T240	8542	55	0	0
T252	4417	15	0	0
T253	4974	13	0	0
T254	16596	115	0	0
T259	10683	15	0	0
T260	13374	47	0	0
T263	5766	19	0	0
T265	7528	28	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2012	0	0
T227	8481	43	0	0
T237	8649	32	0	0
T240	8542	45	0	0
T252	4417	4	0	0
T253	4974	8	0	0
T254	16596	123	0	0
T259	10683	28	0	0
T260	13374	55	0	0
T263	5766	13	0	0
T264	3418	2	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2226	0	0
T227	8481	10	0	0
T237	8649	12	0	0
T240	8542	50	0	0
T252	4417	60	0	0
T253	4974	9	0	0
T254	16596	94	0	0
T259	10683	23	0	0
T260	13374	59	0	0
T263	5766	4	0	0
T265	7528	21	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110212793	2125	0	0
T227	8481	38	0	0
T237	8649	67	0	0
T240	8542	15	0	0
T252	4417	3	0	0
T253	4974	3	0	0
T254	16596	97	0	0
T259	10683	36	0	0
T260	13374	76	0	0
T263	5766	8	0	0
T264	3418	4	0	0