Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	356	1		T1	5		T3	5		T12	8
all_values[1]	356	1		T1	5		T3	5		T12	8
all_values[2]	356	1		T1	5		T3	5		T12	8
all_values[3]	356	1		T1	5		T3	5		T12	8
all_values[4]	356	1		T1	5		T3	5		T12	8
all_values[5]	356	1		T1	5		T3	5		T12	8
all_values[6]	356	1		T1	5		T3	5		T12	8
all_values[7]	356	1		T1	5		T3	5		T12	8
all_values[8]	356	1		T1	5		T3	5		T12	8
all_values[9]	356	1		T1	5		T3	5		T12	8
all_values[10]	356	1		T1	5		T3	5		T12	8
all_values[11]	356	1		T1	5		T3	5		T12	8
all_values[12]	356	1		T1	5		T3	5		T12	8
all_values[13]	356	1		T1	5		T3	5		T12	8
all_values[14]	356	1		T1	5		T3	5		T12	8
all_values[15]	356	1		T1	5		T3	5		T12	8
all_values[16]	356	1		T1	5		T3	5		T12	8
all_values[17]	356	1		T1	5		T3	5		T12	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3641	1		T1	60		T3	56		T12	67
auto[1]	2767	1		T1	30		T3	34		T12	77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1660	1		T1	22		T3	24		T12	17
auto[1]	4748	1		T1	68		T3	66		T12	127

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	64	1		T3	1		T12	1		T18	2
all_values[0]	auto[0]	auto[1]	124	1		T1	4		T3	4		T13	5
all_values[0]	auto[1]	auto[0]	20	1		T12	3		T62	1		T47	1
all_values[0]	auto[1]	auto[1]	148	1		T1	1		T12	4		T13	3
all_values[1]	auto[0]	auto[0]	58	1		T18	2		T14	1		T22	2
all_values[1]	auto[0]	auto[1]	131	1		T1	4		T12	5		T13	4
all_values[1]	auto[1]	auto[0]	26	1		T12	1		T63	2		T64	1
all_values[1]	auto[1]	auto[1]	141	1		T1	1		T3	5		T12	2
all_values[2]	auto[0]	auto[0]	69	1		T13	1		T18	2		T63	1
all_values[2]	auto[0]	auto[1]	140	1		T3	2		T12	5		T13	1
all_values[2]	auto[1]	auto[0]	31	1		T1	1		T13	1		T25	5
all_values[2]	auto[1]	auto[1]	116	1		T1	4		T3	3		T12	3
all_values[3]	auto[0]	auto[0]	59	1		T18	2		T63	1		T22	2
all_values[3]	auto[0]	auto[1]	132	1		T1	3		T12	2		T13	1
all_values[3]	auto[1]	auto[0]	25	1		T3	5		T12	1		T13	1
all_values[3]	auto[1]	auto[1]	140	1		T1	2		T12	5		T13	6
all_values[4]	auto[0]	auto[0]	65	1		T1	4		T3	1		T12	2
all_values[4]	auto[0]	auto[1]	118	1		T3	4		T12	1		T13	4
all_values[4]	auto[1]	auto[0]	25	1		T1	1		T12	1		T62	1
all_values[4]	auto[1]	auto[1]	148	1		T12	4		T13	4		T25	3
all_values[5]	auto[0]	auto[0]	74	1		T1	1		T13	1		T18	2
all_values[5]	auto[0]	auto[1]	136	1		T1	1		T12	2		T13	4
all_values[5]	auto[1]	auto[0]	20	1		T12	1		T15	1		T64	2
all_values[5]	auto[1]	auto[1]	126	1		T1	3		T3	5		T12	5
all_values[6]	auto[0]	auto[0]	74	1		T12	2		T18	2		T15	1
all_values[6]	auto[0]	auto[1]	138	1		T1	4		T3	5		T13	4
all_values[6]	auto[1]	auto[0]	21	1		T63	1		T46	1		T65	2
all_values[6]	auto[1]	auto[1]	123	1		T1	1		T12	6		T13	4
all_values[7]	auto[0]	auto[0]	68	1		T1	1		T12	1		T18	2
all_values[7]	auto[0]	auto[1]	147	1		T1	3		T3	4		T12	4
all_values[7]	auto[1]	auto[0]	17	1		T62	2		T66	1		T67	2
all_values[7]	auto[1]	auto[1]	124	1		T1	1		T3	1		T12	3
all_values[8]	auto[0]	auto[0]	76	1		T3	1		T18	2		T15	1
all_values[8]	auto[0]	auto[1]	132	1		T1	4		T3	3		T12	4
all_values[8]	auto[1]	auto[0]	26	1		T3	1		T12	1		T47	1
all_values[8]	auto[1]	auto[1]	122	1		T1	1		T12	3		T13	5
all_values[9]	auto[0]	auto[0]	66	1		T13	1		T18	2		T14	5
all_values[9]	auto[0]	auto[1]	140	1		T1	3		T3	3		T12	5
all_values[9]	auto[1]	auto[0]	29	1		T3	1		T12	1		T13	3
all_values[9]	auto[1]	auto[1]	121	1		T1	2		T3	1		T12	2
all_values[10]	auto[0]	auto[0]	61	1		T3	4		T18	2		T25	1
all_values[10]	auto[0]	auto[1]	140	1		T1	1		T12	3		T13	4
all_values[10]	auto[1]	auto[0]	33	1		T3	1		T13	2		T63	1
all_values[10]	auto[1]	auto[1]	122	1		T1	4		T12	5		T13	2
all_values[11]	auto[0]	auto[0]	70	1		T1	1		T3	4		T13	1
all_values[11]	auto[0]	auto[1]	122	1		T1	4		T12	2		T13	4
all_values[11]	auto[1]	auto[0]	35	1		T3	1		T13	1		T25	5
all_values[11]	auto[1]	auto[1]	129	1		T12	6		T13	2		T14	5
all_values[12]	auto[0]	auto[0]	58	1		T18	2		T25	1		T14	1
all_values[12]	auto[0]	auto[1]	134	1		T1	4		T3	2		T12	6
all_values[12]	auto[1]	auto[0]	29	1		T12	1		T25	1		T14	1
all_values[12]	auto[1]	auto[1]	135	1		T1	1		T3	3		T12	1
all_values[13]	auto[0]	auto[0]	61	1		T13	1		T18	2		T63	1
all_values[13]	auto[0]	auto[1]	148	1		T1	4		T3	2		T12	6
all_values[13]	auto[1]	auto[0]	24	1		T13	1		T46	4		T68	2
all_values[13]	auto[1]	auto[1]	123	1		T1	1		T3	3		T12	2
all_values[14]	auto[0]	auto[0]	74	1		T1	1		T3	1		T18	2
all_values[14]	auto[0]	auto[1]	138	1		T1	3		T3	3		T12	4
all_values[14]	auto[1]	auto[0]	31	1		T1	1		T3	1		T12	1
all_values[14]	auto[1]	auto[1]	113	1		T12	3		T13	1		T25	1
all_values[15]	auto[0]	auto[0]	63	1		T1	1		T18	2		T15	1
all_values[15]	auto[0]	auto[1]	163	1		T1	4		T3	4		T12	1
all_values[15]	auto[1]	auto[0]	17	1		T25	1		T45	1		T68	1
all_values[15]	auto[1]	auto[1]	113	1		T3	1		T12	7		T13	2
all_values[16]	auto[0]	auto[0]	64	1		T1	2		T3	1		T13	1
all_values[16]	auto[0]	auto[1]	142	1		T3	4		T12	5		T13	1
all_values[16]	auto[1]	auto[0]	34	1		T1	3		T13	1		T25	4
all_values[16]	auto[1]	auto[1]	116	1		T12	3		T13	5		T14	3
all_values[17]	auto[0]	auto[0]	64	1		T1	3		T18	2		T25	2
all_values[17]	auto[0]	auto[1]	128	1		T3	3		T12	6		T13	4
all_values[17]	auto[1]	auto[0]	29	1		T1	2		T3	1		T25	3
all_values[17]	auto[1]	auto[1]	135	1		T3	1		T12	2		T13	4