| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 68.61 | 66.51 | 61.50 | 87.79 | 0.00 | 70.24 | 98.04 | 96.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 56.06 | 56.06 | 62.17 | 62.17 | 51.10 | 51.10 | 90.57 | 90.57 | 0.00 | 0.00 | 63.31 | 63.31 | 91.90 | 91.90 | 33.33 | 33.33 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3308442521 |
| 63.57 | 7.51 | 62.97 | 0.80 | 52.27 | 1.16 | 94.58 | 4.01 | 0.00 | 0.00 | 63.36 | 0.04 | 92.18 | 0.28 | 79.64 | 46.31 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.969890439 |
| 66.63 | 3.06 | 66.04 | 3.07 | 58.27 | 6.00 | 95.52 | 0.94 | 0.00 | 0.00 | 69.91 | 6.56 | 96.65 | 4.47 | 80.00 | 0.36 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2554752720 |
| 67.77 | 1.15 | 66.04 | 0.00 | 59.34 | 1.07 | 95.99 | 0.47 | 0.00 | 0.00 | 69.99 | 0.08 | 97.49 | 0.84 | 85.59 | 5.59 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1459620385 |
| 68.62 | 0.85 | 66.04 | 0.00 | 59.34 | 0.00 | 95.99 | 0.00 | 0.00 | 0.00 | 69.99 | 0.00 | 97.49 | 0.00 | 91.53 | 5.95 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.585804954 |
| 69.11 | 0.48 | 66.34 | 0.30 | 61.17 | 1.84 | 96.70 | 0.71 | 0.00 | 0.00 | 70.24 | 0.24 | 97.77 | 0.28 | 91.53 | 0.00 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1557628805 |
| 69.31 | 0.21 | 66.34 | 0.00 | 61.17 | 0.00 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 97.77 | 0.00 | 92.97 | 1.44 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.334606531 |
| 69.44 | 0.13 | 66.34 | 0.00 | 61.17 | 0.00 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 97.77 | 0.00 | 93.87 | 0.90 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3002268869 |
| 69.55 | 0.11 | 66.34 | 0.00 | 61.20 | 0.02 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 97.77 | 0.00 | 94.59 | 0.72 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3649719528 |
| 69.63 | 0.08 | 66.34 | 0.00 | 61.29 | 0.09 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.28 | 94.77 | 0.18 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1715265263 |
| 69.70 | 0.08 | 66.34 | 0.00 | 61.29 | 0.00 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 95.32 | 0.54 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.598153526 |
| 69.76 | 0.05 | 66.34 | 0.00 | 61.31 | 0.02 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 95.68 | 0.36 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2078609631 |
| 69.81 | 0.05 | 66.34 | 0.00 | 61.31 | 0.00 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 96.04 | 0.36 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4211749908 |
| 69.85 | 0.04 | 66.51 | 0.17 | 61.43 | 0.12 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 96.04 | 0.00 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2724629121 |
| 69.88 | 0.03 | 66.51 | 0.00 | 61.43 | 0.00 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 96.22 | 0.18 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1809704237 |
| 69.88 | 0.01 | 66.51 | 0.00 | 61.47 | 0.05 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.911697028 |
| 69.89 | 0.01 | 66.51 | 0.00 | 61.50 | 0.02 | 96.70 | 0.00 | 0.00 | 0.00 | 70.24 | 0.00 | 98.04 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3701645264 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3371890541 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1340102666 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1751175209 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.482977987 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.340230849 |
| /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2714815494 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1632928797 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1978737049 |
| /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.624840415 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2260175788 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.447119991 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.888972008 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2675374895 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3255689078 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4198665276 |
| /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2864218111 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3266914340 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.164006759 |
| /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2834341071 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2210444757 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4231948859 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.517956147 |
| /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2874830550 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2476411787 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3039970876 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3511004899 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.203954188 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3287413030 |
| /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3932547079 |
| /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.268473967 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2716231257 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2452861636 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.684852622 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.968064797 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3287220499 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.463078400 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.949306060 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1673950657 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3805076026 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1098547268 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4128300481 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1106842492 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.625371242 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3401086350 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3206396940 |
| /workspace/coverage/cover_reg_top/14.usbdev_intr_test.43661225 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.763714922 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3133816038 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2715832835 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3458307520 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3142100293 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.35665012 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3202207572 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3787148930 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1307727198 |
| /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3287222170 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3232593631 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3886334723 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2719418669 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.189923040 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3969168435 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2253770550 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2082450327 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1919033373 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2054710263 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1582700636 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3200875798 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1286869180 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1602393709 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2772250218 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3824395493 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1181554631 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2988333880 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1657111455 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1512954369 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.452948077 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2465267456 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2845339876 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2377464128 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2150819029 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2207310721 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3436623077 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.424342564 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2891324777 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4248065597 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2083376557 |
| /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2502519134 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2077153115 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3638684760 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2604571835 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2733637163 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.521569084 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.473234107 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4261934038 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.255670723 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2702205852 |
| /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2739099014 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3665209355 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1748499576 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.695194265 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.156214595 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1028426827 |
| /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3152913736 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1592826292 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1689078127 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4242604514 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.875531681 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1065698572 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3363135511 |
| /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3160775092 |
| /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2253974906 |
| /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1339889856 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2622353621 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4149395303 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1286433937 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.926747652 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3853262818 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2492007433 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1649022235 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.117296841 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1816336322 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3203891987 |
| /workspace/coverage/cover_reg_top/42.usbdev_intr_test.9290326 |
| /workspace/coverage/cover_reg_top/43.usbdev_intr_test.279497946 |
| /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1793480321 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.589737166 |
| /workspace/coverage/cover_reg_top/46.usbdev_intr_test.729643491 |
| /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1401334240 |
| /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3272687905 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1155453860 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2229704126 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1381431192 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2001597970 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3135649814 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.594547529 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1310516552 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2296223274 |
| /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1482812520 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1894022746 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.159553502 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.775279854 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3761666448 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1858720136 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2326331657 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1335916191 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3358277220 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1016076519 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4238276607 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1532374790 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1632017843 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1113103086 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1296896054 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1874941084 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2407704924 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.252556153 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1049429860 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1551427630 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2368125975 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1401334240 | Jun 04 01:09:02 PM PDT 24 | Jun 04 01:09:03 PM PDT 24 | 48143905 ps | ||
| T2 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3308442521 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:28 PM PDT 24 | 649916120 ps | ||
| T3 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1049429860 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 42199456 ps | ||
| T4 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2554752720 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 114931639 ps | ||
| T12 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.585804954 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:15 PM PDT 24 | 34179508 ps | ||
| T16 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2492007433 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 207778182 ps | ||
| T6 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1649022235 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:30 PM PDT 24 | 486361297 ps | ||
| T8 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3135649814 | Jun 04 01:08:30 PM PDT 24 | Jun 04 01:08:33 PM PDT 24 | 151748182 ps | ||
| T5 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3649719528 | Jun 04 01:08:40 PM PDT 24 | Jun 04 01:08:46 PM PDT 24 | 1728696073 ps | ||
| T17 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.926747652 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:24 PM PDT 24 | 58616262 ps | ||
| T7 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.255670723 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 87599465 ps | ||
| T13 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.969890439 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 69743541 ps | ||
| T18 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1459620385 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:19 PM PDT 24 | 110811769 ps | ||
| T19 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4238276607 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 177915707 ps | ||
| T25 | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1816336322 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 32414872 ps | ||
| T29 | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3206396940 | Jun 04 01:08:49 PM PDT 24 | Jun 04 01:08:51 PM PDT 24 | 79210535 ps | ||
| T28 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2210444757 | Jun 04 01:08:17 PM PDT 24 | Jun 04 01:08:21 PM PDT 24 | 449740701 ps | ||
| T26 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.424342564 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:20 PM PDT 24 | 453906782 ps | ||
| T30 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.473234107 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:29 PM PDT 24 | 301494933 ps | ||
| T40 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1715265263 | Jun 04 01:08:45 PM PDT 24 | Jun 04 01:08:47 PM PDT 24 | 109777132 ps | ||
| T31 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1512954369 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 124914033 ps | ||
| T32 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.695194265 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 106065713 ps | ||
| T20 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1919033373 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:09:02 PM PDT 24 | 110330822 ps | ||
| T21 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2465267456 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 100170886 ps | ||
| T14 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4211749908 | Jun 04 01:08:46 PM PDT 24 | Jun 04 01:08:47 PM PDT 24 | 40178956 ps | ||
| T15 | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3853262818 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 42244052 ps | ||
| T63 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3160775092 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:08:59 PM PDT 24 | 76586275 ps | ||
| T9 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2675374895 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:17 PM PDT 24 | 148780719 ps | ||
| T22 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2724629121 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 247810191 ps | ||
| T23 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.156214595 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 208992827 ps | ||
| T64 | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1793480321 | Jun 04 01:09:01 PM PDT 24 | Jun 04 01:09:02 PM PDT 24 | 29851565 ps | ||
| T62 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.598153526 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:49 PM PDT 24 | 54426782 ps | ||
| T78 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2622353621 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 96327598 ps | ||
| T10 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1557628805 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 94691683 ps | ||
| T44 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.447119991 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:19 PM PDT 24 | 193568713 ps | ||
| T41 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2296223274 | Jun 04 01:08:33 PM PDT 24 | Jun 04 01:08:35 PM PDT 24 | 51150533 ps | ||
| T33 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3371890541 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:20 PM PDT 24 | 158873377 ps | ||
| T24 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1748499576 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:28 PM PDT 24 | 102976098 ps | ||
| T27 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.159553502 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:36 PM PDT 24 | 312988253 ps | ||
| T45 | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2001597970 | Jun 04 01:08:32 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 103552530 ps | ||
| T46 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.9290326 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 51798613 ps | ||
| T47 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3287222170 | Jun 04 01:08:49 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 80156870 ps | ||
| T48 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2150819029 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:30 PM PDT 24 | 196957431 ps | ||
| T79 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2260175788 | Jun 04 01:08:17 PM PDT 24 | Jun 04 01:08:20 PM PDT 24 | 284622880 ps | ||
| T65 | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2733637163 | Jun 04 01:09:01 PM PDT 24 | Jun 04 01:09:03 PM PDT 24 | 89839332 ps | ||
| T34 | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1307727198 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 52182457 ps | ||
| T70 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2253974906 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:08:59 PM PDT 24 | 39692572 ps | ||
| T68 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.334606531 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:08:59 PM PDT 24 | 39571126 ps | ||
| T72 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2077153115 | Jun 04 01:08:58 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 56854592 ps | ||
| T80 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.189923040 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 92853121 ps | ||
| T35 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2845339876 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 79436412 ps | ||
| T55 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2368125975 | Jun 04 01:08:32 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 147906045 ps | ||
| T59 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3202207572 | Jun 04 01:08:49 PM PDT 24 | Jun 04 01:08:55 PM PDT 24 | 858889848 ps | ||
| T75 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.949306060 | Jun 04 01:08:39 PM PDT 24 | Jun 04 01:08:45 PM PDT 24 | 762005126 ps | ||
| T53 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.35665012 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:52 PM PDT 24 | 306704472 ps | ||
| T81 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.594547529 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 78253911 ps | ||
| T82 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2719418669 | Jun 04 01:08:46 PM PDT 24 | Jun 04 01:08:49 PM PDT 24 | 616854913 ps | ||
| T57 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2715832835 | Jun 04 01:08:46 PM PDT 24 | Jun 04 01:08:48 PM PDT 24 | 177593011 ps | ||
| T42 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.624840415 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:18 PM PDT 24 | 102305995 ps | ||
| T83 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.164006759 | Jun 04 01:08:17 PM PDT 24 | Jun 04 01:08:21 PM PDT 24 | 363750572 ps | ||
| T60 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1673950657 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 177174482 ps | ||
| T69 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1339889856 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:08:59 PM PDT 24 | 34340990 ps | ||
| T84 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3401086350 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 110255611 ps | ||
| T43 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1551427630 | Jun 04 01:08:39 PM PDT 24 | Jun 04 01:08:41 PM PDT 24 | 161250340 ps | ||
| T61 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1286433937 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 238687732 ps | ||
| T77 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1028426827 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:30 PM PDT 24 | 583558651 ps | ||
| T74 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1809704237 | Jun 04 01:08:26 PM PDT 24 | Jun 04 01:08:32 PM PDT 24 | 893865475 ps | ||
| T11 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4261934038 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 246317523 ps | ||
| T85 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3761666448 | Jun 04 01:08:33 PM PDT 24 | Jun 04 01:08:35 PM PDT 24 | 62262681 ps | ||
| T66 | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3363135511 | Jun 04 01:08:53 PM PDT 24 | Jun 04 01:08:54 PM PDT 24 | 39473002 ps | ||
| T86 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2739099014 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 35073788 ps | ||
| T87 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2207310721 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 316614515 ps | ||
| T73 | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1592826292 | Jun 04 01:08:53 PM PDT 24 | Jun 04 01:08:55 PM PDT 24 | 72663153 ps | ||
| T88 | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2326331657 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:33 PM PDT 24 | 43038531 ps | ||
| T67 | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.589737166 | Jun 04 01:09:04 PM PDT 24 | Jun 04 01:09:06 PM PDT 24 | 41017162 ps | ||
| T54 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2988333880 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 152990641 ps | ||
| T76 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1016076519 | Jun 04 01:08:29 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 810182738 ps | ||
| T50 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1113103086 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 110461858 ps | ||
| T89 | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2604571835 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 47534940 ps | ||
| T36 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2054710263 | Jun 04 01:08:58 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 50759286 ps | ||
| T37 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3458307520 | Jun 04 01:08:46 PM PDT 24 | Jun 04 01:08:48 PM PDT 24 | 81379403 ps | ||
| T90 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.117296841 | Jun 04 01:08:25 PM PDT 24 | Jun 04 01:08:28 PM PDT 24 | 208449963 ps | ||
| T51 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2078609631 | Jun 04 01:08:37 PM PDT 24 | Jun 04 01:08:43 PM PDT 24 | 848702933 ps | ||
| T91 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3002268869 | Jun 04 01:08:58 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 49492033 ps | ||
| T38 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1532374790 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:33 PM PDT 24 | 145112310 ps | ||
| T92 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1155453860 | Jun 04 01:09:03 PM PDT 24 | Jun 04 01:09:05 PM PDT 24 | 53839559 ps | ||
| T93 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2874830550 | Jun 04 01:08:42 PM PDT 24 | Jun 04 01:08:44 PM PDT 24 | 67927342 ps | ||
| T56 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.911697028 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:19 PM PDT 24 | 239435232 ps | ||
| T94 | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.968064797 | Jun 04 01:08:37 PM PDT 24 | Jun 04 01:08:39 PM PDT 24 | 56143144 ps | ||
| T39 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3266914340 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:17 PM PDT 24 | 91565459 ps | ||
| T95 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3142100293 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:49 PM PDT 24 | 92739586 ps | ||
| T96 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2772250218 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 109208201 ps | ||
| T97 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1181554631 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:09:01 PM PDT 24 | 155888060 ps | ||
| T98 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4128300481 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 325824804 ps | ||
| T71 | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3203891987 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 43543408 ps | ||
| T99 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1310516552 | Jun 04 01:08:32 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 106444235 ps | ||
| T100 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.729643491 | Jun 04 01:09:03 PM PDT 24 | Jun 04 01:09:04 PM PDT 24 | 57681979 ps | ||
| T101 | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1065698572 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 102731831 ps | ||
| T102 | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.875531681 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:08:59 PM PDT 24 | 38249315 ps | ||
| T58 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3701645264 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:53 PM PDT 24 | 978190167 ps | ||
| T103 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1632928797 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:16 PM PDT 24 | 62082785 ps | ||
| T104 | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2714815494 | Jun 04 01:08:17 PM PDT 24 | Jun 04 01:08:19 PM PDT 24 | 51399346 ps | ||
| T105 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.340230849 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:17 PM PDT 24 | 146201933 ps | ||
| T106 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1286869180 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:09:05 PM PDT 24 | 920086617 ps | ||
| T107 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.463078400 | Jun 04 01:08:42 PM PDT 24 | Jun 04 01:08:45 PM PDT 24 | 141012231 ps | ||
| T108 | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1689078127 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 52234828 ps | ||
| T109 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.763714922 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:51 PM PDT 24 | 232464960 ps | ||
| T110 | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4242604514 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:08:59 PM PDT 24 | 38990244 ps | ||
| T111 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3932547079 | Jun 04 01:08:39 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 44311673 ps | ||
| T112 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.684852622 | Jun 04 01:08:39 PM PDT 24 | Jun 04 01:08:41 PM PDT 24 | 157318058 ps | ||
| T113 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4198665276 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:17 PM PDT 24 | 84342288 ps | ||
| T114 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3152913736 | Jun 04 01:08:52 PM PDT 24 | Jun 04 01:08:53 PM PDT 24 | 40038475 ps | ||
| T115 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3255689078 | Jun 04 01:08:13 PM PDT 24 | Jun 04 01:08:15 PM PDT 24 | 102533251 ps | ||
| T116 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2702205852 | Jun 04 01:08:24 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 54998877 ps | ||
| T117 | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1632017843 | Jun 04 01:08:30 PM PDT 24 | Jun 04 01:08:32 PM PDT 24 | 73108925 ps | ||
| T118 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4231948859 | Jun 04 01:08:37 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 190745833 ps | ||
| T119 | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2891324777 | Jun 04 01:08:53 PM PDT 24 | Jun 04 01:08:55 PM PDT 24 | 29013874 ps | ||
| T120 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.203954188 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:41 PM PDT 24 | 181759605 ps | ||
| T121 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3805076026 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 73304426 ps | ||
| T122 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1296896054 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 115157394 ps | ||
| T123 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1335916191 | Jun 04 01:08:33 PM PDT 24 | Jun 04 01:08:36 PM PDT 24 | 143372723 ps | ||
| T124 | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4248065597 | Jun 04 01:08:59 PM PDT 24 | Jun 04 01:09:01 PM PDT 24 | 39824677 ps | ||
| T52 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1657111455 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:09:01 PM PDT 24 | 312291263 ps | ||
| T125 | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3824395493 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 101223159 ps | ||
| T126 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3287413030 | Jun 04 01:08:42 PM PDT 24 | Jun 04 01:08:44 PM PDT 24 | 99464043 ps | ||
| T127 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3787148930 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 103394829 ps | ||
| T128 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2082450327 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:51 PM PDT 24 | 212537827 ps | ||
| T129 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3886334723 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 58611672 ps | ||
| T130 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3039970876 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 148216178 ps | ||
| T131 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3200875798 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 176746936 ps | ||
| T132 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2502519134 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 28782583 ps | ||
| T133 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2229704126 | Jun 04 01:08:33 PM PDT 24 | Jun 04 01:08:35 PM PDT 24 | 96544226 ps | ||
| T134 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3969168435 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:50 PM PDT 24 | 88267478 ps | ||
| T49 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1751175209 | Jun 04 01:08:16 PM PDT 24 | Jun 04 01:08:18 PM PDT 24 | 81803908 ps | ||
| T135 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2476411787 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 77322876 ps | ||
| T136 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.517956147 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 64139785 ps | ||
| T137 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.452948077 | Jun 04 01:08:21 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 956248483 ps | ||
| T138 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2834341071 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:16 PM PDT 24 | 156221421 ps | ||
| T139 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.625371242 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:44 PM PDT 24 | 1287465822 ps | ||
| T140 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1602393709 | Jun 04 01:08:58 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 92160662 ps | ||
| T141 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3638684760 | Jun 04 01:08:56 PM PDT 24 | Jun 04 01:08:58 PM PDT 24 | 36999105 ps | ||
| T142 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.775279854 | Jun 04 01:08:29 PM PDT 24 | Jun 04 01:08:34 PM PDT 24 | 1126970589 ps | ||
| T143 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1381431192 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:33 PM PDT 24 | 77591793 ps | ||
| T144 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2377464128 | Jun 04 01:08:23 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 56719773 ps | ||
| T145 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1894022746 | Jun 04 01:08:30 PM PDT 24 | Jun 04 01:08:32 PM PDT 24 | 261224791 ps | ||
| T146 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1340102666 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:19 PM PDT 24 | 629465471 ps | ||
| T147 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2407704924 | Jun 04 01:08:37 PM PDT 24 | Jun 04 01:08:39 PM PDT 24 | 110892767 ps | ||
| T148 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.43661225 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:48 PM PDT 24 | 46266539 ps | ||
| T149 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1978737049 | Jun 04 01:08:12 PM PDT 24 | Jun 04 01:08:17 PM PDT 24 | 492042640 ps | ||
| T150 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3232593631 | Jun 04 01:08:49 PM PDT 24 | Jun 04 01:08:51 PM PDT 24 | 75396966 ps | ||
| T151 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.268473967 | Jun 04 01:08:36 PM PDT 24 | Jun 04 01:08:38 PM PDT 24 | 208677362 ps | ||
| T152 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1858720136 | Jun 04 01:08:32 PM PDT 24 | Jun 04 01:08:33 PM PDT 24 | 55555270 ps | ||
| T153 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4149395303 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:27 PM PDT 24 | 331947721 ps | ||
| T154 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.279497946 | Jun 04 01:08:57 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 40222939 ps | ||
| T155 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1106842492 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:42 PM PDT 24 | 209578154 ps | ||
| T156 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3436623077 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:19 PM PDT 24 | 301979045 ps | ||
| T157 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1098547268 | Jun 04 01:08:47 PM PDT 24 | Jun 04 01:08:48 PM PDT 24 | 32557150 ps | ||
| T158 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2253770550 | Jun 04 01:08:55 PM PDT 24 | Jun 04 01:08:57 PM PDT 24 | 155092860 ps | ||
| T159 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.482977987 | Jun 04 01:08:15 PM PDT 24 | Jun 04 01:08:18 PM PDT 24 | 285158974 ps | ||
| T160 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2864218111 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:15 PM PDT 24 | 54299020 ps | ||
| T161 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1582700636 | Jun 04 01:08:58 PM PDT 24 | Jun 04 01:09:01 PM PDT 24 | 136827591 ps | ||
| T162 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2716231257 | Jun 04 01:08:37 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 137662332 ps | ||
| T163 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3511004899 | Jun 04 01:08:37 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 401297710 ps | ||
| T164 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2452861636 | Jun 04 01:08:40 PM PDT 24 | Jun 04 01:08:43 PM PDT 24 | 180707058 ps | ||
| T165 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3665209355 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:25 PM PDT 24 | 223152844 ps | ||
| T166 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3287220499 | Jun 04 01:08:38 PM PDT 24 | Jun 04 01:08:40 PM PDT 24 | 94246753 ps | ||
| T167 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1874941084 | Jun 04 01:08:33 PM PDT 24 | Jun 04 01:08:39 PM PDT 24 | 880176399 ps | ||
| T168 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1482812520 | Jun 04 01:08:31 PM PDT 24 | Jun 04 01:08:33 PM PDT 24 | 52093002 ps | ||
| T169 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3358277220 | Jun 04 01:08:29 PM PDT 24 | Jun 04 01:08:32 PM PDT 24 | 81703022 ps | ||
| T170 | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2083376557 | Jun 04 01:08:58 PM PDT 24 | Jun 04 01:09:00 PM PDT 24 | 36602278 ps | ||
| T171 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.521569084 | Jun 04 01:08:22 PM PDT 24 | Jun 04 01:08:26 PM PDT 24 | 184754479 ps | ||
| T172 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.252556153 | Jun 04 01:08:39 PM PDT 24 | Jun 04 01:08:41 PM PDT 24 | 81555014 ps | ||
| T173 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3133816038 | Jun 04 01:08:48 PM PDT 24 | Jun 04 01:08:51 PM PDT 24 | 634237978 ps | ||
| T174 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.888972008 | Jun 04 01:08:14 PM PDT 24 | Jun 04 01:08:23 PM PDT 24 | 1612128271 ps | ||
| T175 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3272687905 | Jun 04 01:09:02 PM PDT 24 | Jun 04 01:09:03 PM PDT 24 | 43755277 ps |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3308442521 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 649916120 ps |
| CPU time | 4.77 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:28 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-a14e35ec-9a83-45a1-97a6-af04a27ee110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3308442521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3308442521 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.969890439 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 69743541 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-77981fa9-f15a-4cc1-9e64-b59c80d8b792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=969890439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.969890439 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2554752720 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 114931639 ps |
| CPU time | 0.97 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-b6c6011d-afc0-4139-8c78-38e73f093bc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2554752720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2554752720 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1459620385 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 110811769 ps |
| CPU time | 2.81 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:19 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-17bfffbb-fd5c-4591-926e-6f65d9f47a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1459620385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1459620385 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.585804954 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 34179508 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:15 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-a9af09f5-4b77-4e4f-a166-758680624ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=585804954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.585804954 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1557628805 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 94691683 ps |
| CPU time | 0.96 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-803dfd5d-1e93-4dee-9b07-a7cb6670da60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1557628805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1557628805 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.334606531 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 39571126 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:08:59 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-a8536f4d-e195-4c57-ab01-a6edaba57c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=334606531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.334606531 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3002268869 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 49492033 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:58 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-98895495-1c6c-4d9f-a723-1cb7be6e1494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3002268869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3002268869 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3649719528 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 1728696073 ps |
| CPU time | 5.45 seconds |
| Started | Jun 04 01:08:40 PM PDT 24 |
| Finished | Jun 04 01:08:46 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-739dca89-10d3-40fe-be29-99614ddbe540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3649719528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3649719528 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1715265263 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 109777132 ps |
| CPU time | 1.2 seconds |
| Started | Jun 04 01:08:45 PM PDT 24 |
| Finished | Jun 04 01:08:47 PM PDT 24 |
| Peak memory | 204868 kb |
| Host | smart-3758c62e-7dd8-4fee-aca7-11fb1cd2e746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1715265263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1715265263 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.598153526 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 54426782 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:49 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-5972e3e8-3289-4f52-bfd1-bf243a25b125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=598153526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.598153526 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2078609631 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 848702933 ps |
| CPU time | 5.01 seconds |
| Started | Jun 04 01:08:37 PM PDT 24 |
| Finished | Jun 04 01:08:43 PM PDT 24 |
| Peak memory | 204844 kb |
| Host | smart-b062b11f-a47c-451b-a61f-591a68c635c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2078609631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2078609631 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4211749908 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 40178956 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 01:08:46 PM PDT 24 |
| Finished | Jun 04 01:08:47 PM PDT 24 |
| Peak memory | 204516 kb |
| Host | smart-28f3199f-e209-463a-bc48-1b4202a91db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4211749908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.4211749908 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2724629121 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 247810191 ps |
| CPU time | 2.88 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 220592 kb |
| Host | smart-71758125-4647-4043-ad31-d8c0ee526b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2724629121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2724629121 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1809704237 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 893865475 ps |
| CPU time | 4.86 seconds |
| Started | Jun 04 01:08:26 PM PDT 24 |
| Finished | Jun 04 01:08:32 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-989bf433-2fb7-4a3a-bc45-6194252cb8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1809704237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1809704237 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.911697028 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 239435232 ps |
| CPU time | 2.8 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:19 PM PDT 24 |
| Peak memory | 213020 kb |
| Host | smart-7c69921c-ae4f-4685-808d-756f5be7d9c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=911697028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.911697028 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3701645264 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 978190167 ps |
| CPU time | 5.31 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:53 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-8c2766c5-0620-48c3-a5ea-f1951d5af510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3701645264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3701645264 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3371890541 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 158873377 ps |
| CPU time | 3.45 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:20 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-f88c143b-18d0-42eb-a00d-6f93f55531d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3371890541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3371890541 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1340102666 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 629465471 ps |
| CPU time | 4.6 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:19 PM PDT 24 |
| Peak memory | 204732 kb |
| Host | smart-f60ee896-3369-4fe0-a031-a38ae7c42dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1340102666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1340102666 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1751175209 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 81803908 ps |
| CPU time | 0.82 seconds |
| Started | Jun 04 01:08:16 PM PDT 24 |
| Finished | Jun 04 01:08:18 PM PDT 24 |
| Peak memory | 204608 kb |
| Host | smart-a1ab8f8d-69d8-4afa-a0a8-8774e6c4ed0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1751175209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1751175209 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.482977987 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 285158974 ps |
| CPU time | 2.03 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:18 PM PDT 24 |
| Peak memory | 213008 kb |
| Host | smart-5cb7d1e0-78e5-44fa-8537-3699d007efd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482977987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev _csr_mem_rw_with_rand_reset.482977987 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.340230849 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 146201933 ps |
| CPU time | 0.89 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:17 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-9a1819aa-73e9-46a6-a9d0-2e1bd1521c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=340230849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.340230849 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2714815494 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 51399346 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 01:08:17 PM PDT 24 |
| Finished | Jun 04 01:08:19 PM PDT 24 |
| Peak memory | 204456 kb |
| Host | smart-67a330c4-f599-4631-9fcf-a6f44c792a0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2714815494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2714815494 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1632928797 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 62082785 ps |
| CPU time | 1.33 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:16 PM PDT 24 |
| Peak memory | 212936 kb |
| Host | smart-2753593d-df7e-48a2-bba7-76a545291029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1632928797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1632928797 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.1978737049 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 492042640 ps |
| CPU time | 4.33 seconds |
| Started | Jun 04 01:08:12 PM PDT 24 |
| Finished | Jun 04 01:08:17 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-d944d66d-3ff1-4526-a125-84afac37c4b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1978737049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.1978737049 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.624840415 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 102305995 ps |
| CPU time | 1.14 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:18 PM PDT 24 |
| Peak memory | 204976 kb |
| Host | smart-7fb3b7e5-be16-47cc-9212-f1c54a46a9fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=624840415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.624840415 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2260175788 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 284622880 ps |
| CPU time | 2.41 seconds |
| Started | Jun 04 01:08:17 PM PDT 24 |
| Finished | Jun 04 01:08:20 PM PDT 24 |
| Peak memory | 204840 kb |
| Host | smart-ebd274aa-a58a-43b5-bd06-a352078d9fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2260175788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2260175788 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.447119991 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 193568713 ps |
| CPU time | 2.09 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:19 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-6ddc4283-32ec-476a-b722-49c0294afacc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=447119991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.447119991 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.888972008 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1612128271 ps |
| CPU time | 8.99 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:23 PM PDT 24 |
| Peak memory | 204680 kb |
| Host | smart-3105f41b-f981-46e7-9ff9-5c033e1e3ab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=888972008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.888972008 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2675374895 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 148780719 ps |
| CPU time | 0.95 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:17 PM PDT 24 |
| Peak memory | 204604 kb |
| Host | smart-ea573847-c179-4f82-a944-685c3a3203cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2675374895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2675374895 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3255689078 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 102533251 ps |
| CPU time | 1.32 seconds |
| Started | Jun 04 01:08:13 PM PDT 24 |
| Finished | Jun 04 01:08:15 PM PDT 24 |
| Peak memory | 214316 kb |
| Host | smart-4b1de931-a0fc-49c2-b78d-3ca814544025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255689078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.3255689078 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4198665276 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 84342288 ps |
| CPU time | 1.01 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:17 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-e95a94df-e3af-4687-947d-cc0090aa20c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4198665276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4198665276 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2864218111 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 54299020 ps |
| CPU time | 0.73 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:15 PM PDT 24 |
| Peak memory | 204472 kb |
| Host | smart-0e078ce3-8394-4dfe-afe6-5f57d7f3c2f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2864218111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2864218111 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3266914340 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 91565459 ps |
| CPU time | 1.43 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:17 PM PDT 24 |
| Peak memory | 213020 kb |
| Host | smart-1ab93381-2831-4973-b7bc-bd086a1d97a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3266914340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3266914340 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.164006759 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 363750572 ps |
| CPU time | 2.68 seconds |
| Started | Jun 04 01:08:17 PM PDT 24 |
| Finished | Jun 04 01:08:21 PM PDT 24 |
| Peak memory | 204660 kb |
| Host | smart-9f87f452-2359-4743-b039-be88bdcec95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=164006759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.164006759 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2834341071 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 156221421 ps |
| CPU time | 1.14 seconds |
| Started | Jun 04 01:08:14 PM PDT 24 |
| Finished | Jun 04 01:08:16 PM PDT 24 |
| Peak memory | 204788 kb |
| Host | smart-1d735245-478f-4cf3-a7e7-cb7923c84603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2834341071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2834341071 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2210444757 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 449740701 ps |
| CPU time | 2.84 seconds |
| Started | Jun 04 01:08:17 PM PDT 24 |
| Finished | Jun 04 01:08:21 PM PDT 24 |
| Peak memory | 204900 kb |
| Host | smart-e4af67de-9dbb-480a-8db4-4cc42e7b1551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2210444757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2210444757 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4231948859 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 190745833 ps |
| CPU time | 1.96 seconds |
| Started | Jun 04 01:08:37 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 213064 kb |
| Host | smart-c1c43488-750f-4524-9e85-6599a9d564ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231948859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd ev_csr_mem_rw_with_rand_reset.4231948859 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.517956147 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 64139785 ps |
| CPU time | 0.96 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204852 kb |
| Host | smart-c60f1d3e-3e95-48be-9534-905a9ad9e247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=517956147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.517956147 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2874830550 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 67927342 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 01:08:42 PM PDT 24 |
| Finished | Jun 04 01:08:44 PM PDT 24 |
| Peak memory | 204496 kb |
| Host | smart-0271c01d-2e73-4371-92c1-09d5d354fadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2874830550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2874830550 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2476411787 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 77322876 ps |
| CPU time | 1.13 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204712 kb |
| Host | smart-600f484e-d7db-425e-a8c3-acfeaf95ad38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2476411787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2476411787 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3039970876 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 148216178 ps |
| CPU time | 2.03 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204912 kb |
| Host | smart-88a0e71f-d854-4293-8fa9-162e2b250581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3039970876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3039970876 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3511004899 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 401297710 ps |
| CPU time | 2.68 seconds |
| Started | Jun 04 01:08:37 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-32dc1bb0-a216-4cd3-8db2-55aad8704b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3511004899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3511004899 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.203954188 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 181759605 ps |
| CPU time | 1.74 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:41 PM PDT 24 |
| Peak memory | 213020 kb |
| Host | smart-a17e6530-b9d1-48da-8341-e932a90361d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203954188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde v_csr_mem_rw_with_rand_reset.203954188 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3287413030 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 99464043 ps |
| CPU time | 0.9 seconds |
| Started | Jun 04 01:08:42 PM PDT 24 |
| Finished | Jun 04 01:08:44 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-df3f8eb0-718d-4d69-bf58-ff107a01d1bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3287413030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3287413030 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3932547079 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 44311673 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 01:08:39 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-59908dad-2751-47a8-9ff9-5161a6e1567d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3932547079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3932547079 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.268473967 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 208677362 ps |
| CPU time | 1.62 seconds |
| Started | Jun 04 01:08:36 PM PDT 24 |
| Finished | Jun 04 01:08:38 PM PDT 24 |
| Peak memory | 204736 kb |
| Host | smart-9951cee4-ecdd-43cc-add7-6da4eafb62fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=268473967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.268473967 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2716231257 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 137662332 ps |
| CPU time | 2.14 seconds |
| Started | Jun 04 01:08:37 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 220408 kb |
| Host | smart-1a5cbc78-7cc0-4417-8263-b6bf9abe80bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2716231257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2716231257 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2452861636 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 180707058 ps |
| CPU time | 1.85 seconds |
| Started | Jun 04 01:08:40 PM PDT 24 |
| Finished | Jun 04 01:08:43 PM PDT 24 |
| Peak memory | 212888 kb |
| Host | smart-7c0a3104-ad59-445b-a9db-a9f2b2d45ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452861636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd ev_csr_mem_rw_with_rand_reset.2452861636 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.684852622 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 157318058 ps |
| CPU time | 1.2 seconds |
| Started | Jun 04 01:08:39 PM PDT 24 |
| Finished | Jun 04 01:08:41 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-fac79620-7f6f-4a01-b156-01d1e6190d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=684852622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.684852622 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.968064797 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 56143144 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:37 PM PDT 24 |
| Finished | Jun 04 01:08:39 PM PDT 24 |
| Peak memory | 204556 kb |
| Host | smart-ef4c1e6d-1c67-4aa3-a399-2c05b5c3ff71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=968064797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.968064797 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3287220499 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 94246753 ps |
| CPU time | 1.19 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204768 kb |
| Host | smart-83b78034-24c0-4f21-bfcb-1de3ae214df3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3287220499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3287220499 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.463078400 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 141012231 ps |
| CPU time | 1.78 seconds |
| Started | Jun 04 01:08:42 PM PDT 24 |
| Finished | Jun 04 01:08:45 PM PDT 24 |
| Peak memory | 204820 kb |
| Host | smart-471930dd-6918-4d5b-bb44-34ddd3a0f8b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=463078400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.463078400 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.949306060 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 762005126 ps |
| CPU time | 5.12 seconds |
| Started | Jun 04 01:08:39 PM PDT 24 |
| Finished | Jun 04 01:08:45 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-92a531f0-4db0-404f-8345-0831cc2ef697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=949306060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.949306060 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1673950657 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 177174482 ps |
| CPU time | 1.79 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 213072 kb |
| Host | smart-8792df97-1c35-4714-aaa6-5f450eb89247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673950657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.1673950657 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3805076026 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 73304426 ps |
| CPU time | 1.07 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-13cf9845-849f-434c-a749-5f71d6d4f974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3805076026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3805076026 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1098547268 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 32557150 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:48 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-74be9170-bfc2-4828-83ae-7e8f889064a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1098547268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1098547268 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4128300481 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 325824804 ps |
| CPU time | 1.4 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-8e1ab62f-6bf1-4260-9bde-81b4d9ae2ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4128300481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.4128300481 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1106842492 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 209578154 ps |
| CPU time | 2.86 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:42 PM PDT 24 |
| Peak memory | 204844 kb |
| Host | smart-ad80f106-b4ff-4600-be58-ec9d9d38f99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1106842492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1106842492 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.625371242 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 1287465822 ps |
| CPU time | 5.44 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:44 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-25c48197-4831-45c2-9052-fff764e28dc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=625371242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.625371242 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3401086350 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 110255611 ps |
| CPU time | 2.41 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 212996 kb |
| Host | smart-cf761289-8dbc-42c5-9c23-538daf20f607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401086350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.3401086350 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3206396940 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 79210535 ps |
| CPU time | 1.15 seconds |
| Started | Jun 04 01:08:49 PM PDT 24 |
| Finished | Jun 04 01:08:51 PM PDT 24 |
| Peak memory | 204844 kb |
| Host | smart-98279e9b-d320-4085-a6a9-796662b7e824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3206396940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3206396940 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.43661225 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 46266539 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:48 PM PDT 24 |
| Peak memory | 204580 kb |
| Host | smart-abdf941a-b9f9-4e9c-9317-3a27d1cc6bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=43661225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.43661225 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.763714922 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 232464960 ps |
| CPU time | 2.26 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:51 PM PDT 24 |
| Peak memory | 213024 kb |
| Host | smart-ba151e29-d221-4cd0-ba2d-bdb1ec540c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=763714922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.763714922 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3133816038 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 634237978 ps |
| CPU time | 2.79 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:51 PM PDT 24 |
| Peak memory | 204780 kb |
| Host | smart-da4e7f56-2057-40fd-aa4c-c2334e0a733b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3133816038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3133816038 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2715832835 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 177593011 ps |
| CPU time | 1.96 seconds |
| Started | Jun 04 01:08:46 PM PDT 24 |
| Finished | Jun 04 01:08:48 PM PDT 24 |
| Peak memory | 221172 kb |
| Host | smart-2491564e-e88d-4806-8acb-24451a8ce578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715832835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.2715832835 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3458307520 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 81379403 ps |
| CPU time | 1.04 seconds |
| Started | Jun 04 01:08:46 PM PDT 24 |
| Finished | Jun 04 01:08:48 PM PDT 24 |
| Peak memory | 204680 kb |
| Host | smart-764d911b-3bd8-40e1-9b70-41c4c65ff30c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3458307520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3458307520 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3142100293 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 92739586 ps |
| CPU time | 1.08 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:49 PM PDT 24 |
| Peak memory | 204724 kb |
| Host | smart-3a15414e-a94b-4073-9234-132de2b0c8e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3142100293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3142100293 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.35665012 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 306704472 ps |
| CPU time | 3.36 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:52 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-a9b992c0-825e-4ff7-9e18-fc41cfcbf696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=35665012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.35665012 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3202207572 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 858889848 ps |
| CPU time | 5.21 seconds |
| Started | Jun 04 01:08:49 PM PDT 24 |
| Finished | Jun 04 01:08:55 PM PDT 24 |
| Peak memory | 204796 kb |
| Host | smart-443b3403-1fdd-4496-8942-6ad86695c14a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3202207572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3202207572 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3787148930 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 103394829 ps |
| CPU time | 1.37 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 212976 kb |
| Host | smart-c317f7dd-f111-43b5-b4b8-29b4f234506c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787148930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.3787148930 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1307727198 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 52182457 ps |
| CPU time | 0.91 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-b6de5587-d2bf-40a8-bf7f-588f61d3ddc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1307727198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1307727198 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3287222170 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 80156870 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 01:08:49 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-c8961440-0ef8-49d7-9340-c7de749b6fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3287222170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3287222170 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3232593631 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 75396966 ps |
| CPU time | 1.09 seconds |
| Started | Jun 04 01:08:49 PM PDT 24 |
| Finished | Jun 04 01:08:51 PM PDT 24 |
| Peak memory | 204684 kb |
| Host | smart-cbf16295-870b-4b02-945a-11debecdff0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3232593631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3232593631 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3886334723 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 58611672 ps |
| CPU time | 1.58 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 213048 kb |
| Host | smart-94454c30-6911-46f3-b327-ee2ee2d2c181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3886334723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3886334723 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2719418669 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 616854913 ps |
| CPU time | 3.03 seconds |
| Started | Jun 04 01:08:46 PM PDT 24 |
| Finished | Jun 04 01:08:49 PM PDT 24 |
| Peak memory | 204876 kb |
| Host | smart-a508f558-7094-40ca-9964-ad9a60b7c316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2719418669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2719418669 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.189923040 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 92853121 ps |
| CPU time | 1.2 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 214468 kb |
| Host | smart-4ee212d7-8862-4870-bb73-4ee7fc0825cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189923040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde v_csr_mem_rw_with_rand_reset.189923040 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3969168435 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 88267478 ps |
| CPU time | 1.02 seconds |
| Started | Jun 04 01:08:48 PM PDT 24 |
| Finished | Jun 04 01:08:50 PM PDT 24 |
| Peak memory | 204816 kb |
| Host | smart-b9c603bf-0938-43f7-9923-a1783c3cb147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3969168435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3969168435 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2253770550 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 155092860 ps |
| CPU time | 1.19 seconds |
| Started | Jun 04 01:08:55 PM PDT 24 |
| Finished | Jun 04 01:08:57 PM PDT 24 |
| Peak memory | 204788 kb |
| Host | smart-a9a913c8-9531-4502-889a-6198a81b6dfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2253770550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2253770550 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2082450327 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 212537827 ps |
| CPU time | 3 seconds |
| Started | Jun 04 01:08:47 PM PDT 24 |
| Finished | Jun 04 01:08:51 PM PDT 24 |
| Peak memory | 220676 kb |
| Host | smart-c4cbb802-ede6-42f2-a61f-83723a936a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2082450327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2082450327 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1919033373 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 110330822 ps |
| CPU time | 2.46 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:09:02 PM PDT 24 |
| Peak memory | 213052 kb |
| Host | smart-ee9161ee-984e-4540-9f2f-df1779348273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919033373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1919033373 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2054710263 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 50759286 ps |
| CPU time | 0.98 seconds |
| Started | Jun 04 01:08:58 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204828 kb |
| Host | smart-39872f18-51b0-4d4f-b1ee-3835c55acc37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2054710263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2054710263 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1582700636 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 136827591 ps |
| CPU time | 1.67 seconds |
| Started | Jun 04 01:08:58 PM PDT 24 |
| Finished | Jun 04 01:09:01 PM PDT 24 |
| Peak memory | 204804 kb |
| Host | smart-e42211ee-eb60-42aa-b4c4-6ed4758d9d81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1582700636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1582700636 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3200875798 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 176746936 ps |
| CPU time | 1.71 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-2344f4d9-7839-4120-b5dd-e792b880e120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3200875798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3200875798 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1286869180 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 920086617 ps |
| CPU time | 5.87 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:09:05 PM PDT 24 |
| Peak memory | 204712 kb |
| Host | smart-ec3a84e9-5900-4e28-bb61-21e55750e67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1286869180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1286869180 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1602393709 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 92160662 ps |
| CPU time | 1.18 seconds |
| Started | Jun 04 01:08:58 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 213024 kb |
| Host | smart-fa715394-44cf-463d-be70-58d008b6a340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602393709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.1602393709 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2772250218 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 109208201 ps |
| CPU time | 0.92 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204628 kb |
| Host | smart-0316f995-dee9-499d-bf2d-f8b244bd5dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2772250218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2772250218 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3824395493 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 101223159 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-45f11487-de8e-4c70-a461-8bcef54dd866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3824395493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3824395493 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1181554631 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 155888060 ps |
| CPU time | 1.67 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:09:01 PM PDT 24 |
| Peak memory | 204856 kb |
| Host | smart-70e8baee-d1ff-42f2-bf65-6d4208004996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1181554631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1181554631 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2988333880 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 152990641 ps |
| CPU time | 2.09 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 212952 kb |
| Host | smart-8bb08db5-998f-401f-979c-c3690efb668c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2988333880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2988333880 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1657111455 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 312291263 ps |
| CPU time | 2.73 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:09:01 PM PDT 24 |
| Peak memory | 204856 kb |
| Host | smart-06951b73-4904-4e89-bfa1-b6592cd4d292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1657111455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1657111455 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1512954369 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 124914033 ps |
| CPU time | 3.22 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 204768 kb |
| Host | smart-805c4049-de3f-4551-942b-ab9769f58eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1512954369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1512954369 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.452948077 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 956248483 ps |
| CPU time | 5.38 seconds |
| Started | Jun 04 01:08:21 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 204772 kb |
| Host | smart-df267755-5005-43c1-aa92-d1db067e871c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=452948077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.452948077 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2465267456 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 100170886 ps |
| CPU time | 1.36 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 213096 kb |
| Host | smart-9f90896b-3664-4b98-bc8a-ff73a8f414dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465267456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.2465267456 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2845339876 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 79436412 ps |
| CPU time | 0.99 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 204856 kb |
| Host | smart-293b069e-13f4-404a-afa8-e02a9ce97a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2845339876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2845339876 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2377464128 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 56719773 ps |
| CPU time | 1.33 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 212980 kb |
| Host | smart-1ef4ad91-e7dc-4d5d-adb8-99979fb3c8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2377464128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2377464128 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2150819029 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 196957431 ps |
| CPU time | 4.06 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:30 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-494780b8-b7b2-4a42-ba1b-fbe443f77b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2150819029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2150819029 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2207310721 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 316614515 ps |
| CPU time | 1.82 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 204740 kb |
| Host | smart-abe77b4d-53cf-43e3-a50b-cca48f971af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2207310721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2207310721 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3436623077 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 301979045 ps |
| CPU time | 3.07 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:19 PM PDT 24 |
| Peak memory | 204896 kb |
| Host | smart-7bd9c4e2-46c4-40d1-aa32-2ac72366e586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3436623077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3436623077 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.424342564 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 453906782 ps |
| CPU time | 4.27 seconds |
| Started | Jun 04 01:08:15 PM PDT 24 |
| Finished | Jun 04 01:08:20 PM PDT 24 |
| Peak memory | 204732 kb |
| Host | smart-a5806abe-a354-49ce-8b21-cc365540e3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=424342564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.424342564 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2891324777 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 29013874 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 01:08:53 PM PDT 24 |
| Finished | Jun 04 01:08:55 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-b230a1a2-b120-4bdc-b2b5-a2eec515b8f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2891324777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2891324777 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4248065597 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 39824677 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 01:08:59 PM PDT 24 |
| Finished | Jun 04 01:09:01 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-a217f6b8-e9fc-4874-89be-22a5a2a8031e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4248065597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4248065597 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2083376557 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 36602278 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 01:08:58 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-3a460c4f-a0ff-429c-83fd-3c5829ae89a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2083376557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2083376557 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2502519134 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 28782583 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204484 kb |
| Host | smart-33549692-d5c0-4ec6-a8f1-e6c5f1206755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2502519134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2502519134 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2077153115 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 56854592 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:58 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-6d715eac-1840-45bd-8518-b79c0d981bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2077153115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2077153115 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3638684760 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 36999105 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-d1f7ff32-2d40-484a-8e87-710000a4628d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3638684760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3638684760 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2604571835 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 47534940 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-12f8eb09-c00e-4f1a-8c67-45adf81aa26b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2604571835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2604571835 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2733637163 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 89839332 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 01:09:01 PM PDT 24 |
| Finished | Jun 04 01:09:03 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-81aef689-cad3-4ada-94a4-07660e3ab2fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2733637163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2733637163 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.521569084 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 184754479 ps |
| CPU time | 3.37 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 204788 kb |
| Host | smart-b6b40def-ca01-4a3d-85f2-9f9d8245ad1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=521569084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.521569084 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.473234107 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 301494933 ps |
| CPU time | 3.97 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:29 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-f0b0bf46-6133-4a75-8b7d-bf4aa1269740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=473234107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.473234107 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.4261934038 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 246317523 ps |
| CPU time | 1.16 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 204512 kb |
| Host | smart-377b8e52-3c69-4349-ad65-bdf7f5e896cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4261934038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.4261934038 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.255670723 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 87599465 ps |
| CPU time | 1.3 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 221212 kb |
| Host | smart-780a0239-a155-48dc-b668-4e7e2e1537f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255670723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev _csr_mem_rw_with_rand_reset.255670723 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2702205852 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 54998877 ps |
| CPU time | 0.96 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 204624 kb |
| Host | smart-55772135-0334-473e-9a8e-1b4487a41df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2702205852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2702205852 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2739099014 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 35073788 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 204508 kb |
| Host | smart-32b70f41-6a65-4140-8309-8661563746d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2739099014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2739099014 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3665209355 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 223152844 ps |
| CPU time | 2.4 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 212988 kb |
| Host | smart-47746c91-83f1-4e2d-a8d5-fa577a7fada0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3665209355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3665209355 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.1748499576 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 102976098 ps |
| CPU time | 2.34 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:28 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-faa0d994-5b71-488d-89db-69269197b43f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1748499576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.1748499576 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.695194265 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 106065713 ps |
| CPU time | 1.13 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 204752 kb |
| Host | smart-7e892ae0-6bf6-4111-b286-bfaaf3640719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=695194265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.695194265 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.156214595 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 208992827 ps |
| CPU time | 2.08 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 204892 kb |
| Host | smart-ee061851-6134-4c14-bb92-9f50b1645cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=156214595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.156214595 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1028426827 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 583558651 ps |
| CPU time | 4 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:30 PM PDT 24 |
| Peak memory | 204744 kb |
| Host | smart-4ee8dca9-c75a-4893-b717-8161c8634d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1028426827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1028426827 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3152913736 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 40038475 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 01:08:52 PM PDT 24 |
| Finished | Jun 04 01:08:53 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-ec6b3a20-c4d3-4bef-bf47-e0857255a749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3152913736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3152913736 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1592826292 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 72663153 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 01:08:53 PM PDT 24 |
| Finished | Jun 04 01:08:55 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-3f79cdf8-adac-4c45-840f-38661028cf74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1592826292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1592826292 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1689078127 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 52234828 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204528 kb |
| Host | smart-bd79090a-14e1-496f-88eb-71eb31f0bb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1689078127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1689078127 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4242604514 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 38990244 ps |
| CPU time | 0.73 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:08:59 PM PDT 24 |
| Peak memory | 204504 kb |
| Host | smart-48a55f2a-c2ec-4d74-a3ae-65f8f6d355a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4242604514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.4242604514 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.875531681 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 38249315 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:08:59 PM PDT 24 |
| Peak memory | 204500 kb |
| Host | smart-43180e53-2e6d-4fc1-bbc8-7ca2dc45cab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=875531681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.875531681 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1065698572 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 102731831 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204584 kb |
| Host | smart-c5a31cc8-a484-49ca-abb0-26bec4b14bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1065698572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1065698572 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3363135511 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 39473002 ps |
| CPU time | 0.75 seconds |
| Started | Jun 04 01:08:53 PM PDT 24 |
| Finished | Jun 04 01:08:54 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-2bfd6ae5-9f41-4212-b82a-82f99d79b4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3363135511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3363135511 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3160775092 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 76586275 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:08:59 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-ce0a39a8-a2c3-4c46-bab7-c06f2a35abc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3160775092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3160775092 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2253974906 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 39692572 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:08:59 PM PDT 24 |
| Peak memory | 204540 kb |
| Host | smart-b68c3db9-a4f6-4297-922f-01d98dcb8154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2253974906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2253974906 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1339889856 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 34340990 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:08:59 PM PDT 24 |
| Peak memory | 204496 kb |
| Host | smart-938ab7ea-2dd7-4d4e-928d-7a9687873525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1339889856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1339889856 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2622353621 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 96327598 ps |
| CPU time | 1.99 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 204804 kb |
| Host | smart-e62c39da-712f-408a-9f27-87c2756dcecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2622353621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2622353621 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4149395303 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 331947721 ps |
| CPU time | 4.5 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:27 PM PDT 24 |
| Peak memory | 204720 kb |
| Host | smart-a639d50e-6f18-4cc2-a755-ff7e4a88a24a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4149395303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4149395303 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1286433937 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 238687732 ps |
| CPU time | 1.98 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 221164 kb |
| Host | smart-52622693-bd91-446e-b664-633c721c76f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286433937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.1286433937 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.926747652 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 58616262 ps |
| CPU time | 0.83 seconds |
| Started | Jun 04 01:08:23 PM PDT 24 |
| Finished | Jun 04 01:08:24 PM PDT 24 |
| Peak memory | 204612 kb |
| Host | smart-13c81834-aa27-4266-868a-65d1eb2f44e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=926747652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.926747652 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3853262818 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 42244052 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 204464 kb |
| Host | smart-5cf660a4-a284-4099-9a77-3605c7ba4243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3853262818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3853262818 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2492007433 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 207778182 ps |
| CPU time | 2.37 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:26 PM PDT 24 |
| Peak memory | 213036 kb |
| Host | smart-7e70d634-1d0f-419b-a9e2-af3f8cc2fa7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2492007433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2492007433 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1649022235 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 486361297 ps |
| CPU time | 4.22 seconds |
| Started | Jun 04 01:08:24 PM PDT 24 |
| Finished | Jun 04 01:08:30 PM PDT 24 |
| Peak memory | 204888 kb |
| Host | smart-5a4459c1-fac0-4fd6-8778-ebee130195a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1649022235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1649022235 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.117296841 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 208449963 ps |
| CPU time | 1.68 seconds |
| Started | Jun 04 01:08:25 PM PDT 24 |
| Finished | Jun 04 01:08:28 PM PDT 24 |
| Peak memory | 204860 kb |
| Host | smart-15b6ce64-9169-4047-8965-cebafe5ae1a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=117296841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.117296841 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1816336322 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 32414872 ps |
| CPU time | 0.67 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204492 kb |
| Host | smart-22178719-6437-46d0-9cdf-2593b118a82d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1816336322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1816336322 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3203891987 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 43543408 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204536 kb |
| Host | smart-3ac7ba18-6e5f-4538-a1dc-d4c6494f0a14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3203891987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3203891987 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.9290326 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 51798613 ps |
| CPU time | 0.65 seconds |
| Started | Jun 04 01:08:56 PM PDT 24 |
| Finished | Jun 04 01:08:58 PM PDT 24 |
| Peak memory | 204568 kb |
| Host | smart-203a8229-2fb3-4bc3-9294-3cc7c25ec680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=9290326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.9290326 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.279497946 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 40222939 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:08:57 PM PDT 24 |
| Finished | Jun 04 01:09:00 PM PDT 24 |
| Peak memory | 204556 kb |
| Host | smart-1d6889aa-bf04-4127-9010-793a1a14d4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=279497946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.279497946 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.1793480321 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 29851565 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 01:09:01 PM PDT 24 |
| Finished | Jun 04 01:09:02 PM PDT 24 |
| Peak memory | 204448 kb |
| Host | smart-1554e9cc-30f6-45a0-89dd-574b5e00a594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1793480321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.1793480321 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.589737166 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 41017162 ps |
| CPU time | 0.68 seconds |
| Started | Jun 04 01:09:04 PM PDT 24 |
| Finished | Jun 04 01:09:06 PM PDT 24 |
| Peak memory | 204560 kb |
| Host | smart-e256ad4c-026f-4ec3-ba2a-25ad6cec72f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=589737166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.589737166 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.729643491 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 57681979 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 01:09:03 PM PDT 24 |
| Finished | Jun 04 01:09:04 PM PDT 24 |
| Peak memory | 204556 kb |
| Host | smart-138537ca-8bb4-409a-9851-60ecaff630cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=729643491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.729643491 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1401334240 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 48143905 ps |
| CPU time | 0.66 seconds |
| Started | Jun 04 01:09:02 PM PDT 24 |
| Finished | Jun 04 01:09:03 PM PDT 24 |
| Peak memory | 204544 kb |
| Host | smart-297c0341-d487-4b59-8cfc-a24141186fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1401334240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1401334240 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3272687905 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 43755277 ps |
| CPU time | 0.74 seconds |
| Started | Jun 04 01:09:02 PM PDT 24 |
| Finished | Jun 04 01:09:03 PM PDT 24 |
| Peak memory | 204592 kb |
| Host | smart-cb55a9a7-a3bf-46f0-8320-b0c8bd353957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3272687905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3272687905 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1155453860 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 53839559 ps |
| CPU time | 0.7 seconds |
| Started | Jun 04 01:09:03 PM PDT 24 |
| Finished | Jun 04 01:09:05 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-2bf2f56e-374c-445f-8b39-3de0a7cb3966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1155453860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1155453860 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2229704126 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 96544226 ps |
| CPU time | 1.19 seconds |
| Started | Jun 04 01:08:33 PM PDT 24 |
| Finished | Jun 04 01:08:35 PM PDT 24 |
| Peak memory | 212892 kb |
| Host | smart-68941fef-f12a-4bf4-86c3-c5dd8dae3c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229704126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.2229704126 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1381431192 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 77591793 ps |
| CPU time | 1.05 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:33 PM PDT 24 |
| Peak memory | 204744 kb |
| Host | smart-cd0e8142-d205-4270-9dcf-cf3f320e0160 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1381431192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1381431192 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2001597970 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 103552530 ps |
| CPU time | 0.79 seconds |
| Started | Jun 04 01:08:32 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 204548 kb |
| Host | smart-c37ae0e4-4f5a-4323-9027-d501ad076c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2001597970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2001597970 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3135649814 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 151748182 ps |
| CPU time | 1.22 seconds |
| Started | Jun 04 01:08:30 PM PDT 24 |
| Finished | Jun 04 01:08:33 PM PDT 24 |
| Peak memory | 204728 kb |
| Host | smart-73e3374e-ccb2-4129-89a1-462f1b9cbdeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3135649814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3135649814 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.594547529 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 78253911 ps |
| CPU time | 1.9 seconds |
| Started | Jun 04 01:08:22 PM PDT 24 |
| Finished | Jun 04 01:08:25 PM PDT 24 |
| Peak memory | 220488 kb |
| Host | smart-08b4cb4a-9f7e-4bca-ae8c-23fcb112590c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=594547529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.594547529 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1310516552 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 106444235 ps |
| CPU time | 1.2 seconds |
| Started | Jun 04 01:08:32 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 213060 kb |
| Host | smart-10ea19c7-c1db-406e-8618-ba360d767f86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310516552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.1310516552 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2296223274 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 51150533 ps |
| CPU time | 0.83 seconds |
| Started | Jun 04 01:08:33 PM PDT 24 |
| Finished | Jun 04 01:08:35 PM PDT 24 |
| Peak memory | 204588 kb |
| Host | smart-d4d2295b-5a19-4bda-94cc-d836507268bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2296223274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2296223274 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1482812520 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 52093002 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:33 PM PDT 24 |
| Peak memory | 204572 kb |
| Host | smart-29c158a5-2281-47fc-8b9d-5c649ca214f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1482812520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1482812520 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1894022746 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 261224791 ps |
| CPU time | 1.85 seconds |
| Started | Jun 04 01:08:30 PM PDT 24 |
| Finished | Jun 04 01:08:32 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-b46a6c82-7abd-4c9f-89e4-ea198b20d8ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1894022746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1894022746 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.159553502 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 312988253 ps |
| CPU time | 3.33 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:36 PM PDT 24 |
| Peak memory | 204832 kb |
| Host | smart-82390837-165e-42de-8ea2-a71db16c3525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=159553502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.159553502 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.775279854 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1126970589 ps |
| CPU time | 3.82 seconds |
| Started | Jun 04 01:08:29 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 204848 kb |
| Host | smart-9483be8d-553d-4813-8ca8-6764f5ee6adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=775279854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.775279854 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3761666448 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 62262681 ps |
| CPU time | 1.21 seconds |
| Started | Jun 04 01:08:33 PM PDT 24 |
| Finished | Jun 04 01:08:35 PM PDT 24 |
| Peak memory | 212896 kb |
| Host | smart-044c3185-47c3-4e25-8906-bd6077d78f93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761666448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.3761666448 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1858720136 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 55555270 ps |
| CPU time | 1 seconds |
| Started | Jun 04 01:08:32 PM PDT 24 |
| Finished | Jun 04 01:08:33 PM PDT 24 |
| Peak memory | 204748 kb |
| Host | smart-a65e950f-b061-4a48-ba8c-5f950e041432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1858720136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1858720136 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2326331657 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 43038531 ps |
| CPU time | 0.71 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:33 PM PDT 24 |
| Peak memory | 204564 kb |
| Host | smart-69b5214b-326f-47d6-9970-e4b98d24b277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2326331657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2326331657 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1335916191 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 143372723 ps |
| CPU time | 1.56 seconds |
| Started | Jun 04 01:08:33 PM PDT 24 |
| Finished | Jun 04 01:08:36 PM PDT 24 |
| Peak memory | 204696 kb |
| Host | smart-0414495b-edff-4af9-97c0-bd898cb5b731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1335916191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1335916191 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3358277220 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 81703022 ps |
| CPU time | 1.99 seconds |
| Started | Jun 04 01:08:29 PM PDT 24 |
| Finished | Jun 04 01:08:32 PM PDT 24 |
| Peak memory | 220592 kb |
| Host | smart-288ac319-2f11-45b1-b195-45f463a5c1b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3358277220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3358277220 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1016076519 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 810182738 ps |
| CPU time | 4.27 seconds |
| Started | Jun 04 01:08:29 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 204692 kb |
| Host | smart-b3b55157-20ec-4029-880b-02eb53e47fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1016076519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1016076519 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.4238276607 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 177915707 ps |
| CPU time | 1.96 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 213028 kb |
| Host | smart-0f0a13c7-18d3-4ef6-a414-1715a7269664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238276607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.4238276607 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1532374790 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 145112310 ps |
| CPU time | 1.11 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:33 PM PDT 24 |
| Peak memory | 204756 kb |
| Host | smart-9688db00-9e38-4060-b24c-d00bbf2080fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1532374790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1532374790 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1632017843 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 73108925 ps |
| CPU time | 0.69 seconds |
| Started | Jun 04 01:08:30 PM PDT 24 |
| Finished | Jun 04 01:08:32 PM PDT 24 |
| Peak memory | 204520 kb |
| Host | smart-c5afbb08-18f4-415e-be42-d279a4ac8de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1632017843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1632017843 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1113103086 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 110461858 ps |
| CPU time | 1.59 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 204768 kb |
| Host | smart-06bddf62-a149-4fb3-a2f5-bc797d2df688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1113103086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1113103086 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.1296896054 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 115157394 ps |
| CPU time | 1.68 seconds |
| Started | Jun 04 01:08:31 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 204800 kb |
| Host | smart-e4da5e22-b189-4ab0-af1a-be0c0717b61e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1296896054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.1296896054 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1874941084 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 880176399 ps |
| CPU time | 4.85 seconds |
| Started | Jun 04 01:08:33 PM PDT 24 |
| Finished | Jun 04 01:08:39 PM PDT 24 |
| Peak memory | 204716 kb |
| Host | smart-213c0e31-81a5-4c69-83c4-0cf5cde0de77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1874941084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1874941084 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2407704924 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 110892767 ps |
| CPU time | 1.47 seconds |
| Started | Jun 04 01:08:37 PM PDT 24 |
| Finished | Jun 04 01:08:39 PM PDT 24 |
| Peak memory | 214648 kb |
| Host | smart-9b8a0497-fb74-4163-b6e4-f16c8740a6fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407704924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.2407704924 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.252556153 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 81555014 ps |
| CPU time | 1.08 seconds |
| Started | Jun 04 01:08:39 PM PDT 24 |
| Finished | Jun 04 01:08:41 PM PDT 24 |
| Peak memory | 204824 kb |
| Host | smart-a5ab166c-6cf4-449a-841b-125c085534d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=252556153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.252556153 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1049429860 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 42199456 ps |
| CPU time | 0.72 seconds |
| Started | Jun 04 01:08:38 PM PDT 24 |
| Finished | Jun 04 01:08:40 PM PDT 24 |
| Peak memory | 204576 kb |
| Host | smart-dcd2ba38-b2d2-4a29-acdd-55d937a2803a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1049429860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1049429860 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1551427630 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 161250340 ps |
| CPU time | 1.67 seconds |
| Started | Jun 04 01:08:39 PM PDT 24 |
| Finished | Jun 04 01:08:41 PM PDT 24 |
| Peak memory | 204736 kb |
| Host | smart-03ad57c1-d658-4d4f-9046-c5f20c3fb020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1551427630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1551427630 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2368125975 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 147906045 ps |
| CPU time | 1.48 seconds |
| Started | Jun 04 01:08:32 PM PDT 24 |
| Finished | Jun 04 01:08:34 PM PDT 24 |
| Peak memory | 204904 kb |
| Host | smart-01588ccf-e275-480c-8746-c6ac59a170b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2368125975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2368125975 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |