Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	356	1		T1	5		T3	5		T12	8
all_pins[1]	356	1		T1	5		T3	5		T12	8
all_pins[2]	356	1		T1	5		T3	5		T12	8
all_pins[3]	356	1		T1	5		T3	5		T12	8
all_pins[4]	356	1		T1	5		T3	5		T12	8
all_pins[5]	356	1		T1	5		T3	5		T12	8
all_pins[6]	356	1		T1	5		T3	5		T12	8
all_pins[7]	356	1		T1	5		T3	5		T12	8
all_pins[8]	356	1		T1	5		T3	5		T12	8
all_pins[9]	356	1		T1	5		T3	5		T12	8
all_pins[10]	356	1		T1	5		T3	5		T12	8
all_pins[11]	356	1		T1	5		T3	5		T12	8
all_pins[12]	356	1		T1	5		T3	5		T12	8
all_pins[13]	356	1		T1	5		T3	5		T12	8
all_pins[14]	356	1		T1	5		T3	5		T12	8
all_pins[15]	356	1		T1	5		T3	5		T12	8
all_pins[16]	356	1		T1	5		T3	5		T12	8
all_pins[17]	356	1		T1	5		T3	5		T12	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5396	1		T1	78		T3	77		T12	122
values[0x1]	1012	1		T1	12		T3	13		T12	22
transitions[0x0=>0x1]	784	1		T1	8		T3	13		T12	20
transitions[0x1=>0x0]	795	1		T1	8		T3	13		T12	20

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	295	1		T1	4		T3	5		T12	6
all_pins[0]	values[0x1]	61	1		T1	1		T12	2		T13	2
all_pins[0]	transitions[0x0=>0x1]	46	1		T1	1		T12	2		T14	3
all_pins[0]	transitions[0x1=>0x0]	38	1		T3	2		T12	2		T25	2
all_pins[1]	values[0x0]	303	1		T1	5		T3	3		T12	6
all_pins[1]	values[0x1]	53	1		T3	2		T12	2		T13	2
all_pins[1]	transitions[0x0=>0x1]	45	1		T3	2		T12	1		T13	1
all_pins[1]	transitions[0x1=>0x0]	47	1		T1	3		T3	2		T13	4
all_pins[2]	values[0x0]	301	1		T1	2		T3	3		T12	7
all_pins[2]	values[0x1]	55	1		T1	3		T3	2		T12	1
all_pins[2]	transitions[0x0=>0x1]	41	1		T1	2		T3	2		T12	1
all_pins[2]	transitions[0x1=>0x0]	42	1		T13	1		T25	1		T62	1
all_pins[3]	values[0x0]	300	1		T1	4		T3	5		T12	8
all_pins[3]	values[0x1]	56	1		T1	1		T13	2		T25	1
all_pins[3]	transitions[0x0=>0x1]	46	1		T1	1		T13	2		T25	1
all_pins[3]	transitions[0x1=>0x0]	59	1		T12	2		T13	2		T14	1
all_pins[4]	values[0x0]	287	1		T1	5		T3	5		T12	6
all_pins[4]	values[0x1]	69	1		T12	2		T13	2		T14	1
all_pins[4]	transitions[0x0=>0x1]	55	1		T12	2		T13	2		T14	1
all_pins[4]	transitions[0x1=>0x0]	44	1		T3	3		T12	1		T13	2
all_pins[5]	values[0x0]	298	1		T1	5		T3	2		T12	7
all_pins[5]	values[0x1]	58	1		T3	3		T12	1		T13	2
all_pins[5]	transitions[0x0=>0x1]	47	1		T3	3		T12	1		T13	1
all_pins[5]	transitions[0x1=>0x0]	42	1		T12	3		T13	1		T14	1
all_pins[6]	values[0x0]	303	1		T1	5		T3	5		T12	5
all_pins[6]	values[0x1]	53	1		T12	3		T13	2		T14	1
all_pins[6]	transitions[0x0=>0x1]	43	1		T12	3		T13	1		T14	1
all_pins[6]	transitions[0x1=>0x0]	45	1		T1	1		T3	1		T13	2
all_pins[7]	values[0x0]	301	1		T1	4		T3	4		T12	8
all_pins[7]	values[0x1]	55	1		T1	1		T3	1		T13	3
all_pins[7]	transitions[0x0=>0x1]	39	1		T3	1		T13	1		T25	1
all_pins[7]	transitions[0x1=>0x0]	36	1		T12	2		T13	1		T25	1
all_pins[8]	values[0x0]	304	1		T1	4		T3	5		T12	6
all_pins[8]	values[0x1]	52	1		T1	1		T12	2		T13	3
all_pins[8]	transitions[0x0=>0x1]	43	1		T12	2		T13	3		T25	1
all_pins[8]	transitions[0x1=>0x0]	47	1		T1	1		T3	1		T12	1
all_pins[9]	values[0x0]	300	1		T1	3		T3	4		T12	7
all_pins[9]	values[0x1]	56	1		T1	2		T3	1		T12	1
all_pins[9]	transitions[0x0=>0x1]	38	1		T1	1		T3	1		T12	1
all_pins[9]	transitions[0x1=>0x0]	35	1		T12	1		T13	1		T14	1
all_pins[10]	values[0x0]	303	1		T1	4		T3	5		T12	7
all_pins[10]	values[0x1]	53	1		T1	1		T12	1		T13	2
all_pins[10]	transitions[0x0=>0x1]	40	1		T1	1		T13	1		T14	1
all_pins[10]	transitions[0x1=>0x0]	48	1		T12	1		T13	1		T14	2
all_pins[11]	values[0x0]	295	1		T1	5		T3	5		T12	6
all_pins[11]	values[0x1]	61	1		T12	2		T13	2		T14	2
all_pins[11]	transitions[0x0=>0x1]	48	1		T12	2		T13	2		T14	2
all_pins[11]	transitions[0x1=>0x0]	55	1		T1	1		T13	3		T25	2
all_pins[12]	values[0x0]	288	1		T1	4		T3	5		T12	8
all_pins[12]	values[0x1]	68	1		T1	1		T13	3		T25	2
all_pins[12]	transitions[0x0=>0x1]	51	1		T1	1		T13	2		T25	2
all_pins[12]	transitions[0x1=>0x0]	42	1		T1	1		T3	2		T13	1
all_pins[13]	values[0x0]	297	1		T1	4		T3	3		T12	8
all_pins[13]	values[0x1]	59	1		T1	1		T3	2		T13	2
all_pins[13]	transitions[0x0=>0x1]	42	1		T1	1		T3	2		T13	2
all_pins[13]	transitions[0x1=>0x0]	42	1		T12	3		T13	1		T25	1
all_pins[14]	values[0x0]	297	1		T1	5		T3	5		T12	5
all_pins[14]	values[0x1]	59	1		T12	3		T13	1		T25	1
all_pins[14]	transitions[0x0=>0x1]	50	1		T12	3		T13	1		T14	1
all_pins[14]	transitions[0x1=>0x0]	44	1		T3	1		T12	2		T13	2
all_pins[15]	values[0x0]	303	1		T1	5		T3	4		T12	6
all_pins[15]	values[0x1]	53	1		T3	1		T12	2		T13	2
all_pins[15]	transitions[0x0=>0x1]	43	1		T3	1		T12	2		T13	2
all_pins[15]	transitions[0x1=>0x0]	38	1		T13	2		T14	1		T15	1
all_pins[16]	values[0x0]	308	1		T1	5		T3	5		T12	8
all_pins[16]	values[0x1]	48	1		T13	2		T14	1		T15	2
all_pins[16]	transitions[0x0=>0x1]	42	1		T13	1		T14	1		T15	2
all_pins[16]	transitions[0x1=>0x0]	37	1		T3	1		T13	1		T15	1
all_pins[17]	values[0x0]	313	1		T1	5		T3	4		T12	8
all_pins[17]	values[0x1]	43	1		T3	1		T13	2		T15	1
all_pins[17]	transitions[0x0=>0x1]	25	1		T3	1		T13	1		T15	1
all_pins[17]	transitions[0x1=>0x0]	54	1		T1	1		T12	2		T13	2