Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T1	4		T3	4		T12	7
all_values[1]	266	1		T1	4		T3	4		T12	7
all_values[2]	266	1		T1	4		T3	4		T12	7
all_values[3]	266	1		T1	4		T3	4		T12	7
all_values[4]	266	1		T1	4		T3	4		T12	7
all_values[5]	266	1		T1	4		T3	4		T12	7
all_values[6]	266	1		T1	4		T3	4		T12	7
all_values[7]	266	1		T1	4		T3	4		T12	7
all_values[8]	266	1		T1	4		T3	4		T12	7
all_values[9]	266	1		T1	4		T3	4		T12	7
all_values[10]	266	1		T1	4		T3	4		T12	7
all_values[11]	266	1		T1	4		T3	4		T12	7
all_values[12]	266	1		T1	4		T3	4		T12	7
all_values[13]	266	1		T1	4		T3	4		T12	7
all_values[14]	266	1		T1	4		T3	4		T12	7
all_values[15]	266	1		T1	4		T3	4		T12	7
all_values[16]	266	1		T1	4		T3	4		T12	7
all_values[17]	266	1		T1	4		T3	4		T12	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2622	1		T1	42		T3	40		T12	55
auto[1]	2166	1		T1	30		T3	32		T12	71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	877	1		T1	19		T3	21		T12	17
auto[1]	3911	1		T1	53		T3	51		T12	109

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2844	1		T1	50		T3	50		T12	72
auto[1]	1944	1		T1	22		T3	22		T12	54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1		T3	1		T12	1		T63	1
all_values[0]	auto[0]	auto[0]	auto[1]	51	1		T1	1		T3	2		T13	2
all_values[0]	auto[0]	auto[1]	auto[0]	17	1		T12	3		T62	1		T65	1
all_values[0]	auto[0]	auto[1]	auto[1]	64	1		T1	1		T12	1		T13	1
all_values[0]	auto[1]	auto[0]	auto[1]	58	1		T1	1		T3	1		T13	1
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T1	1		T12	2		T13	3
all_values[1]	auto[0]	auto[0]	auto[0]	21	1		T14	1		T68	1		T69	1
all_values[1]	auto[0]	auto[0]	auto[1]	59	1		T1	2		T12	2		T13	1
all_values[1]	auto[0]	auto[1]	auto[0]	19	1		T12	1		T63	2		T64	1
all_values[1]	auto[0]	auto[1]	auto[1]	61	1		T3	2		T13	3		T25	1
all_values[1]	auto[1]	auto[0]	auto[1]	54	1		T1	1		T12	1		T14	4
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T1	1		T3	2		T12	3
all_values[2]	auto[0]	auto[0]	auto[0]	33	1		T13	1		T15	1		T63	1
all_values[2]	auto[0]	auto[0]	auto[1]	50	1		T3	1		T12	1		T13	1
all_values[2]	auto[0]	auto[1]	auto[0]	23	1		T1	1		T13	1		T25	4
all_values[2]	auto[0]	auto[1]	auto[1]	56	1		T1	1		T3	2		T12	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1		T3	1		T12	3		T13	1
all_values[2]	auto[1]	auto[1]	auto[1]	39	1		T1	2		T12	2		T13	2
all_values[3]	auto[0]	auto[0]	auto[0]	24	1		T63	1		T62	1		T46	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T1	1		T25	1		T14	1
all_values[3]	auto[0]	auto[1]	auto[0]	17	1		T3	4		T12	1		T13	1
all_values[3]	auto[0]	auto[1]	auto[1]	58	1		T1	2		T12	3		T13	3
all_values[3]	auto[1]	auto[0]	auto[1]	54	1		T12	1		T13	1		T14	2
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T1	1		T12	2		T13	2
all_values[4]	auto[0]	auto[0]	auto[0]	25	1		T1	2		T3	1		T12	2
all_values[4]	auto[0]	auto[0]	auto[1]	47	1		T3	2		T25	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T1	2		T12	1		T45	1
all_values[4]	auto[0]	auto[1]	auto[1]	60	1		T12	1		T13	2		T25	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T3	1		T12	1		T13	4
all_values[4]	auto[1]	auto[1]	auto[1]	53	1		T12	2		T13	1		T14	1
all_values[5]	auto[0]	auto[0]	auto[0]	32	1		T1	1		T13	1		T15	1
all_values[5]	auto[0]	auto[0]	auto[1]	53	1		T1	1		T13	2		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	18	1		T12	1		T64	3		T70	3
all_values[5]	auto[0]	auto[1]	auto[1]	47	1		T1	1		T3	1		T12	2
all_values[5]	auto[1]	auto[0]	auto[1]	74	1		T1	1		T12	1		T13	1
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T3	3		T12	3		T13	1
all_values[6]	auto[0]	auto[0]	auto[0]	33	1		T12	2		T15	1		T45	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1		T1	1		T3	3		T13	1
all_values[6]	auto[0]	auto[1]	auto[0]	19	1		T63	1		T46	1		T65	2
all_values[6]	auto[0]	auto[1]	auto[1]	51	1		T1	1		T12	2		T13	3
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T1	2		T3	1		T13	1
all_values[6]	auto[1]	auto[1]	auto[1]	48	1		T12	3		T13	2		T14	2
all_values[7]	auto[0]	auto[0]	auto[0]	30	1		T1	1		T12	1		T25	1
all_values[7]	auto[0]	auto[0]	auto[1]	60	1		T1	1		T3	2		T12	1
all_values[7]	auto[0]	auto[1]	auto[0]	13	1		T62	2		T67	2		T71	1
all_values[7]	auto[0]	auto[1]	auto[1]	53	1		T1	1		T3	1		T12	2
all_values[7]	auto[1]	auto[0]	auto[1]	67	1		T1	1		T12	3		T13	1
all_values[7]	auto[1]	auto[1]	auto[1]	43	1		T3	1		T13	3		T14	2
all_values[8]	auto[0]	auto[0]	auto[0]	42	1		T15	1		T62	1		T46	2
all_values[8]	auto[0]	auto[0]	auto[1]	44	1		T1	1		T3	1		T12	1
all_values[8]	auto[0]	auto[1]	auto[0]	18	1		T3	2		T12	1		T70	1
all_values[8]	auto[0]	auto[1]	auto[1]	47	1		T1	1		T12	1		T13	3
all_values[8]	auto[1]	auto[0]	auto[1]	71	1		T1	2		T3	1		T12	1
all_values[8]	auto[1]	auto[1]	auto[1]	44	1		T12	3		T13	3		T25	2
all_values[9]	auto[0]	auto[0]	auto[0]	29	1		T13	2		T14	3		T72	1
all_values[9]	auto[0]	auto[0]	auto[1]	50	1		T1	1		T3	2		T12	1
all_values[9]	auto[0]	auto[1]	auto[0]	23	1		T3	1		T12	1		T13	2
all_values[9]	auto[0]	auto[1]	auto[1]	58	1		T1	2		T12	2		T13	2
all_values[9]	auto[1]	auto[0]	auto[1]	58	1		T12	3		T25	3		T15	3
all_values[9]	auto[1]	auto[1]	auto[1]	48	1		T1	1		T3	1		T13	1
all_values[10]	auto[0]	auto[0]	auto[0]	29	1		T3	4		T25	1		T63	2
all_values[10]	auto[0]	auto[0]	auto[1]	53	1		T1	1		T12	2		T13	1
all_values[10]	auto[0]	auto[1]	auto[0]	22	1		T13	2		T64	1		T45	1
all_values[10]	auto[0]	auto[1]	auto[1]	52	1		T1	1		T12	3		T13	1
all_values[10]	auto[1]	auto[0]	auto[1]	60	1		T12	1		T25	1		T14	4
all_values[10]	auto[1]	auto[1]	auto[1]	50	1		T1	2		T12	1		T13	3
all_values[11]	auto[0]	auto[0]	auto[0]	32	1		T1	1		T3	2		T13	1
all_values[11]	auto[0]	auto[0]	auto[1]	51	1		T1	1		T12	1		T13	1
all_values[11]	auto[0]	auto[1]	auto[0]	28	1		T3	2		T13	1		T25	4
all_values[11]	auto[0]	auto[1]	auto[1]	59	1		T12	2		T14	3		T15	3
all_values[11]	auto[1]	auto[0]	auto[1]	49	1		T1	2		T12	1		T13	2
all_values[11]	auto[1]	auto[1]	auto[1]	47	1		T12	3		T13	2		T14	2
all_values[12]	auto[0]	auto[0]	auto[0]	21	1		T14	1		T15	1		T62	4
all_values[12]	auto[0]	auto[0]	auto[1]	61	1		T1	2		T3	1		T12	4
all_values[12]	auto[0]	auto[1]	auto[0]	23	1		T12	1		T25	2		T14	1
all_values[12]	auto[0]	auto[1]	auto[1]	47	1		T1	1		T3	2		T13	1
all_values[12]	auto[1]	auto[0]	auto[1]	59	1		T3	1		T12	2		T13	3
all_values[12]	auto[1]	auto[1]	auto[1]	55	1		T1	1		T13	2		T14	1
all_values[13]	auto[0]	auto[0]	auto[0]	19	1		T13	1		T63	1		T46	1
all_values[13]	auto[0]	auto[0]	auto[1]	64	1		T1	2		T3	1		T12	4
all_values[13]	auto[0]	auto[1]	auto[0]	22	1		T13	1		T46	3		T68	1
all_values[13]	auto[0]	auto[1]	auto[1]	48	1		T1	1		T3	2		T12	1
all_values[13]	auto[1]	auto[0]	auto[1]	66	1		T1	1		T3	1		T12	2
all_values[13]	auto[1]	auto[1]	auto[1]	47	1		T13	2		T25	3		T14	2
all_values[14]	auto[0]	auto[0]	auto[0]	34	1		T1	2		T15	1		T63	2
all_values[14]	auto[0]	auto[0]	auto[1]	54	1		T1	1		T3	1		T12	2
all_values[14]	auto[0]	auto[1]	auto[0]	25	1		T3	2		T12	1		T25	1
all_values[14]	auto[0]	auto[1]	auto[1]	48	1		T12	1		T13	1		T25	1
all_values[14]	auto[1]	auto[0]	auto[1]	66	1		T3	1		T12	1		T13	3
all_values[14]	auto[1]	auto[1]	auto[1]	39	1		T1	1		T12	2		T25	1
all_values[15]	auto[0]	auto[0]	auto[0]	25	1		T1	1		T15	1		T45	2
all_values[15]	auto[0]	auto[0]	auto[1]	69	1		T1	2		T3	1		T12	2
all_values[15]	auto[0]	auto[1]	auto[0]	12	1		T25	1		T73	1		T67	1
all_values[15]	auto[0]	auto[1]	auto[1]	42	1		T12	2		T15	1		T63	2
all_values[15]	auto[1]	auto[0]	auto[1]	70	1		T1	1		T3	1		T13	2
all_values[15]	auto[1]	auto[1]	auto[1]	48	1		T3	2		T12	3		T13	3
all_values[16]	auto[0]	auto[0]	auto[0]	32	1		T1	3		T3	1		T13	1
all_values[16]	auto[0]	auto[0]	auto[1]	60	1		T3	1		T12	2		T13	2
all_values[16]	auto[0]	auto[1]	auto[0]	22	1		T1	1		T13	1		T25	3
all_values[16]	auto[0]	auto[1]	auto[1]	54	1		T12	4		T13	1		T14	1
all_values[16]	auto[1]	auto[0]	auto[1]	61	1		T3	2		T12	1		T14	2
all_values[16]	auto[1]	auto[1]	auto[1]	37	1		T13	2		T14	2		T15	1
all_values[17]	auto[0]	auto[0]	auto[0]	24	1		T1	1		T25	3		T14	2
all_values[17]	auto[0]	auto[0]	auto[1]	58	1		T3	1		T12	2		T13	1
all_values[17]	auto[0]	auto[1]	auto[0]	24	1		T1	3		T3	1		T25	1
all_values[17]	auto[0]	auto[1]	auto[1]	58	1		T12	2		T13	2		T15	2
all_values[17]	auto[1]	auto[0]	auto[1]	60	1		T3	1		T12	2		T13	1
all_values[17]	auto[1]	auto[1]	auto[1]	42	1		T3	1		T12	1		T13	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal