Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16088753	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9465755	1		T1	14		T2	5		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25178972	1		T1	3706		T2	3698		T3	3560
values[0x0]	187787	1		T1	2		T2	5		T3	5
values[0x1]	187749	1		T1	7		T2	4		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12506603	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	13047905	1		T1	923		T2	911		T3	905

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87001	1		T2	14		T3	16		T27	5
valid_sources[0x01]	155985	1		T2	20		T3	12		T27	10
valid_sources[0x02]	90245	1		T2	8		T3	8		T25	3567
valid_sources[0x03]	79187	1		T2	20		T3	13		T27	8
valid_sources[0x04]	91286	1		T2	15		T3	10		T27	15
valid_sources[0x05]	209106	1		T2	12		T3	9		T27	9
valid_sources[0x06]	83165	1		T2	15		T3	10		T27	21
valid_sources[0x07]	84499	1		T2	7		T3	29		T27	20
valid_sources[0x08]	84913	1		T2	20		T3	8		T27	11
valid_sources[0x09]	79975	1		T2	19		T3	8		T27	7
valid_sources[0x0a]	93433	1		T2	14		T3	26		T27	15
valid_sources[0x0b]	299778	1		T2	12		T3	17		T27	17
valid_sources[0x0c]	87860	1		T2	20		T3	7		T27	35
valid_sources[0x0d]	99470	1		T2	21		T3	14		T27	16
valid_sources[0x0e]	97465	1		T2	16		T3	19		T27	6
valid_sources[0x0f]	85470	1		T2	13		T3	7		T27	5
valid_sources[0x10]	79555	1		T2	9		T3	8		T27	12
valid_sources[0x11]	86763	1		T2	11		T3	8		T27	16
valid_sources[0x12]	79489	1		T2	23		T3	12		T27	9
valid_sources[0x13]	86673	1		T2	13		T3	17		T27	9
valid_sources[0x14]	97972	1		T2	14		T3	19		T27	10
valid_sources[0x15]	97539	1		T2	9		T3	22		T27	8
valid_sources[0x16]	86372	1		T2	19		T3	21		T27	9
valid_sources[0x17]	79893	1		T2	13		T3	13		T27	6
valid_sources[0x18]	96439	1		T2	16		T3	13		T27	12
valid_sources[0x19]	91748	1		T2	12		T3	16		T27	10
valid_sources[0x1a]	80152	1		T2	11		T3	11		T27	13
valid_sources[0x1b]	81804	1		T2	7		T3	11		T27	13
valid_sources[0x1c]	84881	1		T2	11		T3	9		T27	15
valid_sources[0x1d]	78986	1		T2	11		T3	19		T27	6
valid_sources[0x1e]	87947	1		T2	7		T3	8		T27	13
valid_sources[0x1f]	88068	1		T2	9		T3	24		T27	13
valid_sources[0x20]	86937	1		T2	14		T3	21		T27	24
valid_sources[0x21]	100089	1		T2	15		T3	9		T27	19
valid_sources[0x22]	138917	1		T2	19		T3	16		T27	30
valid_sources[0x23]	80836	1		T2	22		T3	15		T27	29
valid_sources[0x24]	85514	1		T2	16		T3	9		T27	16
valid_sources[0x25]	124898	1		T2	16		T3	5		T27	13
valid_sources[0x26]	86478	1		T2	15		T3	17		T27	7
valid_sources[0x27]	85612	1		T2	11		T3	13		T27	20
valid_sources[0x28]	83877	1		T2	16		T3	13		T27	13
valid_sources[0x29]	91669	1		T2	15		T3	20		T27	22
valid_sources[0x2a]	83474	1		T2	23		T3	13		T27	13
valid_sources[0x2b]	123884	1		T2	17		T3	13		T27	11
valid_sources[0x2c]	87293	1		T2	12		T3	19		T27	20
valid_sources[0x2d]	82828	1		T2	10		T3	13		T27	7
valid_sources[0x2e]	80271	1		T2	17		T3	16		T27	5
valid_sources[0x2f]	90456	1		T2	15		T3	12		T27	13
valid_sources[0x30]	78205	1		T2	19		T3	10		T27	15
valid_sources[0x31]	82580	1		T2	11		T3	13		T27	16
valid_sources[0x32]	231029	1		T2	18		T3	9		T27	6
valid_sources[0x33]	83505	1		T2	15		T3	12		T27	9
valid_sources[0x34]	88008	1		T2	16		T3	13		T27	10
valid_sources[0x35]	86069	1		T2	15		T3	22		T27	11
valid_sources[0x36]	81609	1		T2	20		T3	7		T27	13
valid_sources[0x37]	84987	1		T2	3		T3	7		T27	20
valid_sources[0x38]	83242	1		T2	15		T3	12		T27	14
valid_sources[0x39]	86655	1		T2	14		T3	25		T27	11
valid_sources[0x3a]	84492	1		T2	15		T3	18		T27	14
valid_sources[0x3b]	88067	1		T2	17		T3	12		T27	8
valid_sources[0x3c]	83303	1		T2	10		T3	20		T27	7
valid_sources[0x3d]	95539	1		T2	17		T3	15		T27	17
valid_sources[0x3e]	93623	1		T2	10		T3	12		T27	26
valid_sources[0x3f]	90671	1		T2	13		T3	17		T27	24
valid_sources[0x40]	144463	1		T2	15		T3	25		T27	10
valid_sources[0x41]	85962	1		T2	17		T3	6		T27	4
valid_sources[0x42]	88433	1		T2	19		T3	9		T27	11
valid_sources[0x43]	87637	1		T2	22		T3	6		T27	16
valid_sources[0x44]	82458	1		T2	9		T3	11		T27	20
valid_sources[0x45]	96013	1		T1	3715		T2	11		T3	12
valid_sources[0x46]	83313	1		T2	12		T3	8		T27	6
valid_sources[0x47]	159106	1		T2	12		T3	12		T27	22
valid_sources[0x48]	91608	1		T2	19		T3	13		T27	20
valid_sources[0x49]	91499	1		T2	20		T3	8		T27	14
valid_sources[0x4a]	85190	1		T2	18		T3	9		T27	16
valid_sources[0x4b]	79911	1		T2	12		T3	6		T27	8
valid_sources[0x4c]	80369	1		T2	20		T3	9		T27	29
valid_sources[0x4d]	87856	1		T2	12		T3	21		T27	19
valid_sources[0x4e]	92396	1		T2	14		T3	12		T27	2
valid_sources[0x4f]	87026	1		T2	12		T3	21		T27	6
valid_sources[0x50]	89010	1		T2	17		T3	11		T27	12
valid_sources[0x51]	82706	1		T2	11		T3	19		T27	27
valid_sources[0x52]	209902	1		T2	16		T3	13		T27	13
valid_sources[0x53]	80010	1		T2	15		T3	17		T27	23
valid_sources[0x54]	95998	1		T2	16		T3	4		T27	7
valid_sources[0x55]	91400	1		T2	14		T3	27		T27	31
valid_sources[0x56]	87121	1		T2	8		T3	11		T27	16
valid_sources[0x57]	81893	1		T2	18		T3	6		T27	16
valid_sources[0x58]	98483	1		T2	23		T3	9		T27	5
valid_sources[0x59]	82013	1		T2	13		T3	26		T27	15
valid_sources[0x5a]	218760	1		T2	14		T3	8		T27	4
valid_sources[0x5b]	165737	1		T2	13		T3	15		T27	25
valid_sources[0x5c]	84416	1		T2	15		T3	16		T27	14
valid_sources[0x5d]	88459	1		T2	16		T3	8		T27	15
valid_sources[0x5e]	80233	1		T2	14		T3	19		T27	11
valid_sources[0x5f]	83040	1		T2	7		T3	18		T27	19
valid_sources[0x60]	90837	1		T2	13		T3	21		T27	9
valid_sources[0x61]	82920	1		T2	15		T3	6		T27	14
valid_sources[0x62]	82930	1		T2	11		T3	19		T27	19
valid_sources[0x63]	86264	1		T2	15		T3	14		T27	23
valid_sources[0x64]	87180	1		T2	11		T3	10		T27	18
valid_sources[0x65]	86297	1		T2	15		T3	18		T27	5
valid_sources[0x66]	83240	1		T2	11		T3	16		T27	10
valid_sources[0x67]	86829	1		T2	17		T3	18		T27	22
valid_sources[0x68]	80947	1		T2	19		T3	12		T27	32
valid_sources[0x69]	94762	1		T2	12		T3	29		T27	8
valid_sources[0x6a]	78473	1		T2	14		T3	10		T27	9
valid_sources[0x6b]	82695	1		T2	15		T3	17		T27	18
valid_sources[0x6c]	277157	1		T2	13		T3	26		T27	32
valid_sources[0x6d]	81235	1		T2	18		T3	13		T27	20
valid_sources[0x6e]	201757	1		T2	12		T3	19		T27	12
valid_sources[0x6f]	84033	1		T2	13		T3	21		T27	22
valid_sources[0x70]	84370	1		T2	13		T3	15		T27	24
valid_sources[0x71]	118836	1		T2	17		T3	18		T27	14
valid_sources[0x72]	97360	1		T2	10		T3	16		T27	7
valid_sources[0x73]	123461	1		T2	10		T3	10		T27	13
valid_sources[0x74]	91404	1		T2	13		T3	15		T27	4
valid_sources[0x75]	87526	1		T2	22		T3	11		T27	14
valid_sources[0x76]	79439	1		T2	15		T3	13		T27	11
valid_sources[0x77]	120943	1		T2	23		T3	6		T27	3
valid_sources[0x78]	79688	1		T2	15		T3	23		T27	18
valid_sources[0x79]	86281	1		T2	17		T3	8		T27	13
valid_sources[0x7a]	83520	1		T2	15		T3	15		T27	17
valid_sources[0x7b]	86548	1		T2	19		T3	18		T27	16
valid_sources[0x7c]	82452	1		T2	11		T3	15		T27	14
valid_sources[0x7d]	86850	1		T2	14		T3	19		T27	9
valid_sources[0x7e]	92121	1		T2	14		T3	11		T27	15
valid_sources[0x7f]	87933	1		T2	23		T3	19		T27	15
valid_sources[0x80]	81883	1		T2	18		T3	10		T27	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9172595

1

T1

11

T3

1

T25

2

values[0x0]

all_enables

biggest_size

152202

1

T1

1

T2

4

T3

3

values[0x1]

all_enables

biggest_size

140958

1

T1

2

T2

1

T3

1