Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16102522	1		T1	3701		T2	3702		T3	3566
full_word	9466740	1		T1	14		T2	5		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	25568952	1		T1	3715		T2	3707		T3	3571
auto[TlIntgErrCmd]	94	1		T186	4		T187	6		T209	2
auto[TlIntgErrData]	115	1		T186	3		T187	8		T209	5
auto[TlIntgErrBoth]	101	1		T186	3		T187	6		T209	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25180754	1		T1	3706		T2	3698		T3	3560
auto[1]	388508	1		T1	9		T2	9		T3	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16007830	1		T1	3695		T2	3698		T3	3559
auto[TlIntgErrNone]	partial	auto[1]	94400	1		T1	6		T2	4		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	9172772	1		T1	11		T3	1		T25	2
auto[TlIntgErrNone]	full_word	auto[1]	293950	1		T1	3		T2	5		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T186	1		T187	3		T280	4
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T186	2		T187	3		T209	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T186	1		T287	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T281	2		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	63	1		T186	1		T187	5		T209	4
auto[TlIntgErrData]	partial	auto[1]	47	1		T186	1		T187	3		T209	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T186	1		T287	1		T288	1
auto[TlIntgErrData]	full_word	auto[1]	1	1		T287	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T187	4		T209	1		T280	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T186	3		T187	2		T209	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T280	2		T289	1		T281	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T209	1		T280	2		T290	1