Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1109872969	11568	0	0
ep_in_enable_rd_A	1109872969	3855	0	0
ep_out_enable_rd_A	1109872969	3897	0	0
in_iso_rd_A	1109872969	4059	0	0
intr_enable_rd_A	1109872969	5787	0	0
out_iso_rd_A	1109872969	3934	0	0
phy_config_rd_A	1109872969	2227	0	0
phy_pins_drive_rd_A	1109872969	2876	0	0
rxenable_setup_rd_A	1109872969	4118	0	0
set_nak_out_rd_A	1109872969	3958	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	11568	0	0
T185	4954	12	0	0
T186	13598	3	0	0
T187	37990	5	0	0
T205	15953	836	0	0
T206	4706	894	0	0
T209	56673	2	0	0
T210	6727	253	0	0
T211	7669	22	0	0
T214	5772	26	0	0
T220	4614	10	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	3855	0	0
T187	37990	358	0	0
T238	60325	239	0	0
T239	54750	226	0	0
T252	3766	3	0	0
T263	10039	12	0	0
T264	3186	52	0	0
T265	7318	44	0	0
T266	5650	7	0	0
T267	5317	5	0	0
T268	4487	47	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	3897	0	0
T187	37990	550	0	0
T238	60325	208	0	0
T239	54750	209	0	0
T252	3766	5	0	0
T263	10039	46	0	0
T264	3186	40	0	0
T265	7318	14	0	0
T266	5650	7	0	0
T268	4487	43	0	0
T269	9112	9	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	4059	0	0
T187	37990	558	0	0
T238	60325	227	0	0
T239	54750	234	0	0
T263	10039	64	0	0
T264	3186	9	0	0
T265	7318	52	0	0
T266	5650	9	0	0
T267	5317	2	0	0
T268	4487	7	0	0
T269	9112	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	5787	0	0
T91	5927	3	0	0
T92	1826	9	0	0
T93	2802	4	0	0
T187	37990	750	0	0
T190	2116	9	0	0
T238	60325	231	0	0
T252	3766	18	0	0
T270	2292	11	0	0
T271	4172	13	0	0
T272	2818	16	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	3934	0	0
T187	37990	334	0	0
T205	15953	8	0	0
T238	60325	223	0	0
T239	54750	226	0	0
T263	10039	76	0	0
T264	3186	49	0	0
T265	7318	28	0	0
T266	5650	38	0	0
T267	5317	4	0	0
T268	4487	64	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	2227	0	0
T187	37990	229	0	0
T213	8939	5	0	0
T238	60325	236	0	0
T239	54750	248	0	0
T252	3766	14	0	0
T263	10039	14	0	0
T264	3186	37	0	0
T265	7318	2	0	0
T266	5650	19	0	0
T267	5317	2	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	2876	0	0
T187	37990	318	0	0
T238	60325	201	0	0
T239	54750	215	0	0
T252	3766	10	0	0
T263	10039	8	0	0
T264	3186	5	0	0
T265	7318	31	0	0
T266	5650	40	0	0
T267	5317	20	0	0
T268	4487	33	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	4118	0	0
T187	37990	525	0	0
T210	6727	3	0	0
T238	60325	201	0	0
T239	54750	215	0	0
T252	3766	16	0	0
T263	10039	64	0	0
T264	3186	5	0	0
T265	7318	15	0	0
T266	5650	9	0	0
T267	5317	10	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1109872969	3958	0	0
T187	37990	560	0	0
T238	60325	222	0	0
T239	54750	211	0	0
T252	3766	19	0	0
T263	10039	49	0	0
T264	3186	5	0	0
T265	7318	20	0	0
T266	5650	14	0	0
T267	5317	9	0	0
T268	4487	44	0	0