Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18570039	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	11932074	1		T1	5		T2	5		T3	72136

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30117284	1		T1	3471		T2	3558		T3	147156
values[0x0]	192146	1		T1	5		T2	8		T3	218
values[0x1]	192683	1		T1	4		T2	2		T3	201

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14485341	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	16016772	1		T1	877		T2	882		T3	87485

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	92426	1		T1	10		T2	15		T3	562
valid_sources[0x01]	89099	1		T1	16		T2	20		T3	577
valid_sources[0x02]	91697	1		T1	19		T2	9		T3	570
valid_sources[0x03]	90304	1		T1	9		T2	19		T3	557
valid_sources[0x04]	89065	1		T1	14		T2	10		T3	608
valid_sources[0x05]	95642	1		T1	21		T2	10		T3	613
valid_sources[0x06]	91061	1		T1	6		T2	8		T3	622
valid_sources[0x07]	92919	1		T1	9		T2	14		T3	591
valid_sources[0x08]	99361	1		T1	10		T2	17		T3	536
valid_sources[0x09]	91654	1		T1	17		T2	8		T3	541
valid_sources[0x0a]	90845	1		T1	16		T2	16		T3	542
valid_sources[0x0b]	112302	1		T1	11		T2	7		T3	617
valid_sources[0x0c]	90604	1		T1	11		T2	14		T3	571
valid_sources[0x0d]	93502	1		T1	14		T2	17		T3	576
valid_sources[0x0e]	182317	1		T1	13		T2	20		T3	595
valid_sources[0x0f]	94810	1		T1	15		T2	16		T3	561
valid_sources[0x10]	102765	1		T1	13		T2	12		T3	574
valid_sources[0x11]	89323	1		T1	14		T2	25		T3	573
valid_sources[0x12]	102196	1		T1	22		T2	13		T3	586
valid_sources[0x13]	95788	1		T1	13		T2	9		T3	535
valid_sources[0x14]	91393	1		T1	19		T2	18		T3	606
valid_sources[0x15]	92629	1		T1	17		T2	12		T3	562
valid_sources[0x16]	93819	1		T1	9		T2	8		T3	579
valid_sources[0x17]	96057	1		T1	17		T2	19		T3	600
valid_sources[0x18]	86359	1		T1	13		T2	28		T3	557
valid_sources[0x19]	103814	1		T1	16		T2	19		T3	539
valid_sources[0x1a]	98998	1		T1	11		T2	14		T3	584
valid_sources[0x1b]	96291	1		T1	12		T2	13		T3	560
valid_sources[0x1c]	95669	1		T1	11		T2	18		T3	569
valid_sources[0x1d]	97185	1		T1	11		T2	18		T3	550
valid_sources[0x1e]	101928	1		T1	13		T2	22		T3	579
valid_sources[0x1f]	191374	1		T1	13		T2	17		T3	597
valid_sources[0x20]	92304	1		T1	16		T2	15		T3	617
valid_sources[0x21]	125263	1		T1	20		T2	16		T3	571
valid_sources[0x22]	88575	1		T1	14		T2	6		T3	602
valid_sources[0x23]	91864	1		T1	18		T2	15		T3	604
valid_sources[0x24]	95021	1		T1	14		T2	13		T3	571
valid_sources[0x25]	91311	1		T1	11		T2	6		T3	614
valid_sources[0x26]	99694	1		T1	13		T2	10		T3	626
valid_sources[0x27]	95227	1		T1	11		T2	13		T3	589
valid_sources[0x28]	89516	1		T1	12		T2	23		T3	589
valid_sources[0x29]	90075	1		T1	18		T2	11		T3	587
valid_sources[0x2a]	88518	1		T1	18		T2	8		T3	617
valid_sources[0x2b]	86817	1		T1	17		T2	9		T3	554
valid_sources[0x2c]	99237	1		T1	18		T2	19		T3	565
valid_sources[0x2d]	93878	1		T1	11		T2	22		T3	526
valid_sources[0x2e]	92617	1		T1	12		T2	8		T3	584
valid_sources[0x2f]	96371	1		T1	11		T2	10		T3	591
valid_sources[0x30]	100369	1		T1	21		T2	10		T3	562
valid_sources[0x31]	96241	1		T1	17		T2	15		T3	565
valid_sources[0x32]	119923	1		T1	12		T2	11		T3	603
valid_sources[0x33]	95297	1		T1	16		T2	19		T3	563
valid_sources[0x34]	98973	1		T1	19		T2	12		T3	576
valid_sources[0x35]	92969	1		T1	13		T2	16		T3	545
valid_sources[0x36]	88298	1		T1	12		T2	14		T3	603
valid_sources[0x37]	88458	1		T1	14		T2	17		T3	610
valid_sources[0x38]	91379	1		T1	9		T2	16		T3	579
valid_sources[0x39]	88164	1		T1	15		T2	29		T3	582
valid_sources[0x3a]	91589	1		T1	9		T2	14		T3	602
valid_sources[0x3b]	96197	1		T1	10		T2	25		T3	555
valid_sources[0x3c]	91716	1		T1	11		T2	16		T3	570
valid_sources[0x3d]	97651	1		T1	13		T2	13		T3	574
valid_sources[0x3e]	99709	1		T1	8		T2	14		T3	556
valid_sources[0x3f]	86677	1		T1	12		T2	16		T3	615
valid_sources[0x40]	95460	1		T1	5		T2	16		T3	549
valid_sources[0x41]	93694	1		T1	17		T2	7		T3	576
valid_sources[0x42]	91399	1		T1	12		T2	10		T3	546
valid_sources[0x43]	91487	1		T1	8		T2	9		T3	569
valid_sources[0x44]	92405	1		T1	13		T2	13		T3	604
valid_sources[0x45]	220378	1		T1	11		T2	12		T3	590
valid_sources[0x46]	101733	1		T1	9		T2	15		T3	567
valid_sources[0x47]	123940	1		T1	20		T2	8		T3	564
valid_sources[0x48]	95080	1		T1	20		T2	14		T3	572
valid_sources[0x49]	91570	1		T1	15		T2	10		T3	585
valid_sources[0x4a]	95023	1		T1	6		T2	19		T3	566
valid_sources[0x4b]	90065	1		T1	12		T2	5		T3	601
valid_sources[0x4c]	184193	1		T1	12		T2	16		T3	571
valid_sources[0x4d]	94408	1		T1	14		T2	15		T3	577
valid_sources[0x4e]	96885	1		T1	16		T2	14		T3	542
valid_sources[0x4f]	344842	1		T1	16		T2	16		T3	615
valid_sources[0x50]	89300	1		T1	11		T2	16		T3	592
valid_sources[0x51]	255769	1		T1	10		T2	17		T3	554
valid_sources[0x52]	210996	1		T1	10		T2	22		T3	579
valid_sources[0x53]	194098	1		T1	21		T2	15		T3	587
valid_sources[0x54]	94328	1		T1	14		T2	17		T3	579
valid_sources[0x55]	94683	1		T1	15		T2	21		T3	557
valid_sources[0x56]	88896	1		T1	9		T2	7		T3	572
valid_sources[0x57]	94530	1		T1	17		T2	5		T3	600
valid_sources[0x58]	88475	1		T1	18		T2	9		T3	590
valid_sources[0x59]	95801	1		T1	6		T2	17		T3	592
valid_sources[0x5a]	89975	1		T1	8		T2	6		T3	592
valid_sources[0x5b]	94760	1		T1	16		T2	18		T3	623
valid_sources[0x5c]	104122	1		T1	16		T2	13		T3	613
valid_sources[0x5d]	101113	1		T1	14		T2	11		T3	585
valid_sources[0x5e]	97959	1		T1	14		T2	12		T3	572
valid_sources[0x5f]	88010	1		T1	9		T2	12		T3	575
valid_sources[0x60]	538626	1		T1	14		T2	16		T3	568
valid_sources[0x61]	104083	1		T1	16		T2	22		T3	597
valid_sources[0x62]	89172	1		T1	16		T2	12		T3	581
valid_sources[0x63]	134786	1		T1	14		T2	8		T3	594
valid_sources[0x64]	99981	1		T1	5		T2	14		T3	571
valid_sources[0x65]	91114	1		T1	11		T2	19		T3	573
valid_sources[0x66]	88940	1		T1	14		T2	11		T3	608
valid_sources[0x67]	103209	1		T1	14		T2	18		T3	560
valid_sources[0x68]	92280	1		T1	16		T2	13		T3	567
valid_sources[0x69]	90967	1		T1	15		T2	13		T3	568
valid_sources[0x6a]	96520	1		T1	12		T2	8		T3	552
valid_sources[0x6b]	98824	1		T1	21		T2	9		T3	555
valid_sources[0x6c]	231223	1		T1	12		T2	11		T3	547
valid_sources[0x6d]	90795	1		T1	9		T2	5		T3	570
valid_sources[0x6e]	92229	1		T1	22		T2	6		T3	569
valid_sources[0x6f]	99394	1		T1	9		T2	17		T3	551
valid_sources[0x70]	95679	1		T1	11		T2	15		T3	595
valid_sources[0x71]	99076	1		T1	5		T2	16		T3	589
valid_sources[0x72]	88465	1		T1	17		T2	14		T3	569
valid_sources[0x73]	96614	1		T1	8		T2	11		T3	535
valid_sources[0x74]	95459	1		T1	15		T2	20		T3	618
valid_sources[0x75]	93102	1		T1	14		T2	21		T3	579
valid_sources[0x76]	362564	1		T1	14		T2	14		T3	612
valid_sources[0x77]	91260	1		T1	17		T2	13		T3	553
valid_sources[0x78]	98895	1		T1	15		T2	9		T3	577
valid_sources[0x79]	99885	1		T1	17		T2	14		T3	557
valid_sources[0x7a]	95022	1		T1	11		T2	12		T3	588
valid_sources[0x7b]	214994	1		T1	19		T2	10		T3	536
valid_sources[0x7c]	93623	1		T1	11		T2	6		T3	543
valid_sources[0x7d]	91802	1		T1	14		T2	15		T3	595
valid_sources[0x7e]	94035	1		T1	13		T2	11		T3	553
valid_sources[0x7f]	95646	1		T1	18		T2	6		T3	545
valid_sources[0x80]	91938	1		T1	14		T2	6		T3	581

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11631781

1

T1

1

T2

1

T3

71834

values[0x0]

all_enables

biggest_size

155802

1

T1

3

T2

4

T3

155

values[0x1]

all_enables

biggest_size

144491

1

T1

1

T3

147

T4

258