Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18585105	1		T1	3475		T2	3563		T3	75439
full_word	11933321	1		T1	5		T2	5		T3	72136

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30518076	1		T1	3480		T2	3568		T3	147575
auto[TlIntgErrCmd]	104	1		T217	7		T218	6		T219	5
auto[TlIntgErrData]	131	1		T217	9		T218	6		T219	8
auto[TlIntgErrBoth]	115	1		T217	4		T218	8		T219	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30119355	1		T1	3471		T2	3558		T3	147156
auto[1]	399071	1		T1	9		T2	10		T3	419

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18487203	1		T1	3470		T2	3557		T3	75322
auto[TlIntgErrNone]	partial	auto[1]	97587	1		T1	5		T2	6		T3	117
auto[TlIntgErrNone]	full_word	auto[0]	11631995	1		T1	1		T2	1		T3	71834
auto[TlIntgErrNone]	full_word	auto[1]	301291	1		T1	4		T2	4		T3	302
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T217	3		T218	2		T219	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T217	4		T218	4		T219	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T233	1		T298	1		T299	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T219	1		T300	1		T275	1
auto[TlIntgErrData]	partial	auto[0]	58	1		T217	5		T218	1		T219	4
auto[TlIntgErrData]	partial	auto[1]	57	1		T217	3		T218	4		T219	4
auto[TlIntgErrData]	full_word	auto[0]	8	1		T300	2		T301	1		T275	2
auto[TlIntgErrData]	full_word	auto[1]	8	1		T217	1		T218	1		T235	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T217	3		T218	2		T219	2
auto[TlIntgErrBoth]	partial	auto[1]	63	1		T217	1		T218	6		T219	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T233	1		T300	1		T298	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T276	1		T296	1		T299	1