Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1116281783	12696	0	0
ep_in_enable_rd_A	1116281783	4210	0	0
ep_out_enable_rd_A	1116281783	4279	0	0
in_iso_rd_A	1116281783	4312	0	0
intr_enable_rd_A	1116281783	5965	0	0
out_iso_rd_A	1116281783	4515	0	0
phy_config_rd_A	1116281783	2586	0	0
phy_pins_drive_rd_A	1116281783	3517	0	0
rxenable_setup_rd_A	1116281783	4279	0	0
set_nak_out_rd_A	1116281783	4168	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	12696	0	0
T193	8136	17	0	0
T194	8944	743	0	0
T195	5738	890	0	0
T210	9546	464	0	0
T214	4786	14	0	0
T217	24503	4	0	0
T218	21853	4	0	0
T219	42870	7	0	0
T226	3211	10	0	0
T230	4339	19	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	4210	0	0
T193	8136	68	0	0
T197	11737	82	0	0
T219	42870	521	0	0
T247	4227	8	0	0
T248	6332	107	0	0
T251	39042	244	0	0
T260	6524	12	0	0
T265	5410	6	0	0
T275	39446	405	0	0
T276	69299	466	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	4279	0	0
T193	8136	51	0	0
T197	11737	7	0	0
T219	42870	493	0	0
T247	4227	40	0	0
T248	6332	10	0	0
T251	39042	191	0	0
T260	6524	44	0	0
T265	5410	25	0	0
T275	39446	534	0	0
T276	69299	525	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	4312	0	0
T193	8136	100	0	0
T197	11737	25	0	0
T219	42870	514	0	0
T247	4227	38	0	0
T248	6332	48	0	0
T251	39042	199	0	0
T260	6524	22	0	0
T265	5410	24	0	0
T275	39446	482	0	0
T276	69299	392	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	5965	0	0
T104	1831	17	0	0
T193	8136	162	0	0
T197	11737	40	0	0
T247	4227	81	0	0
T260	6524	5	0	0
T265	5410	14	0	0
T277	5100	24	0	0
T278	2999	4	0	0
T279	5509	17	0	0
T280	3228	18	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	4515	0	0
T193	8136	70	0	0
T197	11737	29	0	0
T219	42870	521	0	0
T247	4227	42	0	0
T248	6332	82	0	0
T251	39042	236	0	0
T260	6524	29	0	0
T265	5410	39	0	0
T275	39446	421	0	0
T276	69299	394	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	2586	0	0
T193	8136	16	0	0
T197	11737	32	0	0
T219	42870	277	0	0
T247	4227	31	0	0
T248	6332	26	0	0
T251	39042	217	0	0
T260	6524	16	0	0
T265	5410	40	0	0
T275	39446	287	0	0
T276	69299	209	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	3517	0	0
T193	8136	41	0	0
T197	11737	13	0	0
T219	42870	377	0	0
T247	4227	14	0	0
T248	6332	1	0	0
T251	39042	206	0	0
T260	6524	21	0	0
T265	5410	11	0	0
T275	39446	398	0	0
T276	69299	310	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	4279	0	0
T193	8136	108	0	0
T197	11737	45	0	0
T219	42870	364	0	0
T225	11431	46	0	0
T247	4227	5	0	0
T248	6332	66	0	0
T251	39042	166	0	0
T265	5410	21	0	0
T275	39446	494	0	0
T276	69299	493	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1116281783	4168	0	0
T193	8136	45	0	0
T197	11737	30	0	0
T219	42870	658	0	0
T247	4227	51	0	0
T248	6332	105	0	0
T251	39042	262	0	0
T260	6524	9	0	0
T265	5410	3	0	0
T275	39446	460	0	0
T276	69299	511	0	0