Module Definition
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Module : usb_fs_nb_out_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 93.65 82.84 87.50 90.57 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe 90.91 93.65 82.84 87.50 90.57 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 93.65 82.84 87.50 90.57 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 93.65 82.84 87.50 90.57 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12611893.65
CONT_ASSIGN9011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17811100.00
ALWAYS18466100.00
ALWAYS19644100.00
ALWAYS212544685.19
CONT_ASSIGN32511100.00
ALWAYS32833100.00
ALWAYS33633100.00
ALWAYS34577100.00
CONT_ASSIGN35911100.00
ALWAYS36255100.00
ALWAYS37299100.00
ALWAYS38933100.00
ALWAYS40166100.00
CONT_ASSIGN41711100.00
ALWAYS42066100.00
CONT_ASSIGN43411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
131 1 1
132 1 1
134 1 1
140 1 1
144 1 1
148 1 1
152 1 1
157 1 1
163 1 1
164 1 1
171 1 1
172 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
188 1 1
189 1 1
190 1 1
MISSING_ELSE
196 1 1
197 1 1
199 1 1
200 1 1
MISSING_ELSE
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
225 1 1
226 1 1
227 1 1
229 1 1
237 1 1
239 1 1
240 1 1
241 1 1
242 0 1
244 1 1
249 1 1
253 1 1
254 1 1
257 0 1
258 0 1
259 0 1
260 0 1
261 1 1
263 1 1
264 1 1
265 1 1
266 1 1
268 1 1
273 1 1
274 1 1
276 1 1
278 1 1
280 0 1
281 0 1
283 1 1
284 1 1
285 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
295 1 1
296 1 1
297 1 1
304 1 1
306 1 1
308 0 1
311 1 1
312 1 1
325 1 1
328 1 1
329 1 1
331 1 1
336 1 1
337 1 1
339 1 1
345 1 1
347 1 1
348 1 1
349 1 1
350 1 1
MISSING_ELSE
353 1 1
354 1 1
MISSING_ELSE
359 1 1
362 1 1
363 1 1
364 1 1
365 1 1
367 1 1
372 1 1
373 1 1
374 1 1
375 1 1
377 1 1
378 1 1
379 1 1
380 1 1
382 1 1
389 1 1
390 1 1
392 1 1
401 1 1
402 1 1
404 1 1
405 1 1
406 1 1
407 1 1
MISSING_ELSE
417 1 1
420 1 1
421 1 1
423 1 1
424 1 1
425 1 1
426 1 1
MISSING_ELSE
434 1 1


Cond Coverage for Module : usb_fs_nb_out_pe
TotalCoveredPercent
Conditions13411182.84
Logical13411182.84
Non-Logical00
Event00

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT2,T3,T4
1011CoveredT63,T64,T65
1101CoveredT2,T3,T4
1110CoveredT1,T45,T46
1111CoveredT2,T3,T4

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT3,T4,T31
11CoveredT2,T3,T4

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT32,T66,T52
10CoveredT2,T3,T4
11CoveredT66,T52,T67

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT32,T66,T52

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT21,T63,T64

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101CoveredT21,T61,T62
110CoveredT1,T2,T3
111CoveredT2,T3,T4

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT63,T64,T65
110CoveredT2,T3,T4
111CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T3,T4

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT45,T47,T71
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT82,T83,T84
11CoveredT2,T3,T4

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT2,T3,T4
101Not Covered
110CoveredT2,T3,T4
111Not Covered

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11CoveredT66,T52,T67

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11CoveredT2,T3,T4

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT66,T52,T67
10CoveredT2,T3,T4

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T5,T36
10CoveredT54,T75,T85
11CoveredT66,T52,T67

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T4
110CoveredT86,T87,T88
111CoveredT86,T87,T88

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10CoveredT21,T61,T62

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT66,T52,T67
01Not Covered
10Not Covered

 LINE       291
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT2,T3,T4
01Not Covered
10Not Covered

 LINE       306
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT86,T87,T88
01Not Covered
10Not Covered

 LINE       339
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       347
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11CoveredT66,T52,T67

 LINE       392
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01CoveredT54,T75,T85
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       392
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       404
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT2,T3,T4
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       404
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT2,T3,T4
1CoveredT1,T2,T3

 LINE       404
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       406
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT2,T56,T57
10CoveredT2,T3,T4
11CoveredT2,T56,T57

 LINE       417
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT2,T56,T57
101CoveredT3,T4,T28
110CoveredT1,T2,T3
111CoveredT2,T3,T4

 LINE       423
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       425
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       425
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       434
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110CoveredT2,T3,T4
1111Not Covered

 LINE       434
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       434
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------
-1--2-StatusTests
00CoveredT86,T87,T88
01CoveredT1,T2,T3
10Not Covered

FSM Coverage for Module : usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 7 87.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
statesLine No.CoveredTests
StIdle 339 Covered T1,T2,T3
StRcvdDataEnd 266 Covered T2,T3,T4
StRcvdDataStart 240 Covered T2,T3,T4
StRcvdIsoDataEnd 253 Covered T86,T87,T88
StRcvdOut 226 Covered T2,T3,T4


transitionsLine No.CoveredTests
StIdle->StRcvdOut 226 Covered T2,T3,T4
StRcvdDataEnd->StIdle 339 Covered T2,T3,T4
StRcvdDataStart->StIdle 339 Covered T21,T61,T62
StRcvdDataStart->StRcvdDataEnd 266 Covered T2,T3,T4
StRcvdDataStart->StRcvdIsoDataEnd 253 Covered T86,T87,T88
StRcvdIsoDataEnd->StIdle 339 Covered T86,T87,T88
StRcvdOut->StIdle 339 Not Covered
StRcvdOut->StRcvdDataStart 240 Covered T2,T3,T4



Branch Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 53 48 90.57
TERNARY 164 2 2 100.00
IF 184 4 4 100.00
IF 196 3 3 100.00
CASE 221 18 13 72.22
IF 328 2 2 100.00
IF 336 3 3 100.00
IF 347 3 3 100.00
IF 353 2 2 100.00
IF 362 3 3 100.00
IF 372 3 3 100.00
IF 389 2 2 100.00
IF 401 4 4 100.00
IF 420 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T45,T47,T71


LineNo. Expression -1-: 184 if ((!rst_ni)) -2-: 187 if ((setup_token_received && ep_active)) -3-: 189 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T66,T52,T67
0 0 1 Covered T2,T3,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 199 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 case (out_xact_state) -2-: 225 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 239 if (rx_pkt_start_i) -4-: 241 if ((timeout_cntdown_q == '0)) -5-: 249 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 254 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 261 if ((invalid_packet_received || non_data_packet_received)) -8-: 265 if (data_packet_received) -9-: 276 if (current_xact_setup_q) -10-: 278 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 289 if (out_ep_stall_i[out_ep_index]) -12-: 291 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 306 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
StIdle 1 - - - - - - - - - - - Covered T2,T3,T4
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T2,T3,T4
StRcvdOut - 0 1 - - - - - - - - - Not Covered
StRcvdOut - 0 0 - - - - - - - - - Covered T2,T3,T4
StRcvdDataStart - - - 1 - - - - - - - - Covered T86,T87,T88
StRcvdDataStart - - - 0 1 - - - - - - - Not Covered
StRcvdDataStart - - - 0 0 1 - - - - - - Covered T21,T61,T62
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T2,T3,T4
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T2,T3,T4
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T66,T52,T67
StRcvdDataEnd - - - - - - - 0 - 1 - - Covered T29,T33,T34
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T2,T56,T57
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T2,T3,T4
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Covered T86,T87,T88
default - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 328 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 336 if ((!rst_ni)) -2-: 339 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 347 if ((setup_token_received && ep_active)) -2-: 349 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T66,T52,T67
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 353 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T19,T69,T70
0 Covered T1,T2,T3


LineNo. Expression -1-: 362 if ((!rst_ni)) -2-: 364 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 372 if ((!rst_ni)) -2-: 377 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 389 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 401 if ((!rst_ni)) -2-: 404 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 406 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T2,T56,T57
0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 420 if ((!rst_ni)) -2-: 423 if ((out_xact_state == StRcvdOut)) -3-: 425 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T2,T3,T4
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 1114300943 1114148135 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1114300943 1114148135 0 0
T1 482964 482880 0 0
T2 485619 485559 0 0
T3 773326 773276 0 0
T4 241187 241181 0 0
T28 484099 484022 0 0
T29 483740 483670 0 0
T30 484275 484194 0 0
T31 481757 481662 0 0
T32 483643 483580 0 0
T33 484900 484804 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%