Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17496480	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	10846919	1		T1	8		T2	8		T3	18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27973967	1		T1	3558		T2	3559		T3	3490
values[0x0]	184220	1		T1	5		T2	5		T3	4
values[0x1]	185212	1		T1	6		T2	6		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13627001	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	14716398	1		T1	885		T2	860		T3	884

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96779	1		T1	16		T3	21		T34	17
valid_sources[0x01]	95555	1		T1	18		T3	10		T34	15
valid_sources[0x02]	94795	1		T1	14		T3	8		T34	15
valid_sources[0x03]	107422	1		T1	16		T3	16		T34	14
valid_sources[0x04]	88452	1		T1	16		T3	9		T34	20
valid_sources[0x05]	91402	1		T1	9		T3	17		T34	19
valid_sources[0x06]	100835	1		T1	11		T3	14		T34	12
valid_sources[0x07]	102377	1		T1	14		T3	13		T34	16
valid_sources[0x08]	92104	1		T1	11		T3	14		T34	14
valid_sources[0x09]	97214	1		T1	16		T3	15		T34	16
valid_sources[0x0a]	100498	1		T1	9		T3	12		T34	13
valid_sources[0x0b]	100279	1		T1	21		T3	8		T34	10
valid_sources[0x0c]	88934	1		T1	16		T3	15		T34	18
valid_sources[0x0d]	96925	1		T1	12		T3	17		T34	13
valid_sources[0x0e]	308232	1		T1	15		T3	14		T34	11
valid_sources[0x0f]	89547	1		T1	15		T3	8		T34	27
valid_sources[0x10]	90061	1		T1	14		T3	11		T34	16
valid_sources[0x11]	91575	1		T1	10		T3	12		T34	21
valid_sources[0x12]	94530	1		T1	11		T3	12		T34	7
valid_sources[0x13]	94332	1		T1	13		T3	11		T34	18
valid_sources[0x14]	398405	1		T1	16		T3	10		T34	9
valid_sources[0x15]	97359	1		T1	10		T3	11		T34	19
valid_sources[0x16]	88133	1		T1	15		T3	13		T34	19
valid_sources[0x17]	132887	1		T1	15		T3	11		T34	16
valid_sources[0x18]	99321	1		T1	18		T3	8		T34	21
valid_sources[0x19]	195246	1		T1	15		T3	16		T34	17
valid_sources[0x1a]	100004	1		T1	9		T3	11		T34	9
valid_sources[0x1b]	97376	1		T1	21		T3	20		T34	15
valid_sources[0x1c]	89124	1		T1	8		T3	11		T34	17
valid_sources[0x1d]	92397	1		T1	12		T3	10		T34	14
valid_sources[0x1e]	94777	1		T1	12		T3	18		T34	15
valid_sources[0x1f]	92825	1		T1	19		T3	16		T34	6
valid_sources[0x20]	171872	1		T1	15		T3	16		T34	21
valid_sources[0x21]	99142	1		T1	24		T3	17		T34	10
valid_sources[0x22]	99431	1		T1	11		T3	13		T34	15
valid_sources[0x23]	91988	1		T1	18		T3	10		T34	13
valid_sources[0x24]	96461	1		T1	13		T3	12		T34	10
valid_sources[0x25]	96325	1		T1	11		T3	9		T34	17
valid_sources[0x26]	91810	1		T1	13		T3	7		T34	8
valid_sources[0x27]	96168	1		T1	17		T3	17		T34	5
valid_sources[0x28]	92595	1		T1	8		T3	14		T34	17
valid_sources[0x29]	95302	1		T1	9		T3	18		T34	18
valid_sources[0x2a]	92732	1		T1	13		T3	16		T34	18
valid_sources[0x2b]	88096	1		T1	8		T3	11		T34	21
valid_sources[0x2c]	92840	1		T1	20		T3	20		T34	25
valid_sources[0x2d]	166887	1		T1	10		T3	4		T34	9
valid_sources[0x2e]	95664	1		T1	19		T3	9		T34	19
valid_sources[0x2f]	148589	1		T1	14		T3	7		T34	19
valid_sources[0x30]	99055	1		T1	10		T3	11		T34	12
valid_sources[0x31]	96351	1		T1	12		T3	16		T34	7
valid_sources[0x32]	99870	1		T1	15		T3	12		T34	6
valid_sources[0x33]	97283	1		T1	10		T3	25		T34	17
valid_sources[0x34]	96524	1		T1	9		T3	18		T34	12
valid_sources[0x35]	103922	1		T1	14		T3	14		T34	17
valid_sources[0x36]	87893	1		T1	14		T3	14		T34	12
valid_sources[0x37]	96156	1		T1	10		T3	21		T34	8
valid_sources[0x38]	217543	1		T1	11		T3	10		T34	16
valid_sources[0x39]	95523	1		T1	14		T3	16		T34	11
valid_sources[0x3a]	98036	1		T1	10		T3	13		T34	11
valid_sources[0x3b]	92702	1		T1	15		T3	25		T34	11
valid_sources[0x3c]	93262	1		T1	15		T3	11		T34	12
valid_sources[0x3d]	89394	1		T1	11		T3	13		T34	6
valid_sources[0x3e]	96188	1		T1	13		T3	6		T34	11
valid_sources[0x3f]	91716	1		T1	12		T3	17		T34	8
valid_sources[0x40]	95753	1		T1	12		T3	12		T34	15
valid_sources[0x41]	187239	1		T1	20		T3	12		T34	13
valid_sources[0x42]	98999	1		T1	23		T3	13		T34	11
valid_sources[0x43]	96997	1		T1	13		T3	13		T34	5
valid_sources[0x44]	91703	1		T1	13		T3	18		T34	13
valid_sources[0x45]	89516	1		T1	14		T3	8		T34	16
valid_sources[0x46]	92064	1		T1	18		T3	14		T34	17
valid_sources[0x47]	88477	1		T1	17		T3	11		T34	13
valid_sources[0x48]	95846	1		T1	20		T3	24		T34	8
valid_sources[0x49]	96394	1		T1	15		T3	13		T34	13
valid_sources[0x4a]	95671	1		T1	10		T3	16		T34	14
valid_sources[0x4b]	94922	1		T1	20		T3	20		T34	8
valid_sources[0x4c]	95372	1		T1	13		T3	11		T34	10
valid_sources[0x4d]	98221	1		T1	19		T3	7		T34	15
valid_sources[0x4e]	102134	1		T1	16		T3	19		T34	20
valid_sources[0x4f]	100680	1		T1	16		T3	19		T34	19
valid_sources[0x50]	95532	1		T1	21		T3	10		T34	11
valid_sources[0x51]	91875	1		T1	13		T3	8		T34	9
valid_sources[0x52]	93754	1		T1	14		T3	15		T34	14
valid_sources[0x53]	99213	1		T1	17		T3	8		T34	16
valid_sources[0x54]	95317	1		T1	14		T3	12		T34	21
valid_sources[0x55]	97351	1		T1	12		T3	7		T34	9
valid_sources[0x56]	98471	1		T1	12		T3	7		T34	14
valid_sources[0x57]	92012	1		T1	15		T3	11		T34	8
valid_sources[0x58]	88586	1		T1	9		T3	13		T34	21
valid_sources[0x59]	99530	1		T1	12		T3	15		T34	12
valid_sources[0x5a]	92770	1		T1	14		T3	9		T34	11
valid_sources[0x5b]	91850	1		T1	12		T3	8		T34	19
valid_sources[0x5c]	94560	1		T1	12		T3	12		T34	18
valid_sources[0x5d]	96254	1		T1	18		T3	25		T34	14
valid_sources[0x5e]	99145	1		T1	14		T3	11		T34	12
valid_sources[0x5f]	95380	1		T1	12		T3	14		T34	9
valid_sources[0x60]	91815	1		T1	14		T3	16		T34	11
valid_sources[0x61]	95595	1		T1	15		T3	6		T34	16
valid_sources[0x62]	89339	1		T1	13		T3	13		T34	9
valid_sources[0x63]	91946	1		T1	21		T3	14		T34	20
valid_sources[0x64]	107293	1		T1	13		T2	3570		T3	9
valid_sources[0x65]	95983	1		T1	16		T3	5		T34	8
valid_sources[0x66]	92991	1		T1	19		T3	10		T34	14
valid_sources[0x67]	100614	1		T1	17		T3	11		T34	19
valid_sources[0x68]	88529	1		T1	22		T3	14		T34	8
valid_sources[0x69]	100847	1		T1	13		T3	20		T28	3707
valid_sources[0x6a]	89562	1		T1	10		T3	14		T34	12
valid_sources[0x6b]	97266	1		T1	17		T3	8		T34	31
valid_sources[0x6c]	104089	1		T1	21		T3	19		T34	5
valid_sources[0x6d]	152879	1		T1	14		T3	12		T34	22
valid_sources[0x6e]	94889	1		T1	12		T3	11		T34	13
valid_sources[0x6f]	93455	1		T1	13		T3	12		T34	13
valid_sources[0x70]	99737	1		T1	15		T3	20		T34	18
valid_sources[0x71]	95598	1		T1	13		T3	8		T34	7
valid_sources[0x72]	90034	1		T1	19		T3	7		T34	8
valid_sources[0x73]	92743	1		T1	17		T3	13		T34	14
valid_sources[0x74]	96196	1		T1	13		T3	17		T34	12
valid_sources[0x75]	96575	1		T1	18		T3	18		T34	10
valid_sources[0x76]	103038	1		T1	9		T3	12		T34	18
valid_sources[0x77]	101151	1		T1	21		T3	9		T34	13
valid_sources[0x78]	89078	1		T1	13		T3	4		T34	20
valid_sources[0x79]	93646	1		T1	15		T3	10		T34	17
valid_sources[0x7a]	99184	1		T1	8		T3	19		T34	11
valid_sources[0x7b]	99454	1		T1	10		T3	38		T34	11
valid_sources[0x7c]	165579	1		T1	15		T3	11		T34	19
valid_sources[0x7d]	92296	1		T1	12		T3	24		T34	10
valid_sources[0x7e]	92752	1		T1	9		T3	9		T34	13
valid_sources[0x7f]	107849	1		T1	13		T3	9		T34	11
valid_sources[0x80]	95555	1		T1	10		T3	21		T34	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10558096

1

T1

2

T2

2

T3

14

values[0x0]

all_enables

biggest_size

149764

1

T1

3

T2

2

T3

4

values[0x1]

all_enables

biggest_size

139059

1

T1

3

T2

4

T28

2