Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17512780	1		T1	3561		T2	3562		T3	3479
full_word	10848016	1		T1	8		T2	8		T3	18

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28360486	1		T1	3569		T2	3570		T3	3497
auto[TlIntgErrCmd]	108	1		T190	2		T191	4		T192	8
auto[TlIntgErrData]	108	1		T190	5		T191	3		T192	9
auto[TlIntgErrBoth]	94	1		T190	3		T191	3		T192	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27976052	1		T1	3558		T2	3559		T3	3490
auto[1]	384744	1		T1	11		T2	11		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17417626	1		T1	3556		T2	3557		T3	3476
auto[TlIntgErrNone]	partial	auto[1]	94869	1		T1	5		T2	5		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	10558288	1		T1	2		T2	2		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	289703	1		T1	6		T2	6		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	47	1		T190	1		T191	3		T192	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T190	1		T191	1		T192	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T278	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T227	2		T279	1		T259	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T190	2		T191	1		T192	6
auto[TlIntgErrData]	partial	auto[1]	52	1		T190	3		T191	1		T192	2
auto[TlIntgErrData]	full_word	auto[0]	9	1		T227	3		T280	1		T279	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T191	1		T192	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T191	2		T229	4		T280	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T190	3		T191	1		T192	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T229	1		T282	1		T278	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T229	1		T278	1		T283	1