Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.53	79.85	95.41		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1110016068	13754	0	0
ep_in_enable_rd_A	1110016068	2239	0	0
ep_out_enable_rd_A	1110016068	2460	0	0
in_iso_rd_A	1110016068	2468	0	0
intr_enable_rd_A	1110016068	3190	0	0
out_iso_rd_A	1110016068	1931	0	0
phy_config_rd_A	1110016068	1495	0	0
phy_pins_drive_rd_A	1110016068	1610	0	0
rxenable_setup_rd_A	1110016068	2239	0	0
set_nak_out_rd_A	1110016068	1951	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	13754	0	0
T189	4692	819	0	0
T190	21057	3	0	0
T191	14760	1	0	0
T192	34535	6	0	0
T207	4505	732	0	0
T208	7270	1068	0	0
T218	5666	896	0	0
T223	7888	13	0	0
T224	4656	8	0	0
T230	12442	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	2239	0	0
T209	5869	15	0	0
T223	7888	101	0	0
T226	7110	65	0	0
T237	2852	19	0	0
T242	9835	82	0	0
T243	43958	228	0	0
T252	2624	2	0	0
T255	6810	48	0	0
T258	9496	27	0	0
T259	52701	182	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	2460	0	0
T209	5869	8	0	0
T223	7888	16	0	0
T226	7110	10	0	0
T237	2852	32	0	0
T238	4458	49	0	0
T242	9835	114	0	0
T243	43958	209	0	0
T245	2394	62	0	0
T252	2624	2	0	0
T255	6810	102	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	2468	0	0
T209	5869	17	0	0
T223	7888	91	0	0
T226	7110	59	0	0
T237	2852	30	0	0
T238	4458	2	0	0
T242	9835	106	0	0
T243	43958	208	0	0
T245	2394	1	0	0
T252	2624	5	0	0
T255	6810	103	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	3190	0	0
T92	4375	32	0	0
T93	3431	13	0	0
T193	1939	18	0	0
T209	5869	35	0	0
T223	7888	84	0	0
T237	2852	69	0	0
T238	4458	73	0	0
T252	2624	9	0	0
T255	6810	80	0	0
T260	4307	17	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	1931	0	0
T209	5869	8	0	0
T223	7888	31	0	0
T226	7110	47	0	0
T237	2852	2	0	0
T238	4458	4	0	0
T242	9835	89	0	0
T243	43958	226	0	0
T245	2394	4	0	0
T252	2624	57	0	0
T255	6810	14	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	1495	0	0
T209	5869	44	0	0
T223	7888	56	0	0
T237	2852	7	0	0
T238	4458	17	0	0
T242	9835	109	0	0
T243	43958	215	0	0
T245	2394	3	0	0
T246	3927	4	0	0
T252	2624	4	0	0
T255	6810	34	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	1610	0	0
T209	5869	10	0	0
T217	14000	4	0	0
T223	7888	47	0	0
T226	7110	60	0	0
T237	2852	5	0	0
T238	4458	3	0	0
T242	9835	93	0	0
T243	43958	215	0	0
T252	2624	5	0	0
T255	6810	76	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	2239	0	0
T209	5869	49	0	0
T217	14000	5	0	0
T223	7888	20	0	0
T226	7110	2	0	0
T237	2852	33	0	0
T238	4458	1	0	0
T242	9835	105	0	0
T243	43958	283	0	0
T252	2624	33	0	0
T255	6810	102	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1110016068	1951	0	0
T209	5869	46	0	0
T223	7888	38	0	0
T226	7110	4	0	0
T237	2852	1	0	0
T238	4458	2	0	0
T242	9835	92	0	0
T243	43958	213	0	0
T245	2394	54	0	0
T252	2624	3	0	0
T255	6810	53	0	0