Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10805076	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	11178151	1		T1	8		T2	8		T3	5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	21604321	1		T1	7		T2	3		T3	2
values[0x0]	188911	1		T1	5		T2	2		T3	6
values[0x1]	189995	1		T1	2		T2	7		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8623424	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	13359803	1		T1	9		T2	10		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	69175	1		T29	5		T4	510		T8	3
valid_sources[0x01]	69531	1		T29	44		T4	445		T8	2
valid_sources[0x02]	69151	1		T29	13		T37	3		T4	446
valid_sources[0x03]	68934	1		T29	27		T4	471		T17	5
valid_sources[0x04]	70784	1		T29	44		T36	1		T4	466
valid_sources[0x05]	69496	1		T29	44		T30	1		T4	454
valid_sources[0x06]	68398	1		T29	61		T4	423		T8	3
valid_sources[0x07]	69964	1		T29	20		T4	486		T8	1
valid_sources[0x08]	68962	1		T29	21		T4	475		T8	5
valid_sources[0x09]	69873	1		T29	19		T4	429		T8	2
valid_sources[0x0a]	69078	1		T29	40		T4	515		T22	1
valid_sources[0x0b]	68488	1		T29	38		T4	464		T8	3
valid_sources[0x0c]	68089	1		T29	63		T4	534		T8	6
valid_sources[0x0d]	70098	1		T29	34		T4	429		T8	2
valid_sources[0x0e]	69551	1		T29	36		T30	1		T4	527
valid_sources[0x0f]	68560	1		T35	2		T29	65		T4	409
valid_sources[0x10]	70448	1		T29	26		T4	500		T8	3
valid_sources[0x11]	68416	1		T29	38		T4	488		T8	3
valid_sources[0x12]	67582	1		T29	24		T4	467		T8	1
valid_sources[0x13]	69189	1		T29	25		T4	514		T5	1668
valid_sources[0x14]	70256	1		T29	32		T4	503		T8	1
valid_sources[0x15]	70786	1		T29	17		T4	479		T8	2
valid_sources[0x16]	69911	1		T29	60		T4	469		T8	5
valid_sources[0x17]	68019	1		T29	42		T31	1		T4	465
valid_sources[0x18]	69104	1		T29	55		T4	477		T8	3
valid_sources[0x19]	70549	1		T29	26		T4	493		T8	1
valid_sources[0x1a]	69687	1		T29	15		T4	448		T8	2
valid_sources[0x1b]	71317	1		T29	25		T4	466		T8	2
valid_sources[0x1c]	69285	1		T29	17		T30	1		T4	472
valid_sources[0x1d]	71101	1		T29	43		T4	465		T8	1
valid_sources[0x1e]	123911	1		T29	17		T4	471		T8	4
valid_sources[0x1f]	68866	1		T29	34		T4	431		T8	1
valid_sources[0x20]	68393	1		T29	46		T4	463		T8	2
valid_sources[0x21]	68160	1		T29	13		T4	501		T8	2
valid_sources[0x22]	69182	1		T29	12		T4	442		T8	3
valid_sources[0x23]	69635	1		T29	15		T4	427		T8	5
valid_sources[0x24]	146104	1		T29	27		T4	505		T8	3
valid_sources[0x25]	70063	1		T29	21		T4	508		T8	4
valid_sources[0x26]	68502	1		T29	33		T4	411		T8	4
valid_sources[0x27]	68219	1		T35	2		T29	24		T4	446
valid_sources[0x28]	70255	1		T29	22		T4	467		T8	4
valid_sources[0x29]	159735	1		T29	68		T4	552		T8	4
valid_sources[0x2a]	68595	1		T29	13		T4	471		T8	2
valid_sources[0x2b]	70579	1		T29	31		T4	508		T8	4
valid_sources[0x2c]	68803	1		T29	50		T4	474		T5	1668
valid_sources[0x2d]	68635	1		T29	65		T36	2		T4	476
valid_sources[0x2e]	69437	1		T29	23		T4	505		T8	1
valid_sources[0x2f]	68565	1		T29	46		T4	457		T8	2
valid_sources[0x30]	69471	1		T29	23		T4	572		T8	4
valid_sources[0x31]	69191	1		T29	25		T4	455		T21	1
valid_sources[0x32]	69318	1		T29	12		T4	461		T8	7
valid_sources[0x33]	69318	1		T29	28		T4	504		T8	1
valid_sources[0x34]	69054	1		T29	38		T4	464		T8	2
valid_sources[0x35]	275885	1		T29	33		T4	472		T8	2
valid_sources[0x36]	69523	1		T29	10		T4	482		T8	1
valid_sources[0x37]	68590	1		T29	22		T4	457		T8	4
valid_sources[0x38]	68754	1		T29	20		T31	2		T4	444
valid_sources[0x39]	68853	1		T29	26		T4	466		T8	1
valid_sources[0x3a]	184595	1		T29	21		T4	501		T8	2
valid_sources[0x3b]	68474	1		T29	37		T4	399		T8	1
valid_sources[0x3c]	68006	1		T29	25		T4	508		T8	3
valid_sources[0x3d]	68926	1		T29	67		T4	426		T8	3
valid_sources[0x3e]	67636	1		T29	10		T4	468		T8	1
valid_sources[0x3f]	182052	1		T29	52		T4	448		T8	1
valid_sources[0x40]	67283	1		T29	54		T4	418		T5	1656
valid_sources[0x41]	68609	1		T29	33		T4	578		T8	2
valid_sources[0x42]	70010	1		T29	88		T4	440		T8	6
valid_sources[0x43]	68702	1		T29	38		T4	465		T8	3
valid_sources[0x44]	68599	1		T29	23		T30	1		T4	483
valid_sources[0x45]	69038	1		T29	23		T4	555		T8	3
valid_sources[0x46]	68108	1		T29	17		T31	1		T4	454
valid_sources[0x47]	69304	1		T29	43		T4	490		T8	2
valid_sources[0x48]	69415	1		T29	20		T4	445		T8	1
valid_sources[0x49]	68815	1		T29	61		T4	545		T8	4
valid_sources[0x4a]	68338	1		T29	24		T4	520		T8	3
valid_sources[0x4b]	99112	1		T29	35		T37	1		T4	452
valid_sources[0x4c]	382226	1		T29	31		T4	451		T8	3
valid_sources[0x4d]	70497	1		T29	53		T4	464		T8	3
valid_sources[0x4e]	67886	1		T29	15		T4	430		T8	3
valid_sources[0x4f]	69552	1		T29	42		T4	473		T8	1
valid_sources[0x50]	67701	1		T35	3		T29	19		T4	516
valid_sources[0x51]	70025	1		T29	22		T4	414		T8	3
valid_sources[0x52]	68412	1		T29	37		T4	503		T8	3
valid_sources[0x53]	68294	1		T29	26		T4	471		T8	3
valid_sources[0x54]	68967	1		T29	9		T4	474		T8	4
valid_sources[0x55]	68369	1		T29	37		T4	526		T21	1
valid_sources[0x56]	70172	1		T29	45		T4	520		T8	1
valid_sources[0x57]	67519	1		T29	51		T4	433		T8	4
valid_sources[0x58]	172372	1		T29	22		T4	432		T21	1
valid_sources[0x59]	70383	1		T29	44		T37	1		T4	477
valid_sources[0x5a]	69442	1		T29	19		T4	432		T8	1
valid_sources[0x5b]	69303	1		T29	38		T4	582		T8	4
valid_sources[0x5c]	70320	1		T29	47		T37	1		T4	540
valid_sources[0x5d]	71879	1		T29	46		T4	439		T8	2
valid_sources[0x5e]	70174	1		T29	26		T4	481		T8	3
valid_sources[0x5f]	70746	1		T29	33		T4	489		T8	1
valid_sources[0x60]	67978	1		T29	7		T4	473		T8	4
valid_sources[0x61]	68012	1		T29	31		T4	383		T8	1
valid_sources[0x62]	67181	1		T29	45		T36	1		T31	5
valid_sources[0x63]	70063	1		T29	35		T4	339		T8	2
valid_sources[0x64]	70145	1		T29	17		T4	450		T5	1660
valid_sources[0x65]	68586	1		T29	40		T4	478		T8	1
valid_sources[0x66]	67917	1		T29	34		T4	446		T8	3
valid_sources[0x67]	69412	1		T29	36		T4	429		T8	3
valid_sources[0x68]	136281	1		T29	12		T4	440		T8	5
valid_sources[0x69]	68424	1		T29	52		T4	521		T8	1
valid_sources[0x6a]	69667	1		T29	19		T4	405		T5	1647
valid_sources[0x6b]	68984	1		T29	52		T4	429		T8	3
valid_sources[0x6c]	68523	1		T29	43		T4	485		T8	1
valid_sources[0x6d]	69736	1		T29	92		T4	374		T8	2
valid_sources[0x6e]	68894	1		T29	54		T4	452		T8	3
valid_sources[0x6f]	69208	1		T29	19		T30	1		T32	13
valid_sources[0x70]	359504	1		T29	22		T4	441		T8	1
valid_sources[0x71]	69194	1		T29	37		T4	435		T8	3
valid_sources[0x72]	68612	1		T29	39		T37	1		T4	467
valid_sources[0x73]	68807	1		T29	37		T4	434		T8	4
valid_sources[0x74]	69415	1		T29	26		T4	527		T8	2
valid_sources[0x75]	70693	1		T29	36		T4	460		T8	1
valid_sources[0x76]	68383	1		T29	38		T4	410		T8	1
valid_sources[0x77]	69273	1		T29	46		T4	510		T8	1
valid_sources[0x78]	69181	1		T29	27		T4	476		T8	2
valid_sources[0x79]	68179	1		T29	25		T4	509		T8	2
valid_sources[0x7a]	116380	1		T29	71		T4	455		T8	4
valid_sources[0x7b]	68480	1		T29	15		T4	413		T8	4
valid_sources[0x7c]	68609	1		T29	21		T4	493		T8	2
valid_sources[0x7d]	68752	1		T29	57		T4	463		T8	1
valid_sources[0x7e]	68992	1		T29	53		T30	1		T4	500
valid_sources[0x7f]	69196	1		T29	71		T4	540		T8	1
valid_sources[0x80]	68183	1		T29	25		T4	504		T5	1602

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10882899

1

T1

3

T2

2

T35

1

values[0x0]

all_enables

biggest_size

153183

1

T1

4

T2

2

T3

5

values[0x1]

all_enables

biggest_size

142069

1

T1

1

T2

4

T35

1