Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.39	97.53	79.85	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	240925960	12051	0	0
ep_in_enable_rd_A	240925960	2916	0	0
ep_out_enable_rd_A	240925960	3085	0	0
in_iso_rd_A	240925960	3000	0	0
intr_enable_rd_A	240925960	4632	0	0
out_iso_rd_A	240925960	2615	0	0
phy_config_rd_A	240925960	1829	0	0
phy_pins_drive_rd_A	240925960	2684	0	0
rxenable_setup_rd_A	240925960	2818	0	0
set_nak_out_rd_A	240925960	3052	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	12051	0	0
T105	4436	22	0	0
T106	2986	417	0	0
T107	4973	8	0	0
T109	21121	4	0	0
T223	4372	627	0	0
T228	8578	341	0	0
T230	49081	6	0	0
T231	15776	4	0	0
T243	4651	18	0	0
T244	41756	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	2916	0	0
T107	4973	65	0	0
T109	21121	223	0	0
T111	4080	39	0	0
T112	8560	26	0	0
T241	10987	18	0	0
T244	41756	602	0	0
T247	35462	213	0	0
T252	83071	279	0	0
T271	5961	10	0	0
T272	14183	97	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	3085	0	0
T107	4973	12	0	0
T109	21121	203	0	0
T111	4080	64	0	0
T112	8560	24	0	0
T241	10987	48	0	0
T244	41756	411	0	0
T247	35462	267	0	0
T252	83071	259	0	0
T271	5961	70	0	0
T272	14183	57	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	3000	0	0
T107	4973	5	0	0
T109	21121	291	0	0
T111	4080	59	0	0
T112	8560	23	0	0
T241	10987	58	0	0
T244	41756	379	0	0
T247	35462	234	0	0
T252	83071	307	0	0
T271	5961	72	0	0
T272	14183	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	4632	0	0
T107	4973	11	0	0
T109	21121	476	0	0
T111	4080	142	0	0
T112	8560	34	0	0
T117	1943	10	0	0
T118	5413	5	0	0
T244	41756	917	0	0
T247	35462	503	0	0
T252	83071	241	0	0
T273	2348	22	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	2615	0	0
T107	4973	45	0	0
T109	21121	203	0	0
T111	4080	61	0	0
T112	8560	7	0	0
T244	41756	502	0	0
T247	35462	232	0	0
T252	83071	238	0	0
T260	79355	230	0	0
T271	5961	6	0	0
T272	14183	85	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	1829	0	0
T107	4973	8	0	0
T109	21121	140	0	0
T111	4080	25	0	0
T112	8560	22	0	0
T241	10987	26	0	0
T244	41756	234	0	0
T247	35462	119	0	0
T252	83071	212	0	0
T271	5961	30	0	0
T272	14183	22	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	2684	0	0
T107	4973	31	0	0
T109	21121	242	0	0
T111	4080	70	0	0
T112	8560	52	0	0
T241	10987	44	0	0
T244	41756	436	0	0
T247	35462	199	0	0
T252	83071	254	0	0
T271	5961	9	0	0
T272	14183	63	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	2818	0	0
T107	4973	5	0	0
T109	21121	164	0	0
T111	4080	57	0	0
T112	8560	9	0	0
T241	10987	76	0	0
T244	41756	637	0	0
T247	35462	171	0	0
T252	83071	249	0	0
T271	5961	53	0	0
T272	14183	16	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240925960	3052	0	0
T107	4973	65	0	0
T109	21121	232	0	0
T111	4080	48	0	0
T112	8560	13	0	0
T241	10987	33	0	0
T244	41756	525	0	0
T247	35462	292	0	0
T252	83071	267	0	0
T271	5961	75	0	0
T272	14183	22	0	0