Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	118887	1		T1	4		T2	3		T3	2
all_values[1]	118887	1		T1	4		T2	3		T3	2
all_values[2]	118887	1		T1	4		T2	3		T3	2
all_values[3]	118887	1		T1	4		T2	3		T3	2
all_values[4]	118887	1		T1	4		T2	3		T3	2
all_values[5]	118887	1		T1	4		T2	3		T3	2
all_values[6]	118887	1		T1	4		T2	3		T3	2
all_values[7]	118887	1		T1	4		T2	3		T3	2
all_values[8]	118887	1		T1	4		T2	3		T3	2
all_values[9]	118887	1		T1	4		T2	3		T3	2
all_values[10]	118887	1		T1	4		T2	3		T3	2
all_values[11]	118887	1		T1	4		T2	3		T3	2
all_values[12]	118887	1		T1	4		T2	3		T3	2
all_values[13]	118887	1		T1	4		T2	3		T3	2
all_values[14]	118887	1		T1	4		T2	3		T3	2
all_values[15]	118887	1		T1	4		T2	3		T3	2
all_values[16]	118887	1		T1	4		T2	3		T3	2
all_values[17]	118887	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2134008	1		T1	68		T2	51		T3	36
auto[1]	5958	1		T1	4		T2	3		T42	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2135336	1		T1	72		T2	54		T3	36
auto[1]	4630	1		T118	123		T119	133		T120	112

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	118100	1		T3	2		T28	2		T29	3
all_values[0]	auto[0]	auto[1]	118	1		T118	3		T119	5		T120	2
all_values[0]	auto[1]	auto[0]	520	1		T1	4		T2	3		T56	4
all_values[0]	auto[1]	auto[1]	149	1		T118	3		T119	2		T120	6
all_values[1]	auto[0]	auto[0]	116099	1		T1	4		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	156	1		T118	2		T119	5		T120	4
all_values[1]	auto[1]	auto[0]	2521	1		T38	5		T41	20		T58	18
all_values[1]	auto[1]	auto[1]	111	1		T118	4		T119	2		T122	1
all_values[2]	auto[0]	auto[0]	118501	1		T1	4		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	117	1		T118	7		T119	3		T120	1
all_values[2]	auto[1]	auto[0]	132	1		T42	2		T49	2		T17	2
all_values[2]	auto[1]	auto[1]	137	1		T118	1		T119	4		T120	5
all_values[3]	auto[0]	auto[0]	118607	1		T1	4		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	128	1		T118	2		T119	1		T120	5
all_values[3]	auto[1]	auto[0]	38	1		T118	1		T122	1		T270	2
all_values[3]	auto[1]	auto[1]	114	1		T118	4		T119	7		T120	3
all_values[4]	auto[0]	auto[0]	118595	1		T1	4		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	146	1		T118	5		T119	3		T120	6
all_values[4]	auto[1]	auto[0]	25	1		T120	1		T122	1		T271	1
all_values[4]	auto[1]	auto[1]	121	1		T118	3		T119	5		T120	1
all_values[5]	auto[0]	auto[0]	118606	1		T1	4		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	133	1		T118	3		T119	2		T120	6
all_values[5]	auto[1]	auto[0]	28	1		T118	1		T122	1		T272	1
all_values[5]	auto[1]	auto[1]	120	1		T118	4		T119	4		T120	2
all_values[6]	auto[0]	auto[0]	118603	1		T1	4		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	133	1		T118	6		T119	4		T120	5
all_values[6]	auto[1]	auto[0]	13	1		T118	1		T120	1		T273	1
all_values[6]	auto[1]	auto[1]	138	1		T118	1		T119	4		T120	1
all_values[7]	auto[0]	auto[0]	118609	1		T1	4		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	120	1		T118	4		T119	4		T120	1
all_values[7]	auto[1]	auto[0]	46	1		T118	1		T122	4		T272	1
all_values[7]	auto[1]	auto[1]	112	1		T118	2		T119	4		T120	6
all_values[8]	auto[0]	auto[0]	118617	1		T1	4		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	120	1		T118	2		T119	2		T120	5
all_values[8]	auto[1]	auto[0]	21	1		T274	1		T275	1		T276	2
all_values[8]	auto[1]	auto[1]	129	1		T118	6		T119	6		T120	3
all_values[9]	auto[0]	auto[0]	118599	1		T1	4		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	132	1		T118	3		T119	2		T120	1
all_values[9]	auto[1]	auto[0]	32	1		T118	1		T119	1		T270	3
all_values[9]	auto[1]	auto[1]	124	1		T118	4		T119	5		T120	7
all_values[10]	auto[0]	auto[0]	118603	1		T1	4		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	127	1		T118	5		T119	5		T120	3
all_values[10]	auto[1]	auto[0]	16	1		T119	1		T122	1		T272	1
all_values[10]	auto[1]	auto[1]	141	1		T118	3		T119	2		T120	5
all_values[11]	auto[0]	auto[0]	118502	1		T1	4		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	141	1		T118	4		T119	5		T120	1
all_values[11]	auto[1]	auto[0]	119	1		T67	2		T68	2		T69	2
all_values[11]	auto[1]	auto[1]	125	1		T118	1		T119	3		T120	3
all_values[12]	auto[0]	auto[0]	118604	1		T1	4		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	128	1		T118	3		T119	6		T120	1
all_values[12]	auto[1]	auto[0]	28	1		T271	1		T272	2		T277	4
all_values[12]	auto[1]	auto[1]	127	1		T118	5		T119	2		T120	7
all_values[13]	auto[0]	auto[0]	118612	1		T1	4		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	117	1		T118	3		T119	2		T271	1
all_values[13]	auto[1]	auto[0]	24	1		T118	1		T119	1		T120	2
all_values[13]	auto[1]	auto[1]	134	1		T118	4		T119	4		T122	5
all_values[14]	auto[0]	auto[0]	118598	1		T1	4		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	129	1		T118	5		T119	5		T120	5
all_values[14]	auto[1]	auto[0]	28	1		T118	3		T120	1		T273	1
all_values[14]	auto[1]	auto[1]	132	1		T119	3		T122	1		T271	5
all_values[15]	auto[0]	auto[0]	118607	1		T1	4		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	118	1		T118	2		T119	6		T120	4
all_values[15]	auto[1]	auto[0]	24	1		T119	1		T122	1		T271	1
all_values[15]	auto[1]	auto[1]	138	1		T118	5		T120	4		T271	7
all_values[16]	auto[0]	auto[0]	118599	1		T1	4		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	148	1		T118	7		T119	6		T122	4
all_values[16]	auto[1]	auto[0]	25	1		T270	1		T274	4		T273	2
all_values[16]	auto[1]	auto[1]	115	1		T119	2		T120	6		T122	1
all_values[17]	auto[0]	auto[0]	118610	1		T1	4		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	126	1		T118	2		T119	1		T122	3
all_values[17]	auto[1]	auto[0]	25	1		T120	2		T271	1		T272	2
all_values[17]	auto[1]	auto[1]	126	1		T118	5		T119	7		T120	3