Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	118887	1		T1	4		T2	3		T3	2
all_pins[1]	118887	1		T1	4		T2	3		T3	2
all_pins[2]	118887	1		T1	4		T2	3		T3	2
all_pins[3]	118887	1		T1	4		T2	3		T3	2
all_pins[4]	118887	1		T1	4		T2	3		T3	2
all_pins[5]	118887	1		T1	4		T2	3		T3	2
all_pins[6]	118887	1		T1	4		T2	3		T3	2
all_pins[7]	118887	1		T1	4		T2	3		T3	2
all_pins[8]	118887	1		T1	4		T2	3		T3	2
all_pins[9]	118887	1		T1	4		T2	3		T3	2
all_pins[10]	118887	1		T1	4		T2	3		T3	2
all_pins[11]	118887	1		T1	4		T2	3		T3	2
all_pins[12]	118887	1		T1	4		T2	3		T3	2
all_pins[13]	118887	1		T1	4		T2	3		T3	2
all_pins[14]	118887	1		T1	4		T2	3		T3	2
all_pins[15]	118887	1		T1	4		T2	3		T3	2
all_pins[16]	118887	1		T1	4		T2	3		T3	2
all_pins[17]	118887	1		T1	4		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2137472	1		T1	71		T2	54		T3	36
values[0x1]	2494	1		T1	1		T42	1		T49	1
transitions[0x0=>0x1]	2233	1		T1	1		T42	1		T49	1
transitions[0x1=>0x0]	2245	1		T1	1		T42	1		T49	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118777	1		T1	3		T2	3		T3	2
all_pins[0]	values[0x1]	110	1		T1	1		T56	1		T57	1
all_pins[0]	transitions[0x0=>0x1]	98	1		T1	1		T56	1		T57	1
all_pins[0]	transitions[0x1=>0x0]	1326	1		T38	2		T41	18		T58	15
all_pins[1]	values[0x0]	117549	1		T1	4		T2	3		T3	2
all_pins[1]	values[0x1]	1338	1		T38	2		T41	18		T58	15
all_pins[1]	transitions[0x0=>0x1]	1323	1		T38	2		T41	18		T58	15
all_pins[1]	transitions[0x1=>0x0]	124	1		T42	1		T49	1		T17	1
all_pins[2]	values[0x0]	118748	1		T1	4		T2	3		T3	2
all_pins[2]	values[0x1]	139	1		T42	1		T49	1		T17	1
all_pins[2]	transitions[0x0=>0x1]	111	1		T42	1		T49	1		T17	1
all_pins[2]	transitions[0x1=>0x0]	36	1		T118	3		T119	3		T120	1
all_pins[3]	values[0x0]	118823	1		T1	4		T2	3		T3	2
all_pins[3]	values[0x1]	64	1		T118	3		T119	5		T120	1
all_pins[3]	transitions[0x0=>0x1]	50	1		T118	2		T119	2		T120	1
all_pins[3]	transitions[0x1=>0x0]	40	1		T118	1		T120	1		T271	1
all_pins[4]	values[0x0]	118833	1		T1	4		T2	3		T3	2
all_pins[4]	values[0x1]	54	1		T118	2		T119	3		T120	1
all_pins[4]	transitions[0x0=>0x1]	34	1		T118	2		T119	3		T120	1
all_pins[4]	transitions[0x1=>0x0]	36	1		T119	1		T122	2		T271	2
all_pins[5]	values[0x0]	118831	1		T1	4		T2	3		T3	2
all_pins[5]	values[0x1]	56	1		T119	1		T122	2		T271	2
all_pins[5]	transitions[0x0=>0x1]	40	1		T119	1		T122	2		T272	1
all_pins[5]	transitions[0x1=>0x0]	47	1		T118	1		T119	1		T120	1
all_pins[6]	values[0x0]	118824	1		T1	4		T2	3		T3	2
all_pins[6]	values[0x1]	63	1		T118	1		T119	1		T120	1
all_pins[6]	transitions[0x0=>0x1]	55	1		T120	1		T271	4		T272	2
all_pins[6]	transitions[0x1=>0x0]	41	1		T119	1		T120	2		T271	1
all_pins[7]	values[0x0]	118838	1		T1	4		T2	3		T3	2
all_pins[7]	values[0x1]	49	1		T118	1		T119	2		T120	2
all_pins[7]	transitions[0x0=>0x1]	37	1		T118	1		T119	1		T120	1
all_pins[7]	transitions[0x1=>0x0]	37	1		T118	3		T119	2		T272	1
all_pins[8]	values[0x0]	118838	1		T1	4		T2	3		T3	2
all_pins[8]	values[0x1]	49	1		T118	3		T119	3		T120	1
all_pins[8]	transitions[0x0=>0x1]	44	1		T118	3		T119	3		T120	1
all_pins[8]	transitions[0x1=>0x0]	52	1		T118	3		T119	1		T120	2
all_pins[9]	values[0x0]	118830	1		T1	4		T2	3		T3	2
all_pins[9]	values[0x1]	57	1		T118	3		T119	1		T120	2
all_pins[9]	transitions[0x0=>0x1]	46	1		T118	3		T120	2		T274	1
all_pins[9]	transitions[0x1=>0x0]	49	1		T119	1		T120	1		T122	2
all_pins[10]	values[0x0]	118827	1		T1	4		T2	3		T3	2
all_pins[10]	values[0x1]	60	1		T119	2		T120	1		T122	2
all_pins[10]	transitions[0x0=>0x1]	50	1		T119	1		T120	1		T122	2
all_pins[10]	transitions[0x1=>0x0]	95	1		T67	1		T68	1		T69	1
all_pins[11]	values[0x0]	118782	1		T1	4		T2	3		T3	2
all_pins[11]	values[0x1]	105	1		T67	1		T68	1		T69	1
all_pins[11]	transitions[0x0=>0x1]	88	1		T67	1		T68	1		T69	1
all_pins[11]	transitions[0x1=>0x0]	46	1		T118	2		T119	1		T120	1
all_pins[12]	values[0x0]	118824	1		T1	4		T2	3		T3	2
all_pins[12]	values[0x1]	63	1		T118	3		T119	2		T120	3
all_pins[12]	transitions[0x0=>0x1]	48	1		T118	2		T119	2		T120	3
all_pins[12]	transitions[0x1=>0x0]	43	1		T122	4		T272	3		T270	1
all_pins[13]	values[0x0]	118829	1		T1	4		T2	3		T3	2
all_pins[13]	values[0x1]	58	1		T118	1		T122	4		T272	3
all_pins[13]	transitions[0x0=>0x1]	42	1		T118	1		T122	3		T272	2
all_pins[13]	transitions[0x1=>0x0]	48	1		T119	2		T272	1		T273	2
all_pins[14]	values[0x0]	118823	1		T1	4		T2	3		T3	2
all_pins[14]	values[0x1]	64	1		T119	2		T122	1		T272	2
all_pins[14]	transitions[0x0=>0x1]	53	1		T119	2		T122	1		T272	2
all_pins[14]	transitions[0x1=>0x0]	44	1		T118	2		T120	1		T271	4
all_pins[15]	values[0x0]	118832	1		T1	4		T2	3		T3	2
all_pins[15]	values[0x1]	55	1		T118	2		T120	1		T271	4
all_pins[15]	transitions[0x0=>0x1]	40	1		T118	2		T120	1		T271	4
all_pins[15]	transitions[0x1=>0x0]	42	1		T119	2		T120	4		T122	1
all_pins[16]	values[0x0]	118830	1		T1	4		T2	3		T3	2
all_pins[16]	values[0x1]	57	1		T119	2		T120	4		T122	1
all_pins[16]	transitions[0x0=>0x1]	40	1		T119	1		T120	3		T272	1
all_pins[16]	transitions[0x1=>0x0]	36	1		T118	1		T119	2		T122	1
all_pins[17]	values[0x0]	118834	1		T1	4		T2	3		T3	2
all_pins[17]	values[0x1]	53	1		T118	1		T119	3		T120	1
all_pins[17]	transitions[0x0=>0x1]	34	1		T118	1		T119	1		T120	1
all_pins[17]	transitions[0x1=>0x0]	103	1		T1	1		T56	1		T57	1