Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 24 0 24 100.00
Crosses 108 0 108 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 18 0 18 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 108 0 108 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 263 1 T118 7 T119 7 T120 7
all_values[1] 263 1 T118 7 T119 7 T120 7
all_values[2] 263 1 T118 7 T119 7 T120 7
all_values[3] 263 1 T118 7 T119 7 T120 7
all_values[4] 263 1 T118 7 T119 7 T120 7
all_values[5] 263 1 T118 7 T119 7 T120 7
all_values[6] 263 1 T118 7 T119 7 T120 7
all_values[7] 263 1 T118 7 T119 7 T120 7
all_values[8] 263 1 T118 7 T119 7 T120 7
all_values[9] 263 1 T118 7 T119 7 T120 7
all_values[10] 263 1 T118 7 T119 7 T120 7
all_values[11] 263 1 T118 7 T119 7 T120 7
all_values[12] 263 1 T118 7 T119 7 T120 7
all_values[13] 263 1 T118 7 T119 7 T120 7
all_values[14] 263 1 T118 7 T119 7 T120 7
all_values[15] 263 1 T118 7 T119 7 T120 7
all_values[16] 263 1 T118 7 T119 7 T120 7
all_values[17] 263 1 T118 7 T119 7 T120 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2660 1 T118 76 T119 60 T120 63
auto[1] 2074 1 T118 50 T119 66 T120 63



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 928 1 T118 21 T119 11 T120 31
auto[1] 3806 1 T118 105 T119 115 T120 95



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2871 1 T118 73 T119 69 T120 79
auto[1] 1863 1 T118 53 T119 57 T120 47



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 108 0 108 100.00
Automatically Generated Cross Bins 108 0 108 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 34 1 T118 2 T122 1 T271 1
all_values[0] auto[0] auto[0] auto[1] 51 1 T118 1 T119 1 T120 1
all_values[0] auto[0] auto[1] auto[0] 9 1 T119 1 T271 1 T278 1
all_values[0] auto[0] auto[1] auto[1] 56 1 T118 1 T119 2 T120 3
all_values[0] auto[1] auto[0] auto[1] 66 1 T118 3 T119 2 T120 1
all_values[0] auto[1] auto[1] auto[1] 47 1 T119 1 T120 2 T122 1
all_values[1] auto[0] auto[0] auto[0] 26 1 T118 1 T119 1 T120 4
all_values[1] auto[0] auto[0] auto[1] 57 1 T118 1 T119 1 T120 1
all_values[1] auto[0] auto[1] auto[0] 18 1 T118 1 T270 3 T278 2
all_values[1] auto[0] auto[1] auto[1] 50 1 T118 2 T119 2 T271 2
all_values[1] auto[1] auto[0] auto[1] 67 1 T118 2 T119 2 T120 2
all_values[1] auto[1] auto[1] auto[1] 45 1 T119 1 T271 1 T272 1
all_values[2] auto[0] auto[0] auto[0] 36 1 T119 1 T271 2 T276 3
all_values[2] auto[0] auto[0] auto[1] 53 1 T118 4 T119 3 T120 1
all_values[2] auto[0] auto[1] auto[0] 18 1 T120 2 T275 2 T276 1
all_values[2] auto[0] auto[1] auto[1] 45 1 T118 1 T119 1 T120 2
all_values[2] auto[1] auto[0] auto[1] 55 1 T118 1 T119 2 T122 1
all_values[2] auto[1] auto[1] auto[1] 56 1 T118 1 T120 2 T122 2
all_values[3] auto[0] auto[0] auto[0] 44 1 T118 1 T122 1 T271 1
all_values[3] auto[0] auto[0] auto[1] 54 1 T118 1 T120 3 T271 1
all_values[3] auto[0] auto[1] auto[0] 22 1 T118 1 T270 1 T274 1
all_values[3] auto[0] auto[1] auto[1] 43 1 T118 2 T119 3 T120 1
all_values[3] auto[1] auto[0] auto[1] 52 1 T118 1 T120 1 T122 2
all_values[3] auto[1] auto[1] auto[1] 48 1 T118 1 T119 4 T120 2
all_values[4] auto[0] auto[0] auto[0] 26 1 T122 4 T271 1 T272 1
all_values[4] auto[0] auto[0] auto[1] 53 1 T118 1 T120 2 T271 3
all_values[4] auto[0] auto[1] auto[0] 16 1 T120 1 T275 4 T279 2
all_values[4] auto[0] auto[1] auto[1] 48 1 T119 2 T272 4 T270 1
all_values[4] auto[1] auto[0] auto[1] 72 1 T118 2 T119 3 T120 3
all_values[4] auto[1] auto[1] auto[1] 48 1 T118 4 T119 2 T120 1
all_values[5] auto[0] auto[0] auto[0] 41 1 T118 1 T119 2 T122 1
all_values[5] auto[0] auto[0] auto[1] 58 1 T118 3 T119 3 T120 4
all_values[5] auto[0] auto[1] auto[0] 15 1 T273 1 T280 1 T281 4
all_values[5] auto[0] auto[1] auto[1] 51 1 T118 2 T119 1 T120 1
all_values[5] auto[1] auto[0] auto[1] 55 1 T119 1 T120 2 T122 2
all_values[5] auto[1] auto[1] auto[1] 43 1 T118 1 T271 2 T272 2
all_values[6] auto[0] auto[0] auto[0] 29 1 T118 1 T120 2 T122 2
all_values[6] auto[0] auto[0] auto[1] 50 1 T118 2 T119 3 T120 2
all_values[6] auto[0] auto[1] auto[0] 10 1 T273 1 T278 1 T282 1
all_values[6] auto[0] auto[1] auto[1] 62 1 T119 1 T120 1 T271 5
all_values[6] auto[1] auto[0] auto[1] 64 1 T118 2 T120 1 T122 1
all_values[6] auto[1] auto[1] auto[1] 48 1 T118 2 T119 3 T120 1
all_values[7] auto[0] auto[0] auto[0] 41 1 T118 2 T120 1 T122 3
all_values[7] auto[0] auto[0] auto[1] 52 1 T118 2 T119 2 T271 2
all_values[7] auto[0] auto[1] auto[0] 30 1 T122 1 T272 1 T273 2
all_values[7] auto[0] auto[1] auto[1] 44 1 T119 2 T120 3 T271 1
all_values[7] auto[1] auto[0] auto[1] 59 1 T118 1 T120 1 T271 4
all_values[7] auto[1] auto[1] auto[1] 37 1 T118 2 T119 3 T120 2
all_values[8] auto[0] auto[0] auto[0] 41 1 T122 1 T271 1 T272 1
all_values[8] auto[0] auto[0] auto[1] 48 1 T118 1 T119 2 T120 2
all_values[8] auto[0] auto[1] auto[0] 16 1 T274 2 T275 2 T276 2
all_values[8] auto[0] auto[1] auto[1] 53 1 T118 2 T119 1 T120 2
all_values[8] auto[1] auto[0] auto[1] 61 1 T118 1 T119 1 T120 2
all_values[8] auto[1] auto[1] auto[1] 44 1 T118 3 T119 3 T120 1
all_values[9] auto[0] auto[0] auto[0] 29 1 T118 1 T271 2 T270 1
all_values[9] auto[0] auto[0] auto[1] 62 1 T118 1 T119 3 T120 1
all_values[9] auto[0] auto[1] auto[0] 23 1 T119 1 T270 2 T274 1
all_values[9] auto[0] auto[1] auto[1] 51 1 T118 1 T119 1 T120 3
all_values[9] auto[1] auto[0] auto[1] 53 1 T118 2 T122 1 T271 1
all_values[9] auto[1] auto[1] auto[1] 45 1 T118 2 T119 2 T120 3
all_values[10] auto[0] auto[0] auto[0] 29 1 T122 1 T271 1 T272 1
all_values[10] auto[0] auto[0] auto[1] 56 1 T118 3 T119 2 T120 2
all_values[10] auto[0] auto[1] auto[0] 14 1 T119 1 T279 1 T277 1
all_values[10] auto[0] auto[1] auto[1] 63 1 T118 2 T120 1 T122 1
all_values[10] auto[1] auto[0] auto[1] 61 1 T118 1 T119 1 T120 2
all_values[10] auto[1] auto[1] auto[1] 40 1 T118 1 T119 3 T120 2
all_values[11] auto[0] auto[0] auto[0] 35 1 T118 3 T120 4 T270 1
all_values[11] auto[0] auto[0] auto[1] 53 1 T118 2 T119 2 T122 2
all_values[11] auto[0] auto[1] auto[0] 10 1 T273 1 T283 1 T284 1
all_values[11] auto[0] auto[1] auto[1] 65 1 T118 1 T119 2 T120 2
all_values[11] auto[1] auto[0] auto[1] 61 1 T118 1 T119 1 T122 1
all_values[11] auto[1] auto[1] auto[1] 39 1 T119 2 T120 1 T272 2
all_values[12] auto[0] auto[0] auto[0] 35 1 T122 1 T271 1 T272 2
all_values[12] auto[0] auto[0] auto[1] 54 1 T118 1 T119 1 T122 1
all_values[12] auto[0] auto[1] auto[0] 16 1 T272 1 T277 2 T285 1
all_values[12] auto[0] auto[1] auto[1] 55 1 T118 2 T119 1 T120 2
all_values[12] auto[1] auto[0] auto[1] 47 1 T118 1 T119 3 T122 2
all_values[12] auto[1] auto[1] auto[1] 56 1 T118 3 T119 2 T120 5
all_values[13] auto[0] auto[0] auto[0] 46 1 T118 1 T119 2 T120 7
all_values[13] auto[0] auto[0] auto[1] 47 1 T118 1 T119 1 T272 2
all_values[13] auto[0] auto[1] auto[0] 11 1 T273 2 T278 1 T280 1
all_values[13] auto[0] auto[1] auto[1] 61 1 T118 2 T119 3 T122 3
all_values[13] auto[1] auto[0] auto[1] 55 1 T118 2 T122 1 T271 1
all_values[13] auto[1] auto[1] auto[1] 43 1 T118 1 T119 1 T271 3
all_values[14] auto[0] auto[0] auto[0] 33 1 T118 1 T120 2 T122 1
all_values[14] auto[0] auto[0] auto[1] 56 1 T118 1 T119 2 T120 2
all_values[14] auto[0] auto[1] auto[0] 18 1 T118 2 T120 1 T273 1
all_values[14] auto[0] auto[1] auto[1] 63 1 T119 2 T271 4 T272 3
all_values[14] auto[1] auto[0] auto[1] 50 1 T118 2 T119 1 T120 1
all_values[14] auto[1] auto[1] auto[1] 43 1 T118 1 T119 2 T120 1
all_values[15] auto[0] auto[0] auto[0] 39 1 T118 1 T119 2 T122 2
all_values[15] auto[0] auto[0] auto[1] 50 1 T119 3 T120 2 T122 1
all_values[15] auto[0] auto[1] auto[0] 14 1 T274 2 T278 1 T280 1
all_values[15] auto[0] auto[1] auto[1] 57 1 T118 3 T120 2 T271 1
all_values[15] auto[1] auto[0] auto[1] 60 1 T118 2 T119 1 T120 1
all_values[15] auto[1] auto[1] auto[1] 43 1 T118 1 T119 1 T120 2
all_values[16] auto[0] auto[0] auto[0] 31 1 T118 1 T120 2 T270 1
all_values[16] auto[0] auto[0] auto[1] 56 1 T118 2 T119 1 T122 1
all_values[16] auto[0] auto[1] auto[0] 16 1 T274 4 T273 2 T286 1
all_values[16] auto[0] auto[1] auto[1] 52 1 T120 1 T122 1 T271 1
all_values[16] auto[1] auto[0] auto[1] 64 1 T118 4 T119 4 T122 1
all_values[16] auto[1] auto[1] auto[1] 44 1 T119 2 T120 4 T122 1
all_values[17] auto[0] auto[0] auto[0] 38 1 T118 1 T120 1 T271 4
all_values[17] auto[0] auto[0] auto[1] 63 1 T118 3 T122 1 T272 2
all_values[17] auto[0] auto[1] auto[0] 19 1 T120 4 T271 1 T272 2
all_values[17] auto[0] auto[1] auto[1] 51 1 T118 1 T119 4 T120 1
all_values[17] auto[1] auto[0] auto[1] 52 1 T118 1 T122 1 T272 1
all_values[17] auto[1] auto[1] auto[1] 40 1 T118 1 T119 3 T120 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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