Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.36 97.48 92.35 97.44 68.75 95.77 98.17 96.58


Total test records in report: 2216
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T2079 /workspace/coverage/default/2.usbdev_in_iso.1577616774 Jun 11 12:40:16 PM PDT 24 Jun 11 12:40:19 PM PDT 24 207671608 ps
T124 /workspace/coverage/default/4.usbdev_sec_cm.2440335538 Jun 11 12:40:27 PM PDT 24 Jun 11 12:40:30 PM PDT 24 287016026 ps
T2080 /workspace/coverage/default/8.usbdev_aon_wake_resume.369699887 Jun 11 12:40:48 PM PDT 24 Jun 11 12:41:16 PM PDT 24 23370385809 ps
T2081 /workspace/coverage/default/11.usbdev_pkt_buffer.4274684744 Jun 11 12:40:59 PM PDT 24 Jun 11 12:41:47 PM PDT 24 19352616945 ps
T2082 /workspace/coverage/default/1.usbdev_enable.1603665966 Jun 11 12:40:07 PM PDT 24 Jun 11 12:40:11 PM PDT 24 37304979 ps
T2083 /workspace/coverage/default/7.usbdev_enable.2526312352 Jun 11 12:40:56 PM PDT 24 Jun 11 12:40:59 PM PDT 24 59081709 ps
T2084 /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3378358902 Jun 11 12:43:56 PM PDT 24 Jun 11 12:44:05 PM PDT 24 4305642753 ps
T2085 /workspace/coverage/default/10.usbdev_max_length_out_transaction.2039299880 Jun 11 12:40:56 PM PDT 24 Jun 11 12:40:59 PM PDT 24 194868797 ps
T2086 /workspace/coverage/default/4.usbdev_min_length_in_transaction.3886452263 Jun 11 12:40:25 PM PDT 24 Jun 11 12:40:28 PM PDT 24 169653118 ps
T2087 /workspace/coverage/default/3.usbdev_streaming_out.1473280187 Jun 11 12:40:22 PM PDT 24 Jun 11 12:45:58 PM PDT 24 12286727925 ps
T2088 /workspace/coverage/default/46.usbdev_pkt_sent.4150862568 Jun 11 12:44:31 PM PDT 24 Jun 11 12:44:34 PM PDT 24 232516704 ps
T2089 /workspace/coverage/default/24.usbdev_pkt_buffer.3880097730 Jun 11 12:42:32 PM PDT 24 Jun 11 12:43:06 PM PDT 24 14152023128 ps
T2090 /workspace/coverage/default/40.usbdev_in_trans.3832704101 Jun 11 12:43:52 PM PDT 24 Jun 11 12:43:56 PM PDT 24 237268456 ps
T2091 /workspace/coverage/default/22.usbdev_pending_in_trans.1594260358 Jun 11 12:42:09 PM PDT 24 Jun 11 12:42:13 PM PDT 24 157068504 ps
T2092 /workspace/coverage/default/18.usbdev_pkt_sent.1651864471 Jun 11 12:42:04 PM PDT 24 Jun 11 12:42:08 PM PDT 24 175725634 ps
T2093 /workspace/coverage/default/11.usbdev_out_trans_nak.3480382745 Jun 11 12:41:14 PM PDT 24 Jun 11 12:41:19 PM PDT 24 194282587 ps
T2094 /workspace/coverage/default/49.usbdev_endpoint_access.3460741444 Jun 11 12:44:44 PM PDT 24 Jun 11 12:44:49 PM PDT 24 1050648932 ps
T2095 /workspace/coverage/default/31.usbdev_pkt_sent.2550371102 Jun 11 12:43:12 PM PDT 24 Jun 11 12:43:14 PM PDT 24 183026964 ps
T2096 /workspace/coverage/default/2.usbdev_stress_usb_traffic.534084835 Jun 11 12:40:14 PM PDT 24 Jun 11 12:43:25 PM PDT 24 10060866413 ps
T2097 /workspace/coverage/default/36.usbdev_streaming_out.1334050844 Jun 11 12:43:40 PM PDT 24 Jun 11 12:45:38 PM PDT 24 12890260632 ps
T2098 /workspace/coverage/default/45.usbdev_max_usb_traffic.4120461404 Jun 11 12:44:19 PM PDT 24 Jun 11 12:45:13 PM PDT 24 4756827820 ps
T2099 /workspace/coverage/default/46.usbdev_link_suspend.2556283191 Jun 11 12:44:42 PM PDT 24 Jun 11 12:44:48 PM PDT 24 3321303406 ps
T2100 /workspace/coverage/default/39.usbdev_endpoint_access.4249045100 Jun 11 12:43:46 PM PDT 24 Jun 11 12:43:50 PM PDT 24 729476992 ps
T2101 /workspace/coverage/default/10.usbdev_in_trans.482800304 Jun 11 12:41:10 PM PDT 24 Jun 11 12:41:15 PM PDT 24 254146978 ps
T2102 /workspace/coverage/default/9.usbdev_link_in_err.1757633521 Jun 11 12:41:09 PM PDT 24 Jun 11 12:41:14 PM PDT 24 215498667 ps
T2103 /workspace/coverage/default/6.usbdev_min_length_out_transaction.848231561 Jun 11 12:40:27 PM PDT 24 Jun 11 12:40:29 PM PDT 24 150466431 ps
T2104 /workspace/coverage/default/7.usbdev_max_length_in_transaction.4065916500 Jun 11 12:40:48 PM PDT 24 Jun 11 12:40:51 PM PDT 24 230731134 ps
T2105 /workspace/coverage/default/20.usbdev_max_length_in_transaction.2623598250 Jun 11 12:42:04 PM PDT 24 Jun 11 12:42:08 PM PDT 24 297034844 ps
T2106 /workspace/coverage/default/40.usbdev_out_stall.278858563 Jun 11 12:44:09 PM PDT 24 Jun 11 12:44:11 PM PDT 24 156684058 ps
T2107 /workspace/coverage/default/2.usbdev_max_usb_traffic.3328591673 Jun 11 12:40:07 PM PDT 24 Jun 11 12:42:32 PM PDT 24 15532589218 ps
T2108 /workspace/coverage/default/46.usbdev_max_usb_traffic.3406555705 Jun 11 12:44:22 PM PDT 24 Jun 11 12:45:44 PM PDT 24 11692590795 ps
T2109 /workspace/coverage/default/45.usbdev_out_trans_nak.2194836084 Jun 11 12:44:15 PM PDT 24 Jun 11 12:44:18 PM PDT 24 179012206 ps
T2110 /workspace/coverage/default/21.usbdev_enable.4140729725 Jun 11 12:42:07 PM PDT 24 Jun 11 12:42:10 PM PDT 24 76628462 ps
T2111 /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.405602634 Jun 11 12:42:18 PM PDT 24 Jun 11 12:42:20 PM PDT 24 191304076 ps
T2112 /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.2369609481 Jun 11 12:44:34 PM PDT 24 Jun 11 12:44:38 PM PDT 24 192029307 ps
T2113 /workspace/coverage/default/5.usbdev_stall_trans.220697235 Jun 11 12:40:25 PM PDT 24 Jun 11 12:40:28 PM PDT 24 180595033 ps
T2114 /workspace/coverage/default/18.usbdev_smoke.3072317462 Jun 11 12:42:01 PM PDT 24 Jun 11 12:42:04 PM PDT 24 236487631 ps
T2115 /workspace/coverage/default/7.usbdev_in_iso.3660767511 Jun 11 12:40:49 PM PDT 24 Jun 11 12:40:52 PM PDT 24 208376733 ps
T2116 /workspace/coverage/default/47.usbdev_enable.1263557554 Jun 11 12:44:36 PM PDT 24 Jun 11 12:44:39 PM PDT 24 88741443 ps
T2117 /workspace/coverage/default/23.usbdev_random_length_out_transaction.3959759451 Jun 11 12:42:34 PM PDT 24 Jun 11 12:42:36 PM PDT 24 191564899 ps
T2118 /workspace/coverage/default/46.usbdev_out_stall.2095019097 Jun 11 12:44:51 PM PDT 24 Jun 11 12:44:53 PM PDT 24 170682430 ps
T115 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2459654930 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:27 PM PDT 24 370756198 ps
T2119 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.628319607 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:27 PM PDT 24 197283007 ps
T112 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2357583052 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 86857428 ps
T116 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1168210418 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:23 PM PDT 24 88054175 ps
T113 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1148190464 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:23 PM PDT 24 88787458 ps
T117 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1724992791 Jun 11 12:35:28 PM PDT 24 Jun 11 12:35:31 PM PDT 24 284558786 ps
T114 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1804385436 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:37 PM PDT 24 584152280 ps
T220 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1202937739 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:21 PM PDT 24 300277549 ps
T121 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1984721116 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:23 PM PDT 24 86442890 ps
T118 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3292573421 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 62827274 ps
T216 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2024881875 Jun 11 12:35:25 PM PDT 24 Jun 11 12:35:28 PM PDT 24 107221220 ps
T221 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3908996490 Jun 11 12:35:16 PM PDT 24 Jun 11 12:35:22 PM PDT 24 872182423 ps
T259 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2052637533 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 74522104 ps
T2120 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2604059516 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:23 PM PDT 24 112047278 ps
T245 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1999476858 Jun 11 12:35:16 PM PDT 24 Jun 11 12:35:20 PM PDT 24 91432800 ps
T119 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3940470952 Jun 11 12:35:21 PM PDT 24 Jun 11 12:35:25 PM PDT 24 122162536 ps
T120 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3363309468 Jun 11 12:35:22 PM PDT 24 Jun 11 12:35:26 PM PDT 24 37907003 ps
T122 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.120144823 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:35 PM PDT 24 39970559 ps
T2121 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3622088535 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 170744493 ps
T260 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.328854109 Jun 11 12:35:35 PM PDT 24 Jun 11 12:35:38 PM PDT 24 83850915 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.693858874 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 53153012 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.337908258 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:23 PM PDT 24 101929684 ps
T271 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.630701260 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:19 PM PDT 24 51505237 ps
T272 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1257578385 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:31 PM PDT 24 56311380 ps
T229 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2006852677 Jun 11 12:35:15 PM PDT 24 Jun 11 12:35:21 PM PDT 24 588400576 ps
T261 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2375540037 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 100451627 ps
T2122 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3970485462 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:25 PM PDT 24 75435529 ps
T270 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1679263981 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:41 PM PDT 24 91266681 ps
T232 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.399063341 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:37 PM PDT 24 153418785 ps
T233 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.930891935 Jun 11 12:35:23 PM PDT 24 Jun 11 12:35:28 PM PDT 24 529494967 ps
T248 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1811897021 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 80411751 ps
T222 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2299601056 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:42 PM PDT 24 62781594 ps
T274 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1907421654 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:37 PM PDT 24 39564641 ps
T231 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1786668475 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:38 PM PDT 24 220421029 ps
T262 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1288441950 Jun 11 12:35:39 PM PDT 24 Jun 11 12:35:43 PM PDT 24 392710752 ps
T249 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2514048384 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:34 PM PDT 24 68401415 ps
T234 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.36054381 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 190758435 ps
T235 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1566975349 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:33 PM PDT 24 384762139 ps
T225 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1767859567 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:26 PM PDT 24 204665032 ps
T265 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.253381374 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:37 PM PDT 24 117032983 ps
T2123 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3815356304 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:21 PM PDT 24 75834727 ps
T275 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1525169220 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:40 PM PDT 24 37652997 ps
T273 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3927988276 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 71101223 ps
T250 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3554648243 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:20 PM PDT 24 99668444 ps
T226 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.122568891 Jun 11 12:35:37 PM PDT 24 Jun 11 12:35:41 PM PDT 24 170772094 ps
T263 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2629570748 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:37 PM PDT 24 55402514 ps
T227 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3179346723 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:39 PM PDT 24 260806966 ps
T278 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3917344442 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:37 PM PDT 24 71313667 ps
T2124 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3645283710 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:28 PM PDT 24 83161826 ps
T2125 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.445376211 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:29 PM PDT 24 1213807132 ps
T2126 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2738028152 Jun 11 12:35:28 PM PDT 24 Jun 11 12:35:30 PM PDT 24 81132204 ps
T276 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1936493288 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 34903025 ps
T286 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1159269628 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 39312796 ps
T2127 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1223248089 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:37 PM PDT 24 39832752 ps
T251 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.138282752 Jun 11 12:35:16 PM PDT 24 Jun 11 12:35:18 PM PDT 24 187207677 ps
T280 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3019524579 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:41 PM PDT 24 87309207 ps
T228 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1480293744 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:35 PM PDT 24 117451098 ps
T296 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1393524932 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:30 PM PDT 24 367048166 ps
T2128 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2880501362 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 200695616 ps
T279 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4179190764 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:40 PM PDT 24 103196848 ps
T2129 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2389403421 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:33 PM PDT 24 61158281 ps
T2130 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1951264417 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:33 PM PDT 24 1806425615 ps
T2131 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3749773685 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 119697849 ps
T266 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1846920095 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:38 PM PDT 24 804495447 ps
T267 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4125328944 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:30 PM PDT 24 297943180 ps
T252 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3003687073 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:28 PM PDT 24 781655103 ps
T269 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.908268264 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:21 PM PDT 24 66035472 ps
T268 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3793217836 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:27 PM PDT 24 1277348328 ps
T2132 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3899764361 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:37 PM PDT 24 70345277 ps
T291 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3678731706 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:32 PM PDT 24 970439852 ps
T2133 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2611489422 Jun 11 12:35:35 PM PDT 24 Jun 11 12:35:37 PM PDT 24 88818054 ps
T2134 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.165935874 Jun 11 12:35:24 PM PDT 24 Jun 11 12:35:28 PM PDT 24 169510252 ps
T2135 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3511485908 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:28 PM PDT 24 38514175 ps
T2136 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2098849048 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:21 PM PDT 24 153656651 ps
T230 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4254574890 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:23 PM PDT 24 93523795 ps
T289 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1606116068 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:34 PM PDT 24 290029351 ps
T2137 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2865115986 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 236438819 ps
T2138 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3467945186 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:37 PM PDT 24 146592985 ps
T2139 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.728989891 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:35 PM PDT 24 177034826 ps
T281 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2469244128 Jun 11 12:35:30 PM PDT 24 Jun 11 12:35:33 PM PDT 24 76573998 ps
T2140 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1621968851 Jun 11 12:35:30 PM PDT 24 Jun 11 12:35:32 PM PDT 24 55660381 ps
T277 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3418103271 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:40 PM PDT 24 47763209 ps
T253 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1157949293 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:24 PM PDT 24 55367767 ps
T2141 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3282939641 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:34 PM PDT 24 105999930 ps
T2142 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4279554249 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:19 PM PDT 24 99395980 ps
T290 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3417423855 Jun 11 12:35:21 PM PDT 24 Jun 11 12:35:28 PM PDT 24 606460639 ps
T2143 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3238226430 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:23 PM PDT 24 63645243 ps
T254 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1116042718 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 53040567 ps
T255 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1343406123 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 61651587 ps
T2144 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1517695370 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:28 PM PDT 24 39663802 ps
T2145 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4219802866 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:24 PM PDT 24 97034003 ps
T2146 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2964426758 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 237860319 ps
T282 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3384408749 Jun 11 12:35:36 PM PDT 24 Jun 11 12:35:39 PM PDT 24 52904616 ps
T2147 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1383340933 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:26 PM PDT 24 170329216 ps
T2148 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.526313973 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:34 PM PDT 24 51901231 ps
T256 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.505850329 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 48469543 ps
T2149 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3806300352 Jun 11 12:35:37 PM PDT 24 Jun 11 12:35:39 PM PDT 24 76446601 ps
T257 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1734332396 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 43046261 ps
T293 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2584241649 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:33 PM PDT 24 1018098843 ps
T2150 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.797534843 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:34 PM PDT 24 114698937 ps
T2151 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3235488006 Jun 11 12:35:36 PM PDT 24 Jun 11 12:35:39 PM PDT 24 112427851 ps
T2152 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2441494398 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:37 PM PDT 24 673539696 ps
T258 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4270920229 Jun 11 12:35:21 PM PDT 24 Jun 11 12:35:27 PM PDT 24 140373355 ps
T285 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4289247812 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 39961055 ps
T287 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.930561511 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:33 PM PDT 24 658498760 ps
T2153 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.825765212 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:21 PM PDT 24 75160881 ps
T2154 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.471919707 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:40 PM PDT 24 39994437 ps
T283 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1530359549 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 44556008 ps
T2155 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3246025138 Jun 11 12:35:26 PM PDT 24 Jun 11 12:35:29 PM PDT 24 138537732 ps
T2156 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2286287216 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:29 PM PDT 24 1937760037 ps
T2157 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2028988049 Jun 11 12:35:21 PM PDT 24 Jun 11 12:35:27 PM PDT 24 115726374 ps
T2158 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1915879912 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:27 PM PDT 24 502337788 ps
T2159 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.182848745 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:23 PM PDT 24 56822287 ps
T2160 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.535486182 Jun 11 12:35:27 PM PDT 24 Jun 11 12:35:29 PM PDT 24 42683863 ps
T2161 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3834362275 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 121822819 ps
T2162 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3753077536 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 68754256 ps
T2163 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.910686296 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:23 PM PDT 24 72936641 ps
T2164 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1623318972 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:31 PM PDT 24 45651026 ps
T284 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1079196188 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:23 PM PDT 24 48253484 ps
T292 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3726936380 Jun 11 12:35:37 PM PDT 24 Jun 11 12:35:44 PM PDT 24 948153314 ps
T2165 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4151046867 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 47537969 ps
T2166 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2210272144 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:31 PM PDT 24 46816577 ps
T2167 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2894715562 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:23 PM PDT 24 203150801 ps
T2168 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1313750707 Jun 11 12:35:21 PM PDT 24 Jun 11 12:35:25 PM PDT 24 39639087 ps
T2169 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.311396471 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:31 PM PDT 24 80132012 ps
T2170 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2214097472 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 152442151 ps
T294 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2726620762 Jun 11 12:35:28 PM PDT 24 Jun 11 12:35:35 PM PDT 24 1347321108 ps
T2171 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4051754666 Jun 11 12:35:36 PM PDT 24 Jun 11 12:35:38 PM PDT 24 33451451 ps
T2172 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3149264225 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:35 PM PDT 24 47441160 ps
T2173 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2659747622 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 53702992 ps
T2174 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.145816333 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 144894734 ps
T2175 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3507705057 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:21 PM PDT 24 125581661 ps
T288 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4261187479 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 420904648 ps
T2176 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.827767739 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:20 PM PDT 24 73276942 ps
T2177 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.936303549 Jun 11 12:35:30 PM PDT 24 Jun 11 12:35:32 PM PDT 24 59571985 ps
T2178 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2564837352 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 88145187 ps
T2179 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3465522769 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:38 PM PDT 24 378974358 ps
T2180 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3579431622 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:21 PM PDT 24 54480030 ps
T2181 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1029417454 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:22 PM PDT 24 34270046 ps
T2182 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3412648394 Jun 11 12:35:25 PM PDT 24 Jun 11 12:35:29 PM PDT 24 224641815 ps
T2183 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.749552641 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:34 PM PDT 24 73899372 ps
T2184 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.254243628 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:34 PM PDT 24 45694126 ps
T2185 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1329495782 Jun 11 12:35:25 PM PDT 24 Jun 11 12:35:29 PM PDT 24 210888268 ps
T2186 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2689083915 Jun 11 12:35:30 PM PDT 24 Jun 11 12:35:33 PM PDT 24 73378937 ps
T2187 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2661491918 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 87461862 ps
T2188 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1008056982 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:23 PM PDT 24 30316409 ps
T2189 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2442267511 Jun 11 12:35:36 PM PDT 24 Jun 11 12:35:39 PM PDT 24 71578159 ps
T295 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3742171204 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:22 PM PDT 24 673806530 ps
T2190 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3102440517 Jun 11 12:35:38 PM PDT 24 Jun 11 12:35:40 PM PDT 24 57444974 ps
T2191 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4169092329 Jun 11 12:35:29 PM PDT 24 Jun 11 12:35:31 PM PDT 24 110197794 ps
T2192 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1728803953 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 48780562 ps
T2193 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1921708791 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:25 PM PDT 24 109208521 ps
T2194 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1970143011 Jun 11 12:35:22 PM PDT 24 Jun 11 12:35:26 PM PDT 24 62812544 ps
T2195 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2245611876 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:25 PM PDT 24 738295127 ps
T2196 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1867481701 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 112926325 ps
T2197 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2320190087 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:25 PM PDT 24 220503655 ps
T2198 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2601411223 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 160381387 ps
T2199 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2672017421 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:20 PM PDT 24 111952424 ps
T2200 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.932618195 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:36 PM PDT 24 207013237 ps
T2201 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2922803153 Jun 11 12:35:25 PM PDT 24 Jun 11 12:35:28 PM PDT 24 76727115 ps
T2202 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2483242991 Jun 11 12:35:17 PM PDT 24 Jun 11 12:35:20 PM PDT 24 102804548 ps
T2203 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.175562020 Jun 11 12:35:30 PM PDT 24 Jun 11 12:35:34 PM PDT 24 281106246 ps
T2204 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3147921464 Jun 11 12:35:34 PM PDT 24 Jun 11 12:35:37 PM PDT 24 26896333 ps
T2205 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2739441307 Jun 11 12:35:22 PM PDT 24 Jun 11 12:35:27 PM PDT 24 60077883 ps
T2206 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3475895131 Jun 11 12:35:20 PM PDT 24 Jun 11 12:35:24 PM PDT 24 89111139 ps
T2207 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3584630607 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 131436552 ps
T2208 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1960002394 Jun 11 12:35:32 PM PDT 24 Jun 11 12:35:38 PM PDT 24 317625150 ps
T2209 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1270347600 Jun 11 12:35:30 PM PDT 24 Jun 11 12:35:32 PM PDT 24 84470892 ps
T2210 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2706181723 Jun 11 12:35:33 PM PDT 24 Jun 11 12:35:36 PM PDT 24 47042985 ps
T2211 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.967589861 Jun 11 12:35:19 PM PDT 24 Jun 11 12:35:24 PM PDT 24 73275668 ps
T2212 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2606464428 Jun 11 12:35:36 PM PDT 24 Jun 11 12:35:38 PM PDT 24 37001667 ps
T2213 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.870033739 Jun 11 12:35:37 PM PDT 24 Jun 11 12:35:40 PM PDT 24 48639337 ps
T2214 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3029260540 Jun 11 12:35:31 PM PDT 24 Jun 11 12:35:34 PM PDT 24 189138300 ps
T2215 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.519558884 Jun 11 12:35:18 PM PDT 24 Jun 11 12:35:22 PM PDT 24 74835856 ps
T2216 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1812510027 Jun 11 12:35:21 PM PDT 24 Jun 11 12:35:29 PM PDT 24 708439422 ps

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.4098257456
Short name T33
Test name
Test status
Simulation time 243725752 ps
CPU time 0.9 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204772 kb
Host smart-54564119-b2dc-4f88-820c-748a6926a596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40982
57456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.4098257456
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1999688077
Short name T5
Test name
Test status
Simulation time 23739071840 ps
CPU time 579.12 seconds
Started Jun 11 12:40:24 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 205016 kb
Host smart-f20d2295-8049-438f-85f7-8a4e57771e62
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1999688077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1999688077
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1257578385
Short name T272
Test name
Test status
Simulation time 56311380 ps
CPU time 0.69 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:31 PM PDT 24
Peak memory 204184 kb
Host smart-0c299efd-1323-41ee-89f5-6bb821d24f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1257578385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1257578385
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.3692423877
Short name T1
Test name
Test status
Simulation time 166847711 ps
CPU time 0.77 seconds
Started Jun 11 12:42:13 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204600 kb
Host smart-4abd7cab-f9c7-48ba-9227-b456afd9235f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36924
23877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3692423877
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3908996490
Short name T221
Test name
Test status
Simulation time 872182423 ps
CPU time 5.55 seconds
Started Jun 11 12:35:16 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204440 kb
Host smart-d0c430ad-ee4a-4e60-9c91-9a3f1cd713cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3908996490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3908996490
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2006911863
Short name T10
Test name
Test status
Simulation time 23314042151 ps
CPU time 21.96 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:47 PM PDT 24
Peak memory 205040 kb
Host smart-6ba7272b-7e58-4d0a-8a9d-da4eeb274346
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2006911863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2006911863
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.159782892
Short name T208
Test name
Test status
Simulation time 18823184496 ps
CPU time 156.09 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:43:39 PM PDT 24
Peak memory 205044 kb
Host smart-ad2bb70c-316c-47e4-a665-3553cb50c1e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=159782892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.159782892
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3878820039
Short name T50
Test name
Test status
Simulation time 150288979 ps
CPU time 0.84 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 203776 kb
Host smart-86ce246a-19e1-4058-9044-ff531b1bc57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38788
20039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3878820039
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3772481880
Short name T170
Test name
Test status
Simulation time 191731087 ps
CPU time 0.85 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 204992 kb
Host smart-c2d3026f-4807-4d93-8238-b3adabc32bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724
81880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3772481880
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3292573421
Short name T118
Test name
Test status
Simulation time 62827274 ps
CPU time 0.69 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204184 kb
Host smart-334ae210-181c-441e-a246-918b9fda4fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3292573421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3292573421
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.456881125
Short name T82
Test name
Test status
Simulation time 234824887 ps
CPU time 0.93 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204660 kb
Host smart-0907cf8f-37b0-42b0-a073-42f8757192b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45688
1125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.456881125
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1637326342
Short name T49
Test name
Test status
Simulation time 141134838 ps
CPU time 0.79 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 204728 kb
Host smart-660fa1d3-94b3-45c7-9c84-d2102f7af067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16373
26342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1637326342
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.418300941
Short name T109
Test name
Test status
Simulation time 231572550 ps
CPU time 1.07 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:26 PM PDT 24
Peak memory 221416 kb
Host smart-4f2ec731-d991-4049-845b-8fd9e2cb4155
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=418300941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.418300941
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2299601056
Short name T222
Test name
Test status
Simulation time 62781594 ps
CPU time 1.52 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:42 PM PDT 24
Peak memory 204540 kb
Host smart-7bba8389-e692-4664-856c-78533d08baed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2299601056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2299601056
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2302065261
Short name T23
Test name
Test status
Simulation time 340245421 ps
CPU time 1.11 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:37 PM PDT 24
Peak memory 204752 kb
Host smart-a2163a75-3d0d-43db-8302-6046cdb36b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
65261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2302065261
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2105560415
Short name T84
Test name
Test status
Simulation time 202322178 ps
CPU time 0.83 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 204728 kb
Host smart-4b483e56-372a-4e87-9c25-255ef003678e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21055
60415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2105560415
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2180553027
Short name T45
Test name
Test status
Simulation time 47945177 ps
CPU time 0.65 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 204684 kb
Host smart-45b5f8ba-fffe-4580-8960-d19a562799d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21805
53027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2180553027
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3256239968
Short name T64
Test name
Test status
Simulation time 148351802 ps
CPU time 0.73 seconds
Started Jun 11 12:44:37 PM PDT 24
Finished Jun 11 12:44:40 PM PDT 24
Peak memory 204724 kb
Host smart-60d8939a-5a98-413e-9146-e4ce692e6bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32562
39968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3256239968
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1136801889
Short name T171
Test name
Test status
Simulation time 5138365325 ps
CPU time 124.29 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 205068 kb
Host smart-45f5c9ff-75fe-44fd-9df8-699a56317cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368
01889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1136801889
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3940470952
Short name T119
Test name
Test status
Simulation time 122162536 ps
CPU time 0.75 seconds
Started Jun 11 12:35:21 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204200 kb
Host smart-d1507a41-6065-48e4-9e2c-81f806b92570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3940470952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3940470952
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.693858874
Short name T246
Test name
Test status
Simulation time 53153012 ps
CPU time 1.44 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 212632 kb
Host smart-2a67272d-c062-4014-a8c2-43eda15e93f7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=693858874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.693858874
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2110875548
Short name T556
Test name
Test status
Simulation time 221396025 ps
CPU time 1.85 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:47 PM PDT 24
Peak memory 205184 kb
Host smart-c7a03147-4933-42c2-9263-3ab260d52790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21108
75548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2110875548
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1675837384
Short name T409
Test name
Test status
Simulation time 150386886 ps
CPU time 0.78 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204688 kb
Host smart-cd6856f9-7983-4fad-a74a-0100aee02d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16758
37384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1675837384
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3927988276
Short name T273
Test name
Test status
Simulation time 71101223 ps
CPU time 0.67 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204196 kb
Host smart-641cce7a-3c74-40b2-862d-ac94074a6be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3927988276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3927988276
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3726936380
Short name T292
Test name
Test status
Simulation time 948153314 ps
CPU time 4.71 seconds
Started Jun 11 12:35:37 PM PDT 24
Finished Jun 11 12:35:44 PM PDT 24
Peak memory 204800 kb
Host smart-e9dd4147-2c59-4955-a64d-9b7ae827bc53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3726936380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3726936380
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1525169220
Short name T275
Test name
Test status
Simulation time 37652997 ps
CPU time 0.63 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:40 PM PDT 24
Peak memory 204208 kb
Host smart-54dff43d-40a6-4180-99ca-9f7539ee6bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1525169220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1525169220
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1089142048
Short name T51
Test name
Test status
Simulation time 13291258242 ps
CPU time 12.37 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204952 kb
Host smart-8c0c1bfe-0e49-40ea-919b-d7d4510e6278
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1089142048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1089142048
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.668773264
Short name T40
Test name
Test status
Simulation time 15611732044 ps
CPU time 37.77 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:42 PM PDT 24
Peak memory 205000 kb
Host smart-49c4fb6b-e6aa-44bb-a272-7cd70fdbdc58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66877
3264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.668773264
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4254574890
Short name T230
Test name
Test status
Simulation time 93523795 ps
CPU time 2.63 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 220372 kb
Host smart-af754b92-3e86-46f2-9b32-8f463e379b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4254574890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4254574890
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2726620762
Short name T294
Test name
Test status
Simulation time 1347321108 ps
CPU time 5.18 seconds
Started Jun 11 12:35:28 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204528 kb
Host smart-1dd9610a-0e20-4945-808c-97ba9bb38418
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2726620762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2726620762
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3691075912
Short name T70
Test name
Test status
Simulation time 141510137 ps
CPU time 0.75 seconds
Started Jun 11 12:41:51 PM PDT 24
Finished Jun 11 12:41:55 PM PDT 24
Peak memory 204636 kb
Host smart-904772f2-7a5c-454c-8bf6-e60ad5d6cc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36910
75912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3691075912
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.70800243
Short name T61
Test name
Test status
Simulation time 193076501 ps
CPU time 0.81 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:18 PM PDT 24
Peak memory 204676 kb
Host smart-c26120b7-25cb-4313-b7e2-fb1374e3703f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70800
243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.70800243
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3944498772
Short name T55
Test name
Test status
Simulation time 4312081883 ps
CPU time 5.57 seconds
Started Jun 11 12:41:30 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204784 kb
Host smart-d98904a9-1644-4ff6-9ee3-5cb8c43577bb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3944498772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3944498772
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3294775134
Short name T161
Test name
Test status
Simulation time 230821945 ps
CPU time 0.9 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204572 kb
Host smart-36d1b089-987a-4310-882d-503644f9d2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
75134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3294775134
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.991833304
Short name T211
Test name
Test status
Simulation time 1239421223 ps
CPU time 2.62 seconds
Started Jun 11 12:40:33 PM PDT 24
Finished Jun 11 12:40:37 PM PDT 24
Peak memory 205008 kb
Host smart-26a1aee0-d556-4eb5-b4ca-c5f9e457521f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99183
3304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.991833304
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1530359549
Short name T283
Test name
Test status
Simulation time 44556008 ps
CPU time 0.64 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204164 kb
Host smart-e8981554-d26b-439c-8b10-b108121f7a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530359549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1530359549
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.930561511
Short name T287
Test name
Test status
Simulation time 658498760 ps
CPU time 2.74 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204480 kb
Host smart-5a4f4bed-820e-42ab-81c5-591cbd9f410c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=930561511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.930561511
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2771128913
Short name T86
Test name
Test status
Simulation time 164793548 ps
CPU time 0.77 seconds
Started Jun 11 12:44:42 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 204712 kb
Host smart-792f722d-7efd-42e1-af7f-2f21e8727516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27711
28913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2771128913
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2360964047
Short name T200
Test name
Test status
Simulation time 1551753693 ps
CPU time 3.37 seconds
Started Jun 11 12:43:14 PM PDT 24
Finished Jun 11 12:43:18 PM PDT 24
Peak memory 204900 kb
Host smart-8403e8f4-0309-4a28-84f5-658d295be375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23609
64047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2360964047
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.1525882395
Short name T77
Test name
Test status
Simulation time 173429115 ps
CPU time 0.85 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 204752 kb
Host smart-25ace5da-d88b-4d81-86da-35ce745c53a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15258
82395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.1525882395
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2847811994
Short name T1921
Test name
Test status
Simulation time 19665619596 ps
CPU time 113.78 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204968 kb
Host smart-f454e451-a2e6-4600-ac94-5cc4f2b13538
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2847811994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2847811994
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3294782765
Short name T1274
Test name
Test status
Simulation time 157114997 ps
CPU time 0.76 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 204708 kb
Host smart-b0b93803-f207-4fc3-b2a1-352891ed14d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
82765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3294782765
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3801822879
Short name T196
Test name
Test status
Simulation time 156160742 ps
CPU time 0.79 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204700 kb
Host smart-3a32c633-283a-46bb-93d6-7d7da09e6054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38018
22879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3801822879
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3814428942
Short name T539
Test name
Test status
Simulation time 238626955 ps
CPU time 0.96 seconds
Started Jun 11 12:40:03 PM PDT 24
Finished Jun 11 12:40:04 PM PDT 24
Peak memory 204724 kb
Host smart-85041798-e839-41ad-bf91-368e90d50df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
28942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3814428942
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3340063400
Short name T78
Test name
Test status
Simulation time 167837140 ps
CPU time 0.81 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204656 kb
Host smart-9857af58-66a8-47fd-b214-d0b7341685b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33400
63400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3340063400
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.437699220
Short name T27
Test name
Test status
Simulation time 46875025 ps
CPU time 0.64 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204684 kb
Host smart-1f2a95b7-9497-446a-b2a9-f3f3d0d10b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43769
9220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.437699220
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1527056405
Short name T1114
Test name
Test status
Simulation time 214682853 ps
CPU time 0.89 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204712 kb
Host smart-47294cbb-1bd2-44d8-8a40-da61a5d45927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15270
56405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1527056405
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3265999931
Short name T188
Test name
Test status
Simulation time 142165727 ps
CPU time 0.74 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204704 kb
Host smart-8d85b0d0-bd0e-4664-ac0a-cc5457bb5c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32659
99931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3265999931
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1440817865
Short name T393
Test name
Test status
Simulation time 156846885 ps
CPU time 0.79 seconds
Started Jun 11 12:41:25 PM PDT 24
Finished Jun 11 12:41:30 PM PDT 24
Peak memory 204728 kb
Host smart-b172784a-4e99-42b3-a2ce-6ff25bcef301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
17865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1440817865
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3710720432
Short name T193
Test name
Test status
Simulation time 180233729 ps
CPU time 0.77 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204704 kb
Host smart-c0e02bf0-0bc9-4fb5-b9ff-07c4d1bd3af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
20432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3710720432
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1776082867
Short name T1861
Test name
Test status
Simulation time 212316726 ps
CPU time 0.87 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204720 kb
Host smart-bbde0191-1998-4bd1-ac37-879811ae6944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17760
82867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1776082867
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.4173308794
Short name T1954
Test name
Test status
Simulation time 205493667 ps
CPU time 0.8 seconds
Started Jun 11 12:41:31 PM PDT 24
Finished Jun 11 12:41:36 PM PDT 24
Peak memory 204572 kb
Host smart-ad1439c8-af68-4962-b252-b752e327913a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
08794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.4173308794
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3640215737
Short name T264
Test name
Test status
Simulation time 166986035 ps
CPU time 0.77 seconds
Started Jun 11 12:41:25 PM PDT 24
Finished Jun 11 12:41:30 PM PDT 24
Peak memory 204568 kb
Host smart-04f0f17b-9139-4e60-8d24-0b1bc0298a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36402
15737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3640215737
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1480293744
Short name T228
Test name
Test status
Simulation time 117451098 ps
CPU time 2.37 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 220292 kb
Host smart-1a9165d2-30eb-4292-8a49-7356eb149dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1480293744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1480293744
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1804385436
Short name T114
Test name
Test status
Simulation time 584152280 ps
CPU time 3.03 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204416 kb
Host smart-aba8cc8e-9fa6-465a-bc22-34c8e3a5e148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1804385436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1804385436
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.711694236
Short name T153
Test name
Test status
Simulation time 230039672 ps
CPU time 0.94 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204744 kb
Host smart-90c92344-87d6-4071-b968-5907563372c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71169
4236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.711694236
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1929155149
Short name T144
Test name
Test status
Simulation time 227466087 ps
CPU time 0.91 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:12 PM PDT 24
Peak memory 204772 kb
Host smart-f8faa53b-497b-494d-9be8-4cf4363de39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
55149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1929155149
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.19226776
Short name T2044
Test name
Test status
Simulation time 233255838 ps
CPU time 0.91 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:06 PM PDT 24
Peak memory 204740 kb
Host smart-c06d753e-5834-4077-a83e-6ce239677ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19226
776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.19226776
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.499654225
Short name T41
Test name
Test status
Simulation time 1071114187 ps
CPU time 2.37 seconds
Started Jun 11 12:41:28 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204896 kb
Host smart-c5eab315-b2ba-41a5-aca6-a5adbb986bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49965
4225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.499654225
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.203151739
Short name T102
Test name
Test status
Simulation time 14654120779 ps
CPU time 33.25 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 205060 kb
Host smart-83e9ee8a-2e2c-4d82-84d8-41e41a7fab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20315
1739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.203151739
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.797047118
Short name T165
Test name
Test status
Simulation time 167605438 ps
CPU time 0.85 seconds
Started Jun 11 12:41:24 PM PDT 24
Finished Jun 11 12:41:28 PM PDT 24
Peak memory 204692 kb
Host smart-6a09ea62-0ce8-4c87-aae8-03462b8c1c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79704
7118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.797047118
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.4161204720
Short name T157
Test name
Test status
Simulation time 215213400 ps
CPU time 0.84 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204600 kb
Host smart-b0397461-1caf-4d2b-98c6-489ae0e3f8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
04720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.4161204720
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2100215145
Short name T207
Test name
Test status
Simulation time 846646072 ps
CPU time 1.92 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204980 kb
Host smart-2dc15e53-844a-4638-8ce4-54e6e29951f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21002
15145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2100215145
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3017971952
Short name T140
Test name
Test status
Simulation time 224110741 ps
CPU time 0.89 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204708 kb
Host smart-ed58b75e-f36a-46d5-b451-e469013ed247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179
71952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3017971952
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2839156556
Short name T137
Test name
Test status
Simulation time 196994429 ps
CPU time 0.85 seconds
Started Jun 11 12:40:12 PM PDT 24
Finished Jun 11 12:40:15 PM PDT 24
Peak memory 204748 kb
Host smart-6ba41bc4-f7f0-47c5-ad2d-e8bba17ebe5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28391
56556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2839156556
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3928833813
Short name T1603
Test name
Test status
Simulation time 172708275 ps
CPU time 0.82 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204708 kb
Host smart-996db9bc-caab-48c1-b06c-c6c8a4782835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288
33813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3928833813
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.874144983
Short name T149
Test name
Test status
Simulation time 254341928 ps
CPU time 0.93 seconds
Started Jun 11 12:42:46 PM PDT 24
Finished Jun 11 12:42:50 PM PDT 24
Peak memory 204640 kb
Host smart-5d7be50c-a25d-4a8c-a245-48976abced6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87414
4983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.874144983
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1377839687
Short name T167
Test name
Test status
Simulation time 221563375 ps
CPU time 0.85 seconds
Started Jun 11 12:42:54 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204628 kb
Host smart-dab9f214-7921-4e3d-aa10-22278d915758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
39687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1377839687
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.702035006
Short name T146
Test name
Test status
Simulation time 204787278 ps
CPU time 0.92 seconds
Started Jun 11 12:43:39 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 204712 kb
Host smart-6830bb14-2443-4c36-9c97-a75d84c31a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70203
5006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.702035006
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4270920229
Short name T258
Test name
Test status
Simulation time 140373355 ps
CPU time 3.03 seconds
Started Jun 11 12:35:21 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 204476 kb
Host smart-05b80445-4804-4a65-af10-c01ac5f3b764
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4270920229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4270920229
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2286287216
Short name T2156
Test name
Test status
Simulation time 1937760037 ps
CPU time 9.98 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 204420 kb
Host smart-ad5aaf09-d778-4062-b759-eafdd707bc52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2286287216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2286287216
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3815356304
Short name T2123
Test name
Test status
Simulation time 75834727 ps
CPU time 0.78 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 204276 kb
Host smart-b34de678-0fae-409e-b9ac-e65ab6043ecd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3815356304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3815356304
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.910686296
Short name T2163
Test name
Test status
Simulation time 72936641 ps
CPU time 1.93 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 212732 kb
Host smart-41648e5d-d62f-471b-867f-a84f67121e0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910686296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.910686296
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2672017421
Short name T2199
Test name
Test status
Simulation time 111952424 ps
CPU time 1.06 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:20 PM PDT 24
Peak memory 204392 kb
Host smart-8e0294b1-0b3b-45eb-aca1-95a6f01a1d0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2672017421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2672017421
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.630701260
Short name T271
Test name
Test status
Simulation time 51505237 ps
CPU time 0.69 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:19 PM PDT 24
Peak memory 204156 kb
Host smart-307cee04-c7b5-4bb3-85c8-8da57f39bbb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=630701260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.630701260
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.4279554249
Short name T2142
Test name
Test status
Simulation time 99395980 ps
CPU time 1.42 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:19 PM PDT 24
Peak memory 212572 kb
Host smart-13dea62b-0ba7-4681-b2fe-13b2034c1c1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4279554249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.4279554249
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.628319607
Short name T2119
Test name
Test status
Simulation time 197283007 ps
CPU time 3.81 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 204404 kb
Host smart-3182954a-1ee5-4782-9576-7f19283d2507
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=628319607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.628319607
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2601411223
Short name T2198
Test name
Test status
Simulation time 160381387 ps
CPU time 1.14 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204272 kb
Host smart-6a797d5e-6035-48cf-a8ba-875a8641d437
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2601411223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2601411223
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1148190464
Short name T113
Test name
Test status
Simulation time 88787458 ps
CPU time 1.91 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204524 kb
Host smart-c2cd86c7-90bc-4f31-9bae-72e852dd568e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1148190464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1148190464
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2006852677
Short name T229
Test name
Test status
Simulation time 588400576 ps
CPU time 4.1 seconds
Started Jun 11 12:35:15 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 204472 kb
Host smart-06dce8ed-d183-4ee8-abd8-3fd845f15113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2006852677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2006852677
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3970485462
Short name T2122
Test name
Test status
Simulation time 75435529 ps
CPU time 2.04 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204448 kb
Host smart-ee06eead-77ce-44b9-9823-a4f50efa9876
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3970485462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3970485462
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.445376211
Short name T2125
Test name
Test status
Simulation time 1213807132 ps
CPU time 9.33 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 204468 kb
Host smart-b5db2f90-2b7d-43b1-be51-10bed718649e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=445376211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.445376211
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.138282752
Short name T251
Test name
Test status
Simulation time 187207677 ps
CPU time 0.89 seconds
Started Jun 11 12:35:16 PM PDT 24
Finished Jun 11 12:35:18 PM PDT 24
Peak memory 204200 kb
Host smart-42f364ce-f32b-44f1-ab63-c6d660e5c732
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=138282752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.138282752
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.825765212
Short name T2153
Test name
Test status
Simulation time 75160881 ps
CPU time 1.56 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 212664 kb
Host smart-2f70918d-93ce-45c1-a0a5-1c265c23d8c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825765212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.825765212
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2564837352
Short name T2178
Test name
Test status
Simulation time 88145187 ps
CPU time 0.96 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204488 kb
Host smart-57f94116-32b0-44c2-9b5c-db69f627fbbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2564837352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2564837352
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3579431622
Short name T2180
Test name
Test status
Simulation time 54480030 ps
CPU time 0.69 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 204148 kb
Host smart-73c48845-8199-4ff5-a905-d3c0a0f4e9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3579431622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3579431622
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.337908258
Short name T247
Test name
Test status
Simulation time 101929684 ps
CPU time 2.15 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 212616 kb
Host smart-0b5fa382-0801-4392-a32e-a1e2be3b892f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=337908258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.337908258
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1812510027
Short name T2216
Test name
Test status
Simulation time 708439422 ps
CPU time 4.71 seconds
Started Jun 11 12:35:21 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 204412 kb
Host smart-42c7d471-05a7-44b9-83dc-c84e7f4658bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1812510027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1812510027
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2375540037
Short name T261
Test name
Test status
Simulation time 100451627 ps
CPU time 1.07 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204488 kb
Host smart-6aa66f00-1d86-490c-b5fc-a48e1fbe6837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2375540037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2375540037
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3238226430
Short name T2143
Test name
Test status
Simulation time 63645243 ps
CPU time 1.39 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204560 kb
Host smart-3c48aa24-6166-4b31-9f4c-dec03bccfc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3238226430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3238226430
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2024881875
Short name T216
Test name
Test status
Simulation time 107221220 ps
CPU time 1.25 seconds
Started Jun 11 12:35:25 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 212720 kb
Host smart-acd71e90-fbc4-41e0-b817-10f44ec3887f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024881875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2024881875
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3645283710
Short name T2124
Test name
Test status
Simulation time 83161826 ps
CPU time 0.86 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 204188 kb
Host smart-bd84a70f-dcf1-41f9-9567-e2589016c3e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3645283710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3645283710
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1970143011
Short name T2194
Test name
Test status
Simulation time 62812544 ps
CPU time 1.01 seconds
Started Jun 11 12:35:22 PM PDT 24
Finished Jun 11 12:35:26 PM PDT 24
Peak memory 204500 kb
Host smart-546712f3-571c-4e44-91de-7e4fb785e289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1970143011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1970143011
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2739441307
Short name T2205
Test name
Test status
Simulation time 60077883 ps
CPU time 1.45 seconds
Started Jun 11 12:35:22 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 204484 kb
Host smart-9d93c21a-76bf-41d1-acc9-5c2db641c7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2739441307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2739441307
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.930891935
Short name T233
Test name
Test status
Simulation time 529494967 ps
CPU time 2.89 seconds
Started Jun 11 12:35:23 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 204508 kb
Host smart-4ce45a14-21c2-42d6-959f-d6c7a833b7d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=930891935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.930891935
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2865115986
Short name T2137
Test name
Test status
Simulation time 236438819 ps
CPU time 1.73 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 215824 kb
Host smart-be38482f-c950-459d-b199-298139600bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865115986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2865115986
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3467945186
Short name T2138
Test name
Test status
Simulation time 146592985 ps
CPU time 1.16 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204456 kb
Host smart-586e6d92-db5c-44fe-a2d7-cd4eb5ed3c4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3467945186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3467945186
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1270347600
Short name T2209
Test name
Test status
Simulation time 84470892 ps
CPU time 1.11 seconds
Started Jun 11 12:35:30 PM PDT 24
Finished Jun 11 12:35:32 PM PDT 24
Peak memory 204392 kb
Host smart-fbdcca9e-cbc1-428f-b09f-86e5d81e6394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1270347600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1270347600
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1566975349
Short name T235
Test name
Test status
Simulation time 384762139 ps
CPU time 2.66 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204432 kb
Host smart-983a0135-0996-4dfe-99e1-f362e445b4b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1566975349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1566975349
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.932618195
Short name T2200
Test name
Test status
Simulation time 207013237 ps
CPU time 1.92 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 220772 kb
Host smart-dfb5021c-be50-44bf-97ae-abeaf82441f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932618195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.932618195
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3149264225
Short name T2172
Test name
Test status
Simulation time 47441160 ps
CPU time 0.92 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204400 kb
Host smart-e17fcfef-44c5-4722-b34c-76374e0942b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3149264225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3149264225
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3282939641
Short name T2141
Test name
Test status
Simulation time 105999930 ps
CPU time 1.07 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204368 kb
Host smart-447f8626-dc60-4792-926e-4acbf16d6375
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3282939641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3282939641
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.728989891
Short name T2139
Test name
Test status
Simulation time 177034826 ps
CPU time 1.79 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 212708 kb
Host smart-ee39c4eb-6e85-4f4c-ac8c-99a026cddd8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728989891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.728989891
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2629570748
Short name T263
Test name
Test status
Simulation time 55402514 ps
CPU time 0.93 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204456 kb
Host smart-584a7a10-9647-469a-8cde-ac6c144b286f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2629570748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2629570748
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2606464428
Short name T2212
Test name
Test status
Simulation time 37001667 ps
CPU time 0.66 seconds
Started Jun 11 12:35:36 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 204212 kb
Host smart-01f86f35-2c6c-4192-af86-28198d5f1a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2606464428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2606464428
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2738028152
Short name T2126
Test name
Test status
Simulation time 81132204 ps
CPU time 1.08 seconds
Started Jun 11 12:35:28 PM PDT 24
Finished Jun 11 12:35:30 PM PDT 24
Peak memory 204472 kb
Host smart-07ea364e-f937-4d70-b12a-e74921a98de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2738028152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2738028152
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2689083915
Short name T2186
Test name
Test status
Simulation time 73378937 ps
CPU time 1.34 seconds
Started Jun 11 12:35:30 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204452 kb
Host smart-a1c84152-debb-406c-8276-9867e102b08c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2689083915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2689083915
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2880501362
Short name T2128
Test name
Test status
Simulation time 200695616 ps
CPU time 1.63 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 212600 kb
Host smart-6a0d94fc-26ed-420b-9dc1-113c1bf0cf90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880501362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2880501362
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1623318972
Short name T2164
Test name
Test status
Simulation time 45651026 ps
CPU time 0.95 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:31 PM PDT 24
Peak memory 204404 kb
Host smart-922675e0-6313-4cce-80d1-e475d8627e8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1623318972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1623318972
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1724992791
Short name T117
Test name
Test status
Simulation time 284558786 ps
CPU time 1.79 seconds
Started Jun 11 12:35:28 PM PDT 24
Finished Jun 11 12:35:31 PM PDT 24
Peak memory 204532 kb
Host smart-135427bc-af12-4153-9d53-bd9bfafc04c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1724992791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1724992791
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2357583052
Short name T112
Test name
Test status
Simulation time 86857428 ps
CPU time 1.6 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204816 kb
Host smart-4be24b62-8788-4cd2-b04a-290007950ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357583052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2357583052
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1846920095
Short name T266
Test name
Test status
Simulation time 804495447 ps
CPU time 2.79 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 204412 kb
Host smart-54315f09-30d1-48c3-874e-13d4509bca89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1846920095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1846920095
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.399063341
Short name T232
Test name
Test status
Simulation time 153418785 ps
CPU time 1.89 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 216088 kb
Host smart-d607f7e1-07cd-445d-a70b-3e6d167dadc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399063341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.399063341
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.254243628
Short name T2184
Test name
Test status
Simulation time 45694126 ps
CPU time 0.83 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204548 kb
Host smart-7c3f3a12-8401-4fc1-aa8a-8a27731c6fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=254243628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.254243628
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2210272144
Short name T2166
Test name
Test status
Simulation time 46816577 ps
CPU time 0.64 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:31 PM PDT 24
Peak memory 204096 kb
Host smart-80985ff4-5777-47d1-8539-c5e1a62e6723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2210272144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2210272144
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1288441950
Short name T262
Test name
Test status
Simulation time 392710752 ps
CPU time 1.81 seconds
Started Jun 11 12:35:39 PM PDT 24
Finished Jun 11 12:35:43 PM PDT 24
Peak memory 204516 kb
Host smart-058c5949-0f0e-4773-9134-4e89fc0b871a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1288441950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1288441950
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.175562020
Short name T2203
Test name
Test status
Simulation time 281106246 ps
CPU time 2.98 seconds
Started Jun 11 12:35:30 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 220256 kb
Host smart-67d36154-a04e-4f20-b547-8fb2603acd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=175562020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.175562020
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2584241649
Short name T293
Test name
Test status
Simulation time 1018098843 ps
CPU time 2.91 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204520 kb
Host smart-179a00f5-8091-4b21-9687-496cb9e18871
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2584241649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2584241649
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2214097472
Short name T2170
Test name
Test status
Simulation time 152442151 ps
CPU time 1.2 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 214052 kb
Host smart-a77a8ca4-0463-4b89-8ef7-d1931d75d1ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214097472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2214097472
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2514048384
Short name T249
Test name
Test status
Simulation time 68401415 ps
CPU time 0.78 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204288 kb
Host smart-a301e3dd-8271-484c-9343-168f21dd1b65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2514048384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2514048384
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.311396471
Short name T2169
Test name
Test status
Simulation time 80132012 ps
CPU time 0.68 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:31 PM PDT 24
Peak memory 204152 kb
Host smart-482f5364-9ad5-4de7-8e5e-f75d39989624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311396471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.311396471
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3584630607
Short name T2207
Test name
Test status
Simulation time 131436552 ps
CPU time 1.14 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204416 kb
Host smart-2b3fce49-76e7-4f0b-b6d2-b2d6c2c53235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3584630607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3584630607
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3179346723
Short name T227
Test name
Test status
Simulation time 260806966 ps
CPU time 3.25 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:39 PM PDT 24
Peak memory 220268 kb
Host smart-b5db4165-17e5-47e3-83d2-5d9827910df2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3179346723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3179346723
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.36054381
Short name T234
Test name
Test status
Simulation time 190758435 ps
CPU time 1.78 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 212560 kb
Host smart-cc588acc-9fee-4094-ac12-c4e07f19ae51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36054381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev
_csr_mem_rw_with_rand_reset.36054381
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2389403421
Short name T2129
Test name
Test status
Simulation time 61158281 ps
CPU time 0.82 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204276 kb
Host smart-a936aa44-5750-409b-8441-70b90e40b7e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2389403421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2389403421
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.4169092329
Short name T2191
Test name
Test status
Simulation time 110197794 ps
CPU time 0.75 seconds
Started Jun 11 12:35:29 PM PDT 24
Finished Jun 11 12:35:31 PM PDT 24
Peak memory 204144 kb
Host smart-13b92b86-e010-4b99-904c-cb951a9e4082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4169092329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.4169092329
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3899764361
Short name T2132
Test name
Test status
Simulation time 70345277 ps
CPU time 1.1 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204484 kb
Host smart-250359c3-e9ba-4c1f-9722-fa308ae31150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3899764361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3899764361
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3465522769
Short name T2179
Test name
Test status
Simulation time 378974358 ps
CPU time 3.9 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 204444 kb
Host smart-03bc3bb9-5ca2-4524-b730-82c40bd13bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3465522769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3465522769
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1606116068
Short name T289
Test name
Test status
Simulation time 290029351 ps
CPU time 2.32 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204396 kb
Host smart-56d7252b-bf28-4661-8dcb-5ffd7794d8d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1606116068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1606116068
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1786668475
Short name T231
Test name
Test status
Simulation time 220421029 ps
CPU time 1.8 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 212680 kb
Host smart-44123315-d1e6-4ba4-8de1-9c5148097675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786668475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1786668475
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1621968851
Short name T2140
Test name
Test status
Simulation time 55660381 ps
CPU time 0.78 seconds
Started Jun 11 12:35:30 PM PDT 24
Finished Jun 11 12:35:32 PM PDT 24
Peak memory 204224 kb
Host smart-73da7fbf-7fb0-40d5-99f5-8f625ad18e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1621968851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1621968851
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.535486182
Short name T2160
Test name
Test status
Simulation time 42683863 ps
CPU time 0.66 seconds
Started Jun 11 12:35:27 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 204220 kb
Host smart-f3af1448-e22a-49f5-b1f5-663cddb3feed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=535486182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.535486182
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3029260540
Short name T2214
Test name
Test status
Simulation time 189138300 ps
CPU time 1.57 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204456 kb
Host smart-b601097d-924c-466d-a88d-897061659f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3029260540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3029260540
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1960002394
Short name T2208
Test name
Test status
Simulation time 317625150 ps
CPU time 3.09 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 220400 kb
Host smart-95d3dbfd-e546-48e5-a3c3-d14100772f7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1960002394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1960002394
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2441494398
Short name T2152
Test name
Test status
Simulation time 673539696 ps
CPU time 3.23 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204404 kb
Host smart-212d2ec2-1fd2-48a8-a26c-3d480d0dd66e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2441494398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2441494398
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.253381374
Short name T265
Test name
Test status
Simulation time 117032983 ps
CPU time 1.33 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 212636 kb
Host smart-2add2904-a168-4c2f-aa38-04ad09e0d583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253381374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.253381374
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1734332396
Short name T257
Test name
Test status
Simulation time 43046261 ps
CPU time 0.98 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204444 kb
Host smart-7a5c3f1c-26ef-49e7-95e6-d70ba372d6e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1734332396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1734332396
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2469244128
Short name T281
Test name
Test status
Simulation time 76573998 ps
CPU time 0.76 seconds
Started Jun 11 12:35:30 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204144 kb
Host smart-6e9fb030-0b5d-45ea-836a-84d6347c4b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2469244128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2469244128
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.328854109
Short name T260
Test name
Test status
Simulation time 83850915 ps
CPU time 1.09 seconds
Started Jun 11 12:35:35 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 204452 kb
Host smart-02af46e2-cd40-4981-9594-b61cf10f6628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=328854109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.328854109
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.122568891
Short name T226
Test name
Test status
Simulation time 170772094 ps
CPU time 1.8 seconds
Started Jun 11 12:35:37 PM PDT 24
Finished Jun 11 12:35:41 PM PDT 24
Peak memory 212708 kb
Host smart-26e4e039-07dd-4623-8509-c1c2645b763f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=122568891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.122568891
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1999476858
Short name T245
Test name
Test status
Simulation time 91432800 ps
CPU time 1.95 seconds
Started Jun 11 12:35:16 PM PDT 24
Finished Jun 11 12:35:20 PM PDT 24
Peak memory 204444 kb
Host smart-d00b6324-60ce-404c-8f3a-c4ed97388076
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1999476858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1999476858
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2459654930
Short name T115
Test name
Test status
Simulation time 370756198 ps
CPU time 4.63 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 204492 kb
Host smart-5dd1ba44-37b8-4050-9158-766fb51fd0db
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2459654930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2459654930
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3475895131
Short name T2206
Test name
Test status
Simulation time 89111139 ps
CPU time 0.82 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204184 kb
Host smart-6a7cbe91-62e5-42cf-94d2-b472e59a0776
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3475895131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3475895131
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3749773685
Short name T2131
Test name
Test status
Simulation time 119697849 ps
CPU time 1.84 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 215912 kb
Host smart-2e7a262f-c478-40bd-9c21-c35421312b39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749773685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3749773685
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.505850329
Short name T256
Test name
Test status
Simulation time 48469543 ps
CPU time 0.97 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204672 kb
Host smart-80aa75db-2900-4ee3-afe7-f533d37e8a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=505850329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.505850329
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1008056982
Short name T2188
Test name
Test status
Simulation time 30316409 ps
CPU time 0.65 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204144 kb
Host smart-75abac10-9e48-4996-9701-5d8cd851983d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1008056982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1008056982
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2483242991
Short name T2202
Test name
Test status
Simulation time 102804548 ps
CPU time 1.43 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:20 PM PDT 24
Peak memory 212624 kb
Host smart-2880907e-7a69-4212-a52e-9a2f3ab698c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2483242991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2483242991
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2604059516
Short name T2120
Test name
Test status
Simulation time 112047278 ps
CPU time 2.23 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204312 kb
Host smart-8f0995ca-0942-40e2-ba37-d3e6d04f574c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2604059516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2604059516
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.967589861
Short name T2211
Test name
Test status
Simulation time 73275668 ps
CPU time 1.39 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204384 kb
Host smart-cc0e1a07-7b03-4187-90d1-9759dcb54c03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=967589861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.967589861
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.519558884
Short name T2215
Test name
Test status
Simulation time 74835856 ps
CPU time 1.55 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204380 kb
Host smart-32a15c2e-845c-4b67-91ef-e0cbb7031a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=519558884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.519558884
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1202937739
Short name T220
Test name
Test status
Simulation time 300277549 ps
CPU time 2.62 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 204484 kb
Host smart-1d4c6afa-16d1-4ae6-9f93-41b1e36dbdc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1202937739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1202937739
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1936493288
Short name T276
Test name
Test status
Simulation time 34903025 ps
CPU time 0.64 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204188 kb
Host smart-58ffffe4-47be-429e-809b-394cf154601a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1936493288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1936493288
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3806300352
Short name T2149
Test name
Test status
Simulation time 76446601 ps
CPU time 0.73 seconds
Started Jun 11 12:35:37 PM PDT 24
Finished Jun 11 12:35:39 PM PDT 24
Peak memory 204460 kb
Host smart-f93d32a8-8368-4126-9a7d-d4014368d208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3806300352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3806300352
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2442267511
Short name T2189
Test name
Test status
Simulation time 71578159 ps
CPU time 0.7 seconds
Started Jun 11 12:35:36 PM PDT 24
Finished Jun 11 12:35:39 PM PDT 24
Peak memory 204460 kb
Host smart-66294b96-5b68-45e4-81bd-fc38b406967b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2442267511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2442267511
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2706181723
Short name T2210
Test name
Test status
Simulation time 47042985 ps
CPU time 0.65 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204204 kb
Host smart-68baab1d-46e6-4ec3-b3b9-4dab3381f1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2706181723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2706181723
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3753077536
Short name T2162
Test name
Test status
Simulation time 68754256 ps
CPU time 0.66 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204128 kb
Host smart-b56fd7c2-33bc-48b7-a27f-422384810dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3753077536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3753077536
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1907421654
Short name T274
Test name
Test status
Simulation time 39564641 ps
CPU time 0.66 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204144 kb
Host smart-a90e4784-da2f-49aa-88ec-e31e672dedb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1907421654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1907421654
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.797534843
Short name T2150
Test name
Test status
Simulation time 114698937 ps
CPU time 0.73 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204164 kb
Host smart-ae2a1ddf-d8aa-4f06-b398-e258ef9cba65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=797534843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.797534843
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4289247812
Short name T285
Test name
Test status
Simulation time 39961055 ps
CPU time 0.63 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204140 kb
Host smart-b8a420b0-1add-44f4-9b6e-ba96d01e5a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4289247812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4289247812
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3917344442
Short name T278
Test name
Test status
Simulation time 71313667 ps
CPU time 0.69 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204208 kb
Host smart-f9d73c87-c2be-4240-b6d4-89a4b7f1d154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3917344442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3917344442
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3384408749
Short name T282
Test name
Test status
Simulation time 52904616 ps
CPU time 0.69 seconds
Started Jun 11 12:35:36 PM PDT 24
Finished Jun 11 12:35:39 PM PDT 24
Peak memory 204460 kb
Host smart-8ec05d1a-dc09-442d-9a77-56001d145c76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3384408749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3384408749
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1383340933
Short name T2147
Test name
Test status
Simulation time 170329216 ps
CPU time 2.12 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:26 PM PDT 24
Peak memory 204512 kb
Host smart-a7868d80-8ea9-463e-930a-c8e487bf870d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1383340933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1383340933
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3003687073
Short name T252
Test name
Test status
Simulation time 781655103 ps
CPU time 6.96 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 204520 kb
Host smart-c25e4d32-209f-4165-8940-94b017dfff42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3003687073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3003687073
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3554648243
Short name T250
Test name
Test status
Simulation time 99668444 ps
CPU time 0.85 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:20 PM PDT 24
Peak memory 204268 kb
Host smart-3dac3910-72c6-4903-b860-2faaa12ce900
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3554648243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3554648243
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2964426758
Short name T2146
Test name
Test status
Simulation time 237860319 ps
CPU time 1.84 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 217436 kb
Host smart-677069fa-20f9-4ab3-98ee-a62b117f4c7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964426758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2964426758
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.182848745
Short name T2159
Test name
Test status
Simulation time 56822287 ps
CPU time 0.82 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204196 kb
Host smart-05bbdc8a-f214-4c6d-83c6-45158590cb79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=182848745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.182848745
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1313750707
Short name T2168
Test name
Test status
Simulation time 39639087 ps
CPU time 0.68 seconds
Started Jun 11 12:35:21 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204196 kb
Host smart-5c54d7cf-3a98-40d6-85fd-6e1ee4872403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1313750707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1313750707
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1116042718
Short name T254
Test name
Test status
Simulation time 53040567 ps
CPU time 1.29 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 212532 kb
Host smart-69a132b5-9a03-40f4-a53e-16a907d39c1a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1116042718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1116042718
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2245611876
Short name T2195
Test name
Test status
Simulation time 738295127 ps
CPU time 4.49 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204364 kb
Host smart-6ec47189-0968-403e-9922-9e9241743347
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2245611876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2245611876
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3507705057
Short name T2175
Test name
Test status
Simulation time 125581661 ps
CPU time 1.27 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 204432 kb
Host smart-824f42c5-f3f0-4742-ad8a-a694afacd03d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3507705057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3507705057
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2659747622
Short name T2173
Test name
Test status
Simulation time 53702992 ps
CPU time 1.08 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204472 kb
Host smart-71ec89b7-d9f4-44dc-b7a9-83a978fe8c80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2659747622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2659747622
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3742171204
Short name T295
Test name
Test status
Simulation time 673806530 ps
CPU time 2.72 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204484 kb
Host smart-da3b9818-dbc4-42f7-b399-406bbd3ffb07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3742171204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3742171204
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.526313973
Short name T2148
Test name
Test status
Simulation time 51901231 ps
CPU time 0.63 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204064 kb
Host smart-8b8f4b50-718e-4a06-b736-5155d5994de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=526313973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.526313973
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1159269628
Short name T286
Test name
Test status
Simulation time 39312796 ps
CPU time 0.69 seconds
Started Jun 11 12:35:32 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204168 kb
Host smart-7a3a5813-3410-414c-90ea-4aa4c46780cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1159269628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1159269628
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1679263981
Short name T270
Test name
Test status
Simulation time 91266681 ps
CPU time 0.73 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:41 PM PDT 24
Peak memory 204204 kb
Host smart-d18b4e58-0989-4caf-911e-8d08b1decb2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1679263981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1679263981
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2611489422
Short name T2133
Test name
Test status
Simulation time 88818054 ps
CPU time 0.69 seconds
Started Jun 11 12:35:35 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204204 kb
Host smart-6f281660-10ff-460c-876a-e577b0f1bc3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2611489422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2611489422
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.749552641
Short name T2183
Test name
Test status
Simulation time 73899372 ps
CPU time 0.67 seconds
Started Jun 11 12:35:31 PM PDT 24
Finished Jun 11 12:35:34 PM PDT 24
Peak memory 204160 kb
Host smart-1fc7eda5-3327-497b-8058-aef305f81716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=749552641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.749552641
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1223248089
Short name T2127
Test name
Test status
Simulation time 39832752 ps
CPU time 0.65 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204140 kb
Host smart-e0942eef-97d5-4997-9dea-a59579ce1182
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1223248089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1223248089
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2661491918
Short name T2187
Test name
Test status
Simulation time 87461862 ps
CPU time 0.7 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:36 PM PDT 24
Peak memory 204160 kb
Host smart-10da5972-28d7-49f5-b884-a35394fdf19d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661491918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2661491918
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.4051754666
Short name T2171
Test name
Test status
Simulation time 33451451 ps
CPU time 0.63 seconds
Started Jun 11 12:35:36 PM PDT 24
Finished Jun 11 12:35:38 PM PDT 24
Peak memory 204456 kb
Host smart-f66b6f24-5800-4818-8b78-d20eaecd2fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4051754666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.4051754666
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4179190764
Short name T279
Test name
Test status
Simulation time 103196848 ps
CPU time 0.71 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:40 PM PDT 24
Peak memory 204180 kb
Host smart-7c5ca4b4-9d64-4df2-8e64-80bb78c99232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4179190764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4179190764
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2894715562
Short name T2167
Test name
Test status
Simulation time 203150801 ps
CPU time 2.15 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204512 kb
Host smart-daf07a20-db7f-48dd-a93b-f7e59b9dc787
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2894715562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2894715562
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1951264417
Short name T2130
Test name
Test status
Simulation time 1806425615 ps
CPU time 11.36 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:33 PM PDT 24
Peak memory 204404 kb
Host smart-a07fea64-0a3a-42b3-bbbd-bfb2ab4b02b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1951264417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1951264417
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1984721116
Short name T121
Test name
Test status
Simulation time 86442890 ps
CPU time 0.9 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204288 kb
Host smart-55ce6e89-7620-424c-af64-316aaaded3a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1984721116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1984721116
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1921708791
Short name T2193
Test name
Test status
Simulation time 109208521 ps
CPU time 1.77 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 212692 kb
Host smart-df8b8411-e76c-461b-bc3b-ece6c52b2f31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921708791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1921708791
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.827767739
Short name T2176
Test name
Test status
Simulation time 73276942 ps
CPU time 0.94 seconds
Started Jun 11 12:35:17 PM PDT 24
Finished Jun 11 12:35:20 PM PDT 24
Peak memory 204484 kb
Host smart-e24ce989-3626-4bd5-90f0-4da0d7003154
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=827767739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.827767739
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1728803953
Short name T2192
Test name
Test status
Simulation time 48780562 ps
CPU time 0.67 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204180 kb
Host smart-c5800b2c-fedd-4d9a-bf70-5c34b7ee4686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1728803953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1728803953
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3622088535
Short name T2121
Test name
Test status
Simulation time 170744493 ps
CPU time 2.35 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204416 kb
Host smart-5485d9fc-96c6-4ed0-b120-fda2197d840a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3622088535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3622088535
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3834362275
Short name T2161
Test name
Test status
Simulation time 121822819 ps
CPU time 1.13 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204512 kb
Host smart-de5b8db1-9c58-4df5-964c-9b43e1fce6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3834362275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3834362275
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.145816333
Short name T2174
Test name
Test status
Simulation time 144894734 ps
CPU time 1.67 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204388 kb
Host smart-1c1f03c5-66a0-49dc-b449-89638539a29d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=145816333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.145816333
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.4261187479
Short name T288
Test name
Test status
Simulation time 420904648 ps
CPU time 2.56 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204528 kb
Host smart-7c75848e-e4ff-4c1c-80b0-1f0102afde8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4261187479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.4261187479
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3147921464
Short name T2204
Test name
Test status
Simulation time 26896333 ps
CPU time 0.67 seconds
Started Jun 11 12:35:34 PM PDT 24
Finished Jun 11 12:35:37 PM PDT 24
Peak memory 204184 kb
Host smart-3fd82860-0623-4e6c-875a-9407b8ea81d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3147921464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3147921464
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3418103271
Short name T277
Test name
Test status
Simulation time 47763209 ps
CPU time 0.63 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:40 PM PDT 24
Peak memory 204188 kb
Host smart-a52af6b3-e263-4206-b499-41722883d48a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3418103271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3418103271
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.120144823
Short name T122
Test name
Test status
Simulation time 39970559 ps
CPU time 0.64 seconds
Started Jun 11 12:35:33 PM PDT 24
Finished Jun 11 12:35:35 PM PDT 24
Peak memory 204144 kb
Host smart-e31bd4d0-f2cd-4941-a177-dfbf9aba4045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=120144823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.120144823
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3235488006
Short name T2151
Test name
Test status
Simulation time 112427851 ps
CPU time 0.73 seconds
Started Jun 11 12:35:36 PM PDT 24
Finished Jun 11 12:35:39 PM PDT 24
Peak memory 204460 kb
Host smart-6ce580f6-e808-486f-ba49-c1ac7530ace3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235488006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3235488006
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.870033739
Short name T2213
Test name
Test status
Simulation time 48639337 ps
CPU time 0.66 seconds
Started Jun 11 12:35:37 PM PDT 24
Finished Jun 11 12:35:40 PM PDT 24
Peak memory 204208 kb
Host smart-d863205d-9b0c-4c6b-85f0-f3a222f6f5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=870033739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.870033739
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.3019524579
Short name T280
Test name
Test status
Simulation time 87309207 ps
CPU time 0.7 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:41 PM PDT 24
Peak memory 204188 kb
Host smart-985d9a97-4177-42c3-a549-fc59479d832b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3019524579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.3019524579
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3102440517
Short name T2190
Test name
Test status
Simulation time 57444974 ps
CPU time 0.65 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:40 PM PDT 24
Peak memory 204184 kb
Host smart-9e05b095-467c-4b91-936e-595c587bed6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3102440517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3102440517
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.936303549
Short name T2177
Test name
Test status
Simulation time 59571985 ps
CPU time 0.67 seconds
Started Jun 11 12:35:30 PM PDT 24
Finished Jun 11 12:35:32 PM PDT 24
Peak memory 204140 kb
Host smart-494b9e97-0900-4d3d-8deb-f6395509c31a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=936303549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.936303549
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.471919707
Short name T2154
Test name
Test status
Simulation time 39994437 ps
CPU time 0.64 seconds
Started Jun 11 12:35:38 PM PDT 24
Finished Jun 11 12:35:40 PM PDT 24
Peak memory 204208 kb
Host smart-b4129125-e209-4fb9-92cf-6f365abd3937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=471919707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.471919707
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4125328944
Short name T267
Test name
Test status
Simulation time 297943180 ps
CPU time 1.98 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:30 PM PDT 24
Peak memory 212744 kb
Host smart-3d9382b8-f385-4921-b12b-ca9dc8bcfbfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125328944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.4125328944
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.908268264
Short name T269
Test name
Test status
Simulation time 66035472 ps
CPU time 0.82 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 204264 kb
Host smart-166a2de6-2262-4329-acdf-db5514035475
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=908268264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.908268264
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3511485908
Short name T2135
Test name
Test status
Simulation time 38514175 ps
CPU time 0.66 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 204188 kb
Host smart-4f43a115-f6e0-44ed-924d-50126e03fea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3511485908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3511485908
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.4219802866
Short name T2145
Test name
Test status
Simulation time 97034003 ps
CPU time 1.07 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204368 kb
Host smart-d3aa49a4-cb45-48ff-aced-40b6af601ffb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4219802866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.4219802866
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1393524932
Short name T296
Test name
Test status
Simulation time 367048166 ps
CPU time 2.55 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:30 PM PDT 24
Peak memory 204420 kb
Host smart-e0ee6f0b-99be-4222-bd04-1e38fa5c4edf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1393524932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1393524932
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.1867481701
Short name T2196
Test name
Test status
Simulation time 112926325 ps
CPU time 1.29 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 214492 kb
Host smart-b6d305d5-0533-4fc4-b812-8b6bf6b8a925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867481701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.1867481701
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3246025138
Short name T2155
Test name
Test status
Simulation time 138537732 ps
CPU time 1.08 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 204496 kb
Host smart-739fff1f-c0b8-4d32-90b6-95b269bf456a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3246025138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3246025138
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1079196188
Short name T284
Test name
Test status
Simulation time 48253484 ps
CPU time 0.63 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204164 kb
Host smart-48be6d0f-732f-4f44-a6cf-c0407487b987
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1079196188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1079196188
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1168210418
Short name T116
Test name
Test status
Simulation time 88054175 ps
CPU time 1.38 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:23 PM PDT 24
Peak memory 204408 kb
Host smart-40fb4b52-e464-4f54-bc23-4fb6f5790b57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1168210418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1168210418
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1767859567
Short name T225
Test name
Test status
Simulation time 204665032 ps
CPU time 2.28 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:26 PM PDT 24
Peak memory 220360 kb
Host smart-f106a78a-9343-4602-81f2-ae1413f051aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1767859567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1767859567
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1915879912
Short name T2158
Test name
Test status
Simulation time 502337788 ps
CPU time 3.92 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 204316 kb
Host smart-7978498a-65eb-4421-ac81-1adc3fef6258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1915879912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1915879912
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.165935874
Short name T2134
Test name
Test status
Simulation time 169510252 ps
CPU time 2.35 seconds
Started Jun 11 12:35:24 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 212704 kb
Host smart-4e139c37-1622-4700-84f8-916b688a1faa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165935874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.165935874
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1811897021
Short name T248
Test name
Test status
Simulation time 80411751 ps
CPU time 0.94 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204404 kb
Host smart-7d4dc359-52f1-4ae9-8a83-952241bf9b0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1811897021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1811897021
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3363309468
Short name T120
Test name
Test status
Simulation time 37907003 ps
CPU time 0.69 seconds
Started Jun 11 12:35:22 PM PDT 24
Finished Jun 11 12:35:26 PM PDT 24
Peak memory 204076 kb
Host smart-7449e147-31ec-48fe-8bc2-58e73068c3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3363309468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3363309468
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2052637533
Short name T259
Test name
Test status
Simulation time 74522104 ps
CPU time 1.02 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204456 kb
Host smart-2e96e3dd-8a99-48dd-a7e4-859cd5dbc8ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2052637533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2052637533
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2098849048
Short name T2136
Test name
Test status
Simulation time 153656651 ps
CPU time 1.65 seconds
Started Jun 11 12:35:18 PM PDT 24
Finished Jun 11 12:35:21 PM PDT 24
Peak memory 212684 kb
Host smart-ad2161b7-a3fd-484e-87a3-7a01ac782006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2098849048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2098849048
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3793217836
Short name T268
Test name
Test status
Simulation time 1277348328 ps
CPU time 3.55 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 204768 kb
Host smart-d35207f8-d962-4f99-979d-6f59d7496e18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3793217836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3793217836
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2922803153
Short name T2201
Test name
Test status
Simulation time 76727115 ps
CPU time 1.56 seconds
Started Jun 11 12:35:25 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 212688 kb
Host smart-623b081d-7c27-4531-9558-9a11ef61383a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922803153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2922803153
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1343406123
Short name T255
Test name
Test status
Simulation time 61651587 ps
CPU time 0.8 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204280 kb
Host smart-c0015908-e055-493a-97a7-198a97e9fd30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1343406123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1343406123
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1029417454
Short name T2181
Test name
Test status
Simulation time 34270046 ps
CPU time 0.67 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:22 PM PDT 24
Peak memory 204156 kb
Host smart-1b00f313-a505-420d-aa78-f54093a879c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1029417454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1029417454
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4151046867
Short name T2165
Test name
Test status
Simulation time 47537969 ps
CPU time 1.06 seconds
Started Jun 11 12:35:19 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204404 kb
Host smart-aea305e5-5c2f-4365-b065-895e5da49bfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4151046867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4151046867
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3412648394
Short name T2182
Test name
Test status
Simulation time 224641815 ps
CPU time 2.34 seconds
Started Jun 11 12:35:25 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 220128 kb
Host smart-b6e8ff7e-f22d-4ec7-8d3d-f874e75277e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412648394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3412648394
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3678731706
Short name T291
Test name
Test status
Simulation time 970439852 ps
CPU time 4.15 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:32 PM PDT 24
Peak memory 204440 kb
Host smart-9c1b84e0-1727-4896-b9dd-2f548d6ad20b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3678731706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3678731706
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2028988049
Short name T2157
Test name
Test status
Simulation time 115726374 ps
CPU time 2.83 seconds
Started Jun 11 12:35:21 PM PDT 24
Finished Jun 11 12:35:27 PM PDT 24
Peak memory 212656 kb
Host smart-db9fb0c8-1d6d-45c1-a2d5-2b4136ee1230
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028988049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2028988049
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1157949293
Short name T253
Test name
Test status
Simulation time 55367767 ps
CPU time 0.77 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:24 PM PDT 24
Peak memory 204164 kb
Host smart-4bb878b3-c616-4c5c-854c-0586664b67c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1157949293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1157949293
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1517695370
Short name T2144
Test name
Test status
Simulation time 39663802 ps
CPU time 0.66 seconds
Started Jun 11 12:35:26 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 204208 kb
Host smart-d30425d8-48f3-4ab3-8aeb-a87b25ac8965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1517695370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1517695370
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2320190087
Short name T2197
Test name
Test status
Simulation time 220503655 ps
CPU time 1.29 seconds
Started Jun 11 12:35:20 PM PDT 24
Finished Jun 11 12:35:25 PM PDT 24
Peak memory 204504 kb
Host smart-5e58152a-be12-40f1-9912-6b0d26150cd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2320190087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2320190087
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1329495782
Short name T2185
Test name
Test status
Simulation time 210888268 ps
CPU time 2.36 seconds
Started Jun 11 12:35:25 PM PDT 24
Finished Jun 11 12:35:29 PM PDT 24
Peak memory 220112 kb
Host smart-a65f53d7-ae2f-45eb-8144-0f2e4d0651cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1329495782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1329495782
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3417423855
Short name T290
Test name
Test status
Simulation time 606460639 ps
CPU time 3.78 seconds
Started Jun 11 12:35:21 PM PDT 24
Finished Jun 11 12:35:28 PM PDT 24
Peak memory 204456 kb
Host smart-2a1e7548-4b08-4ba1-a308-17fe67b642f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3417423855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3417423855
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2552199854
Short name T1200
Test name
Test status
Simulation time 4262858200 ps
CPU time 4.78 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 205072 kb
Host smart-25ba1c26-371f-4dfd-b39b-dba31eed9d63
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2552199854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2552199854
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.279524340
Short name T1859
Test name
Test status
Simulation time 13421347021 ps
CPU time 12.48 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204792 kb
Host smart-a24fc856-7d2a-4832-b616-3e9036b0f0f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=279524340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.279524340
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3566398880
Short name T1235
Test name
Test status
Simulation time 23413629002 ps
CPU time 24.54 seconds
Started Jun 11 12:39:58 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 205092 kb
Host smart-f66ce148-fde7-49ee-88c0-1cc5f70844ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3566398880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3566398880
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2669059858
Short name T1117
Test name
Test status
Simulation time 149816118 ps
CPU time 0.77 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 204736 kb
Host smart-0e17eb8c-5044-4e45-b78f-077bb3612ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26690
59858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2669059858
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3373557757
Short name T1870
Test name
Test status
Simulation time 154606965 ps
CPU time 0.77 seconds
Started Jun 11 12:39:56 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 204676 kb
Host smart-33022313-c067-4d53-9005-3e74d5e063cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33735
57757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3373557757
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.290103807
Short name T1122
Test name
Test status
Simulation time 801121237 ps
CPU time 1.99 seconds
Started Jun 11 12:39:58 PM PDT 24
Finished Jun 11 12:40:02 PM PDT 24
Peak memory 205020 kb
Host smart-5965d5ec-321b-471f-8ab1-cc0ebc1731ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29010
3807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.290103807
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2832610191
Short name T87
Test name
Test status
Simulation time 144164106 ps
CPU time 0.72 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204636 kb
Host smart-15cfa3a7-6053-4bd3-a4e5-0e75bece610c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28326
10191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2832610191
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2359975165
Short name T542
Test name
Test status
Simulation time 62513794 ps
CPU time 0.66 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204596 kb
Host smart-7cd67b8f-7a62-4ee9-ad59-a33f1011e7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23599
75165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2359975165
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3555815332
Short name T1728
Test name
Test status
Simulation time 973473353 ps
CPU time 2.37 seconds
Started Jun 11 12:39:51 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 204952 kb
Host smart-fe9f557b-056d-4482-8c4c-dc503f71a2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35558
15332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3555815332
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.616122993
Short name T1189
Test name
Test status
Simulation time 467948433 ps
CPU time 2.85 seconds
Started Jun 11 12:39:50 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 204808 kb
Host smart-21228091-59d6-481d-8d9a-44492d4caa03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61612
2993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.616122993
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.966465312
Short name T1116
Test name
Test status
Simulation time 238710156 ps
CPU time 0.87 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204720 kb
Host smart-4f441019-3342-4f35-af57-71924529149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96646
5312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.966465312
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.4052482607
Short name T1479
Test name
Test status
Simulation time 292891623 ps
CPU time 1.01 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204732 kb
Host smart-99d41972-c29c-43e8-a2a5-8fa5f5fa4f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40524
82607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.4052482607
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1731669043
Short name T686
Test name
Test status
Simulation time 221433698 ps
CPU time 0.88 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204652 kb
Host smart-03742ff1-03d2-48c0-a6fe-3d28228fa55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
69043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1731669043
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.855863309
Short name T607
Test name
Test status
Simulation time 3304880188 ps
CPU time 3.88 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:40:00 PM PDT 24
Peak memory 204688 kb
Host smart-a9920bad-fd7d-4de9-970a-35f7d61a832e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85586
3309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.855863309
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3488130168
Short name T491
Test name
Test status
Simulation time 252200506 ps
CPU time 0.88 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204696 kb
Host smart-8319dd03-732a-4d95-837a-e6f6689b430b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3488130168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3488130168
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2717534377
Short name T1555
Test name
Test status
Simulation time 197211297 ps
CPU time 0.84 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204696 kb
Host smart-018543bd-39c3-45ce-8bdb-22ff979a58e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27175
34377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2717534377
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.1231301322
Short name T824
Test name
Test status
Simulation time 5300653982 ps
CPU time 50.54 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:40:47 PM PDT 24
Peak memory 204896 kb
Host smart-da6354cd-6735-4200-a09c-4d3456e21041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12313
01322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.1231301322
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3712046577
Short name T665
Test name
Test status
Simulation time 152927936 ps
CPU time 0.79 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204744 kb
Host smart-f03c6f01-6511-4a28-b17e-f0185a65074b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3712046577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3712046577
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.445701786
Short name T643
Test name
Test status
Simulation time 148359904 ps
CPU time 0.81 seconds
Started Jun 11 12:39:56 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 204748 kb
Host smart-03d2c568-91c4-43b0-ab14-1e94f11147ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44570
1786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.445701786
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.3256792110
Short name T91
Test name
Test status
Simulation time 178414985 ps
CPU time 0.86 seconds
Started Jun 11 12:39:56 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 204668 kb
Host smart-fe3a4855-8c47-4916-8c8b-fe129646fe08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32567
92110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.3256792110
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2157336462
Short name T739
Test name
Test status
Simulation time 171909012 ps
CPU time 0.8 seconds
Started Jun 11 12:39:58 PM PDT 24
Finished Jun 11 12:40:00 PM PDT 24
Peak memory 204744 kb
Host smart-321fa1e7-e262-4cd7-b204-3fc24b9fe59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21573
36462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2157336462
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1313113189
Short name T404
Test name
Test status
Simulation time 189343226 ps
CPU time 0.82 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:58 PM PDT 24
Peak memory 204688 kb
Host smart-4763d46d-8092-4830-bd45-2aa2bebf9efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131
13189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1313113189
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.3735296195
Short name T2004
Test name
Test status
Simulation time 224719783 ps
CPU time 0.89 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204728 kb
Host smart-2a014881-0a30-4032-895b-eeb3f418537e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37352
96195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.3735296195
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3166911759
Short name T1978
Test name
Test status
Simulation time 145411892 ps
CPU time 0.77 seconds
Started Jun 11 12:40:03 PM PDT 24
Finished Jun 11 12:40:04 PM PDT 24
Peak memory 204724 kb
Host smart-5b9b7775-4b01-49fe-8bca-8854e358d249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
11759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3166911759
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1112104594
Short name T772
Test name
Test status
Simulation time 33340502 ps
CPU time 0.65 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:08 PM PDT 24
Peak memory 204628 kb
Host smart-62228d71-f433-4f7d-8384-088538b8d3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11121
04594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1112104594
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.4160493790
Short name T1864
Test name
Test status
Simulation time 10891955233 ps
CPU time 25.21 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:40:22 PM PDT 24
Peak memory 205044 kb
Host smart-ed427568-096a-48c5-aa04-a3edbb6ad7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41604
93790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.4160493790
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.1776915810
Short name T1268
Test name
Test status
Simulation time 195743140 ps
CPU time 0.83 seconds
Started Jun 11 12:39:57 PM PDT 24
Finished Jun 11 12:40:00 PM PDT 24
Peak memory 204716 kb
Host smart-376b6df7-7888-443d-8793-257a4a416d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
15810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.1776915810
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1120734960
Short name T1901
Test name
Test status
Simulation time 258505565 ps
CPU time 0.93 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204732 kb
Host smart-18b2ef86-6278-40f2-b725-5b7a5037957e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
34960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1120734960
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1638885616
Short name T240
Test name
Test status
Simulation time 7668851895 ps
CPU time 120.06 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 205060 kb
Host smart-c0999646-6560-41ea-b5b1-ac935d259e15
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1638885616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1638885616
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1240290457
Short name T1230
Test name
Test status
Simulation time 22172420230 ps
CPU time 133.96 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 205296 kb
Host smart-0911b3d0-eebd-432a-9e37-44c1c72414f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1240290457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1240290457
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.85781373
Short name T421
Test name
Test status
Simulation time 185178638 ps
CPU time 0.91 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204756 kb
Host smart-f3004ef6-94c9-4c3d-8712-2001869ef1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85781
373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.85781373
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.886551366
Short name T1266
Test name
Test status
Simulation time 142002238 ps
CPU time 0.8 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:58 PM PDT 24
Peak memory 204596 kb
Host smart-35ab2eae-d104-4ce6-8bc6-2b142dc51180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88655
1366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.886551366
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2414612259
Short name T111
Test name
Test status
Simulation time 806065252 ps
CPU time 1.63 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 222404 kb
Host smart-d40349d5-fb36-475d-aeca-519a554feb3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2414612259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2414612259
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2570368073
Short name T1409
Test name
Test status
Simulation time 169304862 ps
CPU time 0.85 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 204720 kb
Host smart-a2d8d950-7825-4514-8bdb-fc79cf83b856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25703
68073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2570368073
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3039622738
Short name T323
Test name
Test status
Simulation time 203245370 ps
CPU time 0.9 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 204712 kb
Host smart-d1a59643-617b-46c5-ad4a-edb67ed638e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30396
22738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3039622738
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2601350020
Short name T1899
Test name
Test status
Simulation time 183913700 ps
CPU time 0.79 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204768 kb
Host smart-65ebb69d-c829-4d97-aeab-33fb3dce7d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26013
50020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2601350020
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1421976689
Short name T1502
Test name
Test status
Simulation time 152256735 ps
CPU time 0.82 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 204776 kb
Host smart-43bbe932-dafe-469a-b0f5-b9c4982441d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
76689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1421976689
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2246802622
Short name T6
Test name
Test status
Simulation time 11868045566 ps
CPU time 116.49 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:41:52 PM PDT 24
Peak memory 205060 kb
Host smart-9d090fe6-7ea1-444d-a28e-db10a03e3b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
02622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2246802622
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.204774065
Short name T1723
Test name
Test status
Simulation time 20721812730 ps
CPU time 176.65 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 205100 kb
Host smart-b58a9798-3b76-49a4-9a95-7c4fccd5b32f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204774065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bu
s_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_t
raffic.204774065
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1719191581
Short name T1688
Test name
Test status
Simulation time 3773982969 ps
CPU time 4.71 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 205064 kb
Host smart-4239d445-8042-42d3-9e6c-40b2a46b9d50
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1719191581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1719191581
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3013803576
Short name T854
Test name
Test status
Simulation time 13362720534 ps
CPU time 13.04 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204792 kb
Host smart-c52078ce-e676-4393-9070-2d17db3a00f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3013803576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3013803576
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2504972087
Short name T891
Test name
Test status
Simulation time 23311024759 ps
CPU time 23.8 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:35 PM PDT 24
Peak memory 204744 kb
Host smart-1d08016a-d79d-402e-adc2-8c619f215979
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2504972087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2504972087
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.39338013
Short name T1960
Test name
Test status
Simulation time 151799217 ps
CPU time 0.77 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:08 PM PDT 24
Peak memory 204736 kb
Host smart-7eadc76d-89a7-4796-8dee-f0a2d5654dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.39338013
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3443197218
Short name T65
Test name
Test status
Simulation time 157808381 ps
CPU time 0.85 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:12 PM PDT 24
Peak memory 204768 kb
Host smart-707e8275-4eb5-46d6-854e-faf7562dee2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34431
97218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3443197218
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4127931427
Short name T797
Test name
Test status
Simulation time 821236889 ps
CPU time 1.79 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 205020 kb
Host smart-73bd7e5b-2f7a-45a2-9b77-ea13a5f7a548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41279
31427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4127931427
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_enable.1603665966
Short name T2082
Test name
Test status
Simulation time 37304979 ps
CPU time 0.71 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 204708 kb
Host smart-4097b77a-8e85-4dc6-b3b5-f07803ce9afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
65966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1603665966
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2297442737
Short name T1001
Test name
Test status
Simulation time 841765637 ps
CPU time 2.21 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 204924 kb
Host smart-15585131-bec6-48b5-b5c5-5e71fd356a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22974
42737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2297442737
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2349618744
Short name T804
Test name
Test status
Simulation time 275482965 ps
CPU time 1.96 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204924 kb
Host smart-71c0319b-8420-4927-8006-79a2524038fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
18744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2349618744
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1604777445
Short name T1751
Test name
Test status
Simulation time 226622983 ps
CPU time 0.94 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 204744 kb
Host smart-ac501e70-51c4-42c6-87ac-b6d0b1aa6dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16047
77445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1604777445
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2563274681
Short name T647
Test name
Test status
Simulation time 148741308 ps
CPU time 0.73 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 204728 kb
Host smart-e0876faa-23d6-4ecf-9c52-b6a548e0d4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25632
74681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2563274681
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1176020912
Short name T1461
Test name
Test status
Simulation time 208425450 ps
CPU time 0.92 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:12 PM PDT 24
Peak memory 204672 kb
Host smart-cf11d556-6211-4b13-a83f-937508fa3491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
20912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1176020912
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.2716964346
Short name T1913
Test name
Test status
Simulation time 276190835 ps
CPU time 0.96 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 204628 kb
Host smart-ca7ed098-ba36-4014-abfb-090df03a5116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27169
64346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2716964346
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3789800165
Short name T1865
Test name
Test status
Simulation time 3322723391 ps
CPU time 3.79 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204776 kb
Host smart-9dd02056-7f90-452a-9762-9a3bcf4884ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37898
00165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3789800165
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3454642833
Short name T365
Test name
Test status
Simulation time 244341725 ps
CPU time 0.88 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204656 kb
Host smart-0e1c0ad3-525f-4017-866f-c72b94f88402
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3454642833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3454642833
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4282381792
Short name T1178
Test name
Test status
Simulation time 185932050 ps
CPU time 0.87 seconds
Started Jun 11 12:40:03 PM PDT 24
Finished Jun 11 12:40:05 PM PDT 24
Peak memory 204708 kb
Host smart-6ae23838-73f2-4b71-80b0-62ac4740ddb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
81792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4282381792
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2205591855
Short name T1045
Test name
Test status
Simulation time 9315598804 ps
CPU time 88.78 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204988 kb
Host smart-21767d84-aad1-43bc-98aa-b89203a4c155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22055
91855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2205591855
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1920891789
Short name T983
Test name
Test status
Simulation time 154955663 ps
CPU time 0.78 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204700 kb
Host smart-26193a0f-c97a-4ee9-9200-d47fa4b559c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1920891789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1920891789
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2690943032
Short name T1421
Test name
Test status
Simulation time 140066815 ps
CPU time 0.74 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 204664 kb
Host smart-ff5af2d1-e287-4954-a286-83a87b9e5019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26909
43032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2690943032
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3359547824
Short name T90
Test name
Test status
Simulation time 184378084 ps
CPU time 0.89 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 204744 kb
Host smart-9eb16227-e03b-4da0-9291-96f2fac7d7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33595
47824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3359547824
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2686545438
Short name T977
Test name
Test status
Simulation time 189956315 ps
CPU time 0.86 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:08 PM PDT 24
Peak memory 204668 kb
Host smart-58fa1165-38e2-4cb9-8187-41eaaa222614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26865
45438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2686545438
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.171296834
Short name T1884
Test name
Test status
Simulation time 194882803 ps
CPU time 0.81 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204740 kb
Host smart-d220d6ee-533d-4e87-b841-1e054fc461ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17129
6834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.171296834
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_eop_single_bit_handling.3122952823
Short name T751
Test name
Test status
Simulation time 207756732 ps
CPU time 0.91 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 204668 kb
Host smart-28a98201-aa00-4823-9f51-7771ed4b7a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31229
52823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_eop_single_bit_handling.3122952823
Directory /workspace/1.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3967502719
Short name T1405
Test name
Test status
Simulation time 148818735 ps
CPU time 0.81 seconds
Started Jun 11 12:40:10 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204732 kb
Host smart-f648ca1e-d044-4fb5-8638-88b6a154a2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39675
02719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3967502719
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1105068254
Short name T1175
Test name
Test status
Simulation time 46069968 ps
CPU time 0.65 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204676 kb
Host smart-023944d5-04cc-4e5a-9cd4-f195e9d9181c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
68254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1105068254
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1431051044
Short name T1166
Test name
Test status
Simulation time 13652665864 ps
CPU time 30.35 seconds
Started Jun 11 12:40:03 PM PDT 24
Finished Jun 11 12:40:34 PM PDT 24
Peak memory 205040 kb
Host smart-8dbdb9f9-c70e-4c3b-ac19-140dc39cf1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14310
51044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1431051044
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.457293033
Short name T1872
Test name
Test status
Simulation time 182863945 ps
CPU time 0.88 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204672 kb
Host smart-996b8c4b-c674-490c-80f2-65b826833852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45729
3033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.457293033
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1125389994
Short name T1480
Test name
Test status
Simulation time 222744863 ps
CPU time 0.87 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 204688 kb
Host smart-346adf0e-102b-4f6d-94aa-abe2b6cdf2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
89994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1125389994
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.4029840351
Short name T4
Test name
Test status
Simulation time 21913812112 ps
CPU time 174.06 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 205056 kb
Host smart-3f00cbd0-3805-4310-8a5c-9b5fe352e7a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4029840351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.4029840351
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1314682808
Short name T1894
Test name
Test status
Simulation time 19954099507 ps
CPU time 113.13 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:42:02 PM PDT 24
Peak memory 205060 kb
Host smart-b0cbbe92-7936-4b4b-be79-dc5b03a164fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1314682808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1314682808
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1142368170
Short name T1735
Test name
Test status
Simulation time 35062714555 ps
CPU time 211.07 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:43:40 PM PDT 24
Peak memory 204968 kb
Host smart-b940035c-60d7-4fd9-93ae-cf39de9dbbcd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1142368170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1142368170
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2929928914
Short name T1680
Test name
Test status
Simulation time 238204456 ps
CPU time 0.86 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204724 kb
Host smart-a3f53315-5016-43c5-8681-025225e9de1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
28914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2929928914
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2276676959
Short name T1177
Test name
Test status
Simulation time 160380851 ps
CPU time 0.81 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204684 kb
Host smart-cd3ffda0-c073-4df0-9584-7b9eb289ce29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22766
76959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2276676959
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1603671676
Short name T1739
Test name
Test status
Simulation time 194764006 ps
CPU time 0.79 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:08 PM PDT 24
Peak memory 204724 kb
Host smart-0de8d5a4-924c-4d07-8394-9497fd42aca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
71676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1603671676
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2223404541
Short name T110
Test name
Test status
Simulation time 464401713 ps
CPU time 1.34 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 222492 kb
Host smart-6340b68f-0b19-41b0-98c6-ff6b842719fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2223404541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2223404541
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2992048266
Short name T2042
Test name
Test status
Simulation time 150214317 ps
CPU time 0.76 seconds
Started Jun 11 12:40:04 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204716 kb
Host smart-10ba32bd-23d2-4636-a1de-7046383ef899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
48266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2992048266
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1191823812
Short name T2049
Test name
Test status
Simulation time 166344576 ps
CPU time 0.79 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:12 PM PDT 24
Peak memory 204624 kb
Host smart-8afa37a0-3863-485b-87c9-a4bb6a2974ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
23812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1191823812
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1709291165
Short name T1650
Test name
Test status
Simulation time 156538406 ps
CPU time 0.8 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204656 kb
Host smart-edf4706a-d2d0-434f-a6db-299fffb742f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
91165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1709291165
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.767367947
Short name T1401
Test name
Test status
Simulation time 154340119 ps
CPU time 0.91 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:12 PM PDT 24
Peak memory 204624 kb
Host smart-35f7d27c-d057-4eb5-ba91-1cbdccf90529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76736
7947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.767367947
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3491876601
Short name T400
Test name
Test status
Simulation time 12781668313 ps
CPU time 119.84 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 205024 kb
Host smart-3aa7a6ee-33be-4e3a-a9eb-1dfce5152543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34918
76601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3491876601
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1845982576
Short name T1342
Test name
Test status
Simulation time 16587741787 ps
CPU time 106.14 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:41:55 PM PDT 24
Peak memory 205000 kb
Host smart-51bbffed-df74-48fe-ad12-a324e64e1e14
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845982576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_
traffic.1845982576
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1415832795
Short name T815
Test name
Test status
Simulation time 3844691560 ps
CPU time 4.63 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 205008 kb
Host smart-171499d3-174b-4e32-a71d-436b179efdad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1415832795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1415832795
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1505595969
Short name T1144
Test name
Test status
Simulation time 13357232536 ps
CPU time 12.83 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204700 kb
Host smart-c228ea9f-732b-447e-a126-eec18750818e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1505595969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1505595969
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.3189943807
Short name T1874
Test name
Test status
Simulation time 23330913990 ps
CPU time 27.64 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:40 PM PDT 24
Peak memory 204952 kb
Host smart-0497296d-f061-4548-9ad4-3ef0469b8781
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3189943807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.3189943807
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3668478410
Short name T974
Test name
Test status
Simulation time 170754581 ps
CPU time 0.83 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204692 kb
Host smart-6459e595-affa-44b7-be0a-fff79038354f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36684
78410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3668478410
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2345902099
Short name T1334
Test name
Test status
Simulation time 197793783 ps
CPU time 0.8 seconds
Started Jun 11 12:41:00 PM PDT 24
Finished Jun 11 12:41:05 PM PDT 24
Peak memory 204700 kb
Host smart-53bd45bc-db00-4db2-a9a2-ec2211e14571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23459
02099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2345902099
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1990776493
Short name T1945
Test name
Test status
Simulation time 1003527685 ps
CPU time 2.44 seconds
Started Jun 11 12:41:23 PM PDT 24
Finished Jun 11 12:41:30 PM PDT 24
Peak memory 204908 kb
Host smart-51f37040-fcfc-4a0c-b543-14763940e468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
76493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1990776493
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2504696675
Short name T1541
Test name
Test status
Simulation time 177392601 ps
CPU time 0.83 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204648 kb
Host smart-f8db037f-955d-4c9c-aff9-b74104877224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25046
96675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2504696675
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.86686238
Short name T1234
Test name
Test status
Simulation time 41315894 ps
CPU time 0.64 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:06 PM PDT 24
Peak memory 204636 kb
Host smart-66603c51-0b71-4224-abfd-7178999c5b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86686
238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.86686238
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.425463579
Short name T1982
Test name
Test status
Simulation time 843680793 ps
CPU time 2.02 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204920 kb
Host smart-a39546ca-9036-43d1-8659-d5ae83131b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42546
3579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.425463579
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2366216894
Short name T1926
Test name
Test status
Simulation time 362187272 ps
CPU time 2.19 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:05 PM PDT 24
Peak memory 204848 kb
Host smart-2a9b9f22-f953-4689-8b52-bfb885ba0113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662
16894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2366216894
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3712733059
Short name T1822
Test name
Test status
Simulation time 225268431 ps
CPU time 0.83 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204668 kb
Host smart-6fff5e08-b56f-42a7-be31-390f784c3346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37127
33059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3712733059
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.352940197
Short name T1255
Test name
Test status
Simulation time 170280845 ps
CPU time 0.81 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204708 kb
Host smart-6099944e-bc60-420a-bda9-50c8fc36225d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294
0197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.352940197
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.482800304
Short name T2101
Test name
Test status
Simulation time 254146978 ps
CPU time 0.93 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204648 kb
Host smart-4219b212-3c7a-453f-91ca-bad9e18aa558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48280
0304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.482800304
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3832525016
Short name T1734
Test name
Test status
Simulation time 252561343 ps
CPU time 0.89 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204684 kb
Host smart-dcc88793-cd8e-45be-ba08-b4fde91a9f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38325
25016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3832525016
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1029874042
Short name T24
Test name
Test status
Simulation time 3384145686 ps
CPU time 3.7 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204716 kb
Host smart-5dcf4a5e-4e21-4ada-9188-c5bfbab07649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10298
74042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1029874042
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.4051863454
Short name T1548
Test name
Test status
Simulation time 290256918 ps
CPU time 0.93 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204740 kb
Host smart-d0911f0e-ad73-4a46-b635-491fda617f16
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4051863454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.4051863454
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2039299880
Short name T2085
Test name
Test status
Simulation time 194868797 ps
CPU time 0.92 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204700 kb
Host smart-45d3c36d-777b-4c6b-8c05-0f99f6cbee5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20392
99880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2039299880
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.6083242
Short name T394
Test name
Test status
Simulation time 9997614952 ps
CPU time 90.65 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:42:50 PM PDT 24
Peak memory 204996 kb
Host smart-dbec19bb-1da4-42d1-a070-84707e6c72ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60832
42 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.6083242
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1178311919
Short name T965
Test name
Test status
Simulation time 204883595 ps
CPU time 0.82 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204744 kb
Host smart-05691717-b9fe-4b8b-a117-71872610eb59
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1178311919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1178311919
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1966591690
Short name T1216
Test name
Test status
Simulation time 151536336 ps
CPU time 0.74 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204720 kb
Host smart-fd614388-34d7-4492-aa65-a1e14000137d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
91690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1966591690
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2595487189
Short name T1992
Test name
Test status
Simulation time 200502684 ps
CPU time 0.83 seconds
Started Jun 11 12:40:58 PM PDT 24
Finished Jun 11 12:41:03 PM PDT 24
Peak memory 204712 kb
Host smart-18e993a3-64c7-4dc7-a251-c27f8a718108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25954
87189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2595487189
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.3116605675
Short name T1323
Test name
Test status
Simulation time 234605105 ps
CPU time 0.86 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:03 PM PDT 24
Peak memory 204700 kb
Host smart-c79a6199-7bc6-4b60-8570-dea5bc9ce506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31166
05675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3116605675
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.402250140
Short name T898
Test name
Test status
Simulation time 158554706 ps
CPU time 0.79 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204552 kb
Host smart-a24e75f0-004d-4824-b4dc-c28a49c3e867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40225
0140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.402250140
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2312686910
Short name T498
Test name
Test status
Simulation time 166778306 ps
CPU time 0.82 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204528 kb
Host smart-3c2cd606-a6c5-4b46-bef8-2a74acb4976a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
86910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2312686910
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_eop_single_bit_handling.783966402
Short name T658
Test name
Test status
Simulation time 207927051 ps
CPU time 0.83 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204760 kb
Host smart-b52bdb86-dc40-4e74-bb79-630b3442fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78396
6402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_eop_single_bit_handling.783966402
Directory /workspace/10.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.290439433
Short name T1414
Test name
Test status
Simulation time 148740832 ps
CPU time 0.81 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:00 PM PDT 24
Peak memory 204748 kb
Host smart-2bd0e263-4df5-422e-8521-be169e52f4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
9433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.290439433
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.4151340161
Short name T1397
Test name
Test status
Simulation time 14974117067 ps
CPU time 32.79 seconds
Started Jun 11 12:41:00 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204956 kb
Host smart-4904c1a3-57fc-4386-b600-7ee5e8b68f95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41513
40161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.4151340161
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1351954432
Short name T1180
Test name
Test status
Simulation time 172319130 ps
CPU time 0.82 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204712 kb
Host smart-797ee383-baa7-4da4-a192-c16a9f5016bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
54432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1351954432
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1250590435
Short name T370
Test name
Test status
Simulation time 233515490 ps
CPU time 0.91 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204712 kb
Host smart-625d98a5-0e7d-4304-88a8-23a0b72b0d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
90435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1250590435
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1988949466
Short name T1904
Test name
Test status
Simulation time 153334782 ps
CPU time 0.76 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204708 kb
Host smart-d738b212-319f-4a20-83d4-0d38f2636d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19889
49466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1988949466
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.474170175
Short name T1506
Test name
Test status
Simulation time 185784280 ps
CPU time 0.86 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204672 kb
Host smart-232aaf54-10cd-4ac8-a5ef-7538c3cc0b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47417
0175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.474170175
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.982230270
Short name T1213
Test name
Test status
Simulation time 175201295 ps
CPU time 0.75 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204684 kb
Host smart-41be6f10-dbe7-4959-a6d4-047c87195565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98223
0270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.982230270
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2241948864
Short name T1222
Test name
Test status
Simulation time 153520246 ps
CPU time 0.74 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204716 kb
Host smart-85b54200-e266-4bc2-a83b-9599fd360100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
48864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2241948864
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1992018334
Short name T1620
Test name
Test status
Simulation time 138535654 ps
CPU time 0.74 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204700 kb
Host smart-d7409805-fbd0-43f1-95fd-f39206101bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19920
18334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1992018334
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.487511517
Short name T1556
Test name
Test status
Simulation time 161598909 ps
CPU time 0.8 seconds
Started Jun 11 12:40:58 PM PDT 24
Finished Jun 11 12:41:02 PM PDT 24
Peak memory 204696 kb
Host smart-e32fa5f8-1c67-4183-9710-4917191d4107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48751
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.487511517
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4033713801
Short name T922
Test name
Test status
Simulation time 172140524 ps
CPU time 0.76 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204688 kb
Host smart-414d886b-2177-4f58-aa72-ff01aaa9c06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40337
13801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4033713801
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.4046631919
Short name T1463
Test name
Test status
Simulation time 13574289031 ps
CPU time 94.81 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:42:43 PM PDT 24
Peak memory 204960 kb
Host smart-57fcc14c-034a-4bd5-a668-aab68342a57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40466
31919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.4046631919
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1637723061
Short name T775
Test name
Test status
Simulation time 4108132367 ps
CPU time 4.76 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204744 kb
Host smart-d7bfa8e0-55dd-4588-91dd-a34c9e3768a8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1637723061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.1637723061
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1558544467
Short name T2012
Test name
Test status
Simulation time 13426028931 ps
CPU time 15 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:26 PM PDT 24
Peak memory 204764 kb
Host smart-16254ebd-6f17-4714-9ecc-687f6be497e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1558544467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1558544467
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.2005449548
Short name T1211
Test name
Test status
Simulation time 23473349648 ps
CPU time 24.07 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204764 kb
Host smart-ba4a563c-5a30-42fd-9994-f4836e05c279
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2005449548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.2005449548
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4114228348
Short name T1526
Test name
Test status
Simulation time 157331025 ps
CPU time 0.8 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204712 kb
Host smart-a1362132-2541-4f16-b6fd-6f84ce2c9fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41142
28348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4114228348
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2704696402
Short name T66
Test name
Test status
Simulation time 148482587 ps
CPU time 0.82 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204772 kb
Host smart-40c17795-c974-4d0d-8828-0dcc2b89d7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046
96402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2704696402
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2159886811
Short name T2038
Test name
Test status
Simulation time 477313342 ps
CPU time 1.27 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:06 PM PDT 24
Peak memory 204708 kb
Host smart-e0bab2e2-e263-4420-a226-ac9ea565c677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21598
86811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2159886811
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1004062415
Short name T748
Test name
Test status
Simulation time 166971236 ps
CPU time 0.76 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204636 kb
Host smart-31d70796-14f4-4a7c-8870-8c04e803cba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10040
62415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1004062415
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1426543049
Short name T803
Test name
Test status
Simulation time 31161378 ps
CPU time 0.64 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204736 kb
Host smart-dca7e990-63de-44c7-9649-7a7dd4e246c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14265
43049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1426543049
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1066635563
Short name T512
Test name
Test status
Simulation time 1049770954 ps
CPU time 2.33 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204948 kb
Host smart-a7337473-3dbc-41c0-80f5-349a187b2e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10666
35563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1066635563
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1796011223
Short name T1891
Test name
Test status
Simulation time 187500348 ps
CPU time 2.19 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204904 kb
Host smart-5f0cb05b-d181-4a7a-b19e-ea63165cc068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17960
11223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1796011223
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.500761454
Short name T1030
Test name
Test status
Simulation time 223061007 ps
CPU time 0.87 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204736 kb
Host smart-3ec2feb8-8647-4282-aca5-d6f5e3f55bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50076
1454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.500761454
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3705769332
Short name T1621
Test name
Test status
Simulation time 179695504 ps
CPU time 0.76 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204716 kb
Host smart-8be6758a-ac5f-413f-89e7-824d5e5f9a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37057
69332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3705769332
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1703325199
Short name T2073
Test name
Test status
Simulation time 227302004 ps
CPU time 0.94 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204744 kb
Host smart-a6ddd549-450e-48d5-80ff-59c36608534f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
25199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1703325199
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.59160476
Short name T388
Test name
Test status
Simulation time 199075182 ps
CPU time 0.93 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204744 kb
Host smart-0fe3ec59-5d3d-44a3-a34d-343c8a377b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59160
476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.59160476
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.4147041135
Short name T326
Test name
Test status
Simulation time 3352650289 ps
CPU time 4.52 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204784 kb
Host smart-2fed1874-15e1-4fc9-8fac-4b580bd8de0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
41135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.4147041135
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2118852752
Short name T470
Test name
Test status
Simulation time 260541433 ps
CPU time 0.93 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204732 kb
Host smart-6de2aed7-fbe8-4cae-a43d-e44af72ab509
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2118852752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2118852752
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2458979419
Short name T1249
Test name
Test status
Simulation time 205610645 ps
CPU time 0.87 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204700 kb
Host smart-babaf7c3-5bb0-46ef-adeb-9d54fc65032e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24589
79419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2458979419
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3779940794
Short name T1730
Test name
Test status
Simulation time 8960283007 ps
CPU time 60.71 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 205024 kb
Host smart-78d629b6-a625-4d0f-a2f5-c9899d127c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37799
40794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3779940794
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2763062536
Short name T706
Test name
Test status
Simulation time 161366942 ps
CPU time 0.74 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204752 kb
Host smart-3d8572da-36c8-432b-a21f-977ce7de9e35
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2763062536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2763062536
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.294732065
Short name T996
Test name
Test status
Simulation time 147557518 ps
CPU time 0.76 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204632 kb
Host smart-06273232-1b3d-4dca-882a-121af431a55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29473
2065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.294732065
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.542902713
Short name T628
Test name
Test status
Simulation time 257512200 ps
CPU time 0.89 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:18 PM PDT 24
Peak memory 204588 kb
Host smart-d8674099-322d-4b84-995d-84e9eef2bbcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54290
2713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.542902713
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2202590947
Short name T500
Test name
Test status
Simulation time 176507132 ps
CPU time 0.77 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204720 kb
Host smart-0389a78e-c62a-4cc4-8f54-3319f24c7646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22025
90947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2202590947
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3480382745
Short name T2093
Test name
Test status
Simulation time 194282587 ps
CPU time 0.8 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204740 kb
Host smart-1a19559e-7cd1-4837-9e8e-ab67d5497d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34803
82745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3480382745
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.774422488
Short name T180
Test name
Test status
Simulation time 158640138 ps
CPU time 0.8 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204716 kb
Host smart-e8f96863-dcdc-4e0a-a58a-89aad261e96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77442
2488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.774422488
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_eop_single_bit_handling.3197529953
Short name T1668
Test name
Test status
Simulation time 207210110 ps
CPU time 0.9 seconds
Started Jun 11 12:41:17 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204736 kb
Host smart-db9a584f-e0df-4975-8cc7-e895bfc77b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31975
29953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_eop_single_bit_handling.3197529953
Directory /workspace/11.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2807317631
Short name T781
Test name
Test status
Simulation time 146658842 ps
CPU time 0.74 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204632 kb
Host smart-8d478ee6-82e2-458c-8aee-2a8c085391c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28073
17631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2807317631
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.824093326
Short name T25
Test name
Test status
Simulation time 58591136 ps
CPU time 0.66 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204668 kb
Host smart-607056ef-fcbc-462a-84fe-841dc6b7e34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82409
3326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.824093326
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4274684744
Short name T2081
Test name
Test status
Simulation time 19352616945 ps
CPU time 43.74 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:47 PM PDT 24
Peak memory 205016 kb
Host smart-7904334d-5a4a-4542-8b42-883ebd23f342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
84744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4274684744
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.1564238897
Short name T738
Test name
Test status
Simulation time 173999868 ps
CPU time 0.88 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:18 PM PDT 24
Peak memory 204672 kb
Host smart-e50d08bc-fe42-4da4-a269-54923a381c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15642
38897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.1564238897
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2691199553
Short name T903
Test name
Test status
Simulation time 252784612 ps
CPU time 0.94 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204720 kb
Host smart-3aef013a-ee9a-4d8d-ad0c-95741a87dfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26911
99553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2691199553
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.4151152490
Short name T1460
Test name
Test status
Simulation time 194231627 ps
CPU time 0.84 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204716 kb
Host smart-3a843f83-dcf2-485e-95c1-fe57c931f804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41511
52490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.4151152490
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1049347467
Short name T1831
Test name
Test status
Simulation time 182906525 ps
CPU time 0.84 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204744 kb
Host smart-4c47b7a3-4b4e-4277-a0da-4cee04b1c32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10493
47467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1049347467
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1978388869
Short name T1400
Test name
Test status
Simulation time 144417700 ps
CPU time 0.75 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:30 PM PDT 24
Peak memory 204700 kb
Host smart-7e567fab-b084-49ea-bba6-1b2b8adbb0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19783
88869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1978388869
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2075428929
Short name T1341
Test name
Test status
Simulation time 211577393 ps
CPU time 0.86 seconds
Started Jun 11 12:41:17 PM PDT 24
Finished Jun 11 12:41:24 PM PDT 24
Peak memory 204684 kb
Host smart-51ca33c7-07e5-4433-b170-be1c75027173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20754
28929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2075428929
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2961132014
Short name T1634
Test name
Test status
Simulation time 198476496 ps
CPU time 0.82 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204668 kb
Host smart-1806ee96-5648-47f7-81a1-a72697298d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611
32014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2961132014
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.40620364
Short name T673
Test name
Test status
Simulation time 223217734 ps
CPU time 0.92 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204704 kb
Host smart-b850fce3-205f-4590-9ab9-e709b9d48493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40620
364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.40620364
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.476203432
Short name T692
Test name
Test status
Simulation time 196273892 ps
CPU time 0.82 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204732 kb
Host smart-f5773b0c-c2ff-4aee-bbfd-7dbbc48c8ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47620
3432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.476203432
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3022359860
Short name T1826
Test name
Test status
Simulation time 161501647 ps
CPU time 0.77 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204740 kb
Host smart-97e1c718-4d7a-42b6-89ee-28f69b90c1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30223
59860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3022359860
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1655596776
Short name T933
Test name
Test status
Simulation time 14168185989 ps
CPU time 97.23 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204952 kb
Host smart-98b00225-844f-4014-9ca4-6daf76a65cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16555
96776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1655596776
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.254004963
Short name T1347
Test name
Test status
Simulation time 3605339233 ps
CPU time 5.2 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:29 PM PDT 24
Peak memory 204740 kb
Host smart-c2b922f2-22c3-4116-b930-5e43401b1967
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=254004963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.254004963
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.3816719523
Short name T371
Test name
Test status
Simulation time 13351856712 ps
CPU time 12.97 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:31 PM PDT 24
Peak memory 205044 kb
Host smart-158385d3-cdf3-467f-b6ac-e77df488b34a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3816719523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.3816719523
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3285808052
Short name T1404
Test name
Test status
Simulation time 23375372387 ps
CPU time 24.21 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 205276 kb
Host smart-6f5d8afc-5cc7-45d6-a7eb-bd61000af660
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3285808052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.3285808052
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.4123699023
Short name T1363
Test name
Test status
Simulation time 156928960 ps
CPU time 0.77 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204684 kb
Host smart-1c27c728-0aa7-4752-8a26-694bfc553263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
99023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.4123699023
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1570073929
Short name T1152
Test name
Test status
Simulation time 224119948 ps
CPU time 0.79 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204684 kb
Host smart-5c311920-c85b-4175-a441-67e4c9e5f874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700
73929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1570073929
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.528833157
Short name T890
Test name
Test status
Simulation time 603542081 ps
CPU time 1.56 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204684 kb
Host smart-d53738f8-e4d4-436e-bfe4-04d3a6feb86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52883
3157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.528833157
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3238875162
Short name T1564
Test name
Test status
Simulation time 142836957 ps
CPU time 0.73 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204748 kb
Host smart-100f7451-956b-483f-8ace-d7ffa6fcd568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32388
75162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3238875162
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3667801511
Short name T1379
Test name
Test status
Simulation time 73130971 ps
CPU time 0.71 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204744 kb
Host smart-de463dab-1f22-4536-a722-53a676d425a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36678
01511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3667801511
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3856306896
Short name T892
Test name
Test status
Simulation time 368374279 ps
CPU time 2.43 seconds
Started Jun 11 12:41:24 PM PDT 24
Finished Jun 11 12:41:31 PM PDT 24
Peak memory 205036 kb
Host smart-7a71df64-08a2-4ff1-954a-13112213105e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38563
06896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3856306896
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2869772548
Short name T1217
Test name
Test status
Simulation time 201451392 ps
CPU time 0.83 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204712 kb
Host smart-3352077b-9a90-4614-90fd-92fd4b7ed3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28697
72548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2869772548
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1637506502
Short name T1462
Test name
Test status
Simulation time 154299701 ps
CPU time 0.76 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:18 PM PDT 24
Peak memory 204636 kb
Host smart-68d53d0e-72f5-426f-800d-983e6159d309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16375
06502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1637506502
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3254776786
Short name T1674
Test name
Test status
Simulation time 260584177 ps
CPU time 0.94 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204664 kb
Host smart-8283608a-aff2-4d33-8788-dd33194cde4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
76786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3254776786
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3067949771
Short name T1818
Test name
Test status
Simulation time 176601335 ps
CPU time 0.84 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204736 kb
Host smart-89ac3fb9-4075-4c26-bec6-e1a1e3fd8b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30679
49771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3067949771
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.4186110041
Short name T968
Test name
Test status
Simulation time 3386888147 ps
CPU time 4.19 seconds
Started Jun 11 12:41:00 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204796 kb
Host smart-96cf81c2-d3d5-453d-b30a-b7bf5faa4200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41861
10041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.4186110041
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1826990210
Short name T399
Test name
Test status
Simulation time 242270180 ps
CPU time 0.9 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:16 PM PDT 24
Peak memory 204696 kb
Host smart-97415fc3-b565-490f-b537-a175b3da49c4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1826990210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1826990210
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2280035265
Short name T1055
Test name
Test status
Simulation time 192578069 ps
CPU time 0.86 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204680 kb
Host smart-e9aef1d4-5824-4971-9ecd-4bf27fa67dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22800
35265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2280035265
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1832232410
Short name T1766
Test name
Test status
Simulation time 4176903666 ps
CPU time 31.18 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 205036 kb
Host smart-317a9e90-ae66-4ef9-b2c9-e5bc59e6099b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
32410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1832232410
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.1349264941
Short name T1103
Test name
Test status
Simulation time 163666834 ps
CPU time 0.8 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204728 kb
Host smart-5f8d5be0-d562-4600-adc0-eb0948a2c3df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1349264941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.1349264941
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1540405199
Short name T1543
Test name
Test status
Simulation time 149155108 ps
CPU time 0.75 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204776 kb
Host smart-b07c7acc-6503-4109-b8a0-c220e49597a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15404
05199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1540405199
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3353255624
Short name T1275
Test name
Test status
Simulation time 261576293 ps
CPU time 0.93 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204736 kb
Host smart-66456c45-c08c-41e6-b0a3-8a092dc1169a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33532
55624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3353255624
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2696860861
Short name T1286
Test name
Test status
Simulation time 147348314 ps
CPU time 0.84 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204716 kb
Host smart-d3273ec7-50ac-42db-88e4-32883e1d0ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26968
60861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2696860861
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.4174174584
Short name T1769
Test name
Test status
Simulation time 163642989 ps
CPU time 0.83 seconds
Started Jun 11 12:41:21 PM PDT 24
Finished Jun 11 12:41:26 PM PDT 24
Peak memory 204704 kb
Host smart-5ce13eaf-209d-4489-80ff-4123b63cae4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41741
74584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.4174174584
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.4168125575
Short name T1296
Test name
Test status
Simulation time 154205771 ps
CPU time 0.76 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204632 kb
Host smart-15b6bd1f-3d5a-475f-bd46-fcfa08a7a49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41681
25575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.4168125575
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_eop_single_bit_handling.3112950715
Short name T324
Test name
Test status
Simulation time 175217463 ps
CPU time 0.85 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204728 kb
Host smart-552a2d34-6693-4352-894b-be7284cb6089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31129
50715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_eop_single_bit_handling.3112950715
Directory /workspace/12.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.4169677527
Short name T1023
Test name
Test status
Simulation time 161835520 ps
CPU time 0.74 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204760 kb
Host smart-e1ccb55e-a993-49b2-a1d7-b063120f58be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41696
77527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.4169677527
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3508068378
Short name T1535
Test name
Test status
Simulation time 35933188 ps
CPU time 0.63 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204624 kb
Host smart-89767aee-d0b8-42aa-b57d-6e308d6b6164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35080
68378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3508068378
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2828939744
Short name T779
Test name
Test status
Simulation time 188087164 ps
CPU time 0.84 seconds
Started Jun 11 12:41:23 PM PDT 24
Finished Jun 11 12:41:28 PM PDT 24
Peak memory 204720 kb
Host smart-bc51c392-caed-42b3-8139-d6ca546a56e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28289
39744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2828939744
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3033989785
Short name T1890
Test name
Test status
Simulation time 192454116 ps
CPU time 0.82 seconds
Started Jun 11 12:41:28 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204720 kb
Host smart-8806e1d6-4ee9-4342-90e9-7abfd9a6860f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30339
89785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3033989785
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.412776164
Short name T2070
Test name
Test status
Simulation time 220948104 ps
CPU time 0.9 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204756 kb
Host smart-657dccb8-a39b-485d-abcb-286a4d8f9de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41277
6164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.412776164
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3178736615
Short name T966
Test name
Test status
Simulation time 166444652 ps
CPU time 0.77 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204764 kb
Host smart-19d650e0-4e91-4429-8be5-f07a27a20eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31787
36615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3178736615
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.2331512015
Short name T1339
Test name
Test status
Simulation time 173323993 ps
CPU time 0.75 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204772 kb
Host smart-f31bc770-8e7e-4b0d-8902-2aaabed8d59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23315
12015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.2331512015
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3074570943
Short name T997
Test name
Test status
Simulation time 153078772 ps
CPU time 0.77 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204620 kb
Host smart-d80cee6a-5cd6-4998-a653-952ff36c973e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30745
70943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3074570943
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3518571556
Short name T179
Test name
Test status
Simulation time 196981552 ps
CPU time 0.86 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204704 kb
Host smart-c3098bd3-a4ce-40df-9862-cd0c39d59ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
71556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3518571556
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.607401153
Short name T1639
Test name
Test status
Simulation time 185124658 ps
CPU time 0.79 seconds
Started Jun 11 12:41:28 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204724 kb
Host smart-7c14c36a-5247-4de9-ade5-1e60d353a15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60740
1153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.607401153
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.557747981
Short name T1273
Test name
Test status
Simulation time 159320762 ps
CPU time 0.76 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:11 PM PDT 24
Peak memory 204716 kb
Host smart-9a5818c2-a4c9-456b-a9fb-87395c7d53b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55774
7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.557747981
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3775828194
Short name T735
Test name
Test status
Simulation time 11961581799 ps
CPU time 82.99 seconds
Started Jun 11 12:41:25 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 205028 kb
Host smart-dc6c36b6-bcdd-42d4-97ea-389c6d52c6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
28194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3775828194
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.981779721
Short name T1597
Test name
Test status
Simulation time 3775340575 ps
CPU time 5.21 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204808 kb
Host smart-00bf8761-23d5-4fcd-9229-310dfdb31126
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=981779721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.981779721
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2861298865
Short name T382
Test name
Test status
Simulation time 13367718231 ps
CPU time 13.23 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 205032 kb
Host smart-a71647d6-e0a9-44ea-b53a-0aff79826a28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2861298865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2861298865
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.357295954
Short name T590
Test name
Test status
Simulation time 23382909158 ps
CPU time 25.2 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:38 PM PDT 24
Peak memory 204768 kb
Host smart-6b0d27df-20e8-4155-9b0b-7697baa74dfd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=357295954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.357295954
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.111566014
Short name T1967
Test name
Test status
Simulation time 188401037 ps
CPU time 0.78 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204700 kb
Host smart-2f2963d0-cdc0-45ce-b62a-64a724c7bec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11156
6014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.111566014
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3696238686
Short name T578
Test name
Test status
Simulation time 143306437 ps
CPU time 0.75 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:18 PM PDT 24
Peak memory 204660 kb
Host smart-8334b601-9c1f-45dd-8d5d-9a8c47cbf4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36962
38686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3696238686
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.4114581953
Short name T670
Test name
Test status
Simulation time 1335108016 ps
CPU time 2.92 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204960 kb
Host smart-0d86c884-b3f0-4671-b98f-98a9c77aaa42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41145
81953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.4114581953
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1165516476
Short name T75
Test name
Test status
Simulation time 163836119 ps
CPU time 0.75 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204716 kb
Host smart-4a049524-1fbd-4550-ae1b-d456ea1d8604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11655
16476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1165516476
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2866836956
Short name T1264
Test name
Test status
Simulation time 44253646 ps
CPU time 0.65 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204684 kb
Host smart-07155a8f-e6f4-4ef7-b175-bc93070b9805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
36956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2866836956
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2882779079
Short name T749
Test name
Test status
Simulation time 1001410001 ps
CPU time 2.22 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204908 kb
Host smart-fccea55c-2736-40e2-890b-461469b96766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28827
79079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2882779079
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2786815957
Short name T1714
Test name
Test status
Simulation time 253083690 ps
CPU time 1.45 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204844 kb
Host smart-f5b43597-85ce-4f79-93d3-8904c78dd5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868
15957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2786815957
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2809273740
Short name T1325
Test name
Test status
Simulation time 193880729 ps
CPU time 0.88 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204704 kb
Host smart-b0ed3135-476d-43dd-aa9a-5c72afbc5ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28092
73740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2809273740
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3327367610
Short name T1000
Test name
Test status
Simulation time 161755260 ps
CPU time 0.77 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204736 kb
Host smart-31a36d02-41cc-45d9-9e05-0373cd054c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33273
67610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3327367610
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4145774665
Short name T1485
Test name
Test status
Simulation time 199135465 ps
CPU time 0.93 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204660 kb
Host smart-e1f2a90d-46f9-4003-8bb1-6ef0c206433c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
74665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4145774665
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.2785987281
Short name T694
Test name
Test status
Simulation time 209482641 ps
CPU time 0.86 seconds
Started Jun 11 12:41:26 PM PDT 24
Finished Jun 11 12:41:31 PM PDT 24
Peak memory 204764 kb
Host smart-03bda0c7-cb97-48bb-87ad-118124089ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
87281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.2785987281
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3871484703
Short name T1636
Test name
Test status
Simulation time 3315679579 ps
CPU time 4.4 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:24 PM PDT 24
Peak memory 204756 kb
Host smart-24e3cc0f-5dcb-4c5c-9662-cf7f708aba20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714
84703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3871484703
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1880703005
Short name T327
Test name
Test status
Simulation time 234280900 ps
CPU time 0.93 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 205008 kb
Host smart-a9657123-e028-478d-b1db-f4344b85b70f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1880703005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1880703005
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.290517393
Short name T532
Test name
Test status
Simulation time 201751542 ps
CPU time 0.91 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204992 kb
Host smart-12fdcd2a-a0ac-4d58-9388-58c2ab706891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29051
7393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.290517393
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.833245161
Short name T1940
Test name
Test status
Simulation time 12151769109 ps
CPU time 115.82 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204992 kb
Host smart-da6cefe7-3a0b-4c84-9654-841e8408108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83324
5161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.833245161
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2442457138
Short name T904
Test name
Test status
Simulation time 223403865 ps
CPU time 0.83 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204692 kb
Host smart-67381f58-7f68-4431-9280-8e200a47a5a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2442457138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2442457138
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1286078094
Short name T1283
Test name
Test status
Simulation time 141559811 ps
CPU time 0.76 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:17 PM PDT 24
Peak memory 204772 kb
Host smart-0c9f9021-83ba-4af7-86c2-49e185480b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12860
78094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1286078094
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2760928498
Short name T1706
Test name
Test status
Simulation time 226688530 ps
CPU time 0.92 seconds
Started Jun 11 12:41:23 PM PDT 24
Finished Jun 11 12:41:28 PM PDT 24
Peak memory 204776 kb
Host smart-1c1c5787-5add-4f48-9984-5110b0eed9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27609
28498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2760928498
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3849914107
Short name T625
Test name
Test status
Simulation time 209023973 ps
CPU time 0.84 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204684 kb
Host smart-053a7c9e-2551-4b15-8dfb-403fd8f84dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499
14107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3849914107
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.634321487
Short name T1830
Test name
Test status
Simulation time 208048480 ps
CPU time 0.84 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204736 kb
Host smart-98cbcb77-18ee-4ce1-9e08-ad2b51859b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63432
1487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.634321487
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2401334466
Short name T1809
Test name
Test status
Simulation time 174731581 ps
CPU time 0.81 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204728 kb
Host smart-0aa67f25-8f84-4b9a-b0fd-8ad0d8714f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24013
34466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2401334466
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.622053136
Short name T30
Test name
Test status
Simulation time 145915611 ps
CPU time 0.81 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204720 kb
Host smart-ff02591f-6ec0-4e0c-a6c5-6d3b28127577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62205
3136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.622053136
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_eop_single_bit_handling.2957027596
Short name T586
Test name
Test status
Simulation time 185596842 ps
CPU time 0.85 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204980 kb
Host smart-6ffa6318-a0e3-4585-b8a7-c8e7c16a3de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570
27596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_eop_single_bit_handling.2957027596
Directory /workspace/13.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.364855180
Short name T798
Test name
Test status
Simulation time 148915174 ps
CPU time 0.72 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204744 kb
Host smart-a3b70efd-531f-48e0-bd03-91da11ee2718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36485
5180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.364855180
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1011200056
Short name T2065
Test name
Test status
Simulation time 27616066 ps
CPU time 0.63 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204656 kb
Host smart-3c265af0-6f42-42ef-a986-bd8aadf0637f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10112
00056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1011200056
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1561678423
Short name T39
Test name
Test status
Simulation time 13608621377 ps
CPU time 34.7 seconds
Started Jun 11 12:41:29 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204972 kb
Host smart-f49e7f69-e12c-46a8-8562-1f98f83a32cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616
78423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1561678423
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.4289278170
Short name T359
Test name
Test status
Simulation time 196411247 ps
CPU time 0.88 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204652 kb
Host smart-94c60feb-91c3-4500-97e8-3f21099855b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42892
78170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.4289278170
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3304237120
Short name T1694
Test name
Test status
Simulation time 239142183 ps
CPU time 0.87 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204696 kb
Host smart-be954384-7bcf-40ed-87a4-4fd9d846b8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33042
37120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3304237120
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.178930036
Short name T2076
Test name
Test status
Simulation time 163154357 ps
CPU time 0.78 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204728 kb
Host smart-b7e11d3a-f3a0-4605-b4e3-47582877e5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17893
0036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.178930036
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2705113365
Short name T332
Test name
Test status
Simulation time 172433525 ps
CPU time 0.82 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204748 kb
Host smart-5ecae0a2-5bb9-49e1-bb04-f74204c6e7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27051
13365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2705113365
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2335455975
Short name T2052
Test name
Test status
Simulation time 161356901 ps
CPU time 0.77 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204724 kb
Host smart-34196f60-1bbd-4f11-a64e-fb518735993e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23354
55975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2335455975
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.15505176
Short name T2078
Test name
Test status
Simulation time 161192561 ps
CPU time 0.78 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204736 kb
Host smart-32e0416b-59b3-40b4-a77f-43c26422f7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15505
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.15505176
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3086463226
Short name T698
Test name
Test status
Simulation time 191284577 ps
CPU time 0.85 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204708 kb
Host smart-6151c010-a3f8-471a-bb4e-681c7b98b3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864
63226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3086463226
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3346523360
Short name T1071
Test name
Test status
Simulation time 188722810 ps
CPU time 0.79 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204756 kb
Host smart-8eef5627-3b01-43c5-9148-2b12b728502c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33465
23360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3346523360
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.2314481199
Short name T1755
Test name
Test status
Simulation time 4031159859 ps
CPU time 111.41 seconds
Started Jun 11 12:41:33 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 205052 kb
Host smart-b9cfca02-1c02-4f69-8487-b363f56cb62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23144
81199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.2314481199
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1339697697
Short name T218
Test name
Test status
Simulation time 13448498771 ps
CPU time 12.91 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204808 kb
Host smart-4b79a2fd-886b-4bb5-84bc-0e3245210761
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1339697697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1339697697
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1662456749
Short name T1320
Test name
Test status
Simulation time 23426326784 ps
CPU time 22.55 seconds
Started Jun 11 12:41:21 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 204996 kb
Host smart-9f328e2f-ce26-4072-a62e-4fdb24284a3b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1662456749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1662456749
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.81480748
Short name T1986
Test name
Test status
Simulation time 162691065 ps
CPU time 0.81 seconds
Started Jun 11 12:41:32 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204700 kb
Host smart-a48e6305-ffd9-4822-94e3-0b31dfe058f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81480
748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.81480748
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.4171564803
Short name T1696
Test name
Test status
Simulation time 155761133 ps
CPU time 0.81 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204704 kb
Host smart-b734826f-84b3-4a41-b7c4-6a3dc87e229f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715
64803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.4171564803
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.4174861204
Short name T1532
Test name
Test status
Simulation time 376981988 ps
CPU time 1.24 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204720 kb
Host smart-08b1f066-3257-4e76-8db1-197a752fb1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41748
61204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.4174861204
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.992861998
Short name T666
Test name
Test status
Simulation time 144071657 ps
CPU time 0.74 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 204580 kb
Host smart-07faed8d-80a7-4393-8cdf-a557e522d16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99286
1998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.992861998
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.248019077
Short name T1838
Test name
Test status
Simulation time 92362780 ps
CPU time 0.73 seconds
Started Jun 11 12:41:24 PM PDT 24
Finished Jun 11 12:41:29 PM PDT 24
Peak memory 204708 kb
Host smart-b386b070-3f09-4a82-a674-7bc9803c2e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
9077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.248019077
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1581141514
Short name T2066
Test name
Test status
Simulation time 728935728 ps
CPU time 1.9 seconds
Started Jun 11 12:41:17 PM PDT 24
Finished Jun 11 12:41:24 PM PDT 24
Peak memory 204932 kb
Host smart-967041d6-d190-45c7-9dbf-f88d62b14dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15811
41514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1581141514
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3889986389
Short name T1412
Test name
Test status
Simulation time 263351008 ps
CPU time 1.94 seconds
Started Jun 11 12:41:20 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204932 kb
Host smart-040ec063-dc79-470d-aeef-f6ef2542c315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38899
86389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3889986389
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1865676197
Short name T1655
Test name
Test status
Simulation time 214939324 ps
CPU time 0.86 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:42:40 PM PDT 24
Peak memory 204576 kb
Host smart-15ea736c-54ab-4d5b-abfe-d553415af02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18656
76197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1865676197
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.4143193232
Short name T881
Test name
Test status
Simulation time 191585157 ps
CPU time 0.78 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204608 kb
Host smart-00223eb0-a644-4f7b-ba25-b6266ee294ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41431
93232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.4143193232
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3815532258
Short name T309
Test name
Test status
Simulation time 188726818 ps
CPU time 0.89 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204692 kb
Host smart-0d3a7917-d8ae-4373-a792-316d046e65d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38155
32258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3815532258
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.2725574747
Short name T1759
Test name
Test status
Simulation time 182574722 ps
CPU time 0.8 seconds
Started Jun 11 12:41:17 PM PDT 24
Finished Jun 11 12:41:24 PM PDT 24
Peak memory 204756 kb
Host smart-2902b10c-7c22-48e1-be9b-30df714995d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
74747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.2725574747
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.3721181131
Short name T1520
Test name
Test status
Simulation time 3335171209 ps
CPU time 3.86 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:28 PM PDT 24
Peak memory 204792 kb
Host smart-4d5243b6-dcb6-43e7-aa1e-1218d6847367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37211
81131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3721181131
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1587870227
Short name T805
Test name
Test status
Simulation time 232383804 ps
CPU time 0.84 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204580 kb
Host smart-7791211c-8991-4210-9d7c-b73ae3fb0b8e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1587870227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1587870227
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2799278006
Short name T1319
Test name
Test status
Simulation time 204277948 ps
CPU time 0.87 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204992 kb
Host smart-0e3f9e32-dbe2-49ab-a7d9-101f17b791d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27992
78006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2799278006
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.177022804
Short name T2029
Test name
Test status
Simulation time 13286840985 ps
CPU time 129.73 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:43:30 PM PDT 24
Peak memory 205280 kb
Host smart-d7e4b852-1732-464e-a192-acd9cf268488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17702
2804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.177022804
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.4044729059
Short name T747
Test name
Test status
Simulation time 161212587 ps
CPU time 0.79 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204736 kb
Host smart-2b2c6fcd-da85-40e4-804d-77614232630f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4044729059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.4044729059
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.994764177
Short name T236
Test name
Test status
Simulation time 157564217 ps
CPU time 0.79 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204708 kb
Host smart-48c80383-e49c-4669-a700-ea2eaf80ca3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99476
4177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.994764177
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.3252599263
Short name T874
Test name
Test status
Simulation time 178627192 ps
CPU time 0.91 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204712 kb
Host smart-99b7512e-61ed-476d-80dc-bb0de309a82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
99263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3252599263
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1728936994
Short name T1028
Test name
Test status
Simulation time 186140020 ps
CPU time 0.8 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204728 kb
Host smart-94b090f2-cfb7-4be7-84f2-b430c3936071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17289
36994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1728936994
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1687129399
Short name T1705
Test name
Test status
Simulation time 198357340 ps
CPU time 0.81 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:38 PM PDT 24
Peak memory 204580 kb
Host smart-1c496816-0a96-44c7-9b2d-9958014dce5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16871
29399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1687129399
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_eop_single_bit_handling.43926947
Short name T1253
Test name
Test status
Simulation time 156369907 ps
CPU time 0.79 seconds
Started Jun 11 12:41:21 PM PDT 24
Finished Jun 11 12:41:26 PM PDT 24
Peak memory 204700 kb
Host smart-c146da71-fde3-4f20-8a59-65e66a0c7c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43926
947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_eop_single_bit_handling.43926947
Directory /workspace/14.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4206740731
Short name T912
Test name
Test status
Simulation time 186185261 ps
CPU time 0.77 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204700 kb
Host smart-9800a90f-35a0-4a78-a195-cc6802b11032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
40731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4206740731
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3117188663
Short name T487
Test name
Test status
Simulation time 33876567 ps
CPU time 0.6 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204572 kb
Host smart-dd8a19f4-bcde-46d6-a15f-89ced679c545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31171
88663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3117188663
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.1139550860
Short name T2036
Test name
Test status
Simulation time 19188210405 ps
CPU time 41.8 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:42:05 PM PDT 24
Peak memory 205076 kb
Host smart-3b6fadfd-4cb3-4f31-acef-cc373daed916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395
50860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.1139550860
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3609437089
Short name T1145
Test name
Test status
Simulation time 148404214 ps
CPU time 0.74 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:42:40 PM PDT 24
Peak memory 204580 kb
Host smart-29a095cf-8632-4406-84d5-d302efb9e3ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
37089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3609437089
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3961347804
Short name T1079
Test name
Test status
Simulation time 234550535 ps
CPU time 0.97 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204696 kb
Host smart-b038a79a-d043-4382-af05-563851af777c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
47804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3961347804
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2900542476
Short name T300
Test name
Test status
Simulation time 247256273 ps
CPU time 0.87 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204572 kb
Host smart-40c84501-3891-4008-98da-109406e43655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29005
42476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2900542476
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.1888136422
Short name T573
Test name
Test status
Simulation time 156555321 ps
CPU time 0.75 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204584 kb
Host smart-7a8eb12a-b69f-41ac-b9f7-e485f5ccdd06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18881
36422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.1888136422
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2470035579
Short name T931
Test name
Test status
Simulation time 147234545 ps
CPU time 0.76 seconds
Started Jun 11 12:41:21 PM PDT 24
Finished Jun 11 12:41:26 PM PDT 24
Peak memory 204696 kb
Host smart-11041b8a-642f-49af-b991-2633f13612d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24700
35579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2470035579
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1051152014
Short name T1337
Test name
Test status
Simulation time 151374204 ps
CPU time 0.8 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 204612 kb
Host smart-80349f7a-838e-4ec9-9ddc-becd4d962edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10511
52014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1051152014
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1356053966
Short name T571
Test name
Test status
Simulation time 147384878 ps
CPU time 0.75 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 204584 kb
Host smart-0da3e5ca-fa1d-4549-b020-096848977666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
53966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1356053966
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2721686750
Short name T1475
Test name
Test status
Simulation time 191680448 ps
CPU time 0.89 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204728 kb
Host smart-f746695f-b28c-428a-a7da-2598e0f6ad11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27216
86750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2721686750
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2005918353
Short name T484
Test name
Test status
Simulation time 173161259 ps
CPU time 0.78 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204692 kb
Host smart-479cbab6-f205-43ed-9591-0987df5535cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20059
18353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2005918353
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2607653330
Short name T1905
Test name
Test status
Simulation time 145454969 ps
CPU time 0.85 seconds
Started Jun 11 12:42:15 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 203776 kb
Host smart-eb1c3e79-ba47-45a4-bcee-b6025c603fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
53330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2607653330
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2465350698
Short name T477
Test name
Test status
Simulation time 14305740494 ps
CPU time 375.08 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 205044 kb
Host smart-e1350c91-d46e-4769-8d45-3649424b527e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24653
50698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2465350698
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1873036280
Short name T601
Test name
Test status
Simulation time 4338995532 ps
CPU time 5.24 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:29 PM PDT 24
Peak memory 204880 kb
Host smart-9a23bb40-850f-4797-bacb-71a48735dde9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1873036280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1873036280
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3169468197
Short name T1386
Test name
Test status
Simulation time 13418905515 ps
CPU time 14.18 seconds
Started Jun 11 12:41:26 PM PDT 24
Finished Jun 11 12:41:44 PM PDT 24
Peak memory 204832 kb
Host smart-6b45e1c4-fb67-4f52-b954-75c855ec0c76
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3169468197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3169468197
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.943003164
Short name T1131
Test name
Test status
Simulation time 23340038905 ps
CPU time 24.07 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:43 PM PDT 24
Peak memory 204772 kb
Host smart-acd5ce10-ce96-4ba5-91c6-12e432ff5851
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=943003164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.943003164
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3191541296
Short name T1758
Test name
Test status
Simulation time 159482120 ps
CPU time 0.82 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204724 kb
Host smart-c92ea82b-07bf-4cf5-a3af-b50413fd0b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
41296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3191541296
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2902493315
Short name T806
Test name
Test status
Simulation time 825902853 ps
CPU time 2.08 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:28 PM PDT 24
Peak memory 204824 kb
Host smart-358d5fea-d350-418f-a9bc-ea78df8acddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29024
93315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2902493315
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2630433855
Short name T392
Test name
Test status
Simulation time 142508274 ps
CPU time 0.77 seconds
Started Jun 11 12:41:21 PM PDT 24
Finished Jun 11 12:41:26 PM PDT 24
Peak memory 204976 kb
Host smart-a4f8847c-4d48-454d-a022-20a386d9f044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26304
33855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2630433855
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3564442086
Short name T1043
Test name
Test status
Simulation time 115667028 ps
CPU time 0.68 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:41:16 PM PDT 24
Peak memory 204732 kb
Host smart-c08533e3-31a5-4cbf-894c-f9fb802c93ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35644
42086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3564442086
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1527799333
Short name T893
Test name
Test status
Simulation time 829396931 ps
CPU time 1.99 seconds
Started Jun 11 12:41:30 PM PDT 24
Finished Jun 11 12:41:36 PM PDT 24
Peak memory 204980 kb
Host smart-ff98034e-ce58-4a5b-b9ac-9105cdf22812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
99333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1527799333
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1696994731
Short name T588
Test name
Test status
Simulation time 168422056 ps
CPU time 1.4 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204936 kb
Host smart-ceb53b72-56d3-4b92-93c2-db73c0b18b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
94731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1696994731
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2107076958
Short name T1011
Test name
Test status
Simulation time 227451083 ps
CPU time 0.87 seconds
Started Jun 11 12:41:24 PM PDT 24
Finished Jun 11 12:41:29 PM PDT 24
Peak memory 204668 kb
Host smart-46cb33ad-7734-4ed7-9a91-3b71cd340302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21070
76958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2107076958
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3994246263
Short name T1907
Test name
Test status
Simulation time 149279968 ps
CPU time 0.78 seconds
Started Jun 11 12:41:22 PM PDT 24
Finished Jun 11 12:41:27 PM PDT 24
Peak memory 204724 kb
Host smart-d9256457-8e17-4759-a26d-a3dc89cef613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39942
46263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3994246263
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2038864139
Short name T1832
Test name
Test status
Simulation time 212952723 ps
CPU time 0.93 seconds
Started Jun 11 12:41:15 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204720 kb
Host smart-ddab916b-c0cf-4dd4-a0b2-c9944f6606e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20388
64139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2038864139
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3625586546
Short name T129
Test name
Test status
Simulation time 174310185 ps
CPU time 0.82 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204764 kb
Host smart-e7461398-d66d-4a35-8b97-76e12d5bd91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36255
86546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3625586546
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.525460053
Short name T584
Test name
Test status
Simulation time 3329502337 ps
CPU time 3.89 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204756 kb
Host smart-cb77176e-98c2-4251-b6b2-15e1168d1d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52546
0053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.525460053
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3353528662
Short name T612
Test name
Test status
Simulation time 291019783 ps
CPU time 0.96 seconds
Started Jun 11 12:41:39 PM PDT 24
Finished Jun 11 12:41:43 PM PDT 24
Peak memory 204656 kb
Host smart-18eb948e-4e81-4ca5-b2e3-e22c7aa46784
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3353528662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3353528662
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1760307617
Short name T808
Test name
Test status
Simulation time 192892114 ps
CPU time 0.86 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204740 kb
Host smart-ba80b4d0-9409-4827-9e26-cd7e9dac6209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17603
07617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1760307617
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1186849845
Short name T1415
Test name
Test status
Simulation time 14855171649 ps
CPU time 397.17 seconds
Started Jun 11 12:41:12 PM PDT 24
Finished Jun 11 12:47:53 PM PDT 24
Peak memory 204992 kb
Host smart-1850a9f5-5425-4afe-972b-f3ee3f148862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11868
49845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1186849845
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1134336776
Short name T1133
Test name
Test status
Simulation time 205611387 ps
CPU time 0.79 seconds
Started Jun 11 12:41:33 PM PDT 24
Finished Jun 11 12:41:38 PM PDT 24
Peak memory 204716 kb
Host smart-bffb16b2-49fb-46e7-97e0-8280a23f0135
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1134336776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1134336776
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3841033535
Short name T718
Test name
Test status
Simulation time 164435724 ps
CPU time 0.77 seconds
Started Jun 11 12:41:14 PM PDT 24
Finished Jun 11 12:41:20 PM PDT 24
Peak memory 204748 kb
Host smart-3b3a97d2-07cf-425b-893e-53419d2a277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38410
33535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3841033535
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.2516439305
Short name T1500
Test name
Test status
Simulation time 222128809 ps
CPU time 0.89 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204732 kb
Host smart-945bdaad-01f7-40be-b83d-bd840b0eb6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25164
39305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2516439305
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3692019482
Short name T549
Test name
Test status
Simulation time 179328513 ps
CPU time 0.87 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204736 kb
Host smart-38c9822b-594d-484c-8f4e-02e22437d5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36920
19482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3692019482
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3398943142
Short name T2008
Test name
Test status
Simulation time 203434912 ps
CPU time 0.89 seconds
Started Jun 11 12:41:18 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204668 kb
Host smart-8e49b002-5fa1-4d51-8b95-f025cf800304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33989
43142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3398943142
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3607515371
Short name T1968
Test name
Test status
Simulation time 216405311 ps
CPU time 0.82 seconds
Started Jun 11 12:41:32 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204748 kb
Host smart-c9cb4e05-2a36-4283-aff3-5536743fc905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075
15371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3607515371
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.533715382
Short name T906
Test name
Test status
Simulation time 168491303 ps
CPU time 0.79 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204740 kb
Host smart-3a4a1547-b0d2-4b7b-bf41-c07a48109bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53371
5382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.533715382
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_eop_single_bit_handling.1468687688
Short name T531
Test name
Test status
Simulation time 166306696 ps
CPU time 0.8 seconds
Started Jun 11 12:41:30 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204736 kb
Host smart-56346fdd-90b1-4ada-8cb4-4f8d111ffd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14686
87688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_eop_single_bit_handling.1468687688
Directory /workspace/15.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3541004580
Short name T1080
Test name
Test status
Simulation time 164187020 ps
CPU time 0.78 seconds
Started Jun 11 12:41:41 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 204740 kb
Host smart-8a5ee449-51d3-42bc-a717-127da69edc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410
04580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3541004580
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1959629643
Short name T575
Test name
Test status
Simulation time 41102909 ps
CPU time 0.65 seconds
Started Jun 11 12:41:32 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204564 kb
Host smart-875acb0f-6042-4072-a648-c4acddb03767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19596
29643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1959629643
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.1276422362
Short name T237
Test name
Test status
Simulation time 21793843545 ps
CPU time 48.09 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 204988 kb
Host smart-7fb95fd3-cf75-4eda-99d2-c197e6aecceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12764
22362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.1276422362
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.322584344
Short name T429
Test name
Test status
Simulation time 166606198 ps
CPU time 0.77 seconds
Started Jun 11 12:41:29 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204628 kb
Host smart-71b985f2-5c64-4793-8086-1ba118306e57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32258
4344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.322584344
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.3134196621
Short name T621
Test name
Test status
Simulation time 184892404 ps
CPU time 0.85 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:18 PM PDT 24
Peak memory 204624 kb
Host smart-272b9b8c-0b3f-47c6-bff0-a39110577444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31341
96621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.3134196621
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3595540707
Short name T1756
Test name
Test status
Simulation time 216598300 ps
CPU time 0.86 seconds
Started Jun 11 12:41:30 PM PDT 24
Finished Jun 11 12:41:35 PM PDT 24
Peak memory 204768 kb
Host smart-1d3e3776-dd66-4281-98ef-18f5aeb8493a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35955
40707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3595540707
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2923943661
Short name T1311
Test name
Test status
Simulation time 170138115 ps
CPU time 0.78 seconds
Started Jun 11 12:41:32 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204748 kb
Host smart-0c1bdf8d-2096-4ab4-88b0-c048505ab88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
43661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2923943661
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1357186100
Short name T1590
Test name
Test status
Simulation time 175603596 ps
CPU time 0.79 seconds
Started Jun 11 12:41:29 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204756 kb
Host smart-fea183be-555e-4a54-a284-4a9a5c4e7e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13571
86100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1357186100
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2229776801
Short name T1142
Test name
Test status
Simulation time 162209340 ps
CPU time 0.78 seconds
Started Jun 11 12:41:29 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204704 kb
Host smart-c93b1a03-428d-4e0e-b23f-0d10713abdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22297
76801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2229776801
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.4245410381
Short name T2
Test name
Test status
Simulation time 151617999 ps
CPU time 0.84 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 204660 kb
Host smart-2f011389-a88e-4798-a89c-9cace4e7c7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42454
10381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.4245410381
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.512726851
Short name T828
Test name
Test status
Simulation time 224888073 ps
CPU time 0.95 seconds
Started Jun 11 12:41:35 PM PDT 24
Finished Jun 11 12:41:40 PM PDT 24
Peak memory 204712 kb
Host smart-8a275266-3735-493d-b767-93a31ce546c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51272
6851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.512726851
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2650006373
Short name T1644
Test name
Test status
Simulation time 189352765 ps
CPU time 0.8 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204732 kb
Host smart-9bf2ec6a-0cd1-45f3-a823-c62b8dab7325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26500
06373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2650006373
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3369712158
Short name T856
Test name
Test status
Simulation time 193086213 ps
CPU time 0.82 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204764 kb
Host smart-0351cc6f-9d67-41ef-b749-dbc9f3e549f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
12158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3369712158
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.130953297
Short name T942
Test name
Test status
Simulation time 13975716764 ps
CPU time 124.22 seconds
Started Jun 11 12:41:36 PM PDT 24
Finished Jun 11 12:43:44 PM PDT 24
Peak memory 205060 kb
Host smart-35345070-555b-4897-ba99-1f5a944fdd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
3297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.130953297
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3419641512
Short name T1335
Test name
Test status
Simulation time 4374071891 ps
CPU time 5.56 seconds
Started Jun 11 12:41:30 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 205024 kb
Host smart-d8028ec3-a98a-43e6-9fa7-643cacd768e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3419641512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3419641512
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1567401007
Short name T1366
Test name
Test status
Simulation time 13355282725 ps
CPU time 15.29 seconds
Started Jun 11 12:41:32 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 205036 kb
Host smart-5552f360-0745-447d-aab8-c2b405824863
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1567401007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1567401007
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.461877717
Short name T1024
Test name
Test status
Simulation time 23356463696 ps
CPU time 24.27 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:42:02 PM PDT 24
Peak memory 204780 kb
Host smart-b3b5a7b5-abf0-4a8a-b346-eef4d5dbba01
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=461877717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.461877717
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.2629429111
Short name T1303
Test name
Test status
Simulation time 155706266 ps
CPU time 0.79 seconds
Started Jun 11 12:41:39 PM PDT 24
Finished Jun 11 12:41:43 PM PDT 24
Peak memory 204708 kb
Host smart-6f7e4a96-ee06-4b59-a334-8c607b8e98df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26294
29111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2629429111
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.63552105
Short name T1835
Test name
Test status
Simulation time 167725159 ps
CPU time 0.79 seconds
Started Jun 11 12:41:31 PM PDT 24
Finished Jun 11 12:41:36 PM PDT 24
Peak memory 204784 kb
Host smart-6a5da5cf-b940-4ef8-acb9-ab7391a67250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63552
105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.63552105
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3962703789
Short name T71
Test name
Test status
Simulation time 1333773110 ps
CPU time 3.13 seconds
Started Jun 11 12:41:40 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204904 kb
Host smart-87d29458-7822-4900-ad3b-8b24d29e656a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39627
03789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3962703789
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3827941984
Short name T1630
Test name
Test status
Simulation time 175800963 ps
CPU time 0.8 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 204708 kb
Host smart-352cc557-8b2d-461a-af3f-8f654393bc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38279
41984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3827941984
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1943821779
Short name T1433
Test name
Test status
Simulation time 42063451 ps
CPU time 0.65 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204632 kb
Host smart-198d1e58-9c18-40dd-a59e-577f5e822d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19438
21779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1943821779
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3349269718
Short name T757
Test name
Test status
Simulation time 1012505344 ps
CPU time 2.34 seconds
Started Jun 11 12:41:31 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204912 kb
Host smart-f955692f-58ce-440f-b347-b7c9b26fa6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33492
69718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3349269718
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3550227982
Short name T1352
Test name
Test status
Simulation time 222302874 ps
CPU time 1.02 seconds
Started Jun 11 12:41:54 PM PDT 24
Finished Jun 11 12:41:57 PM PDT 24
Peak memory 204728 kb
Host smart-aec60776-ceca-45fc-af26-d1988d65e5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35502
27982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3550227982
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.60496819
Short name T1653
Test name
Test status
Simulation time 142656535 ps
CPU time 0.75 seconds
Started Jun 11 12:41:37 PM PDT 24
Finished Jun 11 12:41:42 PM PDT 24
Peak memory 204632 kb
Host smart-31fda2fb-05cb-42d0-87dc-db3fd6c96a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60496
819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.60496819
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.3999550372
Short name T1333
Test name
Test status
Simulation time 202810810 ps
CPU time 0.92 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204692 kb
Host smart-0b59fc21-1e06-4a46-b524-1332ee577883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39995
50372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3999550372
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1183633961
Short name T1074
Test name
Test status
Simulation time 253600775 ps
CPU time 0.94 seconds
Started Jun 11 12:41:44 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 204732 kb
Host smart-fefbe16b-c902-4a5b-8040-ab0027d92a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11836
33961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1183633961
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1557649665
Short name T1513
Test name
Test status
Simulation time 3337804755 ps
CPU time 3.71 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204760 kb
Host smart-a1b8da56-59bd-471c-812d-e6c21f6f9219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15576
49665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1557649665
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.4176611937
Short name T1682
Test name
Test status
Simulation time 269956865 ps
CPU time 0.93 seconds
Started Jun 11 12:41:51 PM PDT 24
Finished Jun 11 12:41:55 PM PDT 24
Peak memory 204748 kb
Host smart-edfcb3a4-7d66-47b8-87a2-0e9730c07a1e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4176611937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.4176611937
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3914752654
Short name T318
Test name
Test status
Simulation time 188701193 ps
CPU time 0.83 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:40 PM PDT 24
Peak memory 204752 kb
Host smart-d98a218f-420f-401e-ac1a-d366a419f2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39147
52654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3914752654
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.492396447
Short name T462
Test name
Test status
Simulation time 14357406963 ps
CPU time 100.78 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 204964 kb
Host smart-f9814832-c6c2-4455-bae5-8f1cc9045f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49239
6447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.492396447
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1291950176
Short name T363
Test name
Test status
Simulation time 162304629 ps
CPU time 0.84 seconds
Started Jun 11 12:41:49 PM PDT 24
Finished Jun 11 12:41:52 PM PDT 24
Peak memory 204732 kb
Host smart-43da330d-62d7-40e4-bb4b-678bf9950608
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1291950176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1291950176
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1489240671
Short name T467
Test name
Test status
Simulation time 146045597 ps
CPU time 0.78 seconds
Started Jun 11 12:41:31 PM PDT 24
Finished Jun 11 12:41:36 PM PDT 24
Peak memory 204736 kb
Host smart-2425d863-bdc9-4c0f-9421-ed42473a3a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
40671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1489240671
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3544416495
Short name T152
Test name
Test status
Simulation time 229803033 ps
CPU time 0.88 seconds
Started Jun 11 12:41:27 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204688 kb
Host smart-5ad1dc78-f185-4f0f-a605-f1957ce9d1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35444
16495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3544416495
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2018867599
Short name T1215
Test name
Test status
Simulation time 190891215 ps
CPU time 0.82 seconds
Started Jun 11 12:41:49 PM PDT 24
Finished Jun 11 12:41:52 PM PDT 24
Peak memory 204740 kb
Host smart-446e16a0-95d6-41d2-af1b-c21f252dc09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20188
67599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2018867599
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3895876200
Short name T659
Test name
Test status
Simulation time 150808997 ps
CPU time 0.76 seconds
Started Jun 11 12:41:33 PM PDT 24
Finished Jun 11 12:41:38 PM PDT 24
Peak memory 204620 kb
Host smart-c54924ba-855e-4e40-9418-083b056db9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
76200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3895876200
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.233553064
Short name T3
Test name
Test status
Simulation time 154215957 ps
CPU time 0.76 seconds
Started Jun 11 12:41:37 PM PDT 24
Finished Jun 11 12:41:42 PM PDT 24
Peak memory 204700 kb
Host smart-ec75f6eb-d45a-40fd-8b45-cae22ec934cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23355
3064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.233553064
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1570789473
Short name T194
Test name
Test status
Simulation time 152113744 ps
CPU time 0.76 seconds
Started Jun 11 12:41:39 PM PDT 24
Finished Jun 11 12:41:43 PM PDT 24
Peak memory 204652 kb
Host smart-523ad57c-8e80-4838-982c-12ea4e58d64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707
89473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1570789473
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_eop_single_bit_handling.3313434228
Short name T492
Test name
Test status
Simulation time 183820908 ps
CPU time 0.84 seconds
Started Jun 11 12:41:53 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204720 kb
Host smart-9ab99297-ce41-43aa-ad35-359e45a6a624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
34228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_eop_single_bit_handling.3313434228
Directory /workspace/16.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3118314193
Short name T1474
Test name
Test status
Simulation time 149329179 ps
CPU time 0.75 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204684 kb
Host smart-ef637997-3215-4cb3-bfdd-be64d73aaa3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
14193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3118314193
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.923140074
Short name T928
Test name
Test status
Simulation time 36552319 ps
CPU time 0.72 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204728 kb
Host smart-bd68c282-3de7-4a07-b30e-beb1807b7315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92314
0074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.923140074
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3313376477
Short name T558
Test name
Test status
Simulation time 8156870847 ps
CPU time 17.95 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204944 kb
Host smart-a8191a3e-9daf-4a71-9981-f6a2ba3fe0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133
76477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3313376477
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.683716690
Short name T1250
Test name
Test status
Simulation time 187139181 ps
CPU time 0.84 seconds
Started Jun 11 12:41:32 PM PDT 24
Finished Jun 11 12:41:37 PM PDT 24
Peak memory 204768 kb
Host smart-ff2acf23-0a8b-4c3d-978a-708dbbf2c3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68371
6690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.683716690
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.4044340758
Short name T1053
Test name
Test status
Simulation time 234297355 ps
CPU time 0.89 seconds
Started Jun 11 12:41:34 PM PDT 24
Finished Jun 11 12:41:39 PM PDT 24
Peak memory 204720 kb
Host smart-2fff9005-ad39-4e79-9e1a-e8eacf3b7571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40443
40758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.4044340758
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2383131170
Short name T533
Test name
Test status
Simulation time 192511143 ps
CPU time 0.82 seconds
Started Jun 11 12:41:43 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204780 kb
Host smart-ed663a6e-dcab-4a6c-9f7b-04b497827c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23831
31170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2383131170
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3568129959
Short name T468
Test name
Test status
Simulation time 150686832 ps
CPU time 0.79 seconds
Started Jun 11 12:41:30 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204676 kb
Host smart-d39f50c5-54e5-41fc-a606-97e2f81411f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35681
29959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3568129959
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.569972378
Short name T510
Test name
Test status
Simulation time 136683656 ps
CPU time 0.75 seconds
Started Jun 11 12:41:44 PM PDT 24
Finished Jun 11 12:41:47 PM PDT 24
Peak memory 204772 kb
Host smart-b38ba491-d1ef-4470-bac8-5c0e128bb172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56997
2378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.569972378
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1794871245
Short name T1417
Test name
Test status
Simulation time 164919901 ps
CPU time 0.76 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 204728 kb
Host smart-e33ba0ff-723a-4640-8043-657fe768f163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17948
71245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1794871245
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2362429526
Short name T657
Test name
Test status
Simulation time 167455267 ps
CPU time 0.79 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204740 kb
Host smart-4104b00f-d13b-4ec3-b5ce-ef8108049a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23624
29526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2362429526
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2105275375
Short name T1371
Test name
Test status
Simulation time 244642444 ps
CPU time 0.98 seconds
Started Jun 11 12:41:39 PM PDT 24
Finished Jun 11 12:41:43 PM PDT 24
Peak memory 204652 kb
Host smart-78b85b74-0c86-4927-aada-ad71baaa4363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21052
75375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2105275375
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1344927541
Short name T1291
Test name
Test status
Simulation time 186529358 ps
CPU time 0.88 seconds
Started Jun 11 12:41:41 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 205004 kb
Host smart-e4d14822-65b6-438b-9f0c-680001ae4b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13449
27541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1344927541
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2174817278
Short name T1936
Test name
Test status
Simulation time 194089517 ps
CPU time 0.83 seconds
Started Jun 11 12:42:06 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 204696 kb
Host smart-92afc077-37df-4eb9-8cef-0b317bdc108a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
17278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2174817278
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1071780784
Short name T1841
Test name
Test status
Simulation time 6357736665 ps
CPU time 43.23 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 205224 kb
Host smart-7d0c72f5-c943-4785-8e02-cd003f092fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10717
80784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1071780784
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2082279355
Short name T1955
Test name
Test status
Simulation time 3763953488 ps
CPU time 4.44 seconds
Started Jun 11 12:41:35 PM PDT 24
Finished Jun 11 12:41:44 PM PDT 24
Peak memory 204724 kb
Host smart-a45bfd3f-8f26-40e8-b417-0c8725130b8f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2082279355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2082279355
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3470815781
Short name T970
Test name
Test status
Simulation time 13519266913 ps
CPU time 13.07 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 205068 kb
Host smart-7c398415-cabf-44e1-8ac7-9a58e6a2d350
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3470815781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3470815781
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2249347534
Short name T1983
Test name
Test status
Simulation time 23465619857 ps
CPU time 24.34 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204996 kb
Host smart-03b66a9f-6a64-43cd-b997-1e6337300f6f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2249347534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2249347534
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2583791978
Short name T1048
Test name
Test status
Simulation time 176279848 ps
CPU time 0.79 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204744 kb
Host smart-cff5ffde-5b2b-4a4f-b314-719b7c398802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25837
91978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2583791978
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.2161448937
Short name T1423
Test name
Test status
Simulation time 157573435 ps
CPU time 0.77 seconds
Started Jun 11 12:41:47 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204688 kb
Host smart-9e8242d5-50a6-45d9-865e-ee943bdeea5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21614
48937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.2161448937
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2542008934
Short name T650
Test name
Test status
Simulation time 960097047 ps
CPU time 2.55 seconds
Started Jun 11 12:41:41 PM PDT 24
Finished Jun 11 12:41:47 PM PDT 24
Peak memory 204856 kb
Host smart-90f6e08a-b287-4fd6-93bd-03959d9fcc86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
08934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2542008934
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3630944655
Short name T430
Test name
Test status
Simulation time 160509646 ps
CPU time 0.81 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204660 kb
Host smart-83cbfd26-360e-4e91-84c0-fde902088533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36309
44655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3630944655
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1621885344
Short name T345
Test name
Test status
Simulation time 50505156 ps
CPU time 0.65 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204728 kb
Host smart-cc5cc6df-1b71-49c9-9aee-7d8ecf68dcb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16218
85344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1621885344
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.1186968819
Short name T936
Test name
Test status
Simulation time 807335788 ps
CPU time 1.9 seconds
Started Jun 11 12:41:47 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204988 kb
Host smart-4d88249c-e4bb-4faa-83dd-0a165ec6dbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11869
68819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.1186968819
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.415478572
Short name T642
Test name
Test status
Simulation time 193555129 ps
CPU time 1.5 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204820 kb
Host smart-89f7e94d-57ed-453d-82fb-f6bd4004f059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41547
8572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.415478572
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1120058235
Short name T598
Test name
Test status
Simulation time 169367749 ps
CPU time 0.79 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204724 kb
Host smart-8c52e25c-67c4-412a-aa94-e69a529fb3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11200
58235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1120058235
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3539660113
Short name T349
Test name
Test status
Simulation time 150643854 ps
CPU time 0.74 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:01 PM PDT 24
Peak memory 204720 kb
Host smart-17de4d3a-4218-4345-a6fc-7d3e4b3860af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35396
60113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3539660113
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.614645773
Short name T1031
Test name
Test status
Simulation time 210609240 ps
CPU time 0.83 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204624 kb
Host smart-8aaf27f4-9ba4-40c4-aede-87f3f7580f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61464
5773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.614645773
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1484609516
Short name T1378
Test name
Test status
Simulation time 247162075 ps
CPU time 0.9 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204712 kb
Host smart-37329aad-0609-4b3e-92dc-275ca42362d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
09516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1484609516
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1657668393
Short name T599
Test name
Test status
Simulation time 3323914880 ps
CPU time 3.97 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204752 kb
Host smart-ddf80e72-98ba-46c7-b2cc-3a27674f9304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576
68393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1657668393
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2407982888
Short name T1308
Test name
Test status
Simulation time 253013681 ps
CPU time 0.96 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 204632 kb
Host smart-2e151a51-8c31-4288-add1-cbec798730c6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2407982888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2407982888
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2801871878
Short name T1306
Test name
Test status
Simulation time 231357436 ps
CPU time 0.93 seconds
Started Jun 11 12:41:43 PM PDT 24
Finished Jun 11 12:41:47 PM PDT 24
Peak memory 204708 kb
Host smart-e87dc8bf-3299-47fb-a8f9-8a599eccc4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28018
71878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2801871878
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.646552463
Short name T481
Test name
Test status
Simulation time 4736334380 ps
CPU time 122.74 seconds
Started Jun 11 12:41:54 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 205056 kb
Host smart-63b6eb78-e92f-4bcc-9c02-169d34efc611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64655
2463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.646552463
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3621982225
Short name T1439
Test name
Test status
Simulation time 158589556 ps
CPU time 0.81 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204732 kb
Host smart-dfacfcc8-f0cb-4730-a9a1-1d8f6cc02287
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3621982225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3621982225
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.991984483
Short name T1330
Test name
Test status
Simulation time 158221171 ps
CPU time 0.8 seconds
Started Jun 11 12:42:06 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204728 kb
Host smart-e674b515-72de-4425-bd4b-e4a8877aa141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99198
4483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.991984483
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.3620825495
Short name T1908
Test name
Test status
Simulation time 177834084 ps
CPU time 0.81 seconds
Started Jun 11 12:41:49 PM PDT 24
Finished Jun 11 12:41:52 PM PDT 24
Peak memory 204696 kb
Host smart-301a3082-43fd-47b9-82c5-a2999d22c956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208
25495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3620825495
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.1528695704
Short name T1321
Test name
Test status
Simulation time 161816488 ps
CPU time 0.78 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204708 kb
Host smart-225f9129-a2b0-42a1-ae04-a054cf7e15ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15286
95704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1528695704
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2895335825
Short name T1470
Test name
Test status
Simulation time 175947509 ps
CPU time 0.82 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204776 kb
Host smart-57cf146e-c8a8-45f0-b712-8ad2c790c4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28953
35825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2895335825
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3528453073
Short name T1384
Test name
Test status
Simulation time 166660734 ps
CPU time 0.77 seconds
Started Jun 11 12:41:47 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204640 kb
Host smart-228f4cc9-fef4-4269-9edf-a4e62f3a44a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35284
53073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3528453073
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_eop_single_bit_handling.3471978670
Short name T419
Test name
Test status
Simulation time 203075127 ps
CPU time 0.85 seconds
Started Jun 11 12:41:47 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204728 kb
Host smart-530e1aaf-c707-45a8-8810-7a7c1f09ad97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34719
78670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_eop_single_bit_handling.3471978670
Directory /workspace/17.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3022296885
Short name T1531
Test name
Test status
Simulation time 154811812 ps
CPU time 0.86 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 204980 kb
Host smart-ff18b4a3-7206-43f8-b4ba-e7e7f51138ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30222
96885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3022296885
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1040478892
Short name T1220
Test name
Test status
Simulation time 51171795 ps
CPU time 0.67 seconds
Started Jun 11 12:41:51 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 204716 kb
Host smart-651f21ba-8ac8-42a8-8e8c-e2094d4f2169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10404
78892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1040478892
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3074295262
Short name T1085
Test name
Test status
Simulation time 18157314617 ps
CPU time 38.04 seconds
Started Jun 11 12:41:49 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 204976 kb
Host smart-c44c2c52-070a-412d-b854-7689cf55eb0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
95262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3074295262
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.536697027
Short name T938
Test name
Test status
Simulation time 238192205 ps
CPU time 0.86 seconds
Started Jun 11 12:41:51 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 204712 kb
Host smart-2cd379a5-0891-4def-b38c-d89e6221510b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53669
7027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.536697027
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.493953045
Short name T1932
Test name
Test status
Simulation time 203498325 ps
CPU time 0.8 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204712 kb
Host smart-44c3f3e3-5b71-49b9-8976-3c3c80a30ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49395
3045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.493953045
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1676212770
Short name T1443
Test name
Test status
Simulation time 227937529 ps
CPU time 0.85 seconds
Started Jun 11 12:41:44 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 204768 kb
Host smart-bb3c24d8-e80a-4863-9e37-a8c27ca85c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
12770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1676212770
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.518285460
Short name T1588
Test name
Test status
Simulation time 179266634 ps
CPU time 0.88 seconds
Started Jun 11 12:41:46 PM PDT 24
Finished Jun 11 12:41:49 PM PDT 24
Peak memory 204708 kb
Host smart-53db7869-fd22-4f7f-a5a6-c6a5781af88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51828
5460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.518285460
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1937307778
Short name T1383
Test name
Test status
Simulation time 156333345 ps
CPU time 0.79 seconds
Started Jun 11 12:41:44 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 204620 kb
Host smart-aa5eb3af-907a-4170-aa1e-ef790a89c484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19373
07778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1937307778
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.525002944
Short name T185
Test name
Test status
Simulation time 161673552 ps
CPU time 0.77 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204756 kb
Host smart-1911ea91-3c5f-4f86-91a5-7493adee4d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52500
2944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.525002944
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.3998747839
Short name T474
Test name
Test status
Simulation time 154384342 ps
CPU time 0.76 seconds
Started Jun 11 12:41:40 PM PDT 24
Finished Jun 11 12:41:44 PM PDT 24
Peak memory 204676 kb
Host smart-4dc97d99-b6e4-42ed-b6a2-e90d1e610212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39987
47839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.3998747839
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1954297427
Short name T1836
Test name
Test status
Simulation time 252870631 ps
CPU time 0.93 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:46 PM PDT 24
Peak memory 204764 kb
Host smart-9be612a7-83f9-4969-9230-621e4c4ffa6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19542
97427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1954297427
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2435318511
Short name T448
Test name
Test status
Simulation time 232197598 ps
CPU time 0.86 seconds
Started Jun 11 12:41:47 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204992 kb
Host smart-166ee383-83d5-47a4-976f-9dad7139ea1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24353
18511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2435318511
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.698592632
Short name T548
Test name
Test status
Simulation time 178067904 ps
CPU time 0.82 seconds
Started Jun 11 12:41:53 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204632 kb
Host smart-9045fb2d-bdf8-40c6-8412-5f567d2baba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69859
2632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.698592632
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1815804598
Short name T1309
Test name
Test status
Simulation time 4465424946 ps
CPU time 41.96 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204984 kb
Host smart-3ef05ab3-9449-4da8-9808-631257aadd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18158
04598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1815804598
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3374749164
Short name T15
Test name
Test status
Simulation time 4284821347 ps
CPU time 5.13 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204820 kb
Host smart-e792f82e-a5cb-47f9-bfb5-f539dd340b1f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3374749164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3374749164
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4285054934
Short name T1174
Test name
Test status
Simulation time 13366804418 ps
CPU time 16.25 seconds
Started Jun 11 12:41:52 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 204724 kb
Host smart-9804cce3-43ac-4c5f-9c69-d78ba1781987
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4285054934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4285054934
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3350717928
Short name T1236
Test name
Test status
Simulation time 23311834225 ps
CPU time 22.04 seconds
Started Jun 11 12:41:52 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204996 kb
Host smart-b8ce4094-a860-464d-93a0-e9404f50a389
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3350717928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3350717928
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2730972794
Short name T1276
Test name
Test status
Simulation time 150948836 ps
CPU time 0.76 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204684 kb
Host smart-e7c9f583-1fa0-47f7-8976-a57067b75c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
72794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2730972794
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1201643007
Short name T1616
Test name
Test status
Simulation time 155841968 ps
CPU time 0.76 seconds
Started Jun 11 12:41:42 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 204648 kb
Host smart-94fe6d15-1d76-4be6-b22d-c064d0b8c8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
43007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1201643007
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2785317989
Short name T778
Test name
Test status
Simulation time 303951866 ps
CPU time 0.96 seconds
Started Jun 11 12:41:46 PM PDT 24
Finished Jun 11 12:41:49 PM PDT 24
Peak memory 204732 kb
Host smart-1738e18a-7a4a-4097-bce4-7a5c98f1d75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27853
17989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2785317989
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3521797545
Short name T1641
Test name
Test status
Simulation time 166454326 ps
CPU time 0.75 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204672 kb
Host smart-d0265798-c009-48bb-86e3-27b3502627e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217
97545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3521797545
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1643826895
Short name T837
Test name
Test status
Simulation time 35022261 ps
CPU time 0.66 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204680 kb
Host smart-99c789ee-fb34-481a-8d0a-fe1f53f0b57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
26895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1643826895
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1047612271
Short name T1656
Test name
Test status
Simulation time 844157743 ps
CPU time 2.07 seconds
Started Jun 11 12:41:56 PM PDT 24
Finished Jun 11 12:42:01 PM PDT 24
Peak memory 204900 kb
Host smart-4423ef97-ac3d-480d-bf19-70f5d4071e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10476
12271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1047612271
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1767326561
Short name T1622
Test name
Test status
Simulation time 243745196 ps
CPU time 1.42 seconds
Started Jun 11 12:41:52 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204992 kb
Host smart-cf5bd680-0ccf-48d6-b265-4efab8e35b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17673
26561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1767326561
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.3146076070
Short name T707
Test name
Test status
Simulation time 178458490 ps
CPU time 0.81 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204720 kb
Host smart-4abf0e31-9256-402f-99d1-873057ccb035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31460
76070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.3146076070
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1479025624
Short name T346
Test name
Test status
Simulation time 150282102 ps
CPU time 0.76 seconds
Started Jun 11 12:41:51 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 204636 kb
Host smart-7bec037f-ea2c-4220-abd3-2707fa1aadf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14790
25624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1479025624
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1229317336
Short name T836
Test name
Test status
Simulation time 243772642 ps
CPU time 1.08 seconds
Started Jun 11 12:41:41 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 204720 kb
Host smart-88cff469-26f8-4bb8-86ed-6d9339689bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293
17336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1229317336
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4027660567
Short name T1487
Test name
Test status
Simulation time 162445866 ps
CPU time 0.81 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204716 kb
Host smart-fb0aa590-9b63-48b1-9d7f-9324fe39bfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
60567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4027660567
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3967362858
Short name T1635
Test name
Test status
Simulation time 3290262119 ps
CPU time 3.64 seconds
Started Jun 11 12:41:56 PM PDT 24
Finished Jun 11 12:42:02 PM PDT 24
Peak memory 204808 kb
Host smart-af63059e-75ac-4488-b610-f13f4a6b3ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
62858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3967362858
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2764715918
Short name T1184
Test name
Test status
Simulation time 246717777 ps
CPU time 0.95 seconds
Started Jun 11 12:41:44 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 204736 kb
Host smart-7186e723-8aa0-4a65-a6b5-decba377fbd9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2764715918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2764715918
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.20424287
Short name T331
Test name
Test status
Simulation time 196324802 ps
CPU time 0.92 seconds
Started Jun 11 12:41:59 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 204988 kb
Host smart-3f272bdf-10a8-41bf-a33b-e83e9785cbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20424
287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.20424287
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2911757884
Short name T1875
Test name
Test status
Simulation time 7840432769 ps
CPU time 221.71 seconds
Started Jun 11 12:41:56 PM PDT 24
Finished Jun 11 12:45:40 PM PDT 24
Peak memory 204964 kb
Host smart-158f1a93-acd5-45d9-8a9e-7fa1416d55a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29117
57884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2911757884
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2061279488
Short name T777
Test name
Test status
Simulation time 156062568 ps
CPU time 0.79 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 204776 kb
Host smart-2ed6792d-b910-4785-9fc0-80a987e15ece
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2061279488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2061279488
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3938195902
Short name T1012
Test name
Test status
Simulation time 161062346 ps
CPU time 0.79 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:01 PM PDT 24
Peak memory 204720 kb
Host smart-d20b4df5-d791-456d-b935-ce3f24b7095c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39381
95902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3938195902
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4107948372
Short name T156
Test name
Test status
Simulation time 245027963 ps
CPU time 0.89 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204700 kb
Host smart-8e97685c-b864-4c6c-a2cc-ffefa5dd7728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41079
48372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4107948372
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2418543957
Short name T971
Test name
Test status
Simulation time 162025022 ps
CPU time 0.83 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204664 kb
Host smart-abcddf5c-eb45-471b-92fb-e60e96159c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24185
43957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2418543957
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1039148139
Short name T1041
Test name
Test status
Simulation time 177983653 ps
CPU time 0.81 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204700 kb
Host smart-84a44660-b2e0-407d-8dcf-0baa02c8b70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391
48139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1039148139
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.4201302811
Short name T1518
Test name
Test status
Simulation time 185929497 ps
CPU time 0.83 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204728 kb
Host smart-7e1add53-30e7-4f78-90e8-e4ed66910087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42013
02811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.4201302811
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3622204054
Short name T935
Test name
Test status
Simulation time 167566769 ps
CPU time 0.79 seconds
Started Jun 11 12:41:53 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204724 kb
Host smart-6eb43b65-a80f-48a3-8a98-82fc945b03b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36222
04054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3622204054
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_eop_single_bit_handling.3394680270
Short name T976
Test name
Test status
Simulation time 183132728 ps
CPU time 0.82 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204748 kb
Host smart-0a1ddaee-16f2-45ed-b803-d6cf9ea7dcdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33946
80270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_eop_single_bit_handling.3394680270
Directory /workspace/18.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.1329303307
Short name T992
Test name
Test status
Simulation time 147553457 ps
CPU time 0.74 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204732 kb
Host smart-d4901c58-9c49-48f2-819f-3c74fa30b379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13293
03307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.1329303307
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.1089425894
Short name T664
Test name
Test status
Simulation time 34799132 ps
CPU time 0.67 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204716 kb
Host smart-564d9131-d124-4f32-aa4d-a96f0dc88fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
25894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.1089425894
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.640908587
Short name T101
Test name
Test status
Simulation time 21837233904 ps
CPU time 45.72 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:49 PM PDT 24
Peak memory 205016 kb
Host smart-7214d688-a76c-4597-89cf-ef1f2a344f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64090
8587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.640908587
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1018237768
Short name T1663
Test name
Test status
Simulation time 242693257 ps
CPU time 0.8 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204672 kb
Host smart-46393746-2e43-4e0f-b60d-d982f9f12bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10182
37768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1018237768
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1651864471
Short name T2092
Test name
Test status
Simulation time 175725634 ps
CPU time 0.83 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204696 kb
Host smart-57b91c6d-b368-4b80-8421-528374b3459a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
64471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1651864471
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.4227324270
Short name T1585
Test name
Test status
Simulation time 176269074 ps
CPU time 0.81 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204736 kb
Host smart-a0e0f480-dce1-464e-b904-dedc40bbb35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
24270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.4227324270
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3320414821
Short name T1027
Test name
Test status
Simulation time 191786840 ps
CPU time 0.78 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204724 kb
Host smart-b8fab767-cd9f-4f0f-85c2-0bf2934ea6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204
14821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3320414821
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2139403968
Short name T1910
Test name
Test status
Simulation time 152451988 ps
CPU time 0.88 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 205020 kb
Host smart-324e2566-7062-4696-ac97-e729e0a3aecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21394
03968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2139403968
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3072317462
Short name T2114
Test name
Test status
Simulation time 236487631 ps
CPU time 0.99 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204732 kb
Host smart-5c00e3dc-2a15-4c47-bc00-37c3f8611a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30723
17462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3072317462
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3513095391
Short name T769
Test name
Test status
Simulation time 179404606 ps
CPU time 0.85 seconds
Started Jun 11 12:41:52 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204728 kb
Host smart-eedf90d0-0d61-416c-9bfc-94dd445288b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35130
95391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3513095391
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1954382029
Short name T1577
Test name
Test status
Simulation time 211197135 ps
CPU time 0.89 seconds
Started Jun 11 12:41:53 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204732 kb
Host smart-6f341d25-3203-44d5-bb0e-c6dcc6790832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19543
82029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1954382029
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1455499443
Short name T1760
Test name
Test status
Simulation time 7981621158 ps
CPU time 54.99 seconds
Started Jun 11 12:41:46 PM PDT 24
Finished Jun 11 12:42:43 PM PDT 24
Peak memory 205032 kb
Host smart-da602092-8538-47e3-a855-e86b7a8775e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14554
99443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1455499443
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1326986583
Short name T16
Test name
Test status
Simulation time 4205817798 ps
CPU time 5.05 seconds
Started Jun 11 12:41:44 PM PDT 24
Finished Jun 11 12:41:52 PM PDT 24
Peak memory 204756 kb
Host smart-15dbe74f-56ca-48c2-9f43-eaeafeefea7e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1326986583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1326986583
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1173269193
Short name T1008
Test name
Test status
Simulation time 13356561537 ps
CPU time 12.76 seconds
Started Jun 11 12:41:59 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204632 kb
Host smart-82c2780b-5eff-43fd-9d30-6c0681a26353
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1173269193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1173269193
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2809105326
Short name T596
Test name
Test status
Simulation time 23331647650 ps
CPU time 25.34 seconds
Started Jun 11 12:41:49 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204768 kb
Host smart-cb99242d-2b04-40f5-a2fd-6cc23ec591ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2809105326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2809105326
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1651810624
Short name T317
Test name
Test status
Simulation time 165791313 ps
CPU time 0.8 seconds
Started Jun 11 12:41:49 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204736 kb
Host smart-e334c7d9-844d-4dfe-a15b-65acb0e0bba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
10624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1651810624
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.640757353
Short name T926
Test name
Test status
Simulation time 157171140 ps
CPU time 0.76 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:01 PM PDT 24
Peak memory 204764 kb
Host smart-ad2a5652-efef-4f80-8076-dc01da246563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64075
7353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.640757353
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.70874831
Short name T1609
Test name
Test status
Simulation time 130572787 ps
CPU time 0.75 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204608 kb
Host smart-0f8b2c4b-72c7-424a-8e8d-1703f2a71f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70874
831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.70874831
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.83956435
Short name T622
Test name
Test status
Simulation time 59704641 ps
CPU time 0.74 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204728 kb
Host smart-0a6d32ff-2aa6-44c3-adc5-c5cef675a42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83956
435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.83956435
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3029856472
Short name T1298
Test name
Test status
Simulation time 733320416 ps
CPU time 1.78 seconds
Started Jun 11 12:41:47 PM PDT 24
Finished Jun 11 12:41:51 PM PDT 24
Peak memory 204924 kb
Host smart-b33d3c33-228f-4d56-a5b2-b85aeeb1cca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30298
56472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3029856472
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1155274018
Short name T627
Test name
Test status
Simulation time 170491224 ps
CPU time 1.21 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:01 PM PDT 24
Peak memory 204952 kb
Host smart-ed4e5fe7-bb57-4fb6-baee-4ea0f8326497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
74018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1155274018
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3255646819
Short name T725
Test name
Test status
Simulation time 216476958 ps
CPU time 0.88 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204732 kb
Host smart-b111ea3d-99c4-4302-91d4-70fd5f372e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32556
46819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3255646819
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1588986449
Short name T2025
Test name
Test status
Simulation time 206888666 ps
CPU time 0.81 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 204664 kb
Host smart-732e1e99-0527-4c2a-ae3e-fb41fb64f959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15889
86449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1588986449
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3741815893
Short name T734
Test name
Test status
Simulation time 207818311 ps
CPU time 0.91 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 204768 kb
Host smart-483612f6-c3a5-4a12-955c-50c986f3a159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
15893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3741815893
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1310099594
Short name T351
Test name
Test status
Simulation time 278468549 ps
CPU time 0.91 seconds
Started Jun 11 12:41:51 PM PDT 24
Finished Jun 11 12:41:54 PM PDT 24
Peak memory 204712 kb
Host smart-7de7d812-2478-44c2-a84e-70ff56d12ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13100
99594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1310099594
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1754553595
Short name T1790
Test name
Test status
Simulation time 3336672288 ps
CPU time 4 seconds
Started Jun 11 12:41:52 PM PDT 24
Finished Jun 11 12:41:59 PM PDT 24
Peak memory 204696 kb
Host smart-c2f01d05-4a18-4a3f-8f0e-f27265435a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17545
53595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1754553595
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3010953538
Short name T1742
Test name
Test status
Simulation time 245749202 ps
CPU time 0.86 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204676 kb
Host smart-7fe1ed3f-6e6f-4cda-816c-9856c3d0e91c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3010953538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3010953538
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.321896269
Short name T1162
Test name
Test status
Simulation time 234414056 ps
CPU time 0.89 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:05 PM PDT 24
Peak memory 204640 kb
Host smart-00dd42e6-4b7b-4afa-b402-0144f9527776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32189
6269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.321896269
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.817793237
Short name T1794
Test name
Test status
Simulation time 6216736608 ps
CPU time 41.82 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:50 PM PDT 24
Peak memory 204968 kb
Host smart-3dfebbcb-d333-4c7b-b630-372f8dba193c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81779
3237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.817793237
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2179938584
Short name T865
Test name
Test status
Simulation time 157758725 ps
CPU time 0.83 seconds
Started Jun 11 12:41:48 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 204644 kb
Host smart-2cc8bc95-c74e-4e77-b5b2-0ba9f3c62523
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2179938584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2179938584
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.948167878
Short name T1075
Test name
Test status
Simulation time 164272494 ps
CPU time 0.78 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204688 kb
Host smart-7e463df5-9293-4922-b2dc-9d9481664fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94816
7878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.948167878
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.293475426
Short name T1638
Test name
Test status
Simulation time 173520843 ps
CPU time 0.79 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204716 kb
Host smart-3b32b89e-3cfe-4c17-b38e-802b02649795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29347
5426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.293475426
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2061005184
Short name T955
Test name
Test status
Simulation time 197915389 ps
CPU time 0.85 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204716 kb
Host smart-c4c44f27-e142-4a29-aa25-0fa0daebd25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20610
05184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2061005184
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.908075162
Short name T297
Test name
Test status
Simulation time 193682038 ps
CPU time 0.84 seconds
Started Jun 11 12:41:54 PM PDT 24
Finished Jun 11 12:41:57 PM PDT 24
Peak memory 204716 kb
Host smart-1aabbd59-afee-4d80-a59e-cfef74c9c73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90807
5162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.908075162
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.4203496490
Short name T174
Test name
Test status
Simulation time 168081252 ps
CPU time 0.77 seconds
Started Jun 11 12:42:08 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204672 kb
Host smart-4fcef275-5038-4818-b238-91a2017a9416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
96490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.4203496490
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_eop_single_bit_handling.968416994
Short name T1550
Test name
Test status
Simulation time 183807044 ps
CPU time 0.81 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204672 kb
Host smart-a98353a7-893c-48fe-87be-80f6380beb8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96841
6994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_eop_single_bit_handling.968416994
Directory /workspace/19.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3103159715
Short name T1551
Test name
Test status
Simulation time 223005270 ps
CPU time 0.8 seconds
Started Jun 11 12:41:50 PM PDT 24
Finished Jun 11 12:41:53 PM PDT 24
Peak memory 204672 kb
Host smart-383e1de8-60f5-4b3a-a7b7-d2fe172049be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031
59715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3103159715
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2669508336
Short name T1467
Test name
Test status
Simulation time 41322113 ps
CPU time 0.64 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204664 kb
Host smart-4fa10fe1-7edb-424e-afe6-02743c237a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26695
08336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2669508336
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.836843573
Short name T780
Test name
Test status
Simulation time 20725956477 ps
CPU time 44.81 seconds
Started Jun 11 12:41:59 PM PDT 24
Finished Jun 11 12:42:47 PM PDT 24
Peak memory 205044 kb
Host smart-3a04de4d-1c81-4fe0-9780-b5a9c5518dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83684
3573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.836843573
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.583718875
Short name T413
Test name
Test status
Simulation time 190526593 ps
CPU time 0.88 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:01 PM PDT 24
Peak memory 204776 kb
Host smart-93a39b15-d73f-4a9b-a073-75a4f5907259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58371
8875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.583718875
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.733066353
Short name T683
Test name
Test status
Simulation time 311005283 ps
CPU time 1.01 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:59 PM PDT 24
Peak memory 204772 kb
Host smart-7a1b3db8-47fd-4216-bf8c-cc80e848d3f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73306
6353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.733066353
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.839851463
Short name T36
Test name
Test status
Simulation time 230467706 ps
CPU time 0.9 seconds
Started Jun 11 12:41:55 PM PDT 24
Finished Jun 11 12:41:58 PM PDT 24
Peak memory 204672 kb
Host smart-a380c9cf-2caf-45e2-b598-35b8dfc85e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83985
1463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.839851463
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3849999505
Short name T1052
Test name
Test status
Simulation time 215366947 ps
CPU time 0.83 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204780 kb
Host smart-1a22242d-30b5-4fc6-94f8-111f763b357b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499
99505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3849999505
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2904994282
Short name T1839
Test name
Test status
Simulation time 156384873 ps
CPU time 0.8 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204668 kb
Host smart-c0097d33-ae4f-4d4c-b941-5aa8ccae72a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29049
94282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2904994282
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.192553130
Short name T184
Test name
Test status
Simulation time 148791489 ps
CPU time 0.8 seconds
Started Jun 11 12:42:00 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 204664 kb
Host smart-5691736f-6099-4a90-9aff-2f9ad577fdfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19255
3130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.192553130
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3439551859
Short name T89
Test name
Test status
Simulation time 149162821 ps
CPU time 0.77 seconds
Started Jun 11 12:41:52 PM PDT 24
Finished Jun 11 12:41:56 PM PDT 24
Peak memory 204760 kb
Host smart-4918893b-bfa1-495a-bf60-23d66a158dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34395
51859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3439551859
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3998290611
Short name T746
Test name
Test status
Simulation time 199312144 ps
CPU time 0.9 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204736 kb
Host smart-71dec728-7860-4bde-a867-aaf2864fc0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39982
90611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3998290611
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.4247187856
Short name T583
Test name
Test status
Simulation time 193834912 ps
CPU time 0.79 seconds
Started Jun 11 12:42:00 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 204680 kb
Host smart-2ee47f37-daa0-4209-a9eb-b073ef6d1206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42471
87856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.4247187856
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3569438902
Short name T1317
Test name
Test status
Simulation time 243566041 ps
CPU time 0.83 seconds
Started Jun 11 12:41:56 PM PDT 24
Finished Jun 11 12:41:59 PM PDT 24
Peak memory 204692 kb
Host smart-e92c4c1d-697b-41c6-bbcc-7d9cd7a9cb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35694
38902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3569438902
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.4044741146
Short name T479
Test name
Test status
Simulation time 14034226749 ps
CPU time 92.22 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:43:32 PM PDT 24
Peak memory 205064 kb
Host smart-8b3e4a44-dd61-4600-a537-88e49e2348bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40447
41146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.4044741146
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2522466669
Short name T1593
Test name
Test status
Simulation time 4261538057 ps
CPU time 5.13 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 204804 kb
Host smart-384c79c0-52bb-4810-b033-0c9f9658ade8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2522466669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2522466669
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1685218918
Short name T1957
Test name
Test status
Simulation time 13350212625 ps
CPU time 12.8 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 204764 kb
Host smart-676dfc65-2e74-448a-85a4-0975b369b531
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1685218918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1685218918
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1684279677
Short name T426
Test name
Test status
Simulation time 23358874488 ps
CPU time 29.82 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:40 PM PDT 24
Peak memory 205068 kb
Host smart-03921409-bce6-4ff9-8f41-152cf34a8e41
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1684279677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1684279677
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1694062295
Short name T1854
Test name
Test status
Simulation time 151716234 ps
CPU time 0.78 seconds
Started Jun 11 12:40:11 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 204728 kb
Host smart-725352d6-d318-4cdc-bbc6-e00c4405c8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16940
62295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1694062295
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.4009731289
Short name T85
Test name
Test status
Simulation time 223103901 ps
CPU time 0.87 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:12 PM PDT 24
Peak memory 204748 kb
Host smart-7db27ee1-4524-4631-94c9-69c89392546d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40097
31289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4009731289
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.4287014157
Short name T73
Test name
Test status
Simulation time 1004988161 ps
CPU time 2.31 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:15 PM PDT 24
Peak memory 204892 kb
Host smart-53a4260b-6f3b-4e0d-a888-164496c3206c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42870
14157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.4287014157
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2735080850
Short name T1125
Test name
Test status
Simulation time 151042103 ps
CPU time 0.76 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204676 kb
Host smart-cd1ecf21-67ea-48a1-b090-908c8a8c6334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27350
80850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2735080850
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.399612664
Short name T1036
Test name
Test status
Simulation time 44759957 ps
CPU time 0.68 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:09 PM PDT 24
Peak memory 204728 kb
Host smart-cc733e90-50d2-4823-ab88-625d0e791331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
2664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.399612664
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2373956214
Short name T1081
Test name
Test status
Simulation time 849236954 ps
CPU time 1.96 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 204928 kb
Host smart-b5e6f403-52f3-41f4-ab27-904be0a01e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23739
56214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2373956214
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1346970389
Short name T1862
Test name
Test status
Simulation time 354372012 ps
CPU time 1.95 seconds
Started Jun 11 12:40:08 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 204984 kb
Host smart-d81b09a9-2b4e-4f3e-ad3c-d0fbc0b56677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13469
70389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1346970389
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1577616774
Short name T2079
Test name
Test status
Simulation time 207671608 ps
CPU time 0.89 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204716 kb
Host smart-e0773cfc-889f-43f8-98b3-d5b99ee8e89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15776
16774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1577616774
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2974171286
Short name T79
Test name
Test status
Simulation time 150321214 ps
CPU time 0.76 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204740 kb
Host smart-fa3ded2b-7d01-4ec8-9693-ec80ef9ffe4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29741
71286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2974171286
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3697350648
Short name T1316
Test name
Test status
Simulation time 239289700 ps
CPU time 0.91 seconds
Started Jun 11 12:40:10 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 204704 kb
Host smart-1f090a94-1331-4053-8caf-786b381f7a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36973
50648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3697350648
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2053957792
Short name T1685
Test name
Test status
Simulation time 202969934 ps
CPU time 0.88 seconds
Started Jun 11 12:40:11 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 204672 kb
Host smart-d10fb42d-e7b0-4305-9011-85cc65b552f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539
57792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2053957792
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.119056769
Short name T1110
Test name
Test status
Simulation time 3332190509 ps
CPU time 4.7 seconds
Started Jun 11 12:40:10 PM PDT 24
Finished Jun 11 12:40:18 PM PDT 24
Peak memory 204716 kb
Host smart-bbcd8b98-77ef-4159-ba8e-180e8ec35566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11905
6769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.119056769
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2484878248
Short name T336
Test name
Test status
Simulation time 244045250 ps
CPU time 0.91 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204736 kb
Host smart-5e7f4153-0753-4701-89e1-ed1c3ac97b46
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2484878248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2484878248
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3082587022
Short name T305
Test name
Test status
Simulation time 188510016 ps
CPU time 0.84 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:10 PM PDT 24
Peak memory 204720 kb
Host smart-0c74a18f-dba4-4916-9fe4-fa1bd036801c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30825
87022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3082587022
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.3328591673
Short name T2107
Test name
Test status
Simulation time 15532589218 ps
CPU time 143.05 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:42:32 PM PDT 24
Peak memory 205008 kb
Host smart-61b6b01e-3936-4223-8b0a-12b423c787ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33285
91673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.3328591673
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3075799919
Short name T1126
Test name
Test status
Simulation time 160534807 ps
CPU time 0.85 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204724 kb
Host smart-56cbf3ba-51c1-4d82-8c13-05db947a68d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3075799919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3075799919
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1114588432
Short name T433
Test name
Test status
Simulation time 147124212 ps
CPU time 0.75 seconds
Started Jun 11 12:40:10 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204748 kb
Host smart-38ae76f9-cdb6-4f78-a3b7-be6e5abf011d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11145
88432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1114588432
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.1391510568
Short name T2061
Test name
Test status
Simulation time 188589464 ps
CPU time 0.82 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204744 kb
Host smart-2a9d9935-4d8f-47fc-85e3-3eee4adcb1e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13915
10568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1391510568
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.4191312829
Short name T1885
Test name
Test status
Simulation time 183617427 ps
CPU time 0.87 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204688 kb
Host smart-8b7ad5e5-27a6-43ed-b7e2-98544efaf820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41913
12829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4191312829
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3639556097
Short name T1575
Test name
Test status
Simulation time 158182690 ps
CPU time 0.83 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204620 kb
Host smart-08cf719e-cc50-4248-8282-2b9e4b03a915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36395
56097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3639556097
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1804650745
Short name T1240
Test name
Test status
Simulation time 156722948 ps
CPU time 0.78 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204972 kb
Host smart-30b6db92-da73-4524-952a-457989bc8107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046
50745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1804650745
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_eop_single_bit_handling.2192792457
Short name T2007
Test name
Test status
Simulation time 159046664 ps
CPU time 0.76 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204700 kb
Host smart-1c868d54-4cbb-41d2-971d-62115b9d3fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
92457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_eop_single_bit_handling.2192792457
Directory /workspace/2.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2601709075
Short name T1581
Test name
Test status
Simulation time 145209871 ps
CPU time 0.78 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:18 PM PDT 24
Peak memory 204736 kb
Host smart-a77ef2da-60dd-4ad9-a12a-e7730474fa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26017
09075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2601709075
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1363342691
Short name T1370
Test name
Test status
Simulation time 44874923 ps
CPU time 0.67 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204684 kb
Host smart-9c6f2429-4659-4ebd-a572-c54a11eb2cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
42691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1363342691
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.875876095
Short name T1183
Test name
Test status
Simulation time 6548510969 ps
CPU time 15.8 seconds
Started Jun 11 12:40:06 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 204992 kb
Host smart-43cecdf2-d896-4744-b6f4-240bf8b76621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87587
6095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.875876095
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1161178110
Short name T656
Test name
Test status
Simulation time 172967573 ps
CPU time 0.87 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:40:11 PM PDT 24
Peak memory 204640 kb
Host smart-81318f55-1a79-4506-9ce0-c12892496fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
78110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1161178110
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3603486315
Short name T1679
Test name
Test status
Simulation time 195404482 ps
CPU time 0.87 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204656 kb
Host smart-b05bd64e-195d-4847-ac27-ba9e014d1e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034
86315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3603486315
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2186185039
Short name T2048
Test name
Test status
Simulation time 20250488563 ps
CPU time 541.43 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:49:12 PM PDT 24
Peak memory 205140 kb
Host smart-08208c91-cf8c-43e0-b968-e1dffc0401b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2186185039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2186185039
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3090771034
Short name T1563
Test name
Test status
Simulation time 9634328188 ps
CPU time 82.2 seconds
Started Jun 11 12:40:07 PM PDT 24
Finished Jun 11 12:41:33 PM PDT 24
Peak memory 204912 kb
Host smart-499b686a-3685-4dc6-b12f-e275dc249602
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3090771034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3090771034
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3124375246
Short name T944
Test name
Test status
Simulation time 13420718859 ps
CPU time 264.61 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 205088 kb
Host smart-664f0917-6d16-4a56-8d00-f7441ec1313f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3124375246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3124375246
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3960701914
Short name T1553
Test name
Test status
Simulation time 200401760 ps
CPU time 0.82 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:17 PM PDT 24
Peak memory 204668 kb
Host smart-ac77eb6a-89aa-4b3c-9382-a6b18bf55245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
01914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3960701914
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.171087208
Short name T311
Test name
Test status
Simulation time 199818080 ps
CPU time 0.82 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204736 kb
Host smart-771eb25a-e5d8-4f10-9c23-f0bff2d3f2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17108
7208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.171087208
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1253608922
Short name T1297
Test name
Test status
Simulation time 184151482 ps
CPU time 0.79 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204628 kb
Host smart-a53bdb73-ce1e-4991-98fc-c8e3e55dd58f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12536
08922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1253608922
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.4060727156
Short name T1014
Test name
Test status
Simulation time 163475931 ps
CPU time 0.73 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 204660 kb
Host smart-b075c35f-dc07-4106-8cc7-63745f67d4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40607
27156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.4060727156
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3259345211
Short name T529
Test name
Test status
Simulation time 153883790 ps
CPU time 0.8 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:17 PM PDT 24
Peak memory 204772 kb
Host smart-06ad8899-d461-4302-8175-b7721426a3f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32593
45211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3259345211
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.1891755008
Short name T1879
Test name
Test status
Simulation time 218734189 ps
CPU time 0.95 seconds
Started Jun 11 12:40:09 PM PDT 24
Finished Jun 11 12:40:13 PM PDT 24
Peak memory 204696 kb
Host smart-b74b66cf-9145-4155-836d-86e79ad33799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18917
55008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.1891755008
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2086468887
Short name T1225
Test name
Test status
Simulation time 194588365 ps
CPU time 0.84 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:18 PM PDT 24
Peak memory 204740 kb
Host smart-73a2dbb7-4da7-49af-a21d-297253588044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
68887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2086468887
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.4012138803
Short name T1528
Test name
Test status
Simulation time 183623925 ps
CPU time 0.84 seconds
Started Jun 11 12:40:05 PM PDT 24
Finished Jun 11 12:40:07 PM PDT 24
Peak memory 204700 kb
Host smart-cd717e9e-83c5-4d3f-97b3-f210f94a5bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40121
38803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.4012138803
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.371479173
Short name T1307
Test name
Test status
Simulation time 10961029918 ps
CPU time 99.23 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 204976 kb
Host smart-a6adc428-f390-4d8a-aae6-24575f893d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
9173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.371479173
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.534084835
Short name T2096
Test name
Test status
Simulation time 10060866413 ps
CPU time 189.96 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 204936 kb
Host smart-e863a4b0-2ea4-4e59-9a40-87e814e917cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534084835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bu
s_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_t
raffic.534084835
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3452129357
Short name T1221
Test name
Test status
Simulation time 4181740788 ps
CPU time 4.91 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204804 kb
Host smart-535d66b2-03a6-482f-a365-68895859ef24
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3452129357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3452129357
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1753381641
Short name T1988
Test name
Test status
Simulation time 13356359190 ps
CPU time 15.66 seconds
Started Jun 11 12:41:54 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204792 kb
Host smart-837a1319-b0a8-4a50-b5a0-650a504ab930
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1753381641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1753381641
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.4283895454
Short name T1681
Test name
Test status
Simulation time 23395599583 ps
CPU time 24.11 seconds
Started Jun 11 12:42:00 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204832 kb
Host smart-25e7ab70-b064-4b58-84e0-95824cc21dda
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4283895454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.4283895454
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.4138824460
Short name T793
Test name
Test status
Simulation time 152737564 ps
CPU time 0.75 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204732 kb
Host smart-42c03d02-cc97-49d6-b153-10f2becb62e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41388
24460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.4138824460
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1536079050
Short name T1615
Test name
Test status
Simulation time 191878884 ps
CPU time 0.77 seconds
Started Jun 11 12:41:56 PM PDT 24
Finished Jun 11 12:41:59 PM PDT 24
Peak memory 204716 kb
Host smart-b4a55033-4a7a-48b9-a365-a69ee5571914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
79050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1536079050
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2293372415
Short name T1097
Test name
Test status
Simulation time 445067349 ps
CPU time 1.16 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204744 kb
Host smart-c1b3ba50-1f06-438f-93d3-def59ffe9d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22933
72415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2293372415
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2430563501
Short name T1623
Test name
Test status
Simulation time 140908549 ps
CPU time 0.75 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204708 kb
Host smart-e321e1a6-bf8f-4ac2-b222-0998884c2f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24305
63501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2430563501
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1224371735
Short name T449
Test name
Test status
Simulation time 56392822 ps
CPU time 0.67 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204724 kb
Host smart-92adb2be-2620-46f7-be81-cad99a3a8ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12243
71735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1224371735
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.2509387490
Short name T1996
Test name
Test status
Simulation time 730178936 ps
CPU time 1.93 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:02 PM PDT 24
Peak memory 204856 kb
Host smart-457700aa-3fad-4424-9fa4-3b10f5d5b964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25093
87490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2509387490
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1519696047
Short name T846
Test name
Test status
Simulation time 300658569 ps
CPU time 2.19 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204992 kb
Host smart-1379d750-1ae1-43d4-a615-f5a9254d9f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196
96047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1519696047
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.895616401
Short name T1181
Test name
Test status
Simulation time 191011851 ps
CPU time 0.84 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204732 kb
Host smart-318fa069-7fa6-4104-be3b-b858c382a462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89561
6401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.895616401
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.451883772
Short name T83
Test name
Test status
Simulation time 155829305 ps
CPU time 0.73 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204716 kb
Host smart-8eb9a2d6-ac14-484e-a356-c34a17114c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45188
3772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.451883772
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.514575298
Short name T1549
Test name
Test status
Simulation time 196321166 ps
CPU time 0.86 seconds
Started Jun 11 12:42:15 PM PDT 24
Finished Jun 11 12:42:18 PM PDT 24
Peak memory 204636 kb
Host smart-70c9e1db-0819-4402-8c56-2b6fb64dc38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51457
5298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.514575298
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2372903
Short name T459
Test name
Test status
Simulation time 157165289 ps
CPU time 0.78 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204752 kb
Host smart-52264399-eb6b-486b-9976-115ff057cb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23729
03 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2372903
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3242415502
Short name T921
Test name
Test status
Simulation time 3317577460 ps
CPU time 4.07 seconds
Started Jun 11 12:41:59 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204704 kb
Host smart-7d85efb1-ba9b-4d86-9bf8-797b458f7ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32424
15502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3242415502
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2623598250
Short name T2105
Test name
Test status
Simulation time 297034844 ps
CPU time 0.95 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204672 kb
Host smart-bd4c9e5c-cd81-4a6e-a0aa-b2616c97e4d5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2623598250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2623598250
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.4214517382
Short name T1695
Test name
Test status
Simulation time 244969694 ps
CPU time 0.9 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204732 kb
Host smart-5bd529be-5090-487b-a2ef-dc5002a8a70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
17382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.4214517382
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3215891167
Short name T1148
Test name
Test status
Simulation time 14544553124 ps
CPU time 101.74 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204944 kb
Host smart-b5df315d-dcd8-4a25-b4ad-0bfe72bf4310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32158
91167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3215891167
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.4000580438
Short name T681
Test name
Test status
Simulation time 161217762 ps
CPU time 0.8 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204648 kb
Host smart-c1a8a998-4655-4935-936a-d36c63ce31e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4000580438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.4000580438
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4006347837
Short name T582
Test name
Test status
Simulation time 142344196 ps
CPU time 0.73 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:05 PM PDT 24
Peak memory 204712 kb
Host smart-77b5a777-8ff4-48af-8541-0ea63fe0ef45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40063
47837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4006347837
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2976663352
Short name T160
Test name
Test status
Simulation time 206881047 ps
CPU time 0.86 seconds
Started Jun 11 12:42:06 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204664 kb
Host smart-bc7d0cc0-ef34-4b24-8ad6-b24942471828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29766
63352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2976663352
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2743362813
Short name T521
Test name
Test status
Simulation time 199449874 ps
CPU time 0.9 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204716 kb
Host smart-09cdd3b2-2a52-4197-aca1-6b30b9b041bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
62813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2743362813
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3222396944
Short name T786
Test name
Test status
Simulation time 194800760 ps
CPU time 0.9 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204624 kb
Host smart-5f096f7b-d5a4-488f-b638-be0e725f6a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32223
96944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3222396944
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.853187766
Short name T1503
Test name
Test status
Simulation time 230010241 ps
CPU time 0.81 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204672 kb
Host smart-cf709a34-b2a3-483a-b97f-23115cc3a980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85318
7766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.853187766
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2921754268
Short name T1482
Test name
Test status
Simulation time 167891630 ps
CPU time 0.76 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204732 kb
Host smart-570ee7cf-468d-4ded-bf1e-61777347e7b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29217
54268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2921754268
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_eop_single_bit_handling.1926017142
Short name T1372
Test name
Test status
Simulation time 174052854 ps
CPU time 0.82 seconds
Started Jun 11 12:42:00 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 204700 kb
Host smart-8350d0f0-7251-49c4-803a-8c3e13ab04df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19260
17142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_eop_single_bit_handling.1926017142
Directory /workspace/20.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4223593507
Short name T825
Test name
Test status
Simulation time 149321610 ps
CPU time 0.75 seconds
Started Jun 11 12:41:57 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204728 kb
Host smart-85f43458-669a-4a0b-8302-61e548514839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42235
93507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4223593507
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.672168535
Short name T1398
Test name
Test status
Simulation time 41988176 ps
CPU time 0.66 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204668 kb
Host smart-42d9ad3d-d793-4986-823a-017d039947e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67216
8535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.672168535
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.828453399
Short name T214
Test name
Test status
Simulation time 17334567766 ps
CPU time 40.52 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204936 kb
Host smart-8c1e03b9-c9f2-4d94-bee2-ca5051ebd612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82845
3399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.828453399
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3696615580
Short name T788
Test name
Test status
Simulation time 181973094 ps
CPU time 0.83 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204752 kb
Host smart-ee42152c-5c00-4ff6-befb-52826f6ad803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36966
15580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3696615580
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.290260249
Short name T662
Test name
Test status
Simulation time 171204918 ps
CPU time 0.89 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204664 kb
Host smart-341905ad-8613-42bd-8883-24c2c6944790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29026
0249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.290260249
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3425982550
Short name T654
Test name
Test status
Simulation time 206424930 ps
CPU time 0.85 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:04 PM PDT 24
Peak memory 204748 kb
Host smart-868aa608-fc13-4517-83f6-61ec57ff1338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34259
82550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3425982550
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2902976586
Short name T1354
Test name
Test status
Simulation time 190185753 ps
CPU time 0.84 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:28 PM PDT 24
Peak memory 204716 kb
Host smart-3c6b1938-258c-4da0-aa8e-bd25824592fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29029
76586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2902976586
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.601280285
Short name T1997
Test name
Test status
Simulation time 138577537 ps
CPU time 0.78 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204668 kb
Host smart-ca864766-4e81-4dff-b50b-df0e45a4ffc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60128
0285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.601280285
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3597646400
Short name T189
Test name
Test status
Simulation time 167478460 ps
CPU time 0.77 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204620 kb
Host smart-ee6f9171-3571-4160-bb7d-0dc6fcc0c606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35976
46400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3597646400
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1629063239
Short name T1411
Test name
Test status
Simulation time 153490191 ps
CPU time 0.73 seconds
Started Jun 11 12:42:08 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204744 kb
Host smart-de96e37f-fcfb-4d11-8b52-1afbd2030a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16290
63239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1629063239
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1811863120
Short name T182
Test name
Test status
Simulation time 246080967 ps
CPU time 0.97 seconds
Started Jun 11 12:42:00 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204704 kb
Host smart-7f604a44-2296-4017-bff9-3b349a7a69d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18118
63120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1811863120
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.3951316402
Short name T669
Test name
Test status
Simulation time 192871318 ps
CPU time 0.79 seconds
Started Jun 11 12:41:58 PM PDT 24
Finished Jun 11 12:42:00 PM PDT 24
Peak memory 204748 kb
Host smart-f10fc689-914e-4be8-9153-84ed193ad049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39513
16402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.3951316402
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1860369198
Short name T972
Test name
Test status
Simulation time 222282357 ps
CPU time 0.86 seconds
Started Jun 11 12:42:00 PM PDT 24
Finished Jun 11 12:42:03 PM PDT 24
Peak memory 204692 kb
Host smart-3428d164-9072-470f-8e9d-882f8b884ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18603
69198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1860369198
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.567271359
Short name T517
Test name
Test status
Simulation time 8833141949 ps
CPU time 237.69 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 205020 kb
Host smart-fd88c97b-b9d1-4c90-b8b1-bdc1fe1b3b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56727
1359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.567271359
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2440582225
Short name T1793
Test name
Test status
Simulation time 3976874422 ps
CPU time 4.62 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204756 kb
Host smart-b1a40fcb-fe04-4c1d-a76a-e39e7627479a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2440582225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2440582225
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.655147982
Short name T405
Test name
Test status
Simulation time 13380334153 ps
CPU time 13.35 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 205016 kb
Host smart-675dec38-ff34-4c3a-b1c5-1d0a078cf2c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=655147982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.655147982
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2534720755
Short name T2051
Test name
Test status
Simulation time 23360626309 ps
CPU time 22.68 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204756 kb
Host smart-06bab1e4-7c83-4de7-a951-e87e1b9a095c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2534720755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2534720755
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2958155331
Short name T736
Test name
Test status
Simulation time 161914917 ps
CPU time 0.83 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204736 kb
Host smart-a9cee38c-5271-4709-8075-683f50679b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29581
55331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2958155331
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.1040163443
Short name T92
Test name
Test status
Simulation time 164707832 ps
CPU time 0.77 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204760 kb
Host smart-7429afd5-39b9-41c5-b443-51761065292d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401
63443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1040163443
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2736617891
Short name T1194
Test name
Test status
Simulation time 339558234 ps
CPU time 0.99 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:18 PM PDT 24
Peak memory 204752 kb
Host smart-9849774c-2adf-48b3-bbdd-e711d6dc9493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
17891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2736617891
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2343797791
Short name T1843
Test name
Test status
Simulation time 141758778 ps
CPU time 0.75 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204728 kb
Host smart-f9e0551d-54a1-48c4-ad24-8fae17ea18a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23437
97791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2343797791
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.4140729725
Short name T2110
Test name
Test status
Simulation time 76628462 ps
CPU time 0.68 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 204692 kb
Host smart-860d45fb-26ba-456d-9984-7514665a694d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41407
29725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.4140729725
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1302153172
Short name T1591
Test name
Test status
Simulation time 938537257 ps
CPU time 2.32 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204936 kb
Host smart-82749aee-3356-46b4-9aeb-1014ae5df56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
53172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1302153172
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3544143605
Short name T1376
Test name
Test status
Simulation time 195539061 ps
CPU time 1.31 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204996 kb
Host smart-01cec2bb-c6be-4e56-bc69-7df82bcb5884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35441
43605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3544143605
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1507991291
Short name T1999
Test name
Test status
Simulation time 151107511 ps
CPU time 0.74 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204764 kb
Host smart-ccc06755-79a5-49d3-aeaf-cc20f91d8b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15079
91291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1507991291
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.750452574
Short name T855
Test name
Test status
Simulation time 212157436 ps
CPU time 0.86 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204712 kb
Host smart-8c23b1fc-90a0-4b68-a007-08747a26eb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75045
2574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.750452574
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.2132338345
Short name T1845
Test name
Test status
Simulation time 174811132 ps
CPU time 0.82 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204724 kb
Host smart-22d33179-fdd3-4509-acbf-f0a1a249e8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
38345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.2132338345
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2015372571
Short name T444
Test name
Test status
Simulation time 3287431396 ps
CPU time 4.51 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204776 kb
Host smart-ca10ddf3-003a-438b-a73d-4caa47d4012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
72571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2015372571
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1348744654
Short name T1147
Test name
Test status
Simulation time 233049636 ps
CPU time 0.87 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204680 kb
Host smart-f29903e0-f993-4666-9cd0-b43faa7561ed
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1348744654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1348744654
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2941977946
Short name T1104
Test name
Test status
Simulation time 191038035 ps
CPU time 0.87 seconds
Started Jun 11 12:42:06 PM PDT 24
Finished Jun 11 12:42:10 PM PDT 24
Peak memory 204732 kb
Host smart-cadc70dc-8477-4c8c-8583-5ff8f228b257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29419
77946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2941977946
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2078136298
Short name T1820
Test name
Test status
Simulation time 11151437143 ps
CPU time 81.74 seconds
Started Jun 11 12:42:06 PM PDT 24
Finished Jun 11 12:43:31 PM PDT 24
Peak memory 205056 kb
Host smart-8e440a94-7e0b-44f9-81ae-48a0669b5b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
36298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2078136298
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.4091390717
Short name T932
Test name
Test status
Simulation time 162425236 ps
CPU time 0.84 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204772 kb
Host smart-517d4e48-a124-4531-a298-9342043968be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4091390717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.4091390717
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3028467425
Short name T505
Test name
Test status
Simulation time 152643730 ps
CPU time 0.76 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204704 kb
Host smart-8f28b3db-7e2b-43fa-a62f-08427503b73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30284
67425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3028467425
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.867889241
Short name T1718
Test name
Test status
Simulation time 164458479 ps
CPU time 0.8 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204668 kb
Host smart-e23a048a-66a9-4f14-99b2-9ac3559c61fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86788
9241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.867889241
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3436099555
Short name T1985
Test name
Test status
Simulation time 177672846 ps
CPU time 0.84 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204692 kb
Host smart-3bcea35c-fed2-43ac-a2e4-f058b951b6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34360
99555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3436099555
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1122645643
Short name T493
Test name
Test status
Simulation time 245344462 ps
CPU time 0.84 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204700 kb
Host smart-bf15e436-7428-45d0-bae9-bf7b68d00ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11226
45643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1122645643
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.770374667
Short name T606
Test name
Test status
Simulation time 170435429 ps
CPU time 0.8 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204744 kb
Host smart-41c63a4c-3226-4424-bd53-1e8ff3081f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77037
4667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.770374667
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_eop_single_bit_handling.3523737396
Short name T2067
Test name
Test status
Simulation time 171052477 ps
CPU time 0.99 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204744 kb
Host smart-6ceff3e2-ec12-4f29-8fe2-9e6923040ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35237
37396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_eop_single_bit_handling.3523737396
Directory /workspace/21.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2116969086
Short name T923
Test name
Test status
Simulation time 153145963 ps
CPU time 0.75 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204740 kb
Host smart-5287516d-f261-4b7e-bb27-38fd9627d24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21169
69086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2116969086
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.583838329
Short name T708
Test name
Test status
Simulation time 35943400 ps
CPU time 0.66 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204624 kb
Host smart-705f32cd-fcf6-4c89-b9a1-223c7cf82b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58383
8329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.583838329
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.831488313
Short name T241
Test name
Test status
Simulation time 12467044670 ps
CPU time 26.23 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:31 PM PDT 24
Peak memory 204956 kb
Host smart-41311a36-a6bd-4881-9da9-581a3ddccf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83148
8313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.831488313
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3249852100
Short name T1514
Test name
Test status
Simulation time 218250424 ps
CPU time 0.84 seconds
Started Jun 11 12:42:13 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204696 kb
Host smart-bb652b29-07b8-4de2-a149-a0cfbbc27e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498
52100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3249852100
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1219240002
Short name T663
Test name
Test status
Simulation time 229892146 ps
CPU time 0.87 seconds
Started Jun 11 12:41:59 PM PDT 24
Finished Jun 11 12:42:02 PM PDT 24
Peak memory 204568 kb
Host smart-93abc095-1fb7-45fa-baed-87005a9b37a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12192
40002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1219240002
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2279740416
Short name T1892
Test name
Test status
Simulation time 265493078 ps
CPU time 0.87 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204720 kb
Host smart-2bf57605-48fb-47e6-8cd0-e33629ee5e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22797
40416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2279740416
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.380026916
Short name T2060
Test name
Test status
Simulation time 154128922 ps
CPU time 0.8 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204740 kb
Host smart-f8ed0ab5-86ca-4e39-bc01-385bcbc6c7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38002
6916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.380026916
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.3232359883
Short name T354
Test name
Test status
Simulation time 149034982 ps
CPU time 0.78 seconds
Started Jun 11 12:41:59 PM PDT 24
Finished Jun 11 12:42:02 PM PDT 24
Peak memory 204736 kb
Host smart-f7c10a58-f4e9-49cb-a545-e5ba2a830a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32323
59883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.3232359883
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2799436835
Short name T133
Test name
Test status
Simulation time 149452045 ps
CPU time 0.77 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204740 kb
Host smart-80e57d4e-04f2-407f-99fb-dc407ee18b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27994
36835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2799436835
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.409682251
Short name T1966
Test name
Test status
Simulation time 143784725 ps
CPU time 0.77 seconds
Started Jun 11 12:42:02 PM PDT 24
Finished Jun 11 12:42:06 PM PDT 24
Peak memory 204712 kb
Host smart-6ea5ebe6-112a-4226-90eb-4ddaa4b1778f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40968
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.409682251
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1150570276
Short name T1005
Test name
Test status
Simulation time 256878089 ps
CPU time 0.98 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204712 kb
Host smart-694b3e84-ec93-4607-aab2-98328d6b9c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
70276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1150570276
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3398481137
Short name T2053
Test name
Test status
Simulation time 187485076 ps
CPU time 0.82 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204720 kb
Host smart-fa6e4c57-67f0-4a7d-bd63-3676ce8ec21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33984
81137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3398481137
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4186766347
Short name T817
Test name
Test status
Simulation time 173443300 ps
CPU time 0.81 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204648 kb
Host smart-230fd0e7-d9f8-4de9-8eb3-e80609fed000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41867
66347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4186766347
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2909972501
Short name T1134
Test name
Test status
Simulation time 8625566128 ps
CPU time 83.71 seconds
Started Jun 11 12:42:01 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204960 kb
Host smart-55c99af1-c14e-411c-866e-353dec6e5e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29099
72501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2909972501
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.404726912
Short name T104
Test name
Test status
Simulation time 3831785324 ps
CPU time 4.64 seconds
Started Jun 11 12:42:04 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204820 kb
Host smart-04cf5c33-603c-4d19-ba68-eecaefd8546e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=404726912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.404726912
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1737777900
Short name T845
Test name
Test status
Simulation time 13436422141 ps
CPU time 17.12 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 205060 kb
Host smart-383f6508-1982-47db-82ea-962492b432f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1737777900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1737777900
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2547076993
Short name T960
Test name
Test status
Simulation time 23402423572 ps
CPU time 25.05 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204924 kb
Host smart-07d8f7e4-bb57-4688-89e2-ab7e505adb44
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2547076993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.2547076993
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3382840859
Short name T1136
Test name
Test status
Simulation time 179071643 ps
CPU time 0.82 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204732 kb
Host smart-8665289d-9d29-4f59-8b87-7391b9c6d86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33828
40859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3382840859
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.481092954
Short name T952
Test name
Test status
Simulation time 169340308 ps
CPU time 0.77 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204740 kb
Host smart-364b7d7e-7f3f-4c5b-8a67-41728e7ae0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48109
2954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.481092954
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.4108656223
Short name T1554
Test name
Test status
Simulation time 708846639 ps
CPU time 1.71 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:08 PM PDT 24
Peak memory 204908 kb
Host smart-6a9db457-d835-4e9c-9401-8f229536c510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41086
56223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.4108656223
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2800432876
Short name T813
Test name
Test status
Simulation time 209945331 ps
CPU time 0.85 seconds
Started Jun 11 12:42:28 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204660 kb
Host smart-73b110d2-e47e-44fb-91bd-72611caa0dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28004
32876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2800432876
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2669620991
Short name T1130
Test name
Test status
Simulation time 56523241 ps
CPU time 0.67 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204724 kb
Host smart-00367943-00bd-4529-bf70-ff371976e227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
20991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2669620991
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2417784822
Short name T372
Test name
Test status
Simulation time 870394604 ps
CPU time 2.09 seconds
Started Jun 11 12:42:08 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 205016 kb
Host smart-ee8737e8-71a1-4bfa-9bb1-25cf1a745354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24177
84822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2417784822
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1328767286
Short name T95
Test name
Test status
Simulation time 167250538 ps
CPU time 1.73 seconds
Started Jun 11 12:42:13 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204836 kb
Host smart-a01d9dda-c76a-4296-a4b8-eb2267a57ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13287
67286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1328767286
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3627661887
Short name T1969
Test name
Test status
Simulation time 189713219 ps
CPU time 0.83 seconds
Started Jun 11 12:42:23 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204628 kb
Host smart-9ae431d2-37f4-4d95-8911-c1db76a2b86d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36276
61887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3627661887
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3582205778
Short name T690
Test name
Test status
Simulation time 143099780 ps
CPU time 0.75 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204568 kb
Host smart-26b6dfe3-f0f4-49b9-a11e-b9d1392d6d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35822
05778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3582205778
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3360555510
Short name T482
Test name
Test status
Simulation time 186978603 ps
CPU time 0.96 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204664 kb
Host smart-80686b3c-917b-4173-ab27-b503549a79e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33605
55510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3360555510
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.890987929
Short name T754
Test name
Test status
Simulation time 230991274 ps
CPU time 0.9 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204748 kb
Host smart-41ebccf0-954d-4ed8-8cb5-5e69e5a1c277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89098
7929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.890987929
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3086242053
Short name T1571
Test name
Test status
Simulation time 3322716827 ps
CPU time 3.7 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204828 kb
Host smart-635e7839-5b28-4407-aa41-dcec774db16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30862
42053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3086242053
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2817562855
Short name T445
Test name
Test status
Simulation time 285458317 ps
CPU time 0.97 seconds
Started Jun 11 12:42:28 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204748 kb
Host smart-ec536eef-8a60-482c-875c-a169be575161
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2817562855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2817562855
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.4123432476
Short name T1747
Test name
Test status
Simulation time 190521369 ps
CPU time 0.87 seconds
Started Jun 11 12:42:27 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 204704 kb
Host smart-19713c0d-8287-472d-a68b-b8be8cc15f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41234
32476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.4123432476
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.824871598
Short name T1860
Test name
Test status
Simulation time 7438110640 ps
CPU time 205.99 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 205032 kb
Host smart-c8a65ef7-4f09-4e60-bae9-f6c25048b600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82487
1598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.824871598
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2675887985
Short name T1501
Test name
Test status
Simulation time 183618398 ps
CPU time 0.8 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204676 kb
Host smart-b2089ff4-7315-4e53-9d74-024545506dd9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2675887985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2675887985
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2046799674
Short name T1418
Test name
Test status
Simulation time 152465041 ps
CPU time 0.77 seconds
Started Jun 11 12:42:21 PM PDT 24
Finished Jun 11 12:42:24 PM PDT 24
Peak memory 204972 kb
Host smart-72f8eed1-7d82-4ef4-88ca-0e9f3759bda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
99674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2046799674
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1399025939
Short name T561
Test name
Test status
Simulation time 188191465 ps
CPU time 0.94 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204732 kb
Host smart-b17c38dd-813f-4acc-8277-e0d7e4e067dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13990
25939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1399025939
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3495456523
Short name T946
Test name
Test status
Simulation time 189486295 ps
CPU time 0.8 seconds
Started Jun 11 12:42:29 PM PDT 24
Finished Jun 11 12:42:32 PM PDT 24
Peak memory 204712 kb
Host smart-0c0483a4-d04d-4d83-bdb6-1f802da4d193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34954
56523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3495456523
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1375774561
Short name T1313
Test name
Test status
Simulation time 173197610 ps
CPU time 0.82 seconds
Started Jun 11 12:42:22 PM PDT 24
Finished Jun 11 12:42:25 PM PDT 24
Peak memory 204688 kb
Host smart-dee2ed9d-2b08-4da1-9acf-464b69a51a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757
74561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1375774561
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1594260358
Short name T2091
Test name
Test status
Simulation time 157068504 ps
CPU time 0.74 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204736 kb
Host smart-aef937c0-551c-4b6a-ab5b-2eab97a47ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15942
60358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1594260358
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_eop_single_bit_handling.3094877090
Short name T889
Test name
Test status
Simulation time 152171109 ps
CPU time 0.79 seconds
Started Jun 11 12:42:23 PM PDT 24
Finished Jun 11 12:42:25 PM PDT 24
Peak memory 204644 kb
Host smart-51712ac8-8631-4c66-b72e-5f1741a1e784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
77090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_eop_single_bit_handling.3094877090
Directory /workspace/22.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.405602634
Short name T2111
Test name
Test status
Simulation time 191304076 ps
CPU time 0.78 seconds
Started Jun 11 12:42:18 PM PDT 24
Finished Jun 11 12:42:20 PM PDT 24
Peak memory 204732 kb
Host smart-1fa2df93-db82-44f9-a017-52a107a06654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40560
2634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.405602634
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.813313014
Short name T1476
Test name
Test status
Simulation time 42689225 ps
CPU time 0.67 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204692 kb
Host smart-3c044530-8644-43cc-84d4-53283d7cc2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81331
3014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.813313014
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.4150909677
Short name T1118
Test name
Test status
Simulation time 12922173358 ps
CPU time 27.66 seconds
Started Jun 11 12:42:08 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204980 kb
Host smart-fc154df2-6a72-4353-9414-a9cbe63b9346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
09677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.4150909677
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3178537081
Short name T919
Test name
Test status
Simulation time 186009419 ps
CPU time 0.8 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204732 kb
Host smart-c17fe7da-177b-4ab5-83f9-6adb93dfeb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
37081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3178537081
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2027192122
Short name T1657
Test name
Test status
Simulation time 300173913 ps
CPU time 0.89 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204744 kb
Host smart-35cc9cd5-fe0c-4492-a0d7-f2a3fab37ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20271
92122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2027192122
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2307540429
Short name T963
Test name
Test status
Simulation time 216733197 ps
CPU time 0.91 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204748 kb
Host smart-dccccd9f-1ef4-497e-b630-1170de41ea8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23075
40429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2307540429
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3014082596
Short name T2013
Test name
Test status
Simulation time 177239332 ps
CPU time 0.9 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204712 kb
Host smart-fd34c9cb-1318-4811-b2e8-3414304d7db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30140
82596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3014082596
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.681733437
Short name T67
Test name
Test status
Simulation time 163852142 ps
CPU time 0.78 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204720 kb
Host smart-a8582ed3-f32e-4e80-8e21-6cd83aa9c42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68173
3437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.681733437
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3684010015
Short name T183
Test name
Test status
Simulation time 175408628 ps
CPU time 0.77 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:36 PM PDT 24
Peak memory 204728 kb
Host smart-13a60d62-0840-4cb5-a129-a4adc685a344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
10015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3684010015
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3173022639
Short name T1557
Test name
Test status
Simulation time 150732527 ps
CPU time 0.74 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:11 PM PDT 24
Peak memory 204712 kb
Host smart-eea6b2b7-58f1-41a5-9c35-66f6f0a7ec6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31730
22639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3173022639
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2986275376
Short name T843
Test name
Test status
Simulation time 190916296 ps
CPU time 0.85 seconds
Started Jun 11 12:42:05 PM PDT 24
Finished Jun 11 12:42:09 PM PDT 24
Peak memory 204672 kb
Host smart-1956a1c7-f36f-4b18-8a40-65acf59dd3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29862
75376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2986275376
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.4254626741
Short name T732
Test name
Test status
Simulation time 196293207 ps
CPU time 0.84 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204744 kb
Host smart-4cbaf0ed-91fd-4cbe-898a-799cdf092e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42546
26741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4254626741
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2558592826
Short name T1355
Test name
Test status
Simulation time 194186699 ps
CPU time 0.81 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204728 kb
Host smart-2a183056-1a3a-447d-b0a6-f92ed577201e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25585
92826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2558592826
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2327290109
Short name T850
Test name
Test status
Simulation time 10556354524 ps
CPU time 278.23 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 205060 kb
Host smart-a4f5001a-99fc-4fe1-8de4-31dbec25cf27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
90109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2327290109
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3576238733
Short name T1812
Test name
Test status
Simulation time 4204514634 ps
CPU time 5.09 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 205092 kb
Host smart-e2e10115-ea60-4980-a47d-9cc5e5ba8714
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3576238733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3576238733
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2140219130
Short name T1537
Test name
Test status
Simulation time 13339547113 ps
CPU time 13.43 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204800 kb
Host smart-e3b564b3-64f2-438d-8c85-87e508018022
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2140219130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2140219130
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1800018266
Short name T615
Test name
Test status
Simulation time 23415322469 ps
CPU time 26.3 seconds
Started Jun 11 12:42:30 PM PDT 24
Finished Jun 11 12:42:57 PM PDT 24
Peak memory 204780 kb
Host smart-512ae649-9ed0-4282-9874-7063d29850ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1800018266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1800018266
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3359848544
Short name T1646
Test name
Test status
Simulation time 182631667 ps
CPU time 0.81 seconds
Started Jun 11 12:42:15 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204736 kb
Host smart-4d23e92a-8b52-4af0-816b-0ad8ae41d16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33598
48544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3359848544
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.524009330
Short name T1437
Test name
Test status
Simulation time 143001077 ps
CPU time 0.79 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204700 kb
Host smart-93efd94e-28af-407c-a66b-209fade44603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52400
9330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.524009330
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.3377794742
Short name T483
Test name
Test status
Simulation time 954083542 ps
CPU time 2.06 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204908 kb
Host smart-688979fb-bb6d-490b-9dc7-3484d9a2e665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33777
94742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3377794742
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.923073649
Short name T614
Test name
Test status
Simulation time 153592023 ps
CPU time 0.77 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204660 kb
Host smart-fd6b1d45-0865-432a-b50d-7cc7b6b3afb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92307
3649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.923073649
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3245735063
Short name T688
Test name
Test status
Simulation time 59914044 ps
CPU time 0.67 seconds
Started Jun 11 12:42:07 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204704 kb
Host smart-da91161e-ae04-4083-bd67-869c7cb8feba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
35063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3245735063
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4071437141
Short name T1094
Test name
Test status
Simulation time 961330278 ps
CPU time 2.23 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 205044 kb
Host smart-e95075d5-0102-462c-a7dd-4e76d13a8fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714
37141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4071437141
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2530000972
Short name T2020
Test name
Test status
Simulation time 295085184 ps
CPU time 1.85 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 205024 kb
Host smart-174424d7-26de-4a43-8055-8d6958bcb057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300
00972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2530000972
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.715829504
Short name T1394
Test name
Test status
Simulation time 152291304 ps
CPU time 0.75 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204752 kb
Host smart-70a1c1de-e8c8-4676-a7ce-dc80ad4ef202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71582
9504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.715829504
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.915776877
Short name T649
Test name
Test status
Simulation time 139231139 ps
CPU time 0.74 seconds
Started Jun 11 12:42:24 PM PDT 24
Finished Jun 11 12:42:26 PM PDT 24
Peak memory 204744 kb
Host smart-edd1e092-775f-4a15-b9ae-5fa475b7e4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91577
6877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.915776877
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2718702774
Short name T1324
Test name
Test status
Simulation time 298213854 ps
CPU time 1 seconds
Started Jun 11 12:42:22 PM PDT 24
Finished Jun 11 12:42:25 PM PDT 24
Peak memory 204732 kb
Host smart-dc13e1e3-472c-48b5-980f-1ab494676cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27187
02774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2718702774
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2607368137
Short name T1540
Test name
Test status
Simulation time 237392156 ps
CPU time 0.86 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204704 kb
Host smart-e66ea467-095e-48bf-95fa-fd63401bdc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
68137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2607368137
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2745603521
Short name T581
Test name
Test status
Simulation time 3282505036 ps
CPU time 3.75 seconds
Started Jun 11 12:42:22 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204816 kb
Host smart-4f9548a2-2b6d-43bc-be85-1911ad505baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27456
03521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2745603521
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1467522896
Short name T1842
Test name
Test status
Simulation time 248328017 ps
CPU time 0.9 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:38 PM PDT 24
Peak memory 204724 kb
Host smart-d091af8e-8b0e-42fb-9f49-3af3c89e7e2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1467522896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1467522896
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3983030570
Short name T1906
Test name
Test status
Simulation time 215595729 ps
CPU time 0.88 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204752 kb
Host smart-89cae4b5-6f5a-4a4b-a87f-e102b8c83098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39830
30570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3983030570
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2327308657
Short name T988
Test name
Test status
Simulation time 13228668960 ps
CPU time 90.58 seconds
Started Jun 11 12:42:23 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204984 kb
Host smart-934ac9f7-28f7-47f6-a9a6-5970b5da7b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23273
08657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2327308657
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.538626727
Short name T1670
Test name
Test status
Simulation time 161074926 ps
CPU time 0.78 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:42:53 PM PDT 24
Peak memory 204748 kb
Host smart-08df4a4b-2cc1-44a0-b433-ad76d708133b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=538626727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.538626727
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.714275496
Short name T1056
Test name
Test status
Simulation time 150254515 ps
CPU time 0.75 seconds
Started Jun 11 12:42:08 PM PDT 24
Finished Jun 11 12:42:12 PM PDT 24
Peak memory 204744 kb
Host smart-b497794e-f2a8-4ef1-aa42-561c8c5ce7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71427
5496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.714275496
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3248310712
Short name T163
Test name
Test status
Simulation time 231561663 ps
CPU time 0.94 seconds
Started Jun 11 12:42:19 PM PDT 24
Finished Jun 11 12:42:21 PM PDT 24
Peak memory 204596 kb
Host smart-f8fc6b28-66e5-4cdf-991c-fadac17af8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32483
10712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3248310712
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.797895694
Short name T1721
Test name
Test status
Simulation time 184840037 ps
CPU time 0.8 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204716 kb
Host smart-8d51905e-7f8e-4140-888a-d1450da1b657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79789
5694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.797895694
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2654412451
Short name T1448
Test name
Test status
Simulation time 176590974 ps
CPU time 0.79 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204776 kb
Host smart-87d7ccca-a5ef-4cff-8b9d-b8c2109eb178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26544
12451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2654412451
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.2151394799
Short name T21
Test name
Test status
Simulation time 180021008 ps
CPU time 0.83 seconds
Started Jun 11 12:42:28 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204740 kb
Host smart-64f03085-5c07-4d89-95ba-3be67957a620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21513
94799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.2151394799
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2651930392
Short name T1374
Test name
Test status
Simulation time 152939576 ps
CPU time 0.75 seconds
Started Jun 11 12:42:20 PM PDT 24
Finished Jun 11 12:42:22 PM PDT 24
Peak memory 204672 kb
Host smart-9aec324f-b720-4129-b662-a7e2f78b200a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26519
30392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2651930392
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_eop_single_bit_handling.2771629638
Short name T1203
Test name
Test status
Simulation time 152308644 ps
CPU time 0.78 seconds
Started Jun 11 12:42:21 PM PDT 24
Finished Jun 11 12:42:23 PM PDT 24
Peak memory 204704 kb
Host smart-e81e6774-71ec-43de-ab6a-be6e761e9273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
29638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_eop_single_bit_handling.2771629638
Directory /workspace/23.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1681589611
Short name T74
Test name
Test status
Simulation time 159112025 ps
CPU time 0.79 seconds
Started Jun 11 12:42:27 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204728 kb
Host smart-032e6858-bc28-4452-962b-ec511f70f7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
89611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1681589611
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.960522716
Short name T1878
Test name
Test status
Simulation time 70653898 ps
CPU time 0.67 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204564 kb
Host smart-6737e33e-1129-4682-9d4a-3e02cb9f4a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96052
2716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.960522716
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2020137141
Short name T1517
Test name
Test status
Simulation time 7366383345 ps
CPU time 14.91 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:42:47 PM PDT 24
Peak memory 204952 kb
Host smart-212b82d6-2cd3-45b8-bdfc-2a643ae2259e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20201
37141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2020137141
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2156564193
Short name T991
Test name
Test status
Simulation time 179968845 ps
CPU time 0.83 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204744 kb
Host smart-3a7fde99-d630-4dd2-92b5-e95d5e3ccfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21565
64193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2156564193
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3208994754
Short name T506
Test name
Test status
Simulation time 220282563 ps
CPU time 0.86 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:28 PM PDT 24
Peak memory 204748 kb
Host smart-f2b029eb-b586-4e26-b90f-ff8dff182d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32089
94754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3208994754
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3959759451
Short name T2117
Test name
Test status
Simulation time 191564899 ps
CPU time 0.87 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:36 PM PDT 24
Peak memory 204576 kb
Host smart-aa93da7f-1235-4595-9538-54fa03d13bb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39597
59451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3959759451
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2657253731
Short name T680
Test name
Test status
Simulation time 147317691 ps
CPU time 0.77 seconds
Started Jun 11 12:42:15 PM PDT 24
Finished Jun 11 12:42:18 PM PDT 24
Peak memory 204720 kb
Host smart-f086be22-4182-4bf9-bac4-67baef6d8f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
53731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2657253731
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3208676247
Short name T177
Test name
Test status
Simulation time 152322214 ps
CPU time 0.76 seconds
Started Jun 11 12:42:24 PM PDT 24
Finished Jun 11 12:42:26 PM PDT 24
Peak memory 204752 kb
Host smart-05c176cc-a13b-421a-99c2-c6f4dfec9c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
76247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3208676247
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3690318723
Short name T1922
Test name
Test status
Simulation time 185421459 ps
CPU time 0.79 seconds
Started Jun 11 12:42:19 PM PDT 24
Finished Jun 11 12:42:21 PM PDT 24
Peak memory 204752 kb
Host smart-6b4d9dec-3dc0-4938-b1b2-ade2a3915577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36903
18723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3690318723
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.457100038
Short name T957
Test name
Test status
Simulation time 232611109 ps
CPU time 0.89 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:42:34 PM PDT 24
Peak memory 204704 kb
Host smart-3db60348-ff0c-4213-9007-ef2b87c5a58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45710
0038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.457100038
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1442146525
Short name T1153
Test name
Test status
Simulation time 158378607 ps
CPU time 0.77 seconds
Started Jun 11 12:42:24 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204676 kb
Host smart-d4e52f93-aefc-4e01-a5fd-c99b1d2d4c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14421
46525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1442146525
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.311991173
Short name T1642
Test name
Test status
Simulation time 229110594 ps
CPU time 0.87 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204732 kb
Host smart-1b9b36ba-a0dd-4322-8570-4536da7793d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31199
1173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.311991173
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.488331422
Short name T948
Test name
Test status
Simulation time 12019190021 ps
CPU time 84.06 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 204944 kb
Host smart-a71b6233-e97a-4878-8db9-10df6be0a50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48833
1422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.488331422
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2859865944
Short name T1993
Test name
Test status
Simulation time 3466634558 ps
CPU time 4.03 seconds
Started Jun 11 12:42:08 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204724 kb
Host smart-cc53f4f8-399a-452e-b803-44acc72c1f18
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2859865944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2859865944
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.621384244
Short name T1750
Test name
Test status
Simulation time 13410931801 ps
CPU time 12.58 seconds
Started Jun 11 12:42:19 PM PDT 24
Finished Jun 11 12:42:33 PM PDT 24
Peak memory 204992 kb
Host smart-ee28fa0b-a623-488f-80d5-5b500977c226
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=621384244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.621384244
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2194180735
Short name T635
Test name
Test status
Simulation time 23368296882 ps
CPU time 22.2 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:35 PM PDT 24
Peak memory 204972 kb
Host smart-7a8c3ae6-3127-425e-aa14-c2e6aff63f86
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2194180735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2194180735
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.515386779
Short name T373
Test name
Test status
Simulation time 156244250 ps
CPU time 0.76 seconds
Started Jun 11 12:42:25 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204752 kb
Host smart-465b7b9a-d915-4b81-908f-f817c4e5f389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51538
6779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.515386779
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2364978346
Short name T695
Test name
Test status
Simulation time 168171074 ps
CPU time 0.78 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204708 kb
Host smart-383b8cc1-4d06-4108-aedf-2616f9bf7f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23649
78346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2364978346
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.109484732
Short name T1098
Test name
Test status
Simulation time 776416639 ps
CPU time 1.83 seconds
Started Jun 11 12:42:30 PM PDT 24
Finished Jun 11 12:42:33 PM PDT 24
Peak memory 204980 kb
Host smart-17a2869a-dfd4-4471-b991-1f12c359f436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10948
4732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.109484732
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2308942751
Short name T771
Test name
Test status
Simulation time 178448717 ps
CPU time 0.77 seconds
Started Jun 11 12:42:21 PM PDT 24
Finished Jun 11 12:42:24 PM PDT 24
Peak memory 204608 kb
Host smart-1dedb808-41e4-4dc8-a6a8-827ac4b47f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23089
42751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2308942751
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2775755900
Short name T1544
Test name
Test status
Simulation time 54671385 ps
CPU time 0.66 seconds
Started Jun 11 12:42:18 PM PDT 24
Finished Jun 11 12:42:20 PM PDT 24
Peak memory 204732 kb
Host smart-12ca876d-ae8a-4235-a466-5d17591ce299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27757
55900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2775755900
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1945337814
Short name T717
Test name
Test status
Simulation time 825122766 ps
CPU time 1.97 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 205024 kb
Host smart-3fa8f31b-85d7-4d89-a326-d3af0d487c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
37814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1945337814
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2770116213
Short name T784
Test name
Test status
Simulation time 174098164 ps
CPU time 1.79 seconds
Started Jun 11 12:42:40 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204908 kb
Host smart-20dc8502-6cfd-48d1-acfe-112c2353045f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27701
16213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2770116213
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2724340266
Short name T2018
Test name
Test status
Simulation time 197098267 ps
CPU time 0.85 seconds
Started Jun 11 12:42:16 PM PDT 24
Finished Jun 11 12:42:19 PM PDT 24
Peak memory 204720 kb
Host smart-beedc174-05ab-4aeb-a1cc-6561ee201be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27243
40266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2724340266
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1983948744
Short name T1716
Test name
Test status
Simulation time 151702043 ps
CPU time 0.75 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204652 kb
Host smart-fb398fcd-5c4d-4315-9e26-fbd541e14109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
48744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1983948744
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.43407598
Short name T1112
Test name
Test status
Simulation time 217005119 ps
CPU time 0.86 seconds
Started Jun 11 12:42:13 PM PDT 24
Finished Jun 11 12:42:16 PM PDT 24
Peak memory 204728 kb
Host smart-b32c757c-9429-4e43-9155-1e2e5b6662d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43407
598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.43407598
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.3130433418
Short name T545
Test name
Test status
Simulation time 208197930 ps
CPU time 0.85 seconds
Started Jun 11 12:42:25 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204688 kb
Host smart-98b7fd97-81ff-4c32-bd92-cf952e5d785f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
33418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3130433418
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1487423640
Short name T322
Test name
Test status
Simulation time 3297622473 ps
CPU time 4.13 seconds
Started Jun 11 12:42:21 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204704 kb
Host smart-b2a89333-6845-4b62-9a24-086a29fba121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14874
23640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1487423640
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.344800686
Short name T2047
Test name
Test status
Simulation time 302295017 ps
CPU time 1.03 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204672 kb
Host smart-ab7d31c9-8d1d-4644-9374-66b29bbcafb2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=344800686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.344800686
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2343399317
Short name T907
Test name
Test status
Simulation time 213887882 ps
CPU time 0.85 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204736 kb
Host smart-f32a16e9-0e65-4431-b9ec-c49c2a29b803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23433
99317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2343399317
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.157431158
Short name T1990
Test name
Test status
Simulation time 7617676493 ps
CPU time 72.19 seconds
Started Jun 11 12:42:17 PM PDT 24
Finished Jun 11 12:43:32 PM PDT 24
Peak memory 204940 kb
Host smart-7730a442-3458-49f7-9f25-954d0f6bbe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15743
1158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.157431158
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.274766617
Short name T1834
Test name
Test status
Simulation time 219957953 ps
CPU time 0.86 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204656 kb
Host smart-f9154ed4-4282-473a-9a4e-ecdaa408ab5c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=274766617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.274766617
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1106681253
Short name T608
Test name
Test status
Simulation time 181867869 ps
CPU time 0.81 seconds
Started Jun 11 12:42:40 PM PDT 24
Finished Jun 11 12:42:43 PM PDT 24
Peak memory 204732 kb
Host smart-a06252fd-4a9a-4024-861b-3562e3935adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11066
81253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1106681253
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2545916690
Short name T141
Test name
Test status
Simulation time 206015160 ps
CPU time 0.83 seconds
Started Jun 11 12:42:11 PM PDT 24
Finished Jun 11 12:42:15 PM PDT 24
Peak memory 204600 kb
Host smart-97d8a50f-e24e-4791-baa8-14899bebccf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25459
16690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2545916690
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.720704107
Short name T733
Test name
Test status
Simulation time 172008771 ps
CPU time 0.81 seconds
Started Jun 11 12:42:03 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 204664 kb
Host smart-d5e6536f-7696-4b2e-92eb-58aaf4273486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72070
4107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.720704107
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1949597268
Short name T894
Test name
Test status
Simulation time 175118164 ps
CPU time 0.8 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204692 kb
Host smart-5aa17415-2586-4225-99ac-caadcdd3ab57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
97268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1949597268
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.3406814760
Short name T1408
Test name
Test status
Simulation time 183886239 ps
CPU time 0.79 seconds
Started Jun 11 12:42:28 PM PDT 24
Finished Jun 11 12:42:31 PM PDT 24
Peak memory 204688 kb
Host smart-3a36ad6f-4079-4396-a00d-1c547af655f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34068
14760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3406814760
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2129326629
Short name T2001
Test name
Test status
Simulation time 178295721 ps
CPU time 0.82 seconds
Started Jun 11 12:42:18 PM PDT 24
Finished Jun 11 12:42:20 PM PDT 24
Peak memory 204708 kb
Host smart-858d2c10-ac61-4efe-99b5-03cda3b872d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21293
26629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2129326629
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_eop_single_bit_handling.3108160009
Short name T1801
Test name
Test status
Simulation time 212401259 ps
CPU time 0.84 seconds
Started Jun 11 12:42:14 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 204692 kb
Host smart-a9b65eeb-b2f2-4389-b39f-7e05fec85004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31081
60009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_eop_single_bit_handling.3108160009
Directory /workspace/24.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3224700200
Short name T1512
Test name
Test status
Simulation time 146615488 ps
CPU time 0.75 seconds
Started Jun 11 12:42:20 PM PDT 24
Finished Jun 11 12:42:22 PM PDT 24
Peak memory 204712 kb
Host smart-b5c8d8fd-a413-4544-b43d-9a19a03cf62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247
00200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3224700200
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.4184781928
Short name T1229
Test name
Test status
Simulation time 36887734 ps
CPU time 0.64 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204724 kb
Host smart-5f5c795d-37dd-455e-9bcf-975cea941e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41847
81928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.4184781928
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3880097730
Short name T2089
Test name
Test status
Simulation time 14152023128 ps
CPU time 32.39 seconds
Started Jun 11 12:42:32 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 205264 kb
Host smart-cfb2836c-e93f-4a2d-9a94-b92bdccba659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38800
97730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3880097730
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.105078422
Short name T1505
Test name
Test status
Simulation time 177451350 ps
CPU time 0.86 seconds
Started Jun 11 12:42:18 PM PDT 24
Finished Jun 11 12:42:20 PM PDT 24
Peak memory 204700 kb
Host smart-8173e024-80f6-44ee-a5da-c96be926e569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507
8422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.105078422
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.2981379757
Short name T1132
Test name
Test status
Simulation time 300306141 ps
CPU time 0.91 seconds
Started Jun 11 12:42:17 PM PDT 24
Finished Jun 11 12:42:20 PM PDT 24
Peak memory 204664 kb
Host smart-f14f0c04-44f1-480b-bd3a-3cbf21338a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29813
79757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.2981379757
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.759596695
Short name T37
Test name
Test status
Simulation time 231567972 ps
CPU time 0.89 seconds
Started Jun 11 12:42:40 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204724 kb
Host smart-dccfb66f-f3e4-4f2f-af8c-bff0f1cf5986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75959
6695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.759596695
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.221845915
Short name T652
Test name
Test status
Simulation time 166139556 ps
CPU time 0.78 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:14 PM PDT 24
Peak memory 204768 kb
Host smart-5a1a02ac-3f5d-4251-b35b-7d6381b682ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22184
5915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.221845915
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.2332935833
Short name T1065
Test name
Test status
Simulation time 182884327 ps
CPU time 0.8 seconds
Started Jun 11 12:42:09 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204740 kb
Host smart-68e38394-4a79-474d-b7f7-4825f19fc40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23329
35833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.2332935833
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.4293902784
Short name T1509
Test name
Test status
Simulation time 177734941 ps
CPU time 0.78 seconds
Started Jun 11 12:42:10 PM PDT 24
Finished Jun 11 12:42:13 PM PDT 24
Peak memory 204620 kb
Host smart-e9883e70-f800-4ca9-b9e1-0b4e767bc446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42939
02784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.4293902784
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.1116598875
Short name T386
Test name
Test status
Simulation time 171711163 ps
CPU time 0.83 seconds
Started Jun 11 12:42:30 PM PDT 24
Finished Jun 11 12:42:32 PM PDT 24
Peak memory 204700 kb
Host smart-dba3b840-6a00-426c-9513-2434266c8c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11165
98875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.1116598875
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.2943646555
Short name T1741
Test name
Test status
Simulation time 211913536 ps
CPU time 0.92 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 204724 kb
Host smart-b78954ea-fa75-483e-b8d1-2f9008ddde5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29436
46555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.2943646555
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.4126474390
Short name T1676
Test name
Test status
Simulation time 250335717 ps
CPU time 0.83 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:42:38 PM PDT 24
Peak memory 204748 kb
Host smart-288c965a-5de0-4c3f-9dc9-0df85f3db47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
74390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.4126474390
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1784876246
Short name T1450
Test name
Test status
Simulation time 203703974 ps
CPU time 0.78 seconds
Started Jun 11 12:42:23 PM PDT 24
Finished Jun 11 12:42:25 PM PDT 24
Peak memory 204692 kb
Host smart-a1f2c207-0ba4-4e01-b5f4-5c2f46cc3444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17848
76246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1784876246
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2385687556
Short name T1455
Test name
Test status
Simulation time 7039471292 ps
CPU time 52.08 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:43:30 PM PDT 24
Peak memory 205084 kb
Host smart-d8edb210-7c64-4d3c-becd-233826762585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23856
87556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2385687556
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.471109732
Short name T1991
Test name
Test status
Simulation time 3626215356 ps
CPU time 4.93 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:49 PM PDT 24
Peak memory 204956 kb
Host smart-704c6df0-53a3-4371-91fe-a950a8d4aed2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=471109732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.471109732
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3933518678
Short name T1037
Test name
Test status
Simulation time 13387411668 ps
CPU time 13.98 seconds
Started Jun 11 12:42:44 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204796 kb
Host smart-f39cb081-ced5-4213-a518-9cc57655e591
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3933518678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3933518678
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3278619371
Short name T375
Test name
Test status
Simulation time 23300063958 ps
CPU time 22.98 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:42:55 PM PDT 24
Peak memory 204960 kb
Host smart-bf90f7af-bc4d-4571-be7d-b72ee8b420d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3278619371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.3278619371
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.4135781226
Short name T2059
Test name
Test status
Simulation time 148912402 ps
CPU time 0.75 seconds
Started Jun 11 12:42:40 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204680 kb
Host smart-f71c1716-cbb8-4806-ba51-01204fae8e0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
81226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4135781226
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2104715509
Short name T1605
Test name
Test status
Simulation time 157702498 ps
CPU time 0.79 seconds
Started Jun 11 12:42:29 PM PDT 24
Finished Jun 11 12:42:32 PM PDT 24
Peak memory 204724 kb
Host smart-b456ddd4-6fbe-4123-9548-ccb9e8c3bc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
15509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2104715509
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.4066478970
Short name T201
Test name
Test status
Simulation time 992585217 ps
CPU time 2.2 seconds
Started Jun 11 12:42:21 PM PDT 24
Finished Jun 11 12:42:24 PM PDT 24
Peak memory 204972 kb
Host smart-bdc36bb0-f2b7-4158-970b-c0ebaacc92c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
78970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.4066478970
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3604437260
Short name T737
Test name
Test status
Simulation time 144658486 ps
CPU time 0.78 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:42:40 PM PDT 24
Peak memory 204596 kb
Host smart-91ae56ab-3692-4857-a05f-976fa83f1382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36044
37260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3604437260
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.397210454
Short name T407
Test name
Test status
Simulation time 40609699 ps
CPU time 0.65 seconds
Started Jun 11 12:42:32 PM PDT 24
Finished Jun 11 12:42:34 PM PDT 24
Peak memory 204728 kb
Host smart-fde34d1b-dde9-40d5-9e87-0d701db1f594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39721
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.397210454
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.2005051035
Short name T1516
Test name
Test status
Simulation time 1015179980 ps
CPU time 2.35 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204892 kb
Host smart-d4e53506-a4b7-4614-a7dc-5d5c3f5f3cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20050
51035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2005051035
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1838517920
Short name T366
Test name
Test status
Simulation time 335956182 ps
CPU time 2.01 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204880 kb
Host smart-71134bf6-b3be-4367-8099-23adae8b9728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
17920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1838517920
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.3324649335
Short name T1504
Test name
Test status
Simulation time 183125285 ps
CPU time 0.81 seconds
Started Jun 11 12:42:33 PM PDT 24
Finished Jun 11 12:42:35 PM PDT 24
Peak memory 204776 kb
Host smart-29805f66-b0d3-49ed-97ed-9043b60ebaa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246
49335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.3324649335
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1686019463
Short name T1946
Test name
Test status
Simulation time 140943475 ps
CPU time 0.78 seconds
Started Jun 11 12:42:29 PM PDT 24
Finished Jun 11 12:42:31 PM PDT 24
Peak memory 204764 kb
Host smart-f2107192-2cb4-4748-9fd1-367ddce9a176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
19463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1686019463
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3898841665
Short name T1898
Test name
Test status
Simulation time 209171639 ps
CPU time 0.83 seconds
Started Jun 11 12:42:39 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204672 kb
Host smart-06fe090d-7e2b-429f-8c87-86bcb1c523cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
41665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3898841665
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2875301921
Short name T1192
Test name
Test status
Simulation time 181387509 ps
CPU time 0.79 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:38 PM PDT 24
Peak memory 205012 kb
Host smart-72bba0f3-b8e6-4c24-a273-625799b004ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28753
01921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2875301921
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.784935
Short name T514
Test name
Test status
Simulation time 3326106326 ps
CPU time 4 seconds
Started Jun 11 12:42:44 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204636 kb
Host smart-dc62bd03-43fb-49e2-90a3-5a84fc920b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78493
5 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.784935
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.421445050
Short name T564
Test name
Test status
Simulation time 254734982 ps
CPU time 0.93 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204656 kb
Host smart-8b1798d8-d803-4fdb-b2bd-fd5285256d15
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=421445050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.421445050
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1178076062
Short name T589
Test name
Test status
Simulation time 204128192 ps
CPU time 0.88 seconds
Started Jun 11 12:42:30 PM PDT 24
Finished Jun 11 12:42:32 PM PDT 24
Peak memory 204696 kb
Host smart-159706d8-d47f-4f06-b8c7-ac2cfea12a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11780
76062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1178076062
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2661756963
Short name T1707
Test name
Test status
Simulation time 4347501212 ps
CPU time 30.47 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:43:09 PM PDT 24
Peak memory 205012 kb
Host smart-fb3af76f-9d2b-462e-8a00-6725a9f59c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617
56963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2661756963
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3688546791
Short name T1777
Test name
Test status
Simulation time 153881578 ps
CPU time 0.79 seconds
Started Jun 11 12:42:28 PM PDT 24
Finished Jun 11 12:42:31 PM PDT 24
Peak memory 204784 kb
Host smart-aab5e2ff-0cc3-45b6-bbec-0e7622655b66
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3688546791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3688546791
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.244565783
Short name T1912
Test name
Test status
Simulation time 144670185 ps
CPU time 0.74 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:38 PM PDT 24
Peak memory 205020 kb
Host smart-f092acb7-f3d2-4376-bb99-a24b53adc3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24456
5783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.244565783
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1991383086
Short name T1072
Test name
Test status
Simulation time 209559187 ps
CPU time 0.81 seconds
Started Jun 11 12:42:27 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 204752 kb
Host smart-a7b402f1-b94a-427d-9979-c97426e21803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913
83086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1991383086
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.715407031
Short name T1508
Test name
Test status
Simulation time 171160334 ps
CPU time 0.83 seconds
Started Jun 11 12:42:25 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204760 kb
Host smart-614ee4be-d758-49d6-bb9a-b36b3ecaea68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71540
7031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.715407031
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.391877296
Short name T18
Test name
Test status
Simulation time 211066839 ps
CPU time 0.88 seconds
Started Jun 11 12:42:33 PM PDT 24
Finished Jun 11 12:42:36 PM PDT 24
Peak memory 204620 kb
Host smart-c6f00949-70e0-4a0c-94f2-d6228646e792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39187
7296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.391877296
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3467950286
Short name T440
Test name
Test status
Simulation time 209276287 ps
CPU time 0.86 seconds
Started Jun 11 12:42:45 PM PDT 24
Finished Jun 11 12:42:48 PM PDT 24
Peak memory 204700 kb
Host smart-3466dd76-fb84-4ecc-9861-f54fc3e5c157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
50286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3467950286
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2074545488
Short name T982
Test name
Test status
Simulation time 154455641 ps
CPU time 0.77 seconds
Started Jun 11 12:42:24 PM PDT 24
Finished Jun 11 12:42:27 PM PDT 24
Peak memory 204716 kb
Host smart-f579676f-a7b8-44a1-971c-1f6a2b9a7d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20745
45488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2074545488
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_eop_single_bit_handling.2381517356
Short name T546
Test name
Test status
Simulation time 165054374 ps
CPU time 0.8 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204700 kb
Host smart-07f3dbef-e18f-400f-9ec7-51e32d59c393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23815
17356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_eop_single_bit_handling.2381517356
Directory /workspace/25.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2073623466
Short name T896
Test name
Test status
Simulation time 138139268 ps
CPU time 0.76 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:45 PM PDT 24
Peak memory 204692 kb
Host smart-0a0a6422-2c8a-4b00-bf38-663934829eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20736
23466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2073623466
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4162074311
Short name T1929
Test name
Test status
Simulation time 35249999 ps
CPU time 0.64 seconds
Started Jun 11 12:42:39 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204708 kb
Host smart-38eccdc3-6080-4383-977f-81c941d38e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41620
74311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4162074311
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3875688495
Short name T2030
Test name
Test status
Simulation time 20023405359 ps
CPU time 44.33 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 205008 kb
Host smart-2575c771-48c4-46d9-8507-aae774898f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756
88495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3875688495
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2331930995
Short name T617
Test name
Test status
Simulation time 168216469 ps
CPU time 0.84 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204720 kb
Host smart-e38e0ecb-356f-4baf-93dd-e298d7b515cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23319
30995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2331930995
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2060833016
Short name T1601
Test name
Test status
Simulation time 206967706 ps
CPU time 0.86 seconds
Started Jun 11 12:42:37 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204708 kb
Host smart-22d9f138-c69e-4964-96a5-5743cd3b419d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
33016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2060833016
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.297096778
Short name T1351
Test name
Test status
Simulation time 166058741 ps
CPU time 0.75 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:42:43 PM PDT 24
Peak memory 204676 kb
Host smart-147cbb84-97da-466a-a728-09d471806e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29709
6778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.297096778
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3190865138
Short name T127
Test name
Test status
Simulation time 165524710 ps
CPU time 0.85 seconds
Started Jun 11 12:42:46 PM PDT 24
Finished Jun 11 12:42:49 PM PDT 24
Peak memory 204652 kb
Host smart-c5704dc9-a0a6-4758-8e2e-a4f090cd5425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31908
65138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3190865138
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.252027229
Short name T945
Test name
Test status
Simulation time 155325790 ps
CPU time 0.77 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:42:39 PM PDT 24
Peak memory 204724 kb
Host smart-4cfefadf-016f-46c4-bafb-5dedd9c23b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25202
7229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.252027229
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2986840715
Short name T2026
Test name
Test status
Simulation time 152320923 ps
CPU time 0.77 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 204728 kb
Host smart-949730f8-d1ad-4c1a-a632-38b428caee32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29868
40715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2986840715
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1332292671
Short name T1877
Test name
Test status
Simulation time 165384018 ps
CPU time 0.77 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204648 kb
Host smart-1f2b2284-2945-4f79-9732-d2de0c593cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322
92671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1332292671
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1352090363
Short name T2017
Test name
Test status
Simulation time 203846668 ps
CPU time 0.91 seconds
Started Jun 11 12:42:29 PM PDT 24
Finished Jun 11 12:42:31 PM PDT 24
Peak memory 204984 kb
Host smart-10f6b7d8-7f42-48e8-9ae4-c609b193d769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13520
90363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1352090363
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.281233384
Short name T1260
Test name
Test status
Simulation time 163437368 ps
CPU time 0.77 seconds
Started Jun 11 12:42:30 PM PDT 24
Finished Jun 11 12:42:33 PM PDT 24
Peak memory 204684 kb
Host smart-9b1362ab-957f-4230-b0b7-c50bc4c427ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28123
3384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.281233384
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.934123793
Short name T639
Test name
Test status
Simulation time 154411673 ps
CPU time 0.78 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:42:33 PM PDT 24
Peak memory 204720 kb
Host smart-327c6b11-eaec-47ed-b14b-bbcb769ce8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93412
3793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.934123793
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1392500706
Short name T1645
Test name
Test status
Simulation time 11295425839 ps
CPU time 78.58 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 205028 kb
Host smart-69ae2fd4-4584-46fc-94df-e5834af78d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13925
00706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1392500706
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2491242145
Short name T54
Test name
Test status
Simulation time 3950864976 ps
CPU time 5.45 seconds
Started Jun 11 12:42:44 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204848 kb
Host smart-6426cbc3-bb37-4dc8-9a22-428dc402e4e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2491242145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2491242145
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.498355468
Short name T1852
Test name
Test status
Simulation time 13377960398 ps
CPU time 12.46 seconds
Started Jun 11 12:42:44 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204716 kb
Host smart-ba79e4e2-ed64-4fd5-940c-d5516174c811
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=498355468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.498355468
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1271767837
Short name T1560
Test name
Test status
Simulation time 23380130073 ps
CPU time 24.28 seconds
Started Jun 11 12:42:36 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204964 kb
Host smart-c7524802-67b0-4909-bae4-af386edb7296
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1271767837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1271767837
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.4011171106
Short name T1348
Test name
Test status
Simulation time 196783162 ps
CPU time 0.83 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204732 kb
Host smart-0e87340c-64d6-4a4f-87e3-0b9ea2910e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40111
71106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.4011171106
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.2700343368
Short name T1270
Test name
Test status
Simulation time 145438754 ps
CPU time 0.76 seconds
Started Jun 11 12:42:29 PM PDT 24
Finished Jun 11 12:42:31 PM PDT 24
Peak memory 204980 kb
Host smart-2d3a0a7f-163e-4b0f-946a-20c6d65e5936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
43368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.2700343368
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1125131622
Short name T964
Test name
Test status
Simulation time 616614760 ps
CPU time 1.63 seconds
Started Jun 11 12:42:26 PM PDT 24
Finished Jun 11 12:42:29 PM PDT 24
Peak memory 204740 kb
Host smart-42ffbd4b-832e-41c6-b54d-789f7d912e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11251
31622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1125131622
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2984945328
Short name T1359
Test name
Test status
Simulation time 189231994 ps
CPU time 0.85 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204624 kb
Host smart-1c005660-4a0e-404b-b7a1-c7f19a1cd4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29849
45328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2984945328
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.903916607
Short name T330
Test name
Test status
Simulation time 33537456 ps
CPU time 0.63 seconds
Started Jun 11 12:42:45 PM PDT 24
Finished Jun 11 12:42:48 PM PDT 24
Peak memory 204644 kb
Host smart-7db5e065-f6b5-42d3-8899-62cd263a1510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90391
6607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.903916607
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2063945446
Short name T1648
Test name
Test status
Simulation time 798255987 ps
CPU time 2 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204924 kb
Host smart-9b26c4de-4c7a-4a12-a846-ac08d748b0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20639
45446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2063945446
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1241487237
Short name T1678
Test name
Test status
Simulation time 183419473 ps
CPU time 1.19 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204952 kb
Host smart-85a2a376-a0b8-4e7e-be30-be043580c955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12414
87237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1241487237
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.101328722
Short name T343
Test name
Test status
Simulation time 229524098 ps
CPU time 0.87 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204704 kb
Host smart-445c2b44-92fb-426c-bf3d-bf114804958b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10132
8722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.101328722
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3652479420
Short name T648
Test name
Test status
Simulation time 199855480 ps
CPU time 0.78 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:42:43 PM PDT 24
Peak memory 204632 kb
Host smart-d115b41a-be3f-49e9-8fe2-d5a0753d937f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36524
79420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3652479420
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3291447980
Short name T1817
Test name
Test status
Simulation time 177828209 ps
CPU time 0.8 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:40 PM PDT 24
Peak memory 204640 kb
Host smart-08ec8180-a809-4bd9-94a4-39d3c1f4dca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914
47980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3291447980
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.412691394
Short name T570
Test name
Test status
Simulation time 245130236 ps
CPU time 0.97 seconds
Started Jun 11 12:42:40 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204688 kb
Host smart-bcd00e6e-751a-4ffd-83f4-a25377279d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
1394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.412691394
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.342932543
Short name T580
Test name
Test status
Simulation time 3410673745 ps
CPU time 4.1 seconds
Started Jun 11 12:42:46 PM PDT 24
Finished Jun 11 12:42:53 PM PDT 24
Peak memory 204708 kb
Host smart-69bf989a-5e97-4700-b41d-9215c8ae4e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34293
2543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.342932543
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1383883231
Short name T637
Test name
Test status
Simulation time 295238510 ps
CPU time 0.93 seconds
Started Jun 11 12:42:44 PM PDT 24
Finished Jun 11 12:42:47 PM PDT 24
Peak memory 204744 kb
Host smart-36e8ef49-2d1e-47db-ac07-6d97035c71c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1383883231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1383883231
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.863732558
Short name T1161
Test name
Test status
Simulation time 226443112 ps
CPU time 0.87 seconds
Started Jun 11 12:42:28 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 204784 kb
Host smart-ad91e501-2ac0-476c-8e64-db9b51763abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86373
2558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.863732558
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3151756905
Short name T785
Test name
Test status
Simulation time 8520917324 ps
CPU time 59.85 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 204996 kb
Host smart-e7cd19ec-a5c7-4174-8f2e-df7568f90535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31517
56905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3151756905
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1995817454
Short name T1547
Test name
Test status
Simulation time 156277427 ps
CPU time 0.78 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204624 kb
Host smart-cef49c2f-a92e-4a70-ac7d-23e3af3dc1ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1995817454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1995817454
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.65350933
Short name T1608
Test name
Test status
Simulation time 151806486 ps
CPU time 0.77 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204732 kb
Host smart-e1057cb5-8ae6-4876-81c9-0458dae9bc2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65350
933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.65350933
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.694622614
Short name T724
Test name
Test status
Simulation time 185542039 ps
CPU time 0.83 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204636 kb
Host smart-3244fe45-cdf1-4817-86dd-3dfc3a916b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69462
2614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.694622614
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.812621525
Short name T420
Test name
Test status
Simulation time 181617575 ps
CPU time 0.82 seconds
Started Jun 11 12:42:32 PM PDT 24
Finished Jun 11 12:42:34 PM PDT 24
Peak memory 204664 kb
Host smart-ddf37f91-f4c2-41f0-aa47-d5313936b5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81262
1525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.812621525
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2903446027
Short name T1314
Test name
Test status
Simulation time 157031944 ps
CPU time 0.78 seconds
Started Jun 11 12:42:34 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204724 kb
Host smart-3cfb8c21-7325-4a35-a562-d2e35992b68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
46027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2903446027
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.3497709919
Short name T461
Test name
Test status
Simulation time 151536283 ps
CPU time 0.81 seconds
Started Jun 11 12:42:39 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204748 kb
Host smart-970c8a97-d4d9-4e0c-8cba-f435b4e3949a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34977
09919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.3497709919
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_eop_single_bit_handling.552773693
Short name T1651
Test name
Test status
Simulation time 171563104 ps
CPU time 0.78 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:45 PM PDT 24
Peak memory 204708 kb
Host smart-a2c8f856-2045-4a06-9f28-80a136c785ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55277
3693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_eop_single_bit_handling.552773693
Directory /workspace/26.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.179250393
Short name T1429
Test name
Test status
Simulation time 163943166 ps
CPU time 0.75 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:45 PM PDT 24
Peak memory 204736 kb
Host smart-ecdf718c-d7c1-4d68-98ff-3ed21ea52d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17925
0393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.179250393
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.171398856
Short name T1827
Test name
Test status
Simulation time 33865038 ps
CPU time 0.64 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204704 kb
Host smart-ae3025cd-7cae-43c4-a1c8-bdc98f527de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139
8856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.171398856
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4207275637
Short name T238
Test name
Test status
Simulation time 7405397532 ps
CPU time 16.97 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204992 kb
Host smart-ee49cb56-1904-4861-a327-57e20dcb7e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
75637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4207275637
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.277378754
Short name T1063
Test name
Test status
Simulation time 190800518 ps
CPU time 0.89 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:42:53 PM PDT 24
Peak memory 204744 kb
Host smart-a560a909-0d6c-4fa3-b704-21bfd0b13984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27737
8754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.277378754
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.259582806
Short name T344
Test name
Test status
Simulation time 151684526 ps
CPU time 0.77 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204704 kb
Host smart-309b7ccc-e5eb-423d-b769-7666cf0dced5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.259582806
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2382449732
Short name T1497
Test name
Test status
Simulation time 209599111 ps
CPU time 0.89 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204636 kb
Host smart-03ca9146-3bf3-452f-9524-c7e4b7168ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824
49732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2382449732
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4238227439
Short name T550
Test name
Test status
Simulation time 186820004 ps
CPU time 0.83 seconds
Started Jun 11 12:42:39 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204716 kb
Host smart-b24a170e-c7b0-41a0-8415-64602d0ea699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42382
27439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4238227439
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.4151557192
Short name T1362
Test name
Test status
Simulation time 148385701 ps
CPU time 0.76 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204740 kb
Host smart-0eaee0ce-0c85-46cc-99cf-edc49d1f9094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41515
57192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.4151557192
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.311105813
Short name T175
Test name
Test status
Simulation time 184785079 ps
CPU time 0.83 seconds
Started Jun 11 12:42:46 PM PDT 24
Finished Jun 11 12:42:50 PM PDT 24
Peak memory 204636 kb
Host smart-4c99346b-8a83-457e-a0af-dc30dad20b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31110
5813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.311105813
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3860008590
Short name T391
Test name
Test status
Simulation time 155348906 ps
CPU time 0.76 seconds
Started Jun 11 12:42:48 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204580 kb
Host smart-9edcaaec-a862-46a3-804a-d048975b0504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38600
08590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3860008590
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3888151758
Short name T1288
Test name
Test status
Simulation time 224786557 ps
CPU time 0.93 seconds
Started Jun 11 12:42:31 PM PDT 24
Finished Jun 11 12:42:34 PM PDT 24
Peak memory 204728 kb
Host smart-e44e3fbe-a3af-4fd5-ac52-bb10b7e435f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38881
51758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3888151758
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.4011460694
Short name T611
Test name
Test status
Simulation time 176006380 ps
CPU time 0.8 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204744 kb
Host smart-f9edb3d5-fbf2-4373-a8b5-095abb036e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40114
60694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.4011460694
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3811715818
Short name T930
Test name
Test status
Simulation time 158870185 ps
CPU time 0.8 seconds
Started Jun 11 12:42:39 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204728 kb
Host smart-3d6e5d25-af80-4158-9153-cb0a4d72e326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38117
15818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3811715818
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.297377141
Short name T1784
Test name
Test status
Simulation time 14407074448 ps
CPU time 402 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 204936 kb
Host smart-18180557-d857-4570-8a6b-99e7fe5d43af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29737
7141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.297377141
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.617911046
Short name T876
Test name
Test status
Simulation time 3670686198 ps
CPU time 4.86 seconds
Started Jun 11 12:42:52 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 205032 kb
Host smart-39a2a9f0-e38c-43b5-808d-5f2cdabfbe22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=617911046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.617911046
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1209038415
Short name T705
Test name
Test status
Simulation time 13444827724 ps
CPU time 12.6 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204712 kb
Host smart-f7201fc3-f519-463e-b9b3-2b2ecad5149c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1209038415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1209038415
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3913064158
Short name T1021
Test name
Test status
Simulation time 23309568945 ps
CPU time 23.87 seconds
Started Jun 11 12:42:39 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 205052 kb
Host smart-f87af2c1-a8f5-49a2-900c-cfb66c038aae
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3913064158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3913064158
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2616348307
Short name T1970
Test name
Test status
Simulation time 185174331 ps
CPU time 0.78 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:42:46 PM PDT 24
Peak memory 204740 kb
Host smart-b9859bda-3947-4d29-82f5-dc2329888b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26163
48307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2616348307
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1444160532
Short name T2024
Test name
Test status
Simulation time 190206321 ps
CPU time 0.88 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:57 PM PDT 24
Peak memory 204704 kb
Host smart-06348674-3c80-4707-bb1b-641abdd5c6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14441
60532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1444160532
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2846348381
Short name T1614
Test name
Test status
Simulation time 669716873 ps
CPU time 1.6 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204888 kb
Host smart-c27d3502-980d-4160-ab76-22971ac76835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28463
48381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2846348381
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1826351128
Short name T17
Test name
Test status
Simulation time 156105580 ps
CPU time 0.76 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204712 kb
Host smart-11454a33-2a10-4a70-b166-71511fc52e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
51128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1826351128
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3242154177
Short name T1972
Test name
Test status
Simulation time 50427029 ps
CPU time 0.66 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204720 kb
Host smart-d315b065-57c1-4b75-bf30-79a514080f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421
54177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3242154177
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3823303681
Short name T851
Test name
Test status
Simulation time 839440565 ps
CPU time 1.98 seconds
Started Jun 11 12:42:54 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204848 kb
Host smart-7d0003a1-c268-4f05-9301-47c0b7bfb961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38233
03681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3823303681
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1417246217
Short name T485
Test name
Test status
Simulation time 184360110 ps
CPU time 1.97 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204880 kb
Host smart-a7424aea-cda6-4a9b-ae8e-44afb3028103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14172
46217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1417246217
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2614847692
Short name T80
Test name
Test status
Simulation time 181326396 ps
CPU time 0.79 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204980 kb
Host smart-bd750ead-dc1a-4cb8-bc85-706f850934ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26148
47692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2614847692
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.762786110
Short name T660
Test name
Test status
Simulation time 192261914 ps
CPU time 0.82 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204744 kb
Host smart-883602ea-3f9a-4be8-9b4e-8a4c80ddb2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76278
6110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.762786110
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1529982098
Short name T308
Test name
Test status
Simulation time 184014599 ps
CPU time 0.84 seconds
Started Jun 11 12:42:33 PM PDT 24
Finished Jun 11 12:42:35 PM PDT 24
Peak memory 204652 kb
Host smart-3acfba31-6e86-423b-9338-00d3d18e1a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15299
82098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1529982098
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1768715910
Short name T1942
Test name
Test status
Simulation time 228751073 ps
CPU time 0.84 seconds
Started Jun 11 12:42:44 PM PDT 24
Finished Jun 11 12:42:47 PM PDT 24
Peak memory 204672 kb
Host smart-b7a7fe7d-fbd4-4495-9ee4-d68087917863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17687
15910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1768715910
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1414800598
Short name T1187
Test name
Test status
Simulation time 3328033651 ps
CPU time 4.38 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:14 PM PDT 24
Peak memory 204800 kb
Host smart-13acc276-9aff-4618-acbe-7654f1823ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14148
00598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1414800598
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.206867704
Short name T1519
Test name
Test status
Simulation time 252832116 ps
CPU time 0.87 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204660 kb
Host smart-0810018e-3dd7-4298-a9c4-377013e7c8a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=206867704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.206867704
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.4059332285
Short name T1976
Test name
Test status
Simulation time 222050235 ps
CPU time 0.84 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204772 kb
Host smart-6da02cb8-e61f-428d-974b-9dd103950bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40593
32285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.4059332285
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4100936301
Short name T1312
Test name
Test status
Simulation time 10257861928 ps
CPU time 281.27 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:47:34 PM PDT 24
Peak memory 205016 kb
Host smart-d13c065c-2dba-433f-be64-c1b42c1067eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41009
36301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4100936301
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2915351190
Short name T870
Test name
Test status
Simulation time 179145811 ps
CPU time 0.8 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204672 kb
Host smart-7ff70780-3ea1-4bff-b9e9-0777eebd7d0f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2915351190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2915351190
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.909135437
Short name T224
Test name
Test status
Simulation time 170068627 ps
CPU time 0.81 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204676 kb
Host smart-c8f1aed9-523f-4b32-a949-4dbd83a0240c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90913
5437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.909135437
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1510844129
Short name T159
Test name
Test status
Simulation time 220626865 ps
CPU time 0.94 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204672 kb
Host smart-f5b51258-b46e-41e9-a731-02e8a16c7387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15108
44129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1510844129
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3649104241
Short name T1848
Test name
Test status
Simulation time 145629600 ps
CPU time 0.74 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:50 PM PDT 24
Peak memory 204732 kb
Host smart-1dc0266f-150f-43cb-ac4f-ff459dca624d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36491
04241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3649104241
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1142840224
Short name T1720
Test name
Test status
Simulation time 189330423 ps
CPU time 0.81 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204648 kb
Host smart-47dbf3e1-164f-4c3e-998d-322ce714084e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11428
40224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1142840224
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.936276359
Short name T1757
Test name
Test status
Simulation time 186565186 ps
CPU time 0.86 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204736 kb
Host smart-cefbcfdd-9f0b-462b-ba70-76bf550f362d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93627
6359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.936276359
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1782354515
Short name T1422
Test name
Test status
Simulation time 160551033 ps
CPU time 0.78 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204672 kb
Host smart-32bc338b-0436-4206-b94d-fa3cb54d812f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17823
54515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1782354515
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_eop_single_bit_handling.1113449239
Short name T1083
Test name
Test status
Simulation time 178352350 ps
CPU time 0.85 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204768 kb
Host smart-d93a18d6-6734-48d2-bd7b-a86b42bbb02b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
49239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_eop_single_bit_handling.1113449239
Directory /workspace/27.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1190225871
Short name T1010
Test name
Test status
Simulation time 162933161 ps
CPU time 0.74 seconds
Started Jun 11 12:42:48 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204648 kb
Host smart-7198de93-7969-4188-8424-0f6c083d5cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11902
25871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1190225871
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3616496891
Short name T2072
Test name
Test status
Simulation time 82140405 ps
CPU time 0.72 seconds
Started Jun 11 12:42:35 PM PDT 24
Finished Jun 11 12:42:37 PM PDT 24
Peak memory 204624 kb
Host smart-279ce9fc-209d-42c9-a3a1-77ba45a6fa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36164
96891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3616496891
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1901961888
Short name T206
Test name
Test status
Simulation time 16512473681 ps
CPU time 40.3 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:43:30 PM PDT 24
Peak memory 204932 kb
Host smart-a2a63947-e365-4100-8f75-3c46fe0cb670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19019
61888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1901961888
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1996221675
Short name T1261
Test name
Test status
Simulation time 166248066 ps
CPU time 0.83 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204692 kb
Host smart-127fb6cf-5a9d-4ccb-a102-42c6906ec153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19962
21675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1996221675
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.835021276
Short name T720
Test name
Test status
Simulation time 212190899 ps
CPU time 0.86 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204716 kb
Host smart-70716e90-ab22-431d-879f-09e50fea879c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83502
1276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.835021276
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.3694166739
Short name T416
Test name
Test status
Simulation time 264500329 ps
CPU time 0.89 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:42:47 PM PDT 24
Peak memory 204640 kb
Host smart-ed8e8bfb-d40f-4351-912a-529d9d51b89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
66739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.3694166739
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.502801901
Short name T651
Test name
Test status
Simulation time 164576235 ps
CPU time 0.79 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204644 kb
Host smart-66615755-3ae4-44bf-b63e-5c7d275f4243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50280
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.502801901
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3130689642
Short name T1909
Test name
Test status
Simulation time 157746661 ps
CPU time 0.78 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204620 kb
Host smart-09c288b7-e03d-4942-829b-bcf5b90a4e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31306
89642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3130689642
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3627948995
Short name T1498
Test name
Test status
Simulation time 150143385 ps
CPU time 0.74 seconds
Started Jun 11 12:42:42 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204648 kb
Host smart-20f3e7bf-51a8-4233-84d7-ae984d98fec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
48995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3627948995
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.418695081
Short name T1428
Test name
Test status
Simulation time 158188086 ps
CPU time 0.78 seconds
Started Jun 11 12:42:41 PM PDT 24
Finished Jun 11 12:42:44 PM PDT 24
Peak memory 204696 kb
Host smart-3840c866-ebea-4ab9-9699-a98916e938c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
5081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.418695081
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.172062144
Short name T1064
Test name
Test status
Simulation time 193412275 ps
CPU time 0.91 seconds
Started Jun 11 12:42:45 PM PDT 24
Finished Jun 11 12:42:48 PM PDT 24
Peak memory 204740 kb
Host smart-4f1752a0-56be-4c29-ba75-708d9139a4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
2144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.172062144
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.32335708
Short name T1524
Test name
Test status
Simulation time 202876973 ps
CPU time 0.82 seconds
Started Jun 11 12:42:48 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204988 kb
Host smart-01dba676-7295-4a99-97f9-9162e3cac52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32335
708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.32335708
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1117118295
Short name T713
Test name
Test status
Simulation time 166333483 ps
CPU time 0.76 seconds
Started Jun 11 12:42:38 PM PDT 24
Finished Jun 11 12:42:41 PM PDT 24
Peak memory 204708 kb
Host smart-83ba7835-358a-4f8d-9074-03868555d500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11171
18295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1117118295
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1243775397
Short name T1583
Test name
Test status
Simulation time 4539825707 ps
CPU time 30.54 seconds
Started Jun 11 12:42:43 PM PDT 24
Finished Jun 11 12:43:15 PM PDT 24
Peak memory 204936 kb
Host smart-fb0c1080-3a97-4fb3-9a35-9abc3baa0f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
75397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1243775397
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.653137465
Short name T1244
Test name
Test status
Simulation time 3768944523 ps
CPU time 4.68 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204988 kb
Host smart-26a1786c-c91a-44f6-ad33-a1325d44938e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=653137465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.653137465
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1692111619
Short name T1677
Test name
Test status
Simulation time 13364829399 ps
CPU time 12.8 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 205048 kb
Host smart-adca797b-49e6-40e3-a22e-4f0ee50e0eb0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1692111619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1692111619
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3983785061
Short name T1158
Test name
Test status
Simulation time 23353019080 ps
CPU time 26.88 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204720 kb
Host smart-22d94716-f4aa-459a-b8e7-f5e53cefc4ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3983785061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3983785061
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.2803304144
Short name T22
Test name
Test status
Simulation time 173729841 ps
CPU time 0.8 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204632 kb
Host smart-e7ec2506-b977-43b4-a935-1a8776f2eb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
04144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2803304144
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2483145548
Short name T1897
Test name
Test status
Simulation time 162998898 ps
CPU time 0.79 seconds
Started Jun 11 12:42:54 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204736 kb
Host smart-29bcc96b-d58d-48c0-890c-51bfdbcc3bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24831
45548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2483145548
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1661033585
Short name T2039
Test name
Test status
Simulation time 1574538915 ps
CPU time 3.27 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:08 PM PDT 24
Peak memory 204816 kb
Host smart-6e7e2697-eb0c-40c9-a343-1a1863353ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610
33585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1661033585
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.4066438655
Short name T1143
Test name
Test status
Simulation time 133378900 ps
CPU time 0.79 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204744 kb
Host smart-28fb0c53-fd13-40a8-920a-fed4f2b00a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
38655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.4066438655
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3596578983
Short name T489
Test name
Test status
Simulation time 109041447 ps
CPU time 0.68 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204748 kb
Host smart-9a71c273-d323-4a93-b427-8685b228f0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
78983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3596578983
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1929055384
Short name T58
Test name
Test status
Simulation time 963654424 ps
CPU time 2.2 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204856 kb
Host smart-2b8b6c1f-ac18-4d38-8342-47dcd7a4c17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19290
55384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1929055384
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2747065673
Short name T795
Test name
Test status
Simulation time 181274506 ps
CPU time 1.66 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204856 kb
Host smart-94b6bc63-4e61-48db-89e5-a92bfe004b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27470
65673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2747065673
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3854451074
Short name T1611
Test name
Test status
Simulation time 227896725 ps
CPU time 0.87 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204720 kb
Host smart-ec5822c1-d6df-4de8-ae5d-b49b49a8e387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
51074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3854451074
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3101908469
Short name T314
Test name
Test status
Simulation time 146890164 ps
CPU time 0.75 seconds
Started Jun 11 12:42:48 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204720 kb
Host smart-d98bdf65-2eb6-4c3e-8451-74b557e5e380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31019
08469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3101908469
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3088953026
Short name T38
Test name
Test status
Simulation time 213324606 ps
CPU time 0.89 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204700 kb
Host smart-b831c028-2df5-4708-9ecc-ca814ed008c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30889
53026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3088953026
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.4006048977
Short name T655
Test name
Test status
Simulation time 203623185 ps
CPU time 0.85 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204660 kb
Host smart-b8ea1dfe-0d33-495c-b32f-0c4628ad0e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40060
48977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4006048977
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.165183163
Short name T1034
Test name
Test status
Simulation time 3340998137 ps
CPU time 4.18 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:43:03 PM PDT 24
Peak memory 204816 kb
Host smart-e59991b7-8520-44ff-817a-a600ca842e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
3163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.165183163
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.2129500258
Short name T1241
Test name
Test status
Simulation time 237568221 ps
CPU time 0.92 seconds
Started Jun 11 12:43:05 PM PDT 24
Finished Jun 11 12:43:09 PM PDT 24
Peak memory 204704 kb
Host smart-40716a56-dbe6-473a-b6a8-ecf4363b59d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2129500258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.2129500258
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2106292045
Short name T339
Test name
Test status
Simulation time 196433942 ps
CPU time 0.93 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204756 kb
Host smart-5b689087-0ed2-48da-9d6a-d9408b65a70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21062
92045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2106292045
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2649206539
Short name T1484
Test name
Test status
Simulation time 4995725942 ps
CPU time 46.43 seconds
Started Jun 11 12:42:52 PM PDT 24
Finished Jun 11 12:43:42 PM PDT 24
Peak memory 205004 kb
Host smart-33f11dc8-05e7-49ad-86f7-8b16f67022e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26492
06539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2649206539
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.4108432991
Short name T424
Test name
Test status
Simulation time 164819319 ps
CPU time 0.79 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204744 kb
Host smart-af3852e3-656a-4982-968c-946fbc397c5f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4108432991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.4108432991
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.277385336
Short name T841
Test name
Test status
Simulation time 140786107 ps
CPU time 0.8 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204724 kb
Host smart-ff5a52e5-b922-45e7-b595-762d9e6482b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27738
5336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.277385336
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1082606492
Short name T1974
Test name
Test status
Simulation time 205382101 ps
CPU time 0.86 seconds
Started Jun 11 12:42:47 PM PDT 24
Finished Jun 11 12:42:51 PM PDT 24
Peak memory 204640 kb
Host smart-6f0680fd-a54c-4c8b-8bdf-051d36bd3d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10826
06492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1082606492
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3113254660
Short name T464
Test name
Test status
Simulation time 155564473 ps
CPU time 0.8 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204740 kb
Host smart-dbaaf73f-9e8a-438a-9a9a-2ae1d93f5274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
54660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3113254660
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1466929941
Short name T313
Test name
Test status
Simulation time 183316647 ps
CPU time 0.81 seconds
Started Jun 11 12:42:52 PM PDT 24
Finished Jun 11 12:42:57 PM PDT 24
Peak memory 204740 kb
Host smart-180526ea-843b-47c1-9945-6499ad177e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669
29941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1466929941
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2025149014
Short name T414
Test name
Test status
Simulation time 193958223 ps
CPU time 0.8 seconds
Started Jun 11 12:43:09 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204656 kb
Host smart-dfa34056-b8e6-4569-adad-b834509f04b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20251
49014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2025149014
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2663142901
Short name T1016
Test name
Test status
Simulation time 176832071 ps
CPU time 0.77 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204740 kb
Host smart-76c8e4cc-af49-4b0e-a65b-cde285710667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26631
42901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2663142901
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_eop_single_bit_handling.1914400250
Short name T1304
Test name
Test status
Simulation time 154552899 ps
CPU time 0.79 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204724 kb
Host smart-c589aca2-c66e-4a7b-9ca6-10a86a73fca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144
00250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_eop_single_bit_handling.1914400250
Directory /workspace/28.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3396060792
Short name T2019
Test name
Test status
Simulation time 163081412 ps
CPU time 0.77 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204724 kb
Host smart-9f58ecfb-3606-4311-9bdf-f32640aea1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33960
60792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3396060792
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2811685322
Short name T1917
Test name
Test status
Simulation time 46384241 ps
CPU time 0.67 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:55 PM PDT 24
Peak memory 204716 kb
Host smart-dcb35831-fde6-41f5-aa23-153082b13312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28116
85322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2811685322
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4159926029
Short name T1248
Test name
Test status
Simulation time 198027256 ps
CPU time 0.86 seconds
Started Jun 11 12:42:54 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204736 kb
Host smart-ac6e4770-821e-4820-b036-462c9ce37aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41599
26029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4159926029
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1305956819
Short name T334
Test name
Test status
Simulation time 203490817 ps
CPU time 0.85 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204984 kb
Host smart-1ddc1db5-b99d-4598-aaa3-9024066d30f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059
56819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1305956819
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1491460084
Short name T1980
Test name
Test status
Simulation time 221292499 ps
CPU time 1.01 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204736 kb
Host smart-21b223d9-5fb6-47bf-b04c-d11b53e73580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
60084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1491460084
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3873067685
Short name T1727
Test name
Test status
Simulation time 157642439 ps
CPU time 0.8 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204716 kb
Host smart-029b594b-b91f-48ef-9b74-a8fd45bd70ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38730
67685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3873067685
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2429117773
Short name T1169
Test name
Test status
Simulation time 140471125 ps
CPU time 0.73 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204764 kb
Host smart-e327d127-7ec2-4d7b-be07-9f8bec2d2551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24291
17773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2429117773
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.2665108092
Short name T1745
Test name
Test status
Simulation time 196545630 ps
CPU time 0.78 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:42:53 PM PDT 24
Peak memory 204744 kb
Host smart-695bcf85-83d2-439e-80e0-87756973cdcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26651
08092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2665108092
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3029988171
Short name T1120
Test name
Test status
Simulation time 157534207 ps
CPU time 0.81 seconds
Started Jun 11 12:42:52 PM PDT 24
Finished Jun 11 12:42:57 PM PDT 24
Peak memory 204732 kb
Host smart-bb17bf87-9ba4-47fb-9dae-6b5480b82acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30299
88171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3029988171
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.3875799989
Short name T178
Test name
Test status
Simulation time 218562349 ps
CPU time 0.91 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204572 kb
Host smart-fab79440-0804-453f-bf50-93c9e935b143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38757
99989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3875799989
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2725868432
Short name T367
Test name
Test status
Simulation time 193398275 ps
CPU time 0.82 seconds
Started Jun 11 12:42:54 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204608 kb
Host smart-2d46289d-c6dc-47c9-8e24-ffe5f64e9ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27258
68432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2725868432
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1889601420
Short name T1534
Test name
Test status
Simulation time 157986666 ps
CPU time 0.82 seconds
Started Jun 11 12:42:48 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204740 kb
Host smart-3731974c-0fa4-4dc8-8b9b-924fca4631a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18896
01420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1889601420
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3978290385
Short name T369
Test name
Test status
Simulation time 5442754861 ps
CPU time 49.89 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 205020 kb
Host smart-43854e7c-0deb-4ce2-86c6-1ddd2a2a9c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782
90385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3978290385
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1029527640
Short name T105
Test name
Test status
Simulation time 3610536160 ps
CPU time 4.23 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204772 kb
Host smart-26049225-8066-4502-aee4-0b68295a97e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1029527640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1029527640
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1466334305
Short name T1580
Test name
Test status
Simulation time 23326861032 ps
CPU time 24.49 seconds
Started Jun 11 12:43:04 PM PDT 24
Finished Jun 11 12:43:32 PM PDT 24
Peak memory 204704 kb
Host smart-52fe5301-5f8a-4ace-945d-43820c64a73d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1466334305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.1466334305
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1063861051
Short name T2056
Test name
Test status
Simulation time 147005727 ps
CPU time 0.76 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204768 kb
Host smart-b991d145-2b8f-48fc-8439-87aa54b32931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10638
61051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1063861051
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.436379388
Short name T1489
Test name
Test status
Simulation time 196546342 ps
CPU time 0.8 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:03 PM PDT 24
Peak memory 204720 kb
Host smart-286a1f9a-9f4c-4630-af40-e168db565e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43637
9388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.436379388
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1583933844
Short name T833
Test name
Test status
Simulation time 773257120 ps
CPU time 1.94 seconds
Started Jun 11 12:42:58 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204964 kb
Host smart-ee74ca69-56cb-4fd8-a140-9cbd268adba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15839
33844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1583933844
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1208244155
Short name T773
Test name
Test status
Simulation time 168338498 ps
CPU time 0.82 seconds
Started Jun 11 12:42:51 PM PDT 24
Finished Jun 11 12:42:56 PM PDT 24
Peak memory 204708 kb
Host smart-f1a3c1d2-93ad-4f2a-a227-8dcb43f27b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12082
44155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1208244155
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1587936873
Short name T927
Test name
Test status
Simulation time 64293089 ps
CPU time 0.67 seconds
Started Jun 11 12:42:52 PM PDT 24
Finished Jun 11 12:42:57 PM PDT 24
Peak memory 204716 kb
Host smart-30e4a5c5-d52b-40cd-95e6-8e8acf55edb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
36873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1587936873
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3600881021
Short name T1797
Test name
Test status
Simulation time 897296384 ps
CPU time 2.13 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:59 PM PDT 24
Peak memory 204964 kb
Host smart-b8b9a2fb-9aa4-46da-8423-63d7a6037c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
81021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3600881021
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2264950988
Short name T563
Test name
Test status
Simulation time 206692663 ps
CPU time 1.45 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 205200 kb
Host smart-64fe6416-1bdf-438b-b469-ff217afc0a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22649
50988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2264950988
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.142763356
Short name T552
Test name
Test status
Simulation time 254074031 ps
CPU time 1.01 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204744 kb
Host smart-7f10cda7-c8f2-4b3f-aa9e-237e5d93dabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14276
3356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.142763356
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.102042909
Short name T1562
Test name
Test status
Simulation time 189308517 ps
CPU time 0.81 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204696 kb
Host smart-d4e3a766-3e84-4b0b-abbe-d54fe1e21be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
2909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.102042909
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.973009146
Short name T396
Test name
Test status
Simulation time 184096940 ps
CPU time 0.81 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 205008 kb
Host smart-f143a244-308c-4aab-bf15-2bb1760e52bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97300
9146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.973009146
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2341166624
Short name T1673
Test name
Test status
Simulation time 273002187 ps
CPU time 0.9 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204692 kb
Host smart-d371155c-426a-4167-8f99-dde25142533e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
66624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2341166624
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.3873257880
Short name T415
Test name
Test status
Simulation time 3366988474 ps
CPU time 3.94 seconds
Started Jun 11 12:42:40 PM PDT 24
Finished Jun 11 12:42:45 PM PDT 24
Peak memory 204792 kb
Host smart-a371d3fe-361f-4171-9a02-1df61ac42df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732
57880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.3873257880
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3095120375
Short name T1582
Test name
Test status
Simulation time 243273963 ps
CPU time 0.93 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204680 kb
Host smart-62182d5a-c0e4-41ac-9eae-83b90c3e1501
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3095120375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3095120375
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3566874441
Short name T1285
Test name
Test status
Simulation time 203397790 ps
CPU time 0.92 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204676 kb
Host smart-ed267dbd-d9f5-42cd-82de-90197caead67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35668
74441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3566874441
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3144911418
Short name T1496
Test name
Test status
Simulation time 11162944198 ps
CPU time 78.73 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:44:11 PM PDT 24
Peak memory 204876 kb
Host smart-eba5e872-7593-42ba-8c53-c79fbf790234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31449
11418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3144911418
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1282659898
Short name T463
Test name
Test status
Simulation time 148631687 ps
CPU time 0.79 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204660 kb
Host smart-7d2c4a18-fd6c-4439-a751-69f9d0d544ed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1282659898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1282659898
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2538826368
Short name T1918
Test name
Test status
Simulation time 179964839 ps
CPU time 0.87 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204708 kb
Host smart-8c6ceeee-cc66-4926-bd43-3419d5c32aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25388
26368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2538826368
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2593204661
Short name T884
Test name
Test status
Simulation time 185129588 ps
CPU time 0.83 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204636 kb
Host smart-eeebf589-a0a0-47a7-8f5d-c4e187b8491d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25932
04661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2593204661
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3992715734
Short name T1454
Test name
Test status
Simulation time 189895371 ps
CPU time 0.81 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204688 kb
Host smart-5a94ac8c-59fe-45f6-aa9c-6bc1bb401d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39927
15734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3992715734
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2756763199
Short name T1810
Test name
Test status
Simulation time 150065075 ps
CPU time 0.8 seconds
Started Jun 11 12:42:50 PM PDT 24
Finished Jun 11 12:42:54 PM PDT 24
Peak memory 204696 kb
Host smart-b378235e-5dbd-4840-8b30-769832308c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27567
63199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2756763199
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.979607389
Short name T176
Test name
Test status
Simulation time 187352074 ps
CPU time 0.82 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204660 kb
Host smart-2ca33900-c93f-4e42-ae7f-9c23ade3be71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97960
7389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.979607389
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_eop_single_bit_handling.2003148482
Short name T412
Test name
Test status
Simulation time 194060221 ps
CPU time 0.92 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204640 kb
Host smart-b6491ee0-1f59-4767-8045-67765972065b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
48482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_eop_single_bit_handling.2003148482
Directory /workspace/29.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.434179669
Short name T879
Test name
Test status
Simulation time 147449563 ps
CPU time 0.8 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204712 kb
Host smart-e134375b-04ec-40d2-b428-08b8201dcfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43417
9669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.434179669
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.4002535566
Short name T1486
Test name
Test status
Simulation time 46831114 ps
CPU time 0.63 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204724 kb
Host smart-b25dc013-846c-4a18-974d-ecacd36de4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
35566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.4002535566
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.3985907544
Short name T244
Test name
Test status
Simulation time 14496663240 ps
CPU time 31 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:43:24 PM PDT 24
Peak memory 204948 kb
Host smart-5af5b3d8-3e84-415d-a9ae-0b5af3a16bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39859
07544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.3985907544
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.617081755
Short name T918
Test name
Test status
Simulation time 163709164 ps
CPU time 0.78 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204640 kb
Host smart-e7772c03-1762-4e3f-98a1-c77de44310bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61708
1755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.617081755
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2888370723
Short name T782
Test name
Test status
Simulation time 212926516 ps
CPU time 0.85 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204668 kb
Host smart-1ce46301-839b-4739-98af-140b20cb1cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28883
70723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2888370723
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1899151541
Short name T403
Test name
Test status
Simulation time 202996025 ps
CPU time 0.84 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204708 kb
Host smart-6a34e33f-8fa3-4564-bddc-e28f53499394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
51541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1899151541
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.770467043
Short name T776
Test name
Test status
Simulation time 180007592 ps
CPU time 0.8 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204672 kb
Host smart-7843581d-2fc6-4d7b-869a-e15cff56879b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77046
7043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.770467043
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.718154139
Short name T475
Test name
Test status
Simulation time 157101751 ps
CPU time 0.75 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204692 kb
Host smart-01afb926-46e1-44a6-88e8-65a795d673b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71815
4139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.718154139
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2447025618
Short name T838
Test name
Test status
Simulation time 196255523 ps
CPU time 0.81 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204724 kb
Host smart-060e4c9d-b82c-4d6c-a8d1-00bcbbb8f83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24470
25618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2447025618
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2119541526
Short name T1924
Test name
Test status
Simulation time 150578575 ps
CPU time 0.76 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:08 PM PDT 24
Peak memory 204648 kb
Host smart-cea43609-e6d0-462a-b10a-10293c92363b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21195
41526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2119541526
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3938259848
Short name T191
Test name
Test status
Simulation time 225206001 ps
CPU time 0.94 seconds
Started Jun 11 12:42:46 PM PDT 24
Finished Jun 11 12:42:50 PM PDT 24
Peak memory 204776 kb
Host smart-0c24f872-0aa8-4cba-bf72-55716528387d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
59848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3938259848
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1613431476
Short name T1637
Test name
Test status
Simulation time 183486426 ps
CPU time 0.82 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204728 kb
Host smart-6c895239-8cc0-4ec3-9848-5c7b3e23760f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16134
31476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1613431476
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.4187539542
Short name T1779
Test name
Test status
Simulation time 150477113 ps
CPU time 0.81 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 204680 kb
Host smart-61892fb0-d374-4b62-9af8-9cf1e31f02b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875
39542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.4187539542
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2520446264
Short name T1559
Test name
Test status
Simulation time 12501552282 ps
CPU time 87.87 seconds
Started Jun 11 12:42:49 PM PDT 24
Finished Jun 11 12:44:21 PM PDT 24
Peak memory 204936 kb
Host smart-bcd5a67f-7a98-44ad-9d13-3f2c1bd5afdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25204
46264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2520446264
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3913820488
Short name T12
Test name
Test status
Simulation time 4041536659 ps
CPU time 5.31 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 204496 kb
Host smart-9c970d72-fc25-4124-a5d1-9ccc7172eba7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3913820488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3913820488
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1354900973
Short name T516
Test name
Test status
Simulation time 13351926753 ps
CPU time 14.1 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:39 PM PDT 24
Peak memory 204832 kb
Host smart-0543937c-554f-4caa-b628-1136216bfee2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1354900973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1354900973
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3154955990
Short name T2027
Test name
Test status
Simulation time 23386233991 ps
CPU time 29.47 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 204792 kb
Host smart-c269b054-5538-461d-845d-73c03cf1ea1c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3154955990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3154955990
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.928324477
Short name T1594
Test name
Test status
Simulation time 164163614 ps
CPU time 0.8 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:40:16 PM PDT 24
Peak memory 204696 kb
Host smart-93f7ab8d-fcac-4e8e-aff0-13632415ed9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92832
4477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.928324477
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3904610210
Short name T1191
Test name
Test status
Simulation time 152200298 ps
CPU time 0.78 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:40:16 PM PDT 24
Peak memory 204644 kb
Host smart-b1ad9e8f-999d-4815-af18-9436e52af520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
10210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3904610210
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3979113641
Short name T1393
Test name
Test status
Simulation time 1327106551 ps
CPU time 2.8 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204956 kb
Host smart-05ec885d-982a-471a-89f7-5e2afb55779f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
13641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3979113641
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1936378845
Short name T1251
Test name
Test status
Simulation time 170872878 ps
CPU time 0.73 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:40:16 PM PDT 24
Peak memory 204752 kb
Host smart-e799660c-f2c2-459d-86a4-8f4f4a2d5f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
78845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1936378845
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1136489086
Short name T1388
Test name
Test status
Simulation time 41082564 ps
CPU time 0.65 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204752 kb
Host smart-6564b059-54cc-40b1-81ea-e71c369c71d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11364
89086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1136489086
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.1133539806
Short name T565
Test name
Test status
Simulation time 934167681 ps
CPU time 2.32 seconds
Started Jun 11 12:40:13 PM PDT 24
Finished Jun 11 12:40:17 PM PDT 24
Peak memory 204900 kb
Host smart-28a73a10-3368-4937-9123-0b4ac148dcd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
39806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.1133539806
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3472739140
Short name T96
Test name
Test status
Simulation time 173852646 ps
CPU time 1.27 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204928 kb
Host smart-a8bf174c-ac86-463c-8767-e03a924c644f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34727
39140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3472739140
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.435846412
Short name T557
Test name
Test status
Simulation time 207387698 ps
CPU time 0.84 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:40:16 PM PDT 24
Peak memory 204640 kb
Host smart-061efc1b-2342-4cd5-a7f8-0dfbd648a512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43584
6412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.435846412
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3413800208
Short name T525
Test name
Test status
Simulation time 190439717 ps
CPU time 0.85 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204588 kb
Host smart-eab9d323-b4a3-414c-9141-c571aed03ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34138
00208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3413800208
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3020315717
Short name T544
Test name
Test status
Simulation time 185513501 ps
CPU time 0.88 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 204980 kb
Host smart-33c78b2c-c0c1-4ac5-8826-ff323a162c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30203
15717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3020315717
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1361252447
Short name T1287
Test name
Test status
Simulation time 201921762 ps
CPU time 0.88 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:18 PM PDT 24
Peak memory 204720 kb
Host smart-d8e5c7d7-7199-419f-a085-1adb780d9dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13612
52447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1361252447
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.4058342301
Short name T1754
Test name
Test status
Simulation time 3329101031 ps
CPU time 3.83 seconds
Started Jun 11 12:40:19 PM PDT 24
Finished Jun 11 12:40:26 PM PDT 24
Peak memory 204840 kb
Host smart-09d2ec20-f263-4a8a-815f-4185c71e7a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40583
42301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.4058342301
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2593952491
Short name T830
Test name
Test status
Simulation time 240946032 ps
CPU time 0.87 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 204668 kb
Host smart-22de9450-9ee9-4ad4-b810-e3490feb03d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2593952491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2593952491
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1231582141
Short name T696
Test name
Test status
Simulation time 193810862 ps
CPU time 0.9 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 205028 kb
Host smart-f3f4fe08-8ca6-4653-85ea-d68134baa019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
82141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1231582141
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.171207097
Short name T301
Test name
Test status
Simulation time 15318306389 ps
CPU time 102.24 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:42:07 PM PDT 24
Peak memory 205004 kb
Host smart-56619a5a-0193-416c-a24d-fa9900ff8bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17120
7097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.171207097
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3753087959
Short name T1318
Test name
Test status
Simulation time 149689683 ps
CPU time 0.79 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204724 kb
Host smart-1a5f2402-e80c-4400-9771-a9d83ff31cb8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3753087959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3753087959
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2228277124
Short name T685
Test name
Test status
Simulation time 169226807 ps
CPU time 0.84 seconds
Started Jun 11 12:40:13 PM PDT 24
Finished Jun 11 12:40:16 PM PDT 24
Peak memory 204644 kb
Host smart-94cf6d50-59d7-4825-a047-25a84f775a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
77124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2228277124
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2889640376
Short name T169
Test name
Test status
Simulation time 234817892 ps
CPU time 0.86 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:17 PM PDT 24
Peak memory 204780 kb
Host smart-5a4187c5-f9f5-4950-9c18-205ad864ebf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28896
40376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2889640376
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2496259020
Short name T700
Test name
Test status
Simulation time 223386225 ps
CPU time 0.89 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:40:17 PM PDT 24
Peak memory 204668 kb
Host smart-8d668bd6-d9de-4827-9f0c-4229364b867f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
59020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2496259020
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.964598229
Short name T1209
Test name
Test status
Simulation time 160340141 ps
CPU time 0.81 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204716 kb
Host smart-6b11e54e-852d-4fd7-9783-21f29a215ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96459
8229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.964598229
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1666490516
Short name T536
Test name
Test status
Simulation time 186172125 ps
CPU time 0.8 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:18 PM PDT 24
Peak memory 204716 kb
Host smart-daa27f79-0460-4941-b6d6-f6357609ae8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
90516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1666490516
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2631354931
Short name T1282
Test name
Test status
Simulation time 160750589 ps
CPU time 0.86 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:22 PM PDT 24
Peak memory 204720 kb
Host smart-76e3d540-7d5e-4b69-8313-97abc8a9b4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26313
54931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2631354931
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_eop_single_bit_handling.2992935150
Short name T1675
Test name
Test status
Simulation time 171537311 ps
CPU time 0.83 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204728 kb
Host smart-dcf97945-eed1-43f0-9d11-ec8ed5ef6440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929
35150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_eop_single_bit_handling.2992935150
Directory /workspace/3.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2135936045
Short name T1763
Test name
Test status
Simulation time 166031430 ps
CPU time 0.8 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204684 kb
Host smart-7fcdbbdb-0f3e-466d-880f-55ec7bed26da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21359
36045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2135936045
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1977122079
Short name T1782
Test name
Test status
Simulation time 37742745 ps
CPU time 0.68 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 205004 kb
Host smart-ea20071b-83b8-4de6-ad43-847aaff36cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771
22079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1977122079
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2860907067
Short name T100
Test name
Test status
Simulation time 18484518943 ps
CPU time 46.94 seconds
Started Jun 11 12:40:14 PM PDT 24
Finished Jun 11 12:41:03 PM PDT 24
Peak memory 204992 kb
Host smart-38c6bed3-211a-4229-9c9b-438e717dd113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28609
07067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2860907067
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3442540117
Short name T1399
Test name
Test status
Simulation time 198231031 ps
CPU time 0.84 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204756 kb
Host smart-5d83fcda-1e7a-4c0b-8571-d05ec1eb2ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34425
40117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3442540117
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3014833037
Short name T298
Test name
Test status
Simulation time 196667240 ps
CPU time 0.86 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204364 kb
Host smart-a42f7393-4dab-48c1-a119-1a95f187f8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30148
33037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3014833037
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3987886270
Short name T320
Test name
Test status
Simulation time 9845405469 ps
CPU time 68.79 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 204976 kb
Host smart-df29ffb6-ad3a-4d7b-b477-ea0d903863cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3987886270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3987886270
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2414747062
Short name T1129
Test name
Test status
Simulation time 30313723537 ps
CPU time 736.52 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:52:40 PM PDT 24
Peak memory 205064 kb
Host smart-692032ff-e21c-4743-b3e2-c3a789c7b6b3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2414747062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2414747062
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.1966400486
Short name T1658
Test name
Test status
Simulation time 33674878714 ps
CPU time 282.66 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 205064 kb
Host smart-9c8e62aa-d571-4b28-8acf-2f3c69c2e032
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1966400486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1966400486
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1392875294
Short name T1938
Test name
Test status
Simulation time 233228949 ps
CPU time 0.92 seconds
Started Jun 11 12:40:19 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204688 kb
Host smart-dcc173b1-aae6-4146-b5c6-129c6e1ac9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13928
75294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1392875294
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3517878165
Short name T576
Test name
Test status
Simulation time 227912783 ps
CPU time 0.87 seconds
Started Jun 11 12:40:20 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204652 kb
Host smart-96cca7bb-a274-4c58-b3a2-23679dd9213d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35178
78165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3517878165
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2539116851
Short name T1029
Test name
Test status
Simulation time 143322419 ps
CPU time 0.8 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 204988 kb
Host smart-7d44cb0b-b1d0-45d8-9756-b28ec1c90c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25391
16851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2539116851
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.862825481
Short name T123
Test name
Test status
Simulation time 225256605 ps
CPU time 1.08 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 221404 kb
Host smart-c339424f-2c2e-4aae-b17c-09d75bcfec63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=862825481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.862825481
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3222739328
Short name T1704
Test name
Test status
Simulation time 151268411 ps
CPU time 0.79 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:24 PM PDT 24
Peak memory 204716 kb
Host smart-b5851416-b007-43d4-82c5-05d394bbdc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227
39328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3222739328
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2330446304
Short name T417
Test name
Test status
Simulation time 159455272 ps
CPU time 0.78 seconds
Started Jun 11 12:40:20 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204632 kb
Host smart-e64535e3-e1fa-4a42-a25b-5f2cdf55c6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23304
46304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2330446304
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3489753755
Short name T476
Test name
Test status
Simulation time 205960462 ps
CPU time 0.86 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:26 PM PDT 24
Peak memory 204696 kb
Host smart-b590deb6-c6c3-42f1-b986-9fddc7e981a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
53755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3489753755
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.193394736
Short name T857
Test name
Test status
Simulation time 180845302 ps
CPU time 0.82 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204700 kb
Host smart-721e7431-e8f8-4d82-a878-b897219bd88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19339
4736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.193394736
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3756861548
Short name T1367
Test name
Test status
Simulation time 203111613 ps
CPU time 0.82 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204752 kb
Host smart-5343a9ca-7c49-4745-9ffb-50b91e87aef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37568
61548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3756861548
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1473280187
Short name T2087
Test name
Test status
Simulation time 12286727925 ps
CPU time 333.28 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:45:58 PM PDT 24
Peak memory 205040 kb
Host smart-b81bf972-d13a-40ee-bb8c-c9681c4fb0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
80187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1473280187
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1744350291
Short name T1195
Test name
Test status
Simulation time 30534669472 ps
CPU time 232.86 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204940 kb
Host smart-a9ac9715-c6ac-4091-90f5-179b862e9ae8
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744350291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_
traffic.1744350291
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3424160825
Short name T342
Test name
Test status
Simulation time 4021913641 ps
CPU time 4.86 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:14 PM PDT 24
Peak memory 204956 kb
Host smart-a6ced03c-fa47-4db8-a66e-d995c45ca510
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3424160825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.3424160825
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2943983053
Short name T53
Test name
Test status
Simulation time 13353736350 ps
CPU time 12.44 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204784 kb
Host smart-c1c10515-53af-411e-9ab0-994c2530f9da
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2943983053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2943983053
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2719909285
Short name T1717
Test name
Test status
Simulation time 23336730089 ps
CPU time 22.67 seconds
Started Jun 11 12:43:03 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 205056 kb
Host smart-c4242ddd-3adf-4c65-8b9e-e6909de19c51
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2719909285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.2719909285
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.4285978653
Short name T97
Test name
Test status
Simulation time 155543039 ps
CPU time 0.79 seconds
Started Jun 11 12:43:05 PM PDT 24
Finished Jun 11 12:43:09 PM PDT 24
Peak memory 204748 kb
Host smart-9edda813-d0f7-4013-bd0c-dfb8a5fc85b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42859
78653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.4285978653
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.643237550
Short name T1814
Test name
Test status
Simulation time 163376473 ps
CPU time 0.78 seconds
Started Jun 11 12:42:58 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204708 kb
Host smart-d5958d75-c9a1-4b5e-be7c-e4f3e08e8c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64323
7550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.643237550
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.841806521
Short name T1095
Test name
Test status
Simulation time 1191459184 ps
CPU time 2.83 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:08 PM PDT 24
Peak memory 204824 kb
Host smart-6244286c-2c9f-473d-b023-7683fed9e174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84180
6521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.841806521
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.568253901
Short name T490
Test name
Test status
Simulation time 132604784 ps
CPU time 0.78 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204660 kb
Host smart-7a232e57-b97e-4e5b-857b-ed8ab057a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56825
3901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.568253901
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3601469494
Short name T469
Test name
Test status
Simulation time 36414000 ps
CPU time 0.64 seconds
Started Jun 11 12:43:09 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204708 kb
Host smart-0ce91ce5-5b7e-4a36-9ef3-e63ce317c525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36014
69494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3601469494
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1752739858
Short name T993
Test name
Test status
Simulation time 918042633 ps
CPU time 2.17 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204900 kb
Host smart-7a417207-80f4-4f57-844e-cf26540c8f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17527
39858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1752739858
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3916110033
Short name T671
Test name
Test status
Simulation time 338955274 ps
CPU time 2.22 seconds
Started Jun 11 12:43:27 PM PDT 24
Finished Jun 11 12:43:30 PM PDT 24
Peak memory 204872 kb
Host smart-7f539035-3f78-48e2-92f7-192e4de65fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161
10033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3916110033
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3757906959
Short name T1349
Test name
Test status
Simulation time 168449636 ps
CPU time 0.77 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204700 kb
Host smart-76ad800b-0076-4b13-907e-8efcbe2b8052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
06959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3757906959
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.27325268
Short name T559
Test name
Test status
Simulation time 180227381 ps
CPU time 0.82 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204744 kb
Host smart-3ab21c76-3871-48fb-82c2-65da7e087450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27325
268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.27325268
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.731269642
Short name T1431
Test name
Test status
Simulation time 157005186 ps
CPU time 0.79 seconds
Started Jun 11 12:43:03 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204692 kb
Host smart-681387fd-0afa-4d5f-9f5f-e3214a17624b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73126
9642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.731269642
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1752374398
Short name T1453
Test name
Test status
Simulation time 155842566 ps
CPU time 0.77 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204768 kb
Host smart-e7a584d2-59ba-443a-8ea5-b0146bec7b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17523
74398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1752374398
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3064501271
Short name T353
Test name
Test status
Simulation time 3314330005 ps
CPU time 3.99 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204748 kb
Host smart-3753da36-65fa-403e-a68e-ae2d77628c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30645
01271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3064501271
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.1246248963
Short name T702
Test name
Test status
Simulation time 241225481 ps
CPU time 0.96 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204704 kb
Host smart-ce162a4b-6e63-4278-ac72-e09cfa6f096a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1246248963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.1246248963
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1278290730
Short name T567
Test name
Test status
Simulation time 220842037 ps
CPU time 0.84 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204748 kb
Host smart-f01f418d-a43c-4ee4-af02-c0280a0e3ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12782
90730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1278290730
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.2400516809
Short name T1900
Test name
Test status
Simulation time 10905304248 ps
CPU time 78.59 seconds
Started Jun 11 12:42:58 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204992 kb
Host smart-3fd53be6-7b3b-4e3f-9853-aa07cfa4e5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24005
16809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.2400516809
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2051021601
Short name T719
Test name
Test status
Simulation time 155335437 ps
CPU time 0.8 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204724 kb
Host smart-baead9b6-0ce7-45ca-b433-7d52d851ca1f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2051021601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2051021601
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.62364472
Short name T2037
Test name
Test status
Simulation time 143486817 ps
CPU time 0.76 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204660 kb
Host smart-c0a3ed08-cc16-433c-9214-c2d4d444de51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62364
472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.62364472
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1674004666
Short name T166
Test name
Test status
Simulation time 183824777 ps
CPU time 0.85 seconds
Started Jun 11 12:43:23 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 204624 kb
Host smart-72c2359e-8459-421d-8230-72574bbf794a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16740
04666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1674004666
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1148893009
Short name T439
Test name
Test status
Simulation time 172328931 ps
CPU time 0.8 seconds
Started Jun 11 12:43:13 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204680 kb
Host smart-cc67d284-bb98-48bb-8e03-a2aefd39298c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11488
93009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1148893009
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2034598141
Short name T883
Test name
Test status
Simulation time 157413857 ps
CPU time 0.76 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:03 PM PDT 24
Peak memory 204708 kb
Host smart-947fe043-c0fb-4119-869c-e5653c493485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20345
98141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2034598141
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2288467907
Short name T1672
Test name
Test status
Simulation time 188321798 ps
CPU time 0.83 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204656 kb
Host smart-ce676e15-f5f5-45b9-8dca-b727ef930bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884
67907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2288467907
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2978492642
Short name T1998
Test name
Test status
Simulation time 144424195 ps
CPU time 0.78 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204724 kb
Host smart-cbcfc343-2724-4476-be18-1af8c7f04ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29784
92642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2978492642
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_eop_single_bit_handling.1930015802
Short name T1269
Test name
Test status
Simulation time 186554056 ps
CPU time 0.84 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204628 kb
Host smart-e997192e-65e4-4811-a3d8-e8c892c63fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19300
15802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_eop_single_bit_handling.1930015802
Directory /workspace/30.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1443821711
Short name T1618
Test name
Test status
Simulation time 170657755 ps
CPU time 0.74 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204760 kb
Host smart-368d18e2-12d5-4f18-b656-b1a4a589496d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14438
21711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1443821711
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.617534203
Short name T46
Test name
Test status
Simulation time 74391433 ps
CPU time 0.67 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204736 kb
Host smart-d6e0da5b-26e9-4abb-9287-afd69f249105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61753
4203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.617534203
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1574472601
Short name T752
Test name
Test status
Simulation time 17998441004 ps
CPU time 35.88 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:40 PM PDT 24
Peak memory 204972 kb
Host smart-65845612-5bc4-4d45-8dc0-5580489338e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15744
72601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1574472601
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2734843613
Short name T1880
Test name
Test status
Simulation time 252253736 ps
CPU time 0.88 seconds
Started Jun 11 12:43:13 PM PDT 24
Finished Jun 11 12:43:15 PM PDT 24
Peak memory 204620 kb
Host smart-ec13d4fc-efd7-40a5-aaf7-d2fa3ef7715b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
43613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2734843613
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1621011804
Short name T790
Test name
Test status
Simulation time 249454280 ps
CPU time 1 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204652 kb
Host smart-f92ecc59-c8af-450c-8fbd-c3e7a690b671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16210
11804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1621011804
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3331427753
Short name T967
Test name
Test status
Simulation time 213169946 ps
CPU time 0.88 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204988 kb
Host smart-cba2a82f-644c-4271-86b5-2a9568f95e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33314
27753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3331427753
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.816074802
Short name T2028
Test name
Test status
Simulation time 205593860 ps
CPU time 0.76 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204728 kb
Host smart-a0466da4-e1f6-4afb-a8ee-371fe5de64e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81607
4802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.816074802
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.114728595
Short name T1833
Test name
Test status
Simulation time 146996089 ps
CPU time 0.73 seconds
Started Jun 11 12:43:20 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 204768 kb
Host smart-8a941984-0f67-40b5-be8f-74fba166c563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11472
8595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.114728595
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2325298630
Short name T1631
Test name
Test status
Simulation time 178769380 ps
CPU time 0.8 seconds
Started Jun 11 12:43:14 PM PDT 24
Finished Jun 11 12:43:16 PM PDT 24
Peak memory 204620 kb
Host smart-dd8928a7-4ab3-4219-a7dc-3d8d2f7ba9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23252
98630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2325298630
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.4014564276
Short name T1365
Test name
Test status
Simulation time 153209970 ps
CPU time 0.78 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204728 kb
Host smart-2b398f28-28bd-42ab-be47-5457f92dea9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40145
64276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.4014564276
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.1878039077
Short name T1156
Test name
Test status
Simulation time 244898628 ps
CPU time 0.93 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204704 kb
Host smart-8cf8d8d2-413b-4fbb-b5a3-dc93b22f48bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18780
39077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.1878039077
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3768000343
Short name T1664
Test name
Test status
Simulation time 176714576 ps
CPU time 0.86 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204720 kb
Host smart-5820940c-751e-44d6-b4c8-540101be59d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37680
00343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3768000343
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.679944235
Short name T1613
Test name
Test status
Simulation time 180377181 ps
CPU time 0.76 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204656 kb
Host smart-8d7bdfe6-b3f6-471e-8dbb-0bfaff28514b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67994
4235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.679944235
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.785152324
Short name T616
Test name
Test status
Simulation time 10619911508 ps
CPU time 299.34 seconds
Started Jun 11 12:42:55 PM PDT 24
Finished Jun 11 12:47:58 PM PDT 24
Peak memory 204996 kb
Host smart-2e54881b-6daa-447c-bdc8-45ba5d0ac7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78515
2324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.785152324
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.4072499706
Short name T995
Test name
Test status
Simulation time 3610227430 ps
CPU time 4.28 seconds
Started Jun 11 12:44:02 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 204876 kb
Host smart-b2f0745c-50a5-4825-8d08-96f9c91c9926
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4072499706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.4072499706
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.153277641
Short name T711
Test name
Test status
Simulation time 13481326037 ps
CPU time 13.28 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204976 kb
Host smart-eef79c63-3ff5-411e-9c24-53dbaeedfa07
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=153277641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.153277641
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2324400519
Short name T14
Test name
Test status
Simulation time 23315162713 ps
CPU time 29.88 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:31 PM PDT 24
Peak memory 204752 kb
Host smart-d351f95a-37d3-4606-8c1f-c2e8a05ecd48
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2324400519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2324400519
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2326223091
Short name T310
Test name
Test status
Simulation time 149055077 ps
CPU time 0.74 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204668 kb
Host smart-b9d3c9c2-8ea4-4123-926d-296f9cde266b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23262
23091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2326223091
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.325966267
Short name T661
Test name
Test status
Simulation time 138909679 ps
CPU time 0.75 seconds
Started Jun 11 12:42:53 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204664 kb
Host smart-51ea4dab-bbfc-48ad-961f-212db1922000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32596
6267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.325966267
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2106128654
Short name T1933
Test name
Test status
Simulation time 831389654 ps
CPU time 1.91 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204948 kb
Host smart-be81ea1b-1224-4635-a721-c698e88672c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21061
28654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2106128654
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.156932016
Short name T1099
Test name
Test status
Simulation time 145121876 ps
CPU time 0.78 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204740 kb
Host smart-1e049250-40d5-4485-b0ba-628ae740239a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15693
2016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.156932016
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2167499462
Short name T943
Test name
Test status
Simulation time 51084297 ps
CPU time 0.66 seconds
Started Jun 11 12:42:58 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204692 kb
Host smart-2ed386ce-4a7c-4039-a178-f5651547c03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21674
99462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2167499462
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2262003775
Short name T1197
Test name
Test status
Simulation time 927909551 ps
CPU time 2.22 seconds
Started Jun 11 12:42:52 PM PDT 24
Finished Jun 11 12:42:58 PM PDT 24
Peak memory 204944 kb
Host smart-8a348bc3-74ba-4f9d-9316-f9fcbf729038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
03775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2262003775
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.1501977015
Short name T1691
Test name
Test status
Simulation time 362197384 ps
CPU time 2.44 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204936 kb
Host smart-fcf91165-15ed-4d60-af63-02607ecf7a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15019
77015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.1501977015
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2473759718
Short name T515
Test name
Test status
Simulation time 212610350 ps
CPU time 0.96 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204640 kb
Host smart-21827d45-cfd8-4644-93e7-40e5aa6cd351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24737
59718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2473759718
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.933519092
Short name T541
Test name
Test status
Simulation time 164453139 ps
CPU time 0.76 seconds
Started Jun 11 12:43:16 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204704 kb
Host smart-f50a8f64-c339-419b-900b-a7ed348a27f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93351
9092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.933519092
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2504974863
Short name T1602
Test name
Test status
Simulation time 171685078 ps
CPU time 0.76 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:13 PM PDT 24
Peak memory 204576 kb
Host smart-ddf2969a-1474-4710-b709-18c8d18e38c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25049
74863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2504974863
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3653358927
Short name T1566
Test name
Test status
Simulation time 217088409 ps
CPU time 0.85 seconds
Started Jun 11 12:42:58 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204684 kb
Host smart-52a4e1fc-6cf6-4c05-bb41-e522e971bb3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36533
58927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3653358927
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3797735627
Short name T398
Test name
Test status
Simulation time 3285009256 ps
CPU time 4.5 seconds
Started Jun 11 12:43:16 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 204688 kb
Host smart-80d5fa85-3969-4864-aea1-7bb581e7708b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
35627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3797735627
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.15903311
Short name T1851
Test name
Test status
Simulation time 295317547 ps
CPU time 0.93 seconds
Started Jun 11 12:43:04 PM PDT 24
Finished Jun 11 12:43:09 PM PDT 24
Peak memory 204748 kb
Host smart-fff5f0b8-149b-41ed-a526-be00e9449f29
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=15903311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.15903311
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1482615291
Short name T1893
Test name
Test status
Simulation time 194499111 ps
CPU time 0.81 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204588 kb
Host smart-a563c042-958e-4471-afb3-ad5f3d7531fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14826
15291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1482615291
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1139972772
Short name T729
Test name
Test status
Simulation time 8622284815 ps
CPU time 78.71 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 205000 kb
Host smart-90de7e31-4651-4072-a48d-e3145a4e3c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11399
72772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1139972772
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3605174581
Short name T1806
Test name
Test status
Simulation time 158696719 ps
CPU time 0.79 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204668 kb
Host smart-5b557ec0-e55c-4478-a8a4-02f5194b3e1d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3605174581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3605174581
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3094980471
Short name T1128
Test name
Test status
Simulation time 146145959 ps
CPU time 0.75 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204728 kb
Host smart-f6a18c16-277e-462f-8ea6-d144fdc3b499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30949
80471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3094980471
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.450849765
Short name T134
Test name
Test status
Simulation time 169241497 ps
CPU time 0.8 seconds
Started Jun 11 12:42:56 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204692 kb
Host smart-e4ef86aa-5355-41fb-9c70-5d79100cacb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45084
9765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.450849765
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4272474097
Short name T1458
Test name
Test status
Simulation time 201122049 ps
CPU time 0.8 seconds
Started Jun 11 12:44:03 PM PDT 24
Finished Jun 11 12:44:10 PM PDT 24
Peak memory 204572 kb
Host smart-3640a72d-22ae-498a-9125-00548a7832f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42724
74097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4272474097
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2311447450
Short name T1660
Test name
Test status
Simulation time 175263900 ps
CPU time 0.8 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204700 kb
Host smart-b9db31e1-6723-4d61-8c68-bbcab4fa0f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23114
47450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2311447450
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1442924009
Short name T802
Test name
Test status
Simulation time 160986528 ps
CPU time 0.79 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204740 kb
Host smart-8672d21f-4647-49f6-867f-e1c75367c59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14429
24009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1442924009
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_eop_single_bit_handling.1795260773
Short name T1137
Test name
Test status
Simulation time 163573906 ps
CPU time 0.81 seconds
Started Jun 11 12:43:12 PM PDT 24
Finished Jun 11 12:43:14 PM PDT 24
Peak memory 204728 kb
Host smart-04849f5e-af4e-43fe-b925-f58925b6a94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17952
60773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_eop_single_bit_handling.1795260773
Directory /workspace/31.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.214223385
Short name T107
Test name
Test status
Simulation time 140171732 ps
CPU time 0.76 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204768 kb
Host smart-bfc53b81-6462-46c6-ae63-deee36f9242a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21422
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.214223385
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3082838941
Short name T1471
Test name
Test status
Simulation time 36516886 ps
CPU time 0.66 seconds
Started Jun 11 12:43:11 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204724 kb
Host smart-6f7f51bd-95f0-42ea-949c-a121165af127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
38941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3082838941
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1344836873
Short name T871
Test name
Test status
Simulation time 14738344111 ps
CPU time 31.57 seconds
Started Jun 11 12:43:13 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 205028 kb
Host smart-5bd227b1-fc88-45d5-a1cc-19caedf909f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13448
36873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1344836873
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1513371583
Short name T1018
Test name
Test status
Simulation time 187608341 ps
CPU time 0.93 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204656 kb
Host smart-0e0e8105-da7c-476e-b217-89793acbcfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15133
71583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1513371583
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2550371102
Short name T2095
Test name
Test status
Simulation time 183026964 ps
CPU time 0.79 seconds
Started Jun 11 12:43:12 PM PDT 24
Finished Jun 11 12:43:14 PM PDT 24
Peak memory 204764 kb
Host smart-cc3163d3-412d-4156-9c50-927201ce4c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503
71102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2550371102
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.162548606
Short name T1987
Test name
Test status
Simulation time 203537090 ps
CPU time 0.88 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204712 kb
Host smart-9f599859-cab6-414c-a2df-e66b34368c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16254
8606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.162548606
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3505835303
Short name T1123
Test name
Test status
Simulation time 217264089 ps
CPU time 0.86 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204736 kb
Host smart-740a2782-8e06-4e2c-b4c9-0a25f89a70c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35058
35303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3505835303
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2094913126
Short name T401
Test name
Test status
Simulation time 166964866 ps
CPU time 0.78 seconds
Started Jun 11 12:43:04 PM PDT 24
Finished Jun 11 12:43:09 PM PDT 24
Peak memory 204624 kb
Host smart-ded37938-bf57-44ba-a1c5-5107680d450c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20949
13126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2094913126
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.872261075
Short name T1157
Test name
Test status
Simulation time 152140743 ps
CPU time 0.78 seconds
Started Jun 11 12:43:23 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204720 kb
Host smart-81585ea7-f25c-4887-95e1-eb189b424fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87226
1075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.872261075
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.150250841
Short name T378
Test name
Test status
Simulation time 200132798 ps
CPU time 0.77 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204752 kb
Host smart-6729957a-0ed9-4415-999c-adb9bcfd26c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15025
0841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.150250841
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.590973928
Short name T1345
Test name
Test status
Simulation time 214226699 ps
CPU time 0.93 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:02 PM PDT 24
Peak memory 204764 kb
Host smart-cf5cd2b2-65d1-4521-8a4c-8421f8963581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59097
3928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.590973928
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2364797365
Short name T958
Test name
Test status
Simulation time 174046887 ps
CPU time 0.82 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204636 kb
Host smart-71f1e6c2-6f7a-46d4-95fd-eecb9e93af81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23647
97365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2364797365
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3395633247
Short name T831
Test name
Test status
Simulation time 187044626 ps
CPU time 0.97 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204716 kb
Host smart-0f04e82e-a8b3-4a72-aedd-2961d9b1b62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33956
33247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3395633247
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3806321824
Short name T528
Test name
Test status
Simulation time 8325113168 ps
CPU time 233.47 seconds
Started Jun 11 12:43:09 PM PDT 24
Finished Jun 11 12:47:04 PM PDT 24
Peak memory 204944 kb
Host smart-5d0ca67d-6ec5-46d1-a97a-0fc8a3ad6a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
21824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3806321824
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.177859619
Short name T217
Test name
Test status
Simulation time 3785098893 ps
CPU time 5.64 seconds
Started Jun 11 12:43:15 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 205088 kb
Host smart-3572428b-fbef-42dd-955e-36e33d6742e4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=177859619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.177859619
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1400626783
Short name T1722
Test name
Test status
Simulation time 13350183831 ps
CPU time 12.11 seconds
Started Jun 11 12:43:23 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204792 kb
Host smart-ca5d5c13-f102-40b0-b312-36f5025e2d16
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1400626783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1400626783
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3983768255
Short name T1107
Test name
Test status
Simulation time 23359243588 ps
CPU time 22.02 seconds
Started Jun 11 12:42:57 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 205020 kb
Host smart-621d38b9-32ca-4066-88ef-7d178405f544
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3983768255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3983768255
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.311082891
Short name T526
Test name
Test status
Simulation time 181261830 ps
CPU time 0.82 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204624 kb
Host smart-6ca1b514-de8d-4245-8f24-60f636d12be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
2891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.311082891
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.948685536
Short name T1633
Test name
Test status
Simulation time 155755616 ps
CPU time 0.82 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204628 kb
Host smart-9d255bbc-b97a-4c1b-b661-0616b793b808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94868
5536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.948685536
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3229686814
Short name T1149
Test name
Test status
Simulation time 136235234 ps
CPU time 0.79 seconds
Started Jun 11 12:43:20 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 204776 kb
Host smart-ca712e76-83d0-4c98-9f8d-1e477c25bb77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32296
86814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3229686814
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2328775581
Short name T223
Test name
Test status
Simulation time 50687098 ps
CPU time 0.7 seconds
Started Jun 11 12:43:05 PM PDT 24
Finished Jun 11 12:43:09 PM PDT 24
Peak memory 204976 kb
Host smart-74385303-e9b7-44ea-b5ee-fb280ee60bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
75581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2328775581
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.1660390021
Short name T842
Test name
Test status
Simulation time 968096423 ps
CPU time 2.33 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204832 kb
Host smart-9f40cc3f-41df-4d70-91c7-5d98d1751af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16603
90021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1660390021
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3354452573
Short name T422
Test name
Test status
Simulation time 156009372 ps
CPU time 1.23 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204904 kb
Host smart-7aa95d26-e35e-4c0c-ace7-6c7712d4092c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544
52573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3354452573
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.799262934
Short name T1165
Test name
Test status
Simulation time 287978869 ps
CPU time 0.92 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204708 kb
Host smart-8c1803bc-3500-4919-9bfc-ffa9825a9c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79926
2934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.799262934
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3088095930
Short name T1199
Test name
Test status
Simulation time 137550465 ps
CPU time 0.74 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:23 PM PDT 24
Peak memory 204740 kb
Host smart-9c3cd080-d1af-4058-bebc-127b66a4847d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
95930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3088095930
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3872739382
Short name T2074
Test name
Test status
Simulation time 256476728 ps
CPU time 0.93 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204704 kb
Host smart-c9a10606-ce4b-4700-864f-265ced9a2ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38727
39382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3872739382
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1534392118
Short name T335
Test name
Test status
Simulation time 217757232 ps
CPU time 0.86 seconds
Started Jun 11 12:43:17 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204696 kb
Host smart-5c3ed994-d311-4d40-8365-cdce62adcc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15343
92118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1534392118
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.510271669
Short name T1084
Test name
Test status
Simulation time 3313634369 ps
CPU time 4.36 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:08 PM PDT 24
Peak memory 204744 kb
Host smart-8af6a250-b49f-40e0-9097-c2b959633ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51027
1669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.510271669
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1848960159
Short name T361
Test name
Test status
Simulation time 236624625 ps
CPU time 0.9 seconds
Started Jun 11 12:43:17 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204608 kb
Host smart-0ee4bba1-94a1-4a7b-8d69-dbec9096cb14
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1848960159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1848960159
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.427788135
Short name T1628
Test name
Test status
Simulation time 244719702 ps
CPU time 0.88 seconds
Started Jun 11 12:43:17 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204756 kb
Host smart-1ceaa2ae-f3c2-4384-b960-ab86d43fc123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
8135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.427788135
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2545492867
Short name T1478
Test name
Test status
Simulation time 13319797241 ps
CPU time 359.28 seconds
Started Jun 11 12:43:06 PM PDT 24
Finished Jun 11 12:49:08 PM PDT 24
Peak memory 205080 kb
Host smart-0f34da8f-e7ca-4b79-b600-11f5685852f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454
92867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2545492867
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1165228759
Short name T579
Test name
Test status
Simulation time 166495682 ps
CPU time 0.81 seconds
Started Jun 11 12:43:11 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204720 kb
Host smart-19e09687-d5dd-4a33-b663-7405c493b71f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1165228759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1165228759
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1418064991
Short name T316
Test name
Test status
Simulation time 147681195 ps
CPU time 0.75 seconds
Started Jun 11 12:42:59 PM PDT 24
Finished Jun 11 12:43:04 PM PDT 24
Peak memory 204740 kb
Host smart-394abcce-b223-4b36-965c-33b019cf9102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
64991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1418064991
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1762754611
Short name T154
Test name
Test status
Simulation time 182999946 ps
CPU time 0.84 seconds
Started Jun 11 12:43:05 PM PDT 24
Finished Jun 11 12:43:14 PM PDT 24
Peak memory 204736 kb
Host smart-6a81bb79-4306-4a24-84e3-921783234329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17627
54611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1762754611
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.46674689
Short name T1654
Test name
Test status
Simulation time 168805214 ps
CPU time 0.8 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204740 kb
Host smart-0c86222f-e9f6-4de6-93a1-2c6c03820324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46674
689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.46674689
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.592650427
Short name T1712
Test name
Test status
Simulation time 198919545 ps
CPU time 0.8 seconds
Started Jun 11 12:43:11 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204700 kb
Host smart-47c60a2e-7b91-4390-9fe1-12565d6b3056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59265
0427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.592650427
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.2908531211
Short name T1163
Test name
Test status
Simulation time 150818750 ps
CPU time 0.79 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:24 PM PDT 24
Peak memory 204688 kb
Host smart-ea74eee8-b07f-4691-8744-7c0b717e98a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
31211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.2908531211
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2529420587
Short name T1278
Test name
Test status
Simulation time 192498657 ps
CPU time 0.79 seconds
Started Jun 11 12:43:14 PM PDT 24
Finished Jun 11 12:43:16 PM PDT 24
Peak memory 204688 kb
Host smart-e2dffad4-af5b-40c4-b555-7907f1610e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25294
20587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2529420587
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_eop_single_bit_handling.2161733267
Short name T1246
Test name
Test status
Simulation time 190478131 ps
CPU time 0.86 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204684 kb
Host smart-f5cec645-b3e2-4122-af00-f1445c42fdb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
33267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_eop_single_bit_handling.2161733267
Directory /workspace/32.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.1413808592
Short name T638
Test name
Test status
Simulation time 151469828 ps
CPU time 0.76 seconds
Started Jun 11 12:43:26 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204708 kb
Host smart-806c0b7e-2c18-4952-8605-4aa5612a07b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
08592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.1413808592
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.894181979
Short name T132
Test name
Test status
Simulation time 34285666 ps
CPU time 0.65 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204564 kb
Host smart-a037ee13-a494-4b96-ae1f-8081c0a33080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89418
1979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.894181979
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.3103903159
Short name T1740
Test name
Test status
Simulation time 15754065856 ps
CPU time 34.25 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 205040 kb
Host smart-b41c556c-359c-4273-b4e3-025e2a800218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039
03159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.3103903159
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1681431081
Short name T527
Test name
Test status
Simulation time 191286119 ps
CPU time 0.84 seconds
Started Jun 11 12:43:15 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204684 kb
Host smart-cea49f4f-bb56-460d-ba04-e22e47516afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
31081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1681431081
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3350742008
Short name T937
Test name
Test status
Simulation time 229323600 ps
CPU time 0.86 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204728 kb
Host smart-a6e06306-e9d9-4402-8388-d5e159eaa0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33507
42008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3350742008
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1538821448
Short name T1190
Test name
Test status
Simulation time 216317689 ps
CPU time 0.82 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204720 kb
Host smart-43df039d-60a2-478e-b0ad-bf519ea366e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15388
21448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1538821448
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.4072388137
Short name T1569
Test name
Test status
Simulation time 186212195 ps
CPU time 0.85 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204576 kb
Host smart-e37896fd-233a-4cd3-980e-76323539588f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723
88137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.4072388137
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.746033432
Short name T1640
Test name
Test status
Simulation time 136659147 ps
CPU time 0.72 seconds
Started Jun 11 12:43:00 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204732 kb
Host smart-a95e85e9-5458-4643-ba50-ffea7c618550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74603
3432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.746033432
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.977879129
Short name T186
Test name
Test status
Simulation time 223542498 ps
CPU time 0.84 seconds
Started Jun 11 12:43:26 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204688 kb
Host smart-1f1dfba6-915a-467f-a1f9-b37968c27869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97787
9129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.977879129
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3957253102
Short name T1788
Test name
Test status
Simulation time 172562459 ps
CPU time 0.78 seconds
Started Jun 11 12:43:20 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204748 kb
Host smart-cf579a87-ab2f-4b98-8e93-b4b274015ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39572
53102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3957253102
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.465048036
Short name T674
Test name
Test status
Simulation time 229310177 ps
CPU time 0.91 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:05 PM PDT 24
Peak memory 204688 kb
Host smart-9cefafbb-a674-4a91-97fa-38c94e14aec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46504
8036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.465048036
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2158481836
Short name T603
Test name
Test status
Simulation time 207174546 ps
CPU time 0.86 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204608 kb
Host smart-5e2599c2-504d-4b27-9274-d6b55ae36b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21584
81836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2158481836
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3758371823
Short name T909
Test name
Test status
Simulation time 191666270 ps
CPU time 0.96 seconds
Started Jun 11 12:43:11 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204736 kb
Host smart-650beb5a-79f6-4998-a8f0-0a932910c3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37583
71823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3758371823
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.4280393850
Short name T524
Test name
Test status
Simulation time 5273157809 ps
CPU time 36.35 seconds
Started Jun 11 12:43:03 PM PDT 24
Finished Jun 11 12:43:43 PM PDT 24
Peak memory 204896 kb
Host smart-99bf586d-bc4d-48dd-b79b-cd824f8b397b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42803
93850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.4280393850
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2488806363
Short name T1811
Test name
Test status
Simulation time 3682147895 ps
CPU time 5.42 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204836 kb
Host smart-44ec4898-bebc-4d50-a87e-2968529bd300
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2488806363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2488806363
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3533142978
Short name T2021
Test name
Test status
Simulation time 13326223822 ps
CPU time 13.09 seconds
Started Jun 11 12:43:09 PM PDT 24
Finished Jun 11 12:43:24 PM PDT 24
Peak memory 204796 kb
Host smart-f28dee75-d645-461a-ad33-e15a866242b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3533142978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3533142978
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.320100813
Short name T2057
Test name
Test status
Simulation time 23428625796 ps
CPU time 23.3 seconds
Started Jun 11 12:43:23 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 205000 kb
Host smart-8eccba46-65ab-4297-a4c5-820196972aee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=320100813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.320100813
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1865582557
Short name T543
Test name
Test status
Simulation time 156451727 ps
CPU time 0.8 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204636 kb
Host smart-70336bb1-5fbf-4c32-94aa-0f1338b53a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18655
82557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1865582557
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2298662594
Short name T1204
Test name
Test status
Simulation time 142370474 ps
CPU time 0.74 seconds
Started Jun 11 12:43:15 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204712 kb
Host smart-6ed5ea7a-8a06-4859-8fc8-652313adc1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22986
62594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2298662594
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3819626120
Short name T925
Test name
Test status
Simulation time 1047352209 ps
CPU time 2.36 seconds
Started Jun 11 12:43:09 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204952 kb
Host smart-f79bb203-2493-492f-8854-bc92e48a9155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38196
26120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3819626120
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1872003152
Short name T1598
Test name
Test status
Simulation time 179132140 ps
CPU time 0.78 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204716 kb
Host smart-169c1006-f467-4d13-ba28-86b2543b6add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18720
03152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1872003152
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3749322532
Short name T1259
Test name
Test status
Simulation time 42601847 ps
CPU time 0.65 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204648 kb
Host smart-a0337ef4-818a-4deb-84ea-7a0caa5e854d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37493
22532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3749322532
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1773778754
Short name T554
Test name
Test status
Simulation time 962497893 ps
CPU time 2.16 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:24 PM PDT 24
Peak memory 204844 kb
Host smart-d778f73a-991a-4b79-ad1d-311e7372f23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17737
78754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1773778754
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.363681422
Short name T1776
Test name
Test status
Simulation time 402835460 ps
CPU time 2.49 seconds
Started Jun 11 12:43:17 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204860 kb
Host smart-82c75392-6ee7-4bf6-9a25-d7c7f0fc59d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36368
1422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.363681422
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2414677354
Short name T1477
Test name
Test status
Simulation time 165607790 ps
CPU time 0.78 seconds
Started Jun 11 12:43:22 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 204632 kb
Host smart-05dd84dd-ba85-4424-a9bd-d3ab9fa2bd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24146
77354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2414677354
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1902467560
Short name T1155
Test name
Test status
Simulation time 144994766 ps
CPU time 0.82 seconds
Started Jun 11 12:43:18 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204712 kb
Host smart-92c1f262-b3d4-4c9d-9a50-3ce001099f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024
67560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1902467560
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1128727488
Short name T1186
Test name
Test status
Simulation time 173738938 ps
CPU time 0.86 seconds
Started Jun 11 12:43:20 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 204700 kb
Host smart-eaca83bb-60ce-4b7b-baa8-ef594588f94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11287
27488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1128727488
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.207153328
Short name T969
Test name
Test status
Simulation time 207251641 ps
CPU time 0.86 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204668 kb
Host smart-8aa97284-9188-42e7-94e1-6efee51d740f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
3328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.207153328
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2601338773
Short name T1761
Test name
Test status
Simulation time 3329760943 ps
CPU time 3.97 seconds
Started Jun 11 12:43:12 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204800 kb
Host smart-77d09a92-c04e-4e74-8cae-8b08f4ed2f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26013
38773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2601338773
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.579899574
Short name T1902
Test name
Test status
Simulation time 263186916 ps
CPU time 1 seconds
Started Jun 11 12:43:29 PM PDT 24
Finished Jun 11 12:43:31 PM PDT 24
Peak memory 204704 kb
Host smart-3393b2d8-dd88-4831-8f95-ac3fbeb92d56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=579899574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.579899574
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1083110087
Short name T689
Test name
Test status
Simulation time 189330609 ps
CPU time 0.85 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204712 kb
Host smart-69fcf0ca-7856-41c4-ad00-34d3e4e5ea16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10831
10087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1083110087
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1920170496
Short name T630
Test name
Test status
Simulation time 8611886132 ps
CPU time 77.93 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 205112 kb
Host smart-d0a9a16d-7541-4420-81a8-0f78ee5b4d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19201
70496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1920170496
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3568288603
Short name T358
Test name
Test status
Simulation time 168454618 ps
CPU time 0.81 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204700 kb
Host smart-a6dd9c2c-6676-41a4-9721-cc04990874a4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3568288603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3568288603
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.496833913
Short name T1873
Test name
Test status
Simulation time 146387025 ps
CPU time 0.76 seconds
Started Jun 11 12:43:18 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204656 kb
Host smart-899d5749-cd54-43ec-925e-54784087d6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49683
3913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.496833913
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.87149772
Short name T162
Test name
Test status
Simulation time 216898600 ps
CPU time 0.9 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:23 PM PDT 24
Peak memory 204700 kb
Host smart-c4ebdd8b-f37b-4326-8c33-c40243f19e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87149
772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.87149772
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.371994418
Short name T1305
Test name
Test status
Simulation time 152913435 ps
CPU time 0.81 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204664 kb
Host smart-d5958101-86e5-4ae9-9035-12d587c5f480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37199
4418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.371994418
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2849323977
Short name T28
Test name
Test status
Simulation time 174493601 ps
CPU time 0.97 seconds
Started Jun 11 12:43:15 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204692 kb
Host smart-59b84002-f89f-45f5-aa08-0f10cbc52f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28493
23977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2849323977
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2975175660
Short name T1344
Test name
Test status
Simulation time 151388108 ps
CPU time 0.76 seconds
Started Jun 11 12:43:16 PM PDT 24
Finished Jun 11 12:43:18 PM PDT 24
Peak memory 204624 kb
Host smart-e5e6e99d-cae4-4ab0-944c-e01456be74ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29751
75660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2975175660
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3656813662
Short name T1732
Test name
Test status
Simulation time 154397926 ps
CPU time 0.8 seconds
Started Jun 11 12:43:01 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 204724 kb
Host smart-adbdd3ae-2c86-490e-8b70-0be4ad941f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36568
13662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3656813662
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_eop_single_bit_handling.605859939
Short name T1803
Test name
Test status
Simulation time 183326314 ps
CPU time 0.86 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204724 kb
Host smart-1d3ab5d9-67a9-49a8-9c8b-6528d2cd33e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60585
9939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_eop_single_bit_handling.605859939
Directory /workspace/33.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2440104802
Short name T1781
Test name
Test status
Simulation time 160807024 ps
CPU time 0.77 seconds
Started Jun 11 12:43:02 PM PDT 24
Finished Jun 11 12:43:07 PM PDT 24
Peak memory 204676 kb
Host smart-2a46bb76-ed33-4b64-907a-4df31d027030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24401
04802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2440104802
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3752000571
Short name T1800
Test name
Test status
Simulation time 34334469 ps
CPU time 0.63 seconds
Started Jun 11 12:43:14 PM PDT 24
Finished Jun 11 12:43:15 PM PDT 24
Peak memory 204716 kb
Host smart-d0a1692a-d3fc-4073-8a65-dfa9817c8361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
00571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3752000571
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.185999917
Short name T1536
Test name
Test status
Simulation time 6466790086 ps
CPU time 14.84 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 205024 kb
Host smart-87460a99-a3e8-435d-b88e-8b7714c4ab8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18599
9917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.185999917
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3211868374
Short name T722
Test name
Test status
Simulation time 158423568 ps
CPU time 0.79 seconds
Started Jun 11 12:43:22 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 204728 kb
Host smart-e909118b-c425-4509-89f6-d502f60c5dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
68374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3211868374
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2327647516
Short name T1931
Test name
Test status
Simulation time 217435294 ps
CPU time 0.87 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204712 kb
Host smart-784eb2a7-73c7-4ff5-a704-4cb3be71e593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23276
47516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2327647516
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3114514394
Short name T1767
Test name
Test status
Simulation time 240938604 ps
CPU time 0.95 seconds
Started Jun 11 12:43:08 PM PDT 24
Finished Jun 11 12:43:11 PM PDT 24
Peak memory 204732 kb
Host smart-5aa81c83-f94c-4518-87c6-4451ed45e024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31145
14394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3114514394
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3510045487
Short name T1380
Test name
Test status
Simulation time 192269264 ps
CPU time 0.84 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:10 PM PDT 24
Peak memory 204716 kb
Host smart-e184d50a-c981-4bc5-9033-a6fb75d86c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35100
45487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3510045487
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3118336914
Short name T1141
Test name
Test status
Simulation time 143607701 ps
CPU time 0.76 seconds
Started Jun 11 12:43:22 PM PDT 24
Finished Jun 11 12:43:24 PM PDT 24
Peak memory 204636 kb
Host smart-0fa311f9-21cd-4037-b66e-44c9a88c2563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
36914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3118336914
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2626009582
Short name T756
Test name
Test status
Simulation time 153220084 ps
CPU time 0.8 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:13 PM PDT 24
Peak memory 204752 kb
Host smart-2f01d722-f86a-4ce3-ba53-9f654dcdff1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
09582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2626009582
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2916779923
Short name T728
Test name
Test status
Simulation time 145276172 ps
CPU time 0.82 seconds
Started Jun 11 12:43:18 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204740 kb
Host smart-45123d1a-2f73-44af-a390-ae6a2eb1954a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29167
79923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2916779923
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1653782452
Short name T1713
Test name
Test status
Simulation time 242413633 ps
CPU time 0.97 seconds
Started Jun 11 12:43:09 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204724 kb
Host smart-ebc60090-6a4b-4314-a024-25ddfde31616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16537
82452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1653782452
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2823036874
Short name T1233
Test name
Test status
Simulation time 166917429 ps
CPU time 0.83 seconds
Started Jun 11 12:43:26 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204740 kb
Host smart-d14c4686-0796-4d60-946a-a56f5328ea8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
36874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2823036874
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3466997503
Short name T1208
Test name
Test status
Simulation time 163972227 ps
CPU time 0.87 seconds
Started Jun 11 12:43:12 PM PDT 24
Finished Jun 11 12:43:14 PM PDT 24
Peak memory 204708 kb
Host smart-4c02b029-b8f3-4c1a-a3f5-f6ce6474cd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34669
97503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3466997503
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1359883460
Short name T610
Test name
Test status
Simulation time 13203449643 ps
CPU time 376.71 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:49:39 PM PDT 24
Peak memory 205020 kb
Host smart-9a16b213-6396-40d6-a70f-f0f739bbaa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13598
83460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1359883460
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.105066267
Short name T604
Test name
Test status
Simulation time 3668563641 ps
CPU time 5.32 seconds
Started Jun 11 12:43:43 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 204996 kb
Host smart-8e083144-856a-4ab0-aaed-2581a9f1e407
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=105066267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.105066267
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3134730973
Short name T1719
Test name
Test status
Simulation time 13314490153 ps
CPU time 16.21 seconds
Started Jun 11 12:43:12 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 205040 kb
Host smart-b3ef4d6a-c1d2-470f-a4ba-056566256d7a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3134730973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3134730973
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.890479673
Short name T675
Test name
Test status
Simulation time 23293867753 ps
CPU time 25.55 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 205032 kb
Host smart-cff67f46-0227-4c66-ab0c-6c65cd76e8b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=890479673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.890479673
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.3891316303
Short name T1527
Test name
Test status
Simulation time 197232967 ps
CPU time 0.9 seconds
Started Jun 11 12:43:20 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 204776 kb
Host smart-41a62ee4-2f3a-461a-87a1-9f21c932a0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38913
16303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.3891316303
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.186341970
Short name T1058
Test name
Test status
Simulation time 141939044 ps
CPU time 0.76 seconds
Started Jun 11 12:43:22 PM PDT 24
Finished Jun 11 12:43:25 PM PDT 24
Peak memory 204736 kb
Host smart-e03ae24e-6633-45b2-aed3-d4875936286f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
1970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.186341970
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1774365758
Short name T209
Test name
Test status
Simulation time 1052786841 ps
CPU time 2.46 seconds
Started Jun 11 12:43:33 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204960 kb
Host smart-38166ec8-40df-4fd5-800a-f52bc158aea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
65758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1774365758
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1979005963
Short name T1855
Test name
Test status
Simulation time 138577146 ps
CPU time 0.84 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204652 kb
Host smart-5f1db4ce-0f91-42fa-9506-eaf878c0aaff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19790
05963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1979005963
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.4259179137
Short name T357
Test name
Test status
Simulation time 32326295 ps
CPU time 0.68 seconds
Started Jun 11 12:43:18 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204756 kb
Host smart-e495b42f-5556-4e23-b8f0-757dabc8b8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42591
79137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.4259179137
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1749052528
Short name T1243
Test name
Test status
Simulation time 944754268 ps
CPU time 2.39 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:35 PM PDT 24
Peak memory 204948 kb
Host smart-26037028-557c-4746-b231-2bad575e6609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17490
52528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1749052528
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3268105827
Short name T1088
Test name
Test status
Simulation time 247601209 ps
CPU time 1.61 seconds
Started Jun 11 12:43:37 PM PDT 24
Finished Jun 11 12:43:40 PM PDT 24
Peak memory 204912 kb
Host smart-bbf9b5f7-718a-4142-8fe5-b9798eb3620c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32681
05827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3268105827
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3958551188
Short name T1350
Test name
Test status
Simulation time 219703697 ps
CPU time 0.88 seconds
Started Jun 11 12:43:33 PM PDT 24
Finished Jun 11 12:43:35 PM PDT 24
Peak memory 204728 kb
Host smart-53406d7d-f306-4b45-a224-0a4ead7dbb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
51188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3958551188
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2230750352
Short name T1886
Test name
Test status
Simulation time 163411958 ps
CPU time 0.8 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:31 PM PDT 24
Peak memory 204648 kb
Host smart-a7c83246-35f7-4bd8-b152-cd83bfbaddd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22307
50352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2230750352
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2829118110
Short name T1882
Test name
Test status
Simulation time 244337574 ps
CPU time 0.86 seconds
Started Jun 11 12:43:35 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204740 kb
Host smart-60e7f4f3-6401-499d-a6a1-9e3b00418b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28291
18110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2829118110
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3802180767
Short name T1434
Test name
Test status
Simulation time 190529697 ps
CPU time 0.84 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204744 kb
Host smart-ef0d9436-f989-40c4-97b4-91b32e1b3f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
80767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3802180767
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3421293743
Short name T929
Test name
Test status
Simulation time 3320688700 ps
CPU time 4.59 seconds
Started Jun 11 12:43:31 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204752 kb
Host smart-551e546c-0528-45b9-b3a8-b2b1ac98076d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34212
93743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3421293743
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3227538733
Short name T727
Test name
Test status
Simulation time 237035587 ps
CPU time 0.99 seconds
Started Jun 11 12:43:29 PM PDT 24
Finished Jun 11 12:43:31 PM PDT 24
Peak memory 204760 kb
Host smart-86e89db4-1e0f-4bdd-8011-c3b13cd3f9a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3227538733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3227538733
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3125704015
Short name T832
Test name
Test status
Simulation time 206467103 ps
CPU time 0.86 seconds
Started Jun 11 12:43:39 PM PDT 24
Finished Jun 11 12:43:42 PM PDT 24
Peak memory 204728 kb
Host smart-69fe3b32-9513-4a96-980d-970f1ecb5a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31257
04015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3125704015
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1763780609
Short name T2014
Test name
Test status
Simulation time 13742698044 ps
CPU time 123.09 seconds
Started Jun 11 12:43:30 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 205036 kb
Host smart-cf1e59f2-3b0a-4003-a591-2ff903467a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
80609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1763780609
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1046546809
Short name T1468
Test name
Test status
Simulation time 150708066 ps
CPU time 0.86 seconds
Started Jun 11 12:43:20 PM PDT 24
Finished Jun 11 12:43:22 PM PDT 24
Peak memory 204780 kb
Host smart-de0c673b-71f5-485f-98d1-1e2b10c74dc7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1046546809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1046546809
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.786006680
Short name T829
Test name
Test status
Simulation time 169010828 ps
CPU time 0.83 seconds
Started Jun 11 12:43:17 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204652 kb
Host smart-b29250c6-24ad-4f2a-8c4b-bf9be42dbfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78600
6680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.786006680
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1731824066
Short name T148
Test name
Test status
Simulation time 218557808 ps
CPU time 0.91 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204744 kb
Host smart-caff24fc-17e5-49e2-9c9c-a9beff1ec8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
24066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1731824066
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1408706317
Short name T1231
Test name
Test status
Simulation time 160494289 ps
CPU time 0.82 seconds
Started Jun 11 12:43:18 PM PDT 24
Finished Jun 11 12:43:20 PM PDT 24
Peak memory 204700 kb
Host smart-de03e89e-5071-4ca0-b0aa-4324605257e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
06317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1408706317
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2578172099
Short name T645
Test name
Test status
Simulation time 182750547 ps
CPU time 0.8 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204636 kb
Host smart-d5bb4b38-67c8-4a16-ac20-d34c432a0f3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25781
72099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2578172099
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3567040592
Short name T811
Test name
Test status
Simulation time 189975272 ps
CPU time 0.84 seconds
Started Jun 11 12:43:22 PM PDT 24
Finished Jun 11 12:43:24 PM PDT 24
Peak memory 204716 kb
Host smart-b76abf66-c791-4c4d-8bd9-d986de22f8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35670
40592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3567040592
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2696188528
Short name T187
Test name
Test status
Simulation time 149024346 ps
CPU time 0.81 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204640 kb
Host smart-24a22e32-ac0c-444a-8b24-92d8b803d646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
88528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2696188528
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_eop_single_bit_handling.1712297343
Short name T1871
Test name
Test status
Simulation time 146619054 ps
CPU time 0.81 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204720 kb
Host smart-0cffc181-68f3-417d-bd96-1bf789e5fb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17122
97343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_eop_single_bit_handling.1712297343
Directory /workspace/34.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.948950772
Short name T108
Test name
Test status
Simulation time 144021360 ps
CPU time 0.72 seconds
Started Jun 11 12:43:10 PM PDT 24
Finished Jun 11 12:43:12 PM PDT 24
Peak memory 204708 kb
Host smart-fb607b27-cb3d-4d60-91a9-3b4b59ea02cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94895
0772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.948950772
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2105501748
Short name T547
Test name
Test status
Simulation time 52224760 ps
CPU time 0.67 seconds
Started Jun 11 12:43:31 PM PDT 24
Finished Jun 11 12:43:33 PM PDT 24
Peak memory 204724 kb
Host smart-e3e1f809-f765-4d2e-9f8f-2e7acdc0fff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21055
01748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2105501748
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.4244489312
Short name T1949
Test name
Test status
Simulation time 21164306584 ps
CPU time 43.1 seconds
Started Jun 11 12:43:07 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204928 kb
Host smart-c60eef39-74fb-4e78-b6dc-ff2fe6daa369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42444
89312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.4244489312
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.200012522
Short name T915
Test name
Test status
Simulation time 146474015 ps
CPU time 0.75 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204748 kb
Host smart-1a4c5c97-0fa3-4632-91c2-f05adb102302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20001
2522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.200012522
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2639890870
Short name T1329
Test name
Test status
Simulation time 189788630 ps
CPU time 0.8 seconds
Started Jun 11 12:43:33 PM PDT 24
Finished Jun 11 12:43:35 PM PDT 24
Peak memory 204668 kb
Host smart-42785200-88e0-4917-be0f-91e9bef9cd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26398
90870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2639890870
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1773273168
Short name T1389
Test name
Test status
Simulation time 238683786 ps
CPU time 0.85 seconds
Started Jun 11 12:43:19 PM PDT 24
Finished Jun 11 12:43:21 PM PDT 24
Peak memory 204708 kb
Host smart-778c0145-d94e-44ef-9ecf-ed098dce31a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17732
73168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1773273168
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1575579106
Short name T1868
Test name
Test status
Simulation time 158264758 ps
CPU time 0.8 seconds
Started Jun 11 12:43:29 PM PDT 24
Finished Jun 11 12:43:30 PM PDT 24
Peak memory 204632 kb
Host smart-ee30ff1e-f36d-4ca0-b331-660e46453eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
79106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1575579106
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1021133123
Short name T69
Test name
Test status
Simulation time 140622090 ps
CPU time 0.75 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:36 PM PDT 24
Peak memory 204732 kb
Host smart-0b59db66-2785-49d7-9b8c-87a24213d106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211
33123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1021133123
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.662482007
Short name T1869
Test name
Test status
Simulation time 152758735 ps
CPU time 0.82 seconds
Started Jun 11 12:43:13 PM PDT 24
Finished Jun 11 12:43:15 PM PDT 24
Peak memory 204740 kb
Host smart-19c51fdb-9838-4d25-ba67-6d7fbebe4c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66248
2007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.662482007
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.4271568657
Short name T1381
Test name
Test status
Simulation time 160562554 ps
CPU time 0.78 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:34 PM PDT 24
Peak memory 204732 kb
Host smart-2a74181f-39f7-4891-b1fe-f22fd281c37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
68657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.4271568657
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1575516933
Short name T1939
Test name
Test status
Simulation time 230992356 ps
CPU time 0.95 seconds
Started Jun 11 12:43:17 PM PDT 24
Finished Jun 11 12:43:19 PM PDT 24
Peak memory 204600 kb
Host smart-9066a3a8-30a5-42b7-9ae3-a409b854c0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15755
16933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1575516933
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.4067699948
Short name T509
Test name
Test status
Simulation time 155523568 ps
CPU time 0.79 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:34 PM PDT 24
Peak memory 204720 kb
Host smart-e64d4a3d-24f2-4201-924a-3990f649cef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40676
99948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.4067699948
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.2888538996
Short name T768
Test name
Test status
Simulation time 173057249 ps
CPU time 0.78 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:44 PM PDT 24
Peak memory 204660 kb
Host smart-d31e2083-b215-4956-aa68-0dd345142586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28885
38996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.2888538996
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1097634549
Short name T1206
Test name
Test status
Simulation time 9479103422 ps
CPU time 260.3 seconds
Started Jun 11 12:43:29 PM PDT 24
Finished Jun 11 12:47:50 PM PDT 24
Peak memory 205004 kb
Host smart-f730e592-966f-4ebb-ba85-3bf076a4a440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10976
34549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1097634549
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2442996722
Short name T1702
Test name
Test status
Simulation time 3721276167 ps
CPU time 5.28 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 205308 kb
Host smart-f73551de-4534-4a6f-8c48-46f56901185d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2442996722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2442996722
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.4058504284
Short name T847
Test name
Test status
Simulation time 13321434431 ps
CPU time 15.01 seconds
Started Jun 11 12:43:31 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204808 kb
Host smart-b6d2b101-d5a4-48b1-bf6f-b17f4ca5fdcd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4058504284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.4058504284
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2997236354
Short name T1210
Test name
Test status
Simulation time 23309596432 ps
CPU time 25.39 seconds
Started Jun 11 12:43:31 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204788 kb
Host smart-8a409533-011e-4fc6-aa48-e78aaee4ab89
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2997236354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2997236354
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3262157844
Short name T1935
Test name
Test status
Simulation time 216563755 ps
CPU time 0.88 seconds
Started Jun 11 12:43:35 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204696 kb
Host smart-ffceae99-978d-45d8-bc7d-a342e4e89b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32621
57844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3262157844
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2518325541
Short name T62
Test name
Test status
Simulation time 188687791 ps
CPU time 0.87 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:36 PM PDT 24
Peak memory 204696 kb
Host smart-d27001a8-ec2f-4205-9e76-be8c324e5c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25183
25541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2518325541
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1081627556
Short name T215
Test name
Test status
Simulation time 1381392188 ps
CPU time 3.34 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204892 kb
Host smart-84356f6d-d604-49bd-9b0b-382abe8247ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10816
27556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1081627556
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3937448890
Short name T812
Test name
Test status
Simulation time 155214937 ps
CPU time 0.77 seconds
Started Jun 11 12:43:15 PM PDT 24
Finished Jun 11 12:43:17 PM PDT 24
Peak memory 204684 kb
Host smart-233e6fc6-cfe4-47c5-9803-8162c74d511d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
48890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3937448890
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1794039553
Short name T379
Test name
Test status
Simulation time 53066232 ps
CPU time 0.66 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204656 kb
Host smart-cfbc6eb7-d242-405c-9db8-56e59d70a6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17940
39553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1794039553
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.969554165
Short name T985
Test name
Test status
Simulation time 895794966 ps
CPU time 2.22 seconds
Started Jun 11 12:43:38 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 204936 kb
Host smart-574a15f2-cb10-473f-8a76-08429c5ab4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96955
4165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.969554165
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2278812757
Short name T2043
Test name
Test status
Simulation time 214094778 ps
CPU time 1.78 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204900 kb
Host smart-76a72424-8b26-41d3-ba4a-b62f25d1088d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
12757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2278812757
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.4032734288
Short name T961
Test name
Test status
Simulation time 230205895 ps
CPU time 0.83 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204628 kb
Host smart-1d7a792e-7ce3-49d8-b4a0-d8634687c254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40327
34288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.4032734288
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.422574298
Short name T2003
Test name
Test status
Simulation time 138584144 ps
CPU time 0.72 seconds
Started Jun 11 12:43:27 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204748 kb
Host smart-1e6a3274-892c-44cd-896f-eb43cad4f95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42257
4298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.422574298
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.3271123230
Short name T667
Test name
Test status
Simulation time 185867843 ps
CPU time 0.83 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204692 kb
Host smart-c8aeefe4-afc6-4f19-817d-e09ad245f4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32711
23230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.3271123230
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2475498785
Short name T457
Test name
Test status
Simulation time 228267266 ps
CPU time 0.85 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204728 kb
Host smart-df73618e-7409-411c-a407-16b6ca9d2d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
98785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2475498785
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.659432920
Short name T594
Test name
Test status
Simulation time 3336176343 ps
CPU time 4.96 seconds
Started Jun 11 12:43:31 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204808 kb
Host smart-79238198-9799-4a5f-8783-03466b926307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65943
2920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.659432920
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2356816697
Short name T1853
Test name
Test status
Simulation time 233805254 ps
CPU time 0.85 seconds
Started Jun 11 12:43:28 PM PDT 24
Finished Jun 11 12:43:30 PM PDT 24
Peak memory 204724 kb
Host smart-67a7a261-ed5f-4e2f-839d-086912480e2b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2356816697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2356816697
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.748619405
Short name T478
Test name
Test status
Simulation time 192209096 ps
CPU time 0.9 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:28 PM PDT 24
Peak memory 204752 kb
Host smart-ab4d999c-6be2-4d8c-838f-977a3832b704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74861
9405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.748619405
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.3100600730
Short name T844
Test name
Test status
Simulation time 12958168706 ps
CPU time 121.9 seconds
Started Jun 11 12:43:12 PM PDT 24
Finished Jun 11 12:45:15 PM PDT 24
Peak memory 204940 kb
Host smart-8e5b8e21-537f-4fff-b9c1-d59d1587f94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006
00730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.3100600730
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1164734713
Short name T2054
Test name
Test status
Simulation time 153192228 ps
CPU time 0.8 seconds
Started Jun 11 12:43:25 PM PDT 24
Finished Jun 11 12:43:27 PM PDT 24
Peak memory 204680 kb
Host smart-1c5f480a-aeeb-434c-8036-b32c12c1b061
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1164734713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1164734713
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1143096277
Short name T34
Test name
Test status
Simulation time 145231679 ps
CPU time 0.77 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204716 kb
Host smart-ef6f96ef-6743-47d3-b209-6311c46d0e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11430
96277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1143096277
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2929694121
Short name T151
Test name
Test status
Simulation time 174364218 ps
CPU time 0.82 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:34 PM PDT 24
Peak memory 204696 kb
Host smart-c2e7450c-55bf-4acf-bfab-38f5b7d3310e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29296
94121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2929694121
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1084307051
Short name T863
Test name
Test status
Simulation time 154496369 ps
CPU time 0.84 seconds
Started Jun 11 12:43:24 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 204700 kb
Host smart-ce703b81-0c96-4088-a14a-73ac3a586fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
07051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1084307051
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.984883873
Short name T1746
Test name
Test status
Simulation time 192467432 ps
CPU time 0.84 seconds
Started Jun 11 12:43:21 PM PDT 24
Finished Jun 11 12:43:23 PM PDT 24
Peak memory 204688 kb
Host smart-251a52b6-6073-4f49-a568-464f67f886e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98488
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.984883873
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3643685852
Short name T1223
Test name
Test status
Simulation time 173985765 ps
CPU time 0.81 seconds
Started Jun 11 12:43:30 PM PDT 24
Finished Jun 11 12:43:32 PM PDT 24
Peak memory 204704 kb
Host smart-65ebe5a0-492f-4da0-bbf1-a6bee2d1e922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
85852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3643685852
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3180657200
Short name T199
Test name
Test status
Simulation time 170981800 ps
CPU time 0.78 seconds
Started Jun 11 12:43:40 PM PDT 24
Finished Jun 11 12:43:42 PM PDT 24
Peak memory 204712 kb
Host smart-3c44cf05-c521-4b2e-a9db-ca61e0e98321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806
57200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3180657200
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_eop_single_bit_handling.44357527
Short name T94
Test name
Test status
Simulation time 152195768 ps
CPU time 0.79 seconds
Started Jun 11 12:44:01 PM PDT 24
Finished Jun 11 12:44:04 PM PDT 24
Peak memory 204672 kb
Host smart-5b2f22af-98db-4bcf-a1fe-8ae698c47d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44357
527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_eop_single_bit_handling.44357527
Directory /workspace/35.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1934662273
Short name T984
Test name
Test status
Simulation time 152834188 ps
CPU time 0.73 seconds
Started Jun 11 12:43:41 PM PDT 24
Finished Jun 11 12:43:43 PM PDT 24
Peak memory 204720 kb
Host smart-c1b80cc7-de92-48c1-8f5a-9f606186fe9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19346
62273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1934662273
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2184270413
Short name T632
Test name
Test status
Simulation time 46132391 ps
CPU time 0.67 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:36 PM PDT 24
Peak memory 204708 kb
Host smart-49ded0c4-bfff-46e0-8734-9a06175e4dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21842
70413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2184270413
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.973545806
Short name T438
Test name
Test status
Simulation time 10179200302 ps
CPU time 22.11 seconds
Started Jun 11 12:43:36 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204932 kb
Host smart-66290044-8a09-48d7-9946-07a012b78bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97354
5806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.973545806
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.80998156
Short name T56
Test name
Test status
Simulation time 174169565 ps
CPU time 0.85 seconds
Started Jun 11 12:43:41 PM PDT 24
Finished Jun 11 12:43:44 PM PDT 24
Peak memory 204760 kb
Host smart-49cbc196-3084-443b-b2bb-f48b366cc173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80998
156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.80998156
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4262473585
Short name T1768
Test name
Test status
Simulation time 203997835 ps
CPU time 0.89 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204688 kb
Host smart-5dfa32db-5e38-48b7-a8ad-89a04bc1c870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42624
73585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4262473585
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.167159216
Short name T1499
Test name
Test status
Simulation time 240808880 ps
CPU time 0.91 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204640 kb
Host smart-0c4f6038-e493-4b84-b356-bdb61c86f172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16715
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.167159216
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1362640991
Short name T908
Test name
Test status
Simulation time 188960887 ps
CPU time 0.85 seconds
Started Jun 11 12:43:35 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204692 kb
Host smart-cbd224de-5693-4016-b840-325987b810e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
40991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1362640991
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.996413287
Short name T1226
Test name
Test status
Simulation time 177577829 ps
CPU time 0.83 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:52 PM PDT 24
Peak memory 204720 kb
Host smart-5552a754-b082-4bdb-af6e-bd3765210a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99641
3287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.996413287
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.433302081
Short name T783
Test name
Test status
Simulation time 166189239 ps
CPU time 0.79 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204696 kb
Host smart-2d3b65ed-40b8-4f8e-9b0d-712fcd695511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43330
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.433302081
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.4157509888
Short name T432
Test name
Test status
Simulation time 158490684 ps
CPU time 0.78 seconds
Started Jun 11 12:43:41 PM PDT 24
Finished Jun 11 12:43:43 PM PDT 24
Peak memory 204676 kb
Host smart-4c846cc6-b9bf-438a-9036-d1f9be369891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
09888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.4157509888
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3808607141
Short name T1432
Test name
Test status
Simulation time 237486759 ps
CPU time 0.93 seconds
Started Jun 11 12:43:27 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 204700 kb
Host smart-199242fa-7df6-49bd-aca7-b9f662526908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38086
07141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3808607141
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.469245628
Short name T1693
Test name
Test status
Simulation time 189301285 ps
CPU time 0.83 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204744 kb
Host smart-fa61adba-f913-48e0-aa91-728239460797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46924
5628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.469245628
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3375053115
Short name T387
Test name
Test status
Simulation time 167095742 ps
CPU time 0.8 seconds
Started Jun 11 12:43:40 PM PDT 24
Finished Jun 11 12:43:42 PM PDT 24
Peak memory 204740 kb
Host smart-7e90c5b4-d16a-4beb-8f71-19b830a3bac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33750
53115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3375053115
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1927567655
Short name T1396
Test name
Test status
Simulation time 4860730149 ps
CPU time 37.12 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 205048 kb
Host smart-165cf800-9e6e-41c2-be06-95da28f77214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19275
67655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1927567655
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3963102142
Short name T1402
Test name
Test status
Simulation time 3696655122 ps
CPU time 4.75 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204820 kb
Host smart-8f5681bd-536c-4a6c-a759-ac8527d12638
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3963102142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3963102142
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1946792824
Short name T11
Test name
Test status
Simulation time 13332126112 ps
CPU time 12.65 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:48 PM PDT 24
Peak memory 204828 kb
Host smart-27688b64-0d2f-4210-b3c3-88b0a7841073
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1946792824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1946792824
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2860898750
Short name T1764
Test name
Test status
Simulation time 23387393681 ps
CPU time 25.55 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 205048 kb
Host smart-9306771d-2f3f-4c13-951a-128f5ea09db4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2860898750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.2860898750
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2904418098
Short name T488
Test name
Test status
Simulation time 151518434 ps
CPU time 0.78 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:36 PM PDT 24
Peak memory 204712 kb
Host smart-35b8435b-d64b-4a1c-b23f-070dfe12a841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044
18098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2904418098
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.718080698
Short name T1774
Test name
Test status
Simulation time 199938008 ps
CPU time 0.82 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204776 kb
Host smart-1dace7b5-4731-48af-9cb3-617b91dffd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71808
0698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.718080698
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3315789124
Short name T213
Test name
Test status
Simulation time 600168754 ps
CPU time 1.51 seconds
Started Jun 11 12:43:33 PM PDT 24
Finished Jun 11 12:43:36 PM PDT 24
Peak memory 204732 kb
Host smart-bc31eb5e-e9c3-4a05-9c1b-96843a8fbeff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33157
89124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3315789124
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.3762510538
Short name T809
Test name
Test status
Simulation time 136165464 ps
CPU time 0.8 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:34 PM PDT 24
Peak memory 204692 kb
Host smart-f6c9811a-8384-4e24-b0fc-e79b49694725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37625
10538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3762510538
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3649954533
Short name T1731
Test name
Test status
Simulation time 42290740 ps
CPU time 0.65 seconds
Started Jun 11 12:43:44 PM PDT 24
Finished Jun 11 12:43:46 PM PDT 24
Peak memory 204636 kb
Host smart-8a9a3407-f4cb-434a-9a23-274f487da52c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36499
54533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3649954533
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.23677062
Short name T602
Test name
Test status
Simulation time 895374468 ps
CPU time 2.08 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204868 kb
Host smart-264118ef-4b29-4fdc-9a8b-176e2c2f4f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23677
062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.23677062
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1875038353
Short name T1956
Test name
Test status
Simulation time 310218245 ps
CPU time 2.1 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:35 PM PDT 24
Peak memory 204940 kb
Host smart-71bae3e5-f6a9-47e1-8967-1b3123911dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
38353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1875038353
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3480727201
Short name T1061
Test name
Test status
Simulation time 239432818 ps
CPU time 0.91 seconds
Started Jun 11 12:43:37 PM PDT 24
Finished Jun 11 12:43:40 PM PDT 24
Peak memory 204728 kb
Host smart-4d20626f-6046-43a5-b379-85ce46dff503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34807
27201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3480727201
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.344876143
Short name T1701
Test name
Test status
Simulation time 141942509 ps
CPU time 0.73 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204756 kb
Host smart-0727cf73-bb89-40e5-9a07-8f06e118d45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34487
6143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.344876143
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1822578895
Short name T975
Test name
Test status
Simulation time 209337304 ps
CPU time 0.88 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204572 kb
Host smart-751fa562-6b5a-4717-b948-55028c867826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225
78895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1822578895
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2873785313
Short name T1426
Test name
Test status
Simulation time 179363802 ps
CPU time 0.81 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:35 PM PDT 24
Peak memory 204672 kb
Host smart-190eb725-2d09-4162-bb7f-51639f084a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28737
85313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2873785313
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1195856516
Short name T48
Test name
Test status
Simulation time 3291027625 ps
CPU time 4.01 seconds
Started Jun 11 12:43:40 PM PDT 24
Finished Jun 11 12:43:46 PM PDT 24
Peak memory 204808 kb
Host smart-575f9ea1-6c0e-4485-8b3e-e5d8b316ab12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11958
56516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1195856516
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2997869316
Short name T2050
Test name
Test status
Simulation time 255515661 ps
CPU time 0.94 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204976 kb
Host smart-4bf49d1d-236f-479f-b359-9b2529b03230
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2997869316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2997869316
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.168081335
Short name T1038
Test name
Test status
Simulation time 201030139 ps
CPU time 0.86 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204712 kb
Host smart-c010fdbb-27d8-4418-8b56-3d40b9e1e2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
1335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.168081335
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1687759318
Short name T861
Test name
Test status
Simulation time 14805464120 ps
CPU time 394.65 seconds
Started Jun 11 12:43:39 PM PDT 24
Finished Jun 11 12:50:15 PM PDT 24
Peak memory 204956 kb
Host smart-982c8db3-24b3-48b4-8289-190c98dcc40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16877
59318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1687759318
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.2758978771
Short name T128
Test name
Test status
Simulation time 161589593 ps
CPU time 0.76 seconds
Started Jun 11 12:43:44 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204656 kb
Host smart-a6610c77-0f5f-4a75-9311-b57cce308f1e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2758978771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.2758978771
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3567133434
Short name T1040
Test name
Test status
Simulation time 141381497 ps
CPU time 0.8 seconds
Started Jun 11 12:43:38 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 204644 kb
Host smart-caaab2dd-974c-49d8-bb3a-65c551442c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35671
33434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3567133434
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3323832787
Short name T1481
Test name
Test status
Simulation time 163232005 ps
CPU time 0.82 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204600 kb
Host smart-ec1b1acf-3691-4ae2-85b0-12ec39e6ba56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238
32787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3323832787
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1149147365
Short name T99
Test name
Test status
Simulation time 176103661 ps
CPU time 0.86 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204764 kb
Host smart-36b22399-4e43-43d9-bf7e-e2b34b1f469f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11491
47365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1149147365
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3940280649
Short name T1466
Test name
Test status
Simulation time 169338048 ps
CPU time 0.78 seconds
Started Jun 11 12:43:27 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 204752 kb
Host smart-0fccad0c-e8e8-4a76-b49d-a416198c1a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39402
80649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3940280649
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1185450383
Short name T1441
Test name
Test status
Simulation time 163676859 ps
CPU time 0.83 seconds
Started Jun 11 12:43:36 PM PDT 24
Finished Jun 11 12:43:38 PM PDT 24
Peak memory 204656 kb
Host smart-c5781f99-e43c-4b06-8a1b-43882c8a7695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11854
50383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1185450383
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_eop_single_bit_handling.545572832
Short name T304
Test name
Test status
Simulation time 179387483 ps
CPU time 0.86 seconds
Started Jun 11 12:43:37 PM PDT 24
Finished Jun 11 12:43:39 PM PDT 24
Peak memory 204656 kb
Host smart-4bc19992-f997-4b0c-ba61-e0979f9ed7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54557
2832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_eop_single_bit_handling.545572832
Directory /workspace/36.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.4139669893
Short name T1042
Test name
Test status
Simulation time 234881435 ps
CPU time 0.81 seconds
Started Jun 11 12:43:33 PM PDT 24
Finished Jun 11 12:43:35 PM PDT 24
Peak memory 204704 kb
Host smart-260e9baf-a9a4-4d38-9dad-861d9f7df802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41396
69893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.4139669893
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.524920983
Short name T1060
Test name
Test status
Simulation time 37914294 ps
CPU time 0.62 seconds
Started Jun 11 12:43:27 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 204728 kb
Host smart-af43930d-1e8b-40db-a40c-4ef7518e600a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52492
0983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.524920983
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.866215614
Short name T1596
Test name
Test status
Simulation time 7722112470 ps
CPU time 17.65 seconds
Started Jun 11 12:43:32 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 205028 kb
Host smart-fcc057df-4be0-464c-8ff0-bf586a5f7941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86621
5614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.866215614
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.200696526
Short name T455
Test name
Test status
Simulation time 178608212 ps
CPU time 0.82 seconds
Started Jun 11 12:43:43 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204732 kb
Host smart-006d6a14-f0c9-4029-b2f2-49b9b510d525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20069
6526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.200696526
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1276037893
Short name T1472
Test name
Test status
Simulation time 202218746 ps
CPU time 0.85 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:48 PM PDT 24
Peak memory 204636 kb
Host smart-b08b8d43-bad3-40ac-8501-25950bce6ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12760
37893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1276037893
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.155932850
Short name T566
Test name
Test status
Simulation time 187739130 ps
CPU time 0.84 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204656 kb
Host smart-7dea33bd-ab9c-4376-9e4a-846990d3fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15593
2850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.155932850
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2252231593
Short name T693
Test name
Test status
Simulation time 166184764 ps
CPU time 0.81 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 204712 kb
Host smart-0544f531-1c2e-4aea-88a2-bb54941fce30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
31593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2252231593
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2247230012
Short name T1159
Test name
Test status
Simulation time 140699441 ps
CPU time 0.79 seconds
Started Jun 11 12:43:39 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 204648 kb
Host smart-d0cd1c80-90df-4327-a725-ad3c581aa642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22472
30012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2247230012
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1927489892
Short name T1232
Test name
Test status
Simulation time 159040845 ps
CPU time 0.83 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204672 kb
Host smart-671067f8-eedc-4c38-96fa-bf3d7d14c953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
89892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1927489892
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2372010265
Short name T341
Test name
Test status
Simulation time 153885981 ps
CPU time 0.77 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204704 kb
Host smart-ebd1a995-ef82-4c1a-b4f9-3d6b6a7fc864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23720
10265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2372010265
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.897063699
Short name T1252
Test name
Test status
Simulation time 252641735 ps
CPU time 0.93 seconds
Started Jun 11 12:43:36 PM PDT 24
Finished Jun 11 12:43:38 PM PDT 24
Peak memory 204744 kb
Host smart-633caf59-0097-411f-84ad-bca3f43e555a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89706
3699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.897063699
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1973992768
Short name T1280
Test name
Test status
Simulation time 211195237 ps
CPU time 0.85 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:44 PM PDT 24
Peak memory 204576 kb
Host smart-5bb5203f-9b92-4568-8184-9f6a6ef854bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19739
92768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1973992768
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.941940302
Short name T1377
Test name
Test status
Simulation time 163437228 ps
CPU time 0.78 seconds
Started Jun 11 12:43:34 PM PDT 24
Finished Jun 11 12:43:36 PM PDT 24
Peak memory 204712 kb
Host smart-f7b81f50-883e-4ed0-88cd-6f433ad55e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94194
0302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.941940302
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1334050844
Short name T2097
Test name
Test status
Simulation time 12890260632 ps
CPU time 116.54 seconds
Started Jun 11 12:43:40 PM PDT 24
Finished Jun 11 12:45:38 PM PDT 24
Peak memory 204972 kb
Host smart-baf5a4d9-1533-4a3c-9911-9bd768153708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13340
50844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1334050844
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1037116447
Short name T1796
Test name
Test status
Simulation time 3533753165 ps
CPU time 4.09 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204788 kb
Host smart-0f6a62b0-6f31-488d-864d-81f4ea00a4fe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1037116447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1037116447
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.26300069
Short name T1332
Test name
Test status
Simulation time 13310109318 ps
CPU time 14.17 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:44:10 PM PDT 24
Peak memory 204792 kb
Host smart-47242d74-f2a9-43b0-ada7-452c13392f48
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=26300069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.26300069
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1118660383
Short name T1089
Test name
Test status
Simulation time 23385297034 ps
CPU time 23.96 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 205052 kb
Host smart-d9ee3f9a-e875-44d4-87cd-d97ceb9819c8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1118660383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1118660383
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2189664979
Short name T315
Test name
Test status
Simulation time 151307721 ps
CPU time 0.78 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204684 kb
Host smart-c4fff5c1-3fc5-44e3-9ce8-4a85bdd33a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21896
64979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2189664979
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1024233523
Short name T1293
Test name
Test status
Simulation time 215770816 ps
CPU time 0.8 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204632 kb
Host smart-fbfac165-1e86-43a3-ac57-72951ad99706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10242
33523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1024233523
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.547018347
Short name T333
Test name
Test status
Simulation time 307358508 ps
CPU time 0.97 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204696 kb
Host smart-809d98ba-008c-47fe-bfda-9a18de32df0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54701
8347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.547018347
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2194007017
Short name T1944
Test name
Test status
Simulation time 157828927 ps
CPU time 0.73 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204700 kb
Host smart-d339617a-f1fd-41ed-82b3-d8e35c749c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21940
07017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2194007017
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2292888259
Short name T1813
Test name
Test status
Simulation time 40735784 ps
CPU time 0.65 seconds
Started Jun 11 12:43:38 PM PDT 24
Finished Jun 11 12:43:41 PM PDT 24
Peak memory 204664 kb
Host smart-374e33e0-6df7-44bf-a3d3-1aff560115c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
88259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2292888259
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3624528239
Short name T450
Test name
Test status
Simulation time 716844978 ps
CPU time 1.8 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 205000 kb
Host smart-58b7e7c8-2dc4-409f-8618-e3405f97cad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245
28239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3624528239
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.4038009076
Short name T384
Test name
Test status
Simulation time 152980272 ps
CPU time 1.13 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204920 kb
Host smart-6a315e13-bbec-425e-b4a5-ef5d9745e6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40380
09076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.4038009076
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3843590082
Short name T1368
Test name
Test status
Simulation time 199829759 ps
CPU time 0.85 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:48 PM PDT 24
Peak memory 204704 kb
Host smart-bed5698e-1fc9-41a8-af50-8fc8cfa54202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38435
90082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3843590082
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1443774074
Short name T1294
Test name
Test status
Simulation time 135669345 ps
CPU time 0.73 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:48 PM PDT 24
Peak memory 204700 kb
Host smart-e614f8b6-a268-4c2f-9922-8f858cbe9f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14437
74074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1443774074
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3944654852
Short name T973
Test name
Test status
Simulation time 215181809 ps
CPU time 0.92 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204740 kb
Host smart-8ab65b8f-1979-44b0-8a3c-8a8b0fa6788d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
54852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3944654852
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3585812499
Short name T593
Test name
Test status
Simulation time 157289557 ps
CPU time 0.79 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204660 kb
Host smart-7cb34f67-6e6a-4d09-b804-1ac1a1b203ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35858
12499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3585812499
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.329164202
Short name T1427
Test name
Test status
Simulation time 3262177085 ps
CPU time 3.7 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204796 kb
Host smart-f03b5bad-a09a-42cd-9407-846d636c1ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32916
4202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.329164202
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.853973458
Short name T1292
Test name
Test status
Simulation time 254911639 ps
CPU time 0.96 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204636 kb
Host smart-e8e37f3a-4c81-4ae3-b18b-1347f741e24e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=853973458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.853973458
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1331032290
Short name T1015
Test name
Test status
Simulation time 240244256 ps
CPU time 0.86 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204644 kb
Host smart-bb1685d2-48e0-4be5-adff-2b99ba5de8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13310
32290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1331032290
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1429196127
Short name T807
Test name
Test status
Simulation time 12316811015 ps
CPU time 86.77 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 204928 kb
Host smart-88f56c64-f124-42a7-a923-27a4651e2f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14291
96127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1429196127
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1108613826
Short name T340
Test name
Test status
Simulation time 150429279 ps
CPU time 0.83 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204732 kb
Host smart-a66326e4-70b8-448b-b96f-63dd52198ee5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1108613826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1108613826
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.313694989
Short name T691
Test name
Test status
Simulation time 167519324 ps
CPU time 0.82 seconds
Started Jun 11 12:43:44 PM PDT 24
Finished Jun 11 12:43:46 PM PDT 24
Peak memory 204736 kb
Host smart-5db89c0a-75ba-4c10-ae87-0472b22b3959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
4989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.313694989
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4268600935
Short name T150
Test name
Test status
Simulation time 204152555 ps
CPU time 0.78 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204620 kb
Host smart-be58434e-a2f5-42d9-876b-25b42209506d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42686
00935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4268600935
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1750419650
Short name T1407
Test name
Test status
Simulation time 154623281 ps
CPU time 0.77 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204980 kb
Host smart-085ab4e6-0948-4ffc-9ce8-d626d6b5c4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504
19650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1750419650
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.252764494
Short name T1525
Test name
Test status
Simulation time 197799485 ps
CPU time 0.84 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204728 kb
Host smart-6817a67a-881d-4b58-9674-c27889250659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
4494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.252764494
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3089209675
Short name T383
Test name
Test status
Simulation time 196892180 ps
CPU time 0.84 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204568 kb
Host smart-399a05f8-8db5-43c6-88a4-aa32923fa3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30892
09675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3089209675
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3569301679
Short name T192
Test name
Test status
Simulation time 218317754 ps
CPU time 0.83 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204704 kb
Host smart-9c755966-9e1d-4696-a001-81406f72418e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35693
01679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3569301679
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_eop_single_bit_handling.3171474927
Short name T513
Test name
Test status
Simulation time 175734946 ps
CPU time 0.8 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204740 kb
Host smart-adea494d-5fcb-4b18-a84c-42bca67989f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31714
74927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_eop_single_bit_handling.3171474927
Directory /workspace/37.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2995686671
Short name T1792
Test name
Test status
Simulation time 163908458 ps
CPU time 0.77 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 205004 kb
Host smart-2028083e-e764-426a-b2f3-1c5c4d3c4a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29956
86671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2995686671
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1880635625
Short name T1154
Test name
Test status
Simulation time 34860019 ps
CPU time 0.64 seconds
Started Jun 11 12:44:03 PM PDT 24
Finished Jun 11 12:44:05 PM PDT 24
Peak memory 204716 kb
Host smart-4ab11ae1-d2ea-4021-bd10-0a82de2aaf42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18806
35625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1880635625
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.3242014538
Short name T1361
Test name
Test status
Simulation time 14460674228 ps
CPU time 34.44 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 204992 kb
Host smart-0ef9949d-2221-49f8-8b26-db6382223606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32420
14538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.3242014538
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2258674298
Short name T1773
Test name
Test status
Simulation time 201903843 ps
CPU time 0.85 seconds
Started Jun 11 12:43:41 PM PDT 24
Finished Jun 11 12:43:44 PM PDT 24
Peak memory 204744 kb
Host smart-2dbb642b-6a9f-4f55-9c5d-558d8c62a25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
74298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2258674298
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1019821002
Short name T605
Test name
Test status
Simulation time 208198753 ps
CPU time 0.84 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204640 kb
Host smart-a9e14637-c749-48d0-8ad1-6d9cfdd9ed2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10198
21002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1019821002
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2474325374
Short name T1538
Test name
Test status
Simulation time 258177916 ps
CPU time 0.93 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204708 kb
Host smart-bcb5a4ed-c262-4607-865f-e36a99900a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
25374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2474325374
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2706042152
Short name T1697
Test name
Test status
Simulation time 158859531 ps
CPU time 0.8 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204972 kb
Host smart-98880f74-db68-4bc7-869c-5a765a602f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27060
42152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2706042152
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2042207701
Short name T2046
Test name
Test status
Simulation time 156441664 ps
CPU time 0.73 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204684 kb
Host smart-af1cba9b-c194-4e79-8e2e-1af895faa9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20422
07701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2042207701
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1381814651
Short name T1093
Test name
Test status
Simulation time 165619451 ps
CPU time 0.74 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204684 kb
Host smart-fca29ab6-3724-488d-b287-a58a389a1daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818
14651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1381814651
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1396850313
Short name T1915
Test name
Test status
Simulation time 155522446 ps
CPU time 0.82 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204696 kb
Host smart-d1c43cd6-2b0b-4385-95f2-6c0761290c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968
50313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1396850313
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2539561401
Short name T766
Test name
Test status
Simulation time 209636757 ps
CPU time 0.91 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 205016 kb
Host smart-c7e06d36-53d4-4eb4-93eb-6d1126b95394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25395
61401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2539561401
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2884717265
Short name T823
Test name
Test status
Simulation time 245559531 ps
CPU time 0.83 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204680 kb
Host smart-952155a6-6efc-40aa-9aec-de314adb32d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28847
17265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2884717265
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3075223979
Short name T940
Test name
Test status
Simulation time 175507242 ps
CPU time 0.82 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204688 kb
Host smart-a30c96a8-9085-420d-bb3c-92e016d59045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
23979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3075223979
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2371283144
Short name T523
Test name
Test status
Simulation time 7452106446 ps
CPU time 68.75 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:45:08 PM PDT 24
Peak memory 205256 kb
Host smart-9c34b62a-be4d-45ff-9562-597fd759ea9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23712
83144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2371283144
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3576236753
Short name T1049
Test name
Test status
Simulation time 4182601151 ps
CPU time 4.95 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204972 kb
Host smart-ca37c638-7b17-49c1-bdb4-24ac02a5e3b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3576236753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3576236753
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3835093442
Short name T1607
Test name
Test status
Simulation time 13370472742 ps
CPU time 12.53 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204980 kb
Host smart-8ee68b31-2650-40f7-97a5-6667eb5cc392
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3835093442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3835093442
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1378856058
Short name T1959
Test name
Test status
Simulation time 23473779885 ps
CPU time 23.68 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 205044 kb
Host smart-9a861a97-04c4-4f98-a1c9-8f748e07e588
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1378856058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1378856058
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.3242976857
Short name T1789
Test name
Test status
Simulation time 169390991 ps
CPU time 0.82 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 204724 kb
Host smart-9319eff7-8585-4f05-9a85-ea5d7a882c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
76857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3242976857
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3478043353
Short name T1948
Test name
Test status
Simulation time 158453540 ps
CPU time 0.79 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204696 kb
Host smart-ecf5c23e-0107-4bf4-b732-5b25a9acf164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780
43353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3478043353
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.1993672347
Short name T677
Test name
Test status
Simulation time 399842835 ps
CPU time 1.13 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:18 PM PDT 24
Peak memory 204720 kb
Host smart-a09f1bc5-78f9-4894-9f81-ac80d875b2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19936
72347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.1993672347
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2660568345
Short name T636
Test name
Test status
Simulation time 218978081 ps
CPU time 0.78 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204628 kb
Host smart-5c549a2c-71a4-4a1b-8b12-3b6c8dbf00c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26605
68345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2660568345
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.4102849918
Short name T2032
Test name
Test status
Simulation time 106770552 ps
CPU time 0.69 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204672 kb
Host smart-a3255cb2-71fb-4657-a8cd-c1c48bce105f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41028
49918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4102849918
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2562233869
Short name T319
Test name
Test status
Simulation time 858530007 ps
CPU time 1.96 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204936 kb
Host smart-a1e5be54-0678-4838-a1d7-22d06f9b6f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25622
33869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2562233869
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.1039812755
Short name T820
Test name
Test status
Simulation time 246832708 ps
CPU time 1.67 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204880 kb
Host smart-bbd70c6f-5914-4ee4-9d4e-fc5acfcbb1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
12755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.1039812755
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3477177128
Short name T453
Test name
Test status
Simulation time 214800944 ps
CPU time 0.94 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204620 kb
Host smart-a5f30c8a-5de3-4f29-99f7-c889ed4b0b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34771
77128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3477177128
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2261008171
Short name T1044
Test name
Test status
Simulation time 149898520 ps
CPU time 0.75 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204708 kb
Host smart-3018cbac-160f-4419-abf4-8000ff14dce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22610
08171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2261008171
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1089444891
Short name T1632
Test name
Test status
Simulation time 198635671 ps
CPU time 0.82 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204684 kb
Host smart-0595ac83-2bc5-4856-918d-fb86858bdedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
44891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1089444891
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3221833204
Short name T1086
Test name
Test status
Simulation time 236025695 ps
CPU time 0.94 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:48 PM PDT 24
Peak memory 204696 kb
Host smart-ac729695-8854-4b9c-8687-af902d12b0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218
33204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3221833204
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2924444988
Short name T1690
Test name
Test status
Simulation time 3283135916 ps
CPU time 4.53 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204692 kb
Host smart-a1371d4f-d598-42c7-ad23-2a3edd2f1954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244
44988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2924444988
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2409707376
Short name T131
Test name
Test status
Simulation time 245638482 ps
CPU time 0.92 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204668 kb
Host smart-790b819b-9c51-4d28-9555-8f1bef8d5407
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2409707376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2409707376
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2053398506
Short name T1961
Test name
Test status
Simulation time 183315506 ps
CPU time 0.83 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204724 kb
Host smart-d113985c-1af9-4a98-8104-d242888bab99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20533
98506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2053398506
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.915456979
Short name T1424
Test name
Test status
Simulation time 9271456375 ps
CPU time 255.44 seconds
Started Jun 11 12:44:09 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 204952 kb
Host smart-bc0e57c5-d647-4b6d-8c4a-48da281f4e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91545
6979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.915456979
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1052612298
Short name T595
Test name
Test status
Simulation time 160256733 ps
CPU time 0.82 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204724 kb
Host smart-1800a732-c829-41a0-931e-714b9ce833ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1052612298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1052612298
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1462353992
Short name T1172
Test name
Test status
Simulation time 149695449 ps
CPU time 0.74 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204688 kb
Host smart-e40be6f5-f139-4217-9677-c699832f1f74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14623
53992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1462353992
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.490687575
Short name T1473
Test name
Test status
Simulation time 229871494 ps
CPU time 0.92 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204740 kb
Host smart-951bbe2c-7907-46ca-836e-93778a99cb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49068
7575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.490687575
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1988401447
Short name T572
Test name
Test status
Simulation time 166429293 ps
CPU time 0.8 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204728 kb
Host smart-20dd2ed3-cfe6-4c9b-948a-7a0d157cfd12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19884
01447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1988401447
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3145427094
Short name T1522
Test name
Test status
Simulation time 149717419 ps
CPU time 0.82 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 204764 kb
Host smart-e883f129-26e5-47ea-a66b-1022504febe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
27094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3145427094
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3025173039
Short name T299
Test name
Test status
Simulation time 176055471 ps
CPU time 0.81 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204744 kb
Host smart-846dfd08-2cc1-461a-9f26-81fa8ada2ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251
73039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3025173039
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.691208979
Short name T1009
Test name
Test status
Simulation time 151808274 ps
CPU time 0.77 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204740 kb
Host smart-f98169a6-9e77-4e80-9fbb-9463368eafdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69120
8979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.691208979
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_eop_single_bit_handling.3696534376
Short name T507
Test name
Test status
Simulation time 174286173 ps
CPU time 0.81 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204748 kb
Host smart-4ca2fe4c-67fb-4546-9658-09570f3c3818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36965
34376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_eop_single_bit_handling.3696534376
Directory /workspace/38.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3556314813
Short name T1625
Test name
Test status
Simulation time 143346253 ps
CPU time 0.82 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204652 kb
Host smart-8152fc98-4828-4785-89d2-35809c490728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35563
14813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3556314813
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1836820639
Short name T885
Test name
Test status
Simulation time 29133455 ps
CPU time 0.62 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 204660 kb
Host smart-9d2b8c55-35c2-422f-adf9-1ea62548f7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18368
20639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1836820639
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1701222793
Short name T1576
Test name
Test status
Simulation time 12057740638 ps
CPU time 28.76 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 205028 kb
Host smart-49059fe5-9af0-40b2-a010-a4fbd9d7796d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17012
22793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1701222793
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1521836646
Short name T1436
Test name
Test status
Simulation time 181582961 ps
CPU time 0.83 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204732 kb
Host smart-a26b8a8b-a6f9-43f8-92ac-4f6f8028e619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15218
36646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1521836646
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2322170114
Short name T540
Test name
Test status
Simulation time 163634146 ps
CPU time 0.76 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:44:05 PM PDT 24
Peak memory 204776 kb
Host smart-bad03e62-4051-4517-ab5c-3c2635078db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
70114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2322170114
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2068219197
Short name T1357
Test name
Test status
Simulation time 189775294 ps
CPU time 0.84 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204776 kb
Host smart-ebdfe561-a7fa-4965-bbc8-0ea44c2211b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20682
19197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2068219197
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3221653643
Short name T355
Test name
Test status
Simulation time 167097409 ps
CPU time 0.8 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204740 kb
Host smart-22f764fd-1ff5-4525-9cf0-ee76147e67b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
53643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3221653643
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1592445398
Short name T1247
Test name
Test status
Simulation time 150206982 ps
CPU time 0.75 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204688 kb
Host smart-2dc402c4-2fda-42c9-943f-7f1aed41f4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15924
45398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1592445398
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.667744381
Short name T1683
Test name
Test status
Simulation time 164379219 ps
CPU time 0.79 seconds
Started Jun 11 12:43:36 PM PDT 24
Finished Jun 11 12:43:37 PM PDT 24
Peak memory 204740 kb
Host smart-e02e8f8c-c19d-42ad-b6e5-614e02063b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66774
4381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.667744381
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.595848922
Short name T1046
Test name
Test status
Simulation time 149881236 ps
CPU time 0.81 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 205012 kb
Host smart-4b2a3071-2dc5-40ef-8ac5-b6a005bb319c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59584
8922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.595848922
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2083077915
Short name T1856
Test name
Test status
Simulation time 182125044 ps
CPU time 0.91 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204712 kb
Host smart-99ad15a9-b7a1-4c6b-88e3-bf093bb43a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20830
77915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2083077915
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.894406148
Short name T1406
Test name
Test status
Simulation time 179016286 ps
CPU time 0.8 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 204724 kb
Host smart-36c1e764-adea-4905-98e7-9f1f34cc517c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89440
6148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.894406148
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2360284345
Short name T710
Test name
Test status
Simulation time 175284737 ps
CPU time 0.81 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204688 kb
Host smart-646329bf-627d-4bdf-b705-7fdb4921c373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
84345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2360284345
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3094867035
Short name T2077
Test name
Test status
Simulation time 5133891991 ps
CPU time 142.24 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:46:17 PM PDT 24
Peak memory 204996 kb
Host smart-aa4920c1-38d4-4f79-ba67-70e01d56ae17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
67035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3094867035
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2885603045
Short name T1019
Test name
Test status
Simulation time 3869270250 ps
CPU time 4.77 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:51 PM PDT 24
Peak memory 204712 kb
Host smart-a8fec1c5-2838-4cf7-96a5-9b56ef2937f9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2885603045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2885603045
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1846830253
Short name T1218
Test name
Test status
Simulation time 13367021538 ps
CPU time 12.74 seconds
Started Jun 11 12:43:40 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204816 kb
Host smart-bf283531-516b-439f-b9bd-aba83b1f21f3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1846830253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1846830253
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1034750485
Short name T623
Test name
Test status
Simulation time 23356185736 ps
CPU time 23.7 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204984 kb
Host smart-dfaba7a2-c11e-4a5b-94e9-8802d9ab9373
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1034750485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1034750485
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2539236076
Short name T1748
Test name
Test status
Simulation time 185153677 ps
CPU time 0.81 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204720 kb
Host smart-759bff21-cb8e-4d0e-9c4f-13851bd10fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25392
36076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2539236076
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.85905527
Short name T1828
Test name
Test status
Simulation time 151805536 ps
CPU time 0.77 seconds
Started Jun 11 12:43:44 PM PDT 24
Finished Jun 11 12:43:46 PM PDT 24
Peak memory 204712 kb
Host smart-0f07d929-589d-441c-92ad-f81c1384aa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85905
527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.85905527
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1597623612
Short name T1744
Test name
Test status
Simulation time 808865232 ps
CPU time 2.18 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204944 kb
Host smart-27cdee89-c202-42b6-94b4-5a4d01c9490c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15976
23612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1597623612
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1758084914
Short name T959
Test name
Test status
Simulation time 152213664 ps
CPU time 0.83 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204716 kb
Host smart-24c387ae-fa5d-40e0-99ec-e292ddb1e78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17580
84914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1758084914
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.219047403
Short name T1272
Test name
Test status
Simulation time 93523773 ps
CPU time 0.68 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:48 PM PDT 24
Peak memory 204764 kb
Host smart-6f1748f5-d236-49ac-b14e-701643f46a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21904
7403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.219047403
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.4249045100
Short name T2100
Test name
Test status
Simulation time 729476992 ps
CPU time 1.9 seconds
Started Jun 11 12:43:46 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 205192 kb
Host smart-c78f9016-f520-4a0f-84a0-7c38265528d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42490
45100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.4249045100
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.177965760
Short name T1552
Test name
Test status
Simulation time 222330719 ps
CPU time 1.57 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204892 kb
Host smart-4f993623-3a36-43cc-937b-46d8efaf9743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
5760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.177965760
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2322361025
Short name T1207
Test name
Test status
Simulation time 194028309 ps
CPU time 0.87 seconds
Started Jun 11 12:43:58 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204684 kb
Host smart-8fd27b1c-70e8-4f3c-8552-3711c0da8bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
61025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2322361025
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2085181948
Short name T1989
Test name
Test status
Simulation time 166287504 ps
CPU time 0.75 seconds
Started Jun 11 12:44:05 PM PDT 24
Finished Jun 11 12:44:07 PM PDT 24
Peak memory 204732 kb
Host smart-687f297b-5f21-421d-a11b-387442acf056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20851
81948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2085181948
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3802368690
Short name T1896
Test name
Test status
Simulation time 271807995 ps
CPU time 0.95 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 204728 kb
Host smart-c97b4afd-c1a0-4c7a-94d3-5db461931a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38023
68690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3802368690
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.939809371
Short name T456
Test name
Test status
Simulation time 203538657 ps
CPU time 0.84 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204696 kb
Host smart-4cecc523-d44d-46b1-be67-058baee7f703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93980
9371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.939809371
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3151319968
Short name T410
Test name
Test status
Simulation time 3340733711 ps
CPU time 3.93 seconds
Started Jun 11 12:43:48 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204748 kb
Host smart-675143cc-9a67-4b5c-b021-474b173a86ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31513
19968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3151319968
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2735227879
Short name T1780
Test name
Test status
Simulation time 245341946 ps
CPU time 0.96 seconds
Started Jun 11 12:44:02 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204740 kb
Host smart-b5ebf92e-0123-40e1-ae47-cc1dc2db4b21
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2735227879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2735227879
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1593624367
Short name T676
Test name
Test status
Simulation time 197279924 ps
CPU time 0.84 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204656 kb
Host smart-bf4d000d-74e3-4d22-b1a8-ea426c508be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
24367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1593624367
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3046577054
Short name T1364
Test name
Test status
Simulation time 11329443556 ps
CPU time 99.37 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:45:30 PM PDT 24
Peak memory 204976 kb
Host smart-c3ff9b61-6548-4910-86b8-26a87fe95d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30465
77054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3046577054
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.348333808
Short name T646
Test name
Test status
Simulation time 152637623 ps
CPU time 0.77 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204712 kb
Host smart-82063df9-fc4a-4995-ac05-e9e3d60562fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=348333808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.348333808
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1195646885
Short name T882
Test name
Test status
Simulation time 153969111 ps
CPU time 0.8 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204740 kb
Host smart-e84e7c56-85b9-4730-a0d1-cfb3fd9ec0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11956
46885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1195646885
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1119721393
Short name T135
Test name
Test status
Simulation time 265334546 ps
CPU time 0.91 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204704 kb
Host smart-8827cfdb-e63b-45c0-ac74-d15ab6ecaade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197
21393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1119721393
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.549783305
Short name T1057
Test name
Test status
Simulation time 182388756 ps
CPU time 0.79 seconds
Started Jun 11 12:43:47 PM PDT 24
Finished Jun 11 12:43:49 PM PDT 24
Peak memory 204760 kb
Host smart-a5624371-024f-4ff7-8f96-4538a733666a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54978
3305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.549783305
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1028279954
Short name T1821
Test name
Test status
Simulation time 166000088 ps
CPU time 0.75 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204632 kb
Host smart-44d91b79-1e52-42bc-ad0f-67c59976f802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282
79954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1028279954
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3544871264
Short name T1073
Test name
Test status
Simulation time 189137847 ps
CPU time 0.82 seconds
Started Jun 11 12:43:42 PM PDT 24
Finished Jun 11 12:43:45 PM PDT 24
Peak memory 204668 kb
Host smart-dfb1b381-c1f0-42f3-ba2c-f6ca0178973f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35448
71264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3544871264
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.4225101538
Short name T2062
Test name
Test status
Simulation time 157072076 ps
CPU time 0.78 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204672 kb
Host smart-2b3e741a-c284-4815-84d1-bf4240397c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42251
01538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.4225101538
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_eop_single_bit_handling.2442206200
Short name T1047
Test name
Test status
Simulation time 216654091 ps
CPU time 0.87 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204756 kb
Host smart-92214acd-be96-417b-8f9a-8b2b8226cfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
06200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_eop_single_bit_handling.2442206200
Directory /workspace/39.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1516786436
Short name T1182
Test name
Test status
Simulation time 151128934 ps
CPU time 0.81 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204724 kb
Host smart-5b565a5a-4895-47de-8a46-e90c1a2bb0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
86436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1516786436
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1603031273
Short name T794
Test name
Test status
Simulation time 47325684 ps
CPU time 0.67 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204724 kb
Host smart-15c53590-73e1-4db8-a8ee-65cc5255324e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16030
31273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1603031273
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3320682898
Short name T1824
Test name
Test status
Simulation time 19448959866 ps
CPU time 43.09 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204948 kb
Host smart-09a76d47-73fd-4010-a424-3d4640efec56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33206
82898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3320682898
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1942355464
Short name T486
Test name
Test status
Simulation time 165567535 ps
CPU time 0.86 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204740 kb
Host smart-44e075af-f820-414d-8a40-6c50ecc3aed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
55464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1942355464
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2398161705
Short name T1941
Test name
Test status
Simulation time 253805564 ps
CPU time 0.87 seconds
Started Jun 11 12:44:02 PM PDT 24
Finished Jun 11 12:44:04 PM PDT 24
Peak memory 204776 kb
Host smart-41303c57-c6bf-43d5-889c-b1b935a7bc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23981
61705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2398161705
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3483293894
Short name T2035
Test name
Test status
Simulation time 319505814 ps
CPU time 0.94 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204672 kb
Host smart-e129446e-31c2-46ad-99ae-e1693d45c38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34832
93894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3483293894
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2076152091
Short name T1669
Test name
Test status
Simulation time 192662305 ps
CPU time 0.83 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204692 kb
Host smart-9fd88f1a-8d22-4958-a65c-3a333331aca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20761
52091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2076152091
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3053404018
Short name T1340
Test name
Test status
Simulation time 145316060 ps
CPU time 0.82 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204700 kb
Host smart-65aa1327-e76d-4577-93ec-6b6fc484b464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30534
04018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3053404018
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3028776536
Short name T859
Test name
Test status
Simulation time 144215151 ps
CPU time 0.82 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 205012 kb
Host smart-fa18cf8d-4736-4a0d-b2e7-2a86aead270e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30287
76536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3028776536
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.553332145
Short name T1228
Test name
Test status
Simulation time 168604966 ps
CPU time 0.79 seconds
Started Jun 11 12:44:01 PM PDT 24
Finished Jun 11 12:44:04 PM PDT 24
Peak memory 204776 kb
Host smart-29c5f400-e8a6-404a-a1aa-514cc3557282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55333
2145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.553332145
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3847782939
Short name T1981
Test name
Test status
Simulation time 246149749 ps
CPU time 0.96 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204572 kb
Host smart-dd080939-ca2c-4332-a892-59b02647eae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38477
82939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3847782939
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3290077392
Short name T2068
Test name
Test status
Simulation time 203056165 ps
CPU time 0.86 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:54 PM PDT 24
Peak memory 204992 kb
Host smart-f93e09bf-0e07-4877-b07c-d31f3d898f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32900
77392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3290077392
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.2769811358
Short name T325
Test name
Test status
Simulation time 155269001 ps
CPU time 0.77 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 204656 kb
Host smart-e4175583-8cc2-4f51-b9e7-bfe750324b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27698
11358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.2769811358
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.986789760
Short name T684
Test name
Test status
Simulation time 12437699455 ps
CPU time 88.18 seconds
Started Jun 11 12:44:10 PM PDT 24
Finished Jun 11 12:45:39 PM PDT 24
Peak memory 204900 kb
Host smart-1e158739-5eed-4a26-8f82-5ecf5fc0292a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98678
9760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.986789760
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.163414154
Short name T431
Test name
Test status
Simulation time 4222647403 ps
CPU time 5.82 seconds
Started Jun 11 12:40:23 PM PDT 24
Finished Jun 11 12:40:31 PM PDT 24
Peak memory 204788 kb
Host smart-bb0525f1-eeaf-4b36-beeb-ca8ff539899e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=163414154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.163414154
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.560276175
Short name T9
Test name
Test status
Simulation time 13407997775 ps
CPU time 13.47 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:34 PM PDT 24
Peak memory 205024 kb
Host smart-29445722-3e0c-40bd-8d20-b19eff369e2a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=560276175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.560276175
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3882945608
Short name T1627
Test name
Test status
Simulation time 23327402707 ps
CPU time 23.12 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:44 PM PDT 24
Peak memory 204680 kb
Host smart-494cb441-fe4e-4809-a9f3-571f3ba62f4a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3882945608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3882945608
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1547504305
Short name T302
Test name
Test status
Simulation time 173290862 ps
CPU time 0.76 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:26 PM PDT 24
Peak memory 204708 kb
Host smart-e7760c6d-c739-4b99-b2f7-47a7d81c387c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
04305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1547504305
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2056514832
Short name T219
Test name
Test status
Simulation time 166302142 ps
CPU time 0.8 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:18 PM PDT 24
Peak memory 204740 kb
Host smart-0e0f5d25-b620-4ce0-a430-97f748ed19cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
14832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2056514832
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2441253520
Short name T205
Test name
Test status
Simulation time 912816762 ps
CPU time 2.24 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204948 kb
Host smart-fba5e8b0-82c8-42a2-8cd8-aa58b89df7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24412
53520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2441253520
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3069774707
Short name T620
Test name
Test status
Simulation time 131106113 ps
CPU time 0.71 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 204708 kb
Host smart-19b9f93a-ae4b-4d3f-b330-2ea735f17aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30697
74707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3069774707
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3096044309
Short name T619
Test name
Test status
Simulation time 37125576 ps
CPU time 0.66 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204644 kb
Host smart-4704e648-aaee-45fe-86cb-b453ea8fcd8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30960
44309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3096044309
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2908937543
Short name T951
Test name
Test status
Simulation time 1011586520 ps
CPU time 2.29 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204872 kb
Host smart-974fc281-6d7e-4ea2-9767-7b975bd47b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29089
37543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2908937543
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1527783917
Short name T19
Test name
Test status
Simulation time 337531507 ps
CPU time 1.86 seconds
Started Jun 11 12:40:22 PM PDT 24
Finished Jun 11 12:40:26 PM PDT 24
Peak memory 204912 kb
Host smart-c0300b89-7d67-45ab-9cb5-eb5c2c3577fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15277
83917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1527783917
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3274359055
Short name T1257
Test name
Test status
Simulation time 230174986 ps
CPU time 0.85 seconds
Started Jun 11 12:40:28 PM PDT 24
Finished Jun 11 12:40:30 PM PDT 24
Peak memory 204636 kb
Host smart-2edf929f-143a-4a17-a82b-90ffed0c2110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32743
59055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3274359055
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.371811639
Short name T1610
Test name
Test status
Simulation time 146095845 ps
CPU time 0.72 seconds
Started Jun 11 12:40:32 PM PDT 24
Finished Jun 11 12:40:33 PM PDT 24
Peak memory 204752 kb
Host smart-93d738bc-db2b-4dab-91b1-a0cf0c786857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37181
1639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.371811639
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3196512732
Short name T1171
Test name
Test status
Simulation time 247326614 ps
CPU time 0.95 seconds
Started Jun 11 12:40:15 PM PDT 24
Finished Jun 11 12:40:17 PM PDT 24
Peak memory 204756 kb
Host smart-8a80ae7d-eb87-4502-9e55-2b5b5bcbd10a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31965
12732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3196512732
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.159205312
Short name T1150
Test name
Test status
Simulation time 193456435 ps
CPU time 0.83 seconds
Started Jun 11 12:40:19 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204676 kb
Host smart-11b2710d-3f8a-434a-8e05-a675c30a98f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15920
5312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.159205312
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3554879473
Short name T1033
Test name
Test status
Simulation time 3306224706 ps
CPU time 3.91 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204836 kb
Host smart-b951d282-236e-4324-900d-8c44452ad0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35548
79473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3554879473
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1671749602
Short name T668
Test name
Test status
Simulation time 247896598 ps
CPU time 0.89 seconds
Started Jun 11 12:40:28 PM PDT 24
Finished Jun 11 12:40:30 PM PDT 24
Peak memory 204732 kb
Host smart-83997242-7226-4560-a825-d38485d4c77c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1671749602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1671749602
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.2014371939
Short name T1951
Test name
Test status
Simulation time 188188427 ps
CPU time 0.83 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204720 kb
Host smart-9cbf71cc-b94e-4b02-a225-096a143a980b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20143
71939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.2014371939
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.1989337485
Short name T402
Test name
Test status
Simulation time 10246956142 ps
CPU time 71.69 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:41:32 PM PDT 24
Peak memory 204984 kb
Host smart-d0f5834a-f7c6-4bae-8bd6-129be6b37be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893
37485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.1989337485
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.3886452263
Short name T2086
Test name
Test status
Simulation time 169653118 ps
CPU time 0.78 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204728 kb
Host smart-7d3e5486-e2fd-48b9-a79f-6e7334ba8b28
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3886452263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.3886452263
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1704092903
Short name T1035
Test name
Test status
Simulation time 144956222 ps
CPU time 0.74 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204752 kb
Host smart-8c0f303c-8b8d-4a7c-bb23-a68fa2393587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17040
92903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1704092903
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.765223635
Short name T168
Test name
Test status
Simulation time 287078638 ps
CPU time 0.92 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204704 kb
Host smart-66249fb7-e8bd-4e1f-88f5-1362ec637654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76522
3635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.765223635
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2767619370
Short name T2034
Test name
Test status
Simulation time 197217770 ps
CPU time 0.85 seconds
Started Jun 11 12:40:19 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204740 kb
Host smart-0fa42bad-533c-496a-8312-4ba72ac1cb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27676
19370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2767619370
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2383163340
Short name T447
Test name
Test status
Simulation time 147536444 ps
CPU time 0.76 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204780 kb
Host smart-a706a6be-2a55-4d54-b0ab-c0b2e3cb5887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23831
63340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2383163340
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.335399205
Short name T480
Test name
Test status
Simulation time 263093724 ps
CPU time 0.91 seconds
Started Jun 11 12:40:23 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204704 kb
Host smart-d58ef58f-1ed2-49f4-998d-ed61525e344d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33539
9205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.335399205
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1268182327
Short name T1358
Test name
Test status
Simulation time 152661016 ps
CPU time 0.77 seconds
Started Jun 11 12:40:41 PM PDT 24
Finished Jun 11 12:40:43 PM PDT 24
Peak memory 204720 kb
Host smart-2f7e11b6-27dd-4688-9dea-ada4d61af611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12681
82327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1268182327
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_eop_single_bit_handling.374896843
Short name T451
Test name
Test status
Simulation time 171824074 ps
CPU time 0.82 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204656 kb
Host smart-c2f5dbcc-44a0-4676-afa2-37672be2b9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
6843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_eop_single_bit_handling.374896843
Directory /workspace/4.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.291174562
Short name T1254
Test name
Test status
Simulation time 156258591 ps
CPU time 0.75 seconds
Started Jun 11 12:40:24 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204744 kb
Host smart-4f6822f1-abe7-4945-a644-07c72a81cf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29117
4562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.291174562
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.639487793
Short name T699
Test name
Test status
Simulation time 45941803 ps
CPU time 0.65 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204636 kb
Host smart-6f196165-6751-4774-9ad2-cab2c5571cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63948
7793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.639487793
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.877372073
Short name T239
Test name
Test status
Simulation time 7995399921 ps
CPU time 18.6 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 205016 kb
Host smart-5ef6d6da-7d71-45fb-85c4-7898767fa2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87737
2073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.877372073
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4259350582
Short name T574
Test name
Test status
Simulation time 200010881 ps
CPU time 0.9 seconds
Started Jun 11 12:40:16 PM PDT 24
Finished Jun 11 12:40:19 PM PDT 24
Peak memory 204712 kb
Host smart-6ac084c8-72ab-4782-b201-a1b07e961e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593
50582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4259350582
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2229588538
Short name T1360
Test name
Test status
Simulation time 230085321 ps
CPU time 0.93 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204704 kb
Host smart-011e69e7-e735-47db-be0a-dbb307843a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22295
88538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2229588538
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.796916078
Short name T1050
Test name
Test status
Simulation time 29937999745 ps
CPU time 183.78 seconds
Started Jun 11 12:40:23 PM PDT 24
Finished Jun 11 12:43:29 PM PDT 24
Peak memory 205012 kb
Host smart-04ec1723-37d2-4dd3-ab8a-25b6bb37b2c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=796916078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.796916078
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.4044409114
Short name T202
Test name
Test status
Simulation time 8958889645 ps
CPU time 57.2 seconds
Started Jun 11 12:40:20 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204944 kb
Host smart-b95e725d-8c81-4c8c-8bf3-cd722ac720ba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4044409114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.4044409114
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.869748565
Short name T1387
Test name
Test status
Simulation time 19456631070 ps
CPU time 141.54 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:42:42 PM PDT 24
Peak memory 204980 kb
Host smart-ef8a956c-7497-47f2-80dc-11bce9499db5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=869748565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.869748565
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2687631780
Short name T348
Test name
Test status
Simulation time 175366666 ps
CPU time 0.81 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204740 kb
Host smart-e2a2e3de-bb81-4773-843b-f9a05b70d0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
31780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2687631780
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3690152606
Short name T1315
Test name
Test status
Simulation time 232008402 ps
CPU time 0.87 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:40:21 PM PDT 24
Peak memory 204628 kb
Host smart-b2038007-808d-4724-afa8-137ff5497df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36901
52606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3690152606
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2746718357
Short name T522
Test name
Test status
Simulation time 156135864 ps
CPU time 0.75 seconds
Started Jun 11 12:40:19 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204688 kb
Host smart-35ecf4df-908f-4065-80b7-3c6c5a66a2e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27467
18357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2746718357
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2440335538
Short name T124
Test name
Test status
Simulation time 287016026 ps
CPU time 1.14 seconds
Started Jun 11 12:40:27 PM PDT 24
Finished Jun 11 12:40:30 PM PDT 24
Peak memory 221392 kb
Host smart-f651a94d-64f9-4326-9aad-7e414cb5e245
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2440335538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2440335538
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2674507647
Short name T172
Test name
Test status
Simulation time 178170348 ps
CPU time 0.78 seconds
Started Jun 11 12:40:34 PM PDT 24
Finished Jun 11 12:40:36 PM PDT 24
Peak memory 204704 kb
Host smart-88b1c430-3bc8-4dbd-8f5d-452c8f864655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26745
07647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2674507647
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2935669440
Short name T1077
Test name
Test status
Simulation time 196399798 ps
CPU time 0.8 seconds
Started Jun 11 12:40:21 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 204704 kb
Host smart-c03a0609-94fd-4f09-bc87-7a5fb6d91ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29356
69440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2935669440
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.509238950
Short name T436
Test name
Test status
Simulation time 244940032 ps
CPU time 0.98 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:20 PM PDT 24
Peak memory 204740 kb
Host smart-a01208fe-4dfd-4796-88d0-e619d8941ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50923
8950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.509238950
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.3704905812
Short name T1440
Test name
Test status
Simulation time 206608014 ps
CPU time 0.87 seconds
Started Jun 11 12:40:19 PM PDT 24
Finished Jun 11 12:40:23 PM PDT 24
Peak memory 204768 kb
Host smart-597cda09-b354-4c0c-a99a-c8497a095052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37049
05812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.3704905812
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.441476431
Short name T905
Test name
Test status
Simulation time 168463058 ps
CPU time 0.78 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:40:25 PM PDT 24
Peak memory 204624 kb
Host smart-39348cd7-3792-4f39-a50c-9439c4391734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44147
6431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.441476431
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1304855300
Short name T2011
Test name
Test status
Simulation time 11238858157 ps
CPU time 83.34 seconds
Started Jun 11 12:40:17 PM PDT 24
Finished Jun 11 12:41:42 PM PDT 24
Peak memory 204948 kb
Host smart-b4aac43b-5204-4722-ad67-0eaab2b86655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13048
55300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1304855300
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.4079612194
Short name T1919
Test name
Test status
Simulation time 24654055620 ps
CPU time 158.63 seconds
Started Jun 11 12:40:18 PM PDT 24
Finished Jun 11 12:43:00 PM PDT 24
Peak memory 204968 kb
Host smart-72ed21fb-57b7-4d86-bd47-47cda7e08213
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079612194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_b
us_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_
traffic.4079612194
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2466508953
Short name T1488
Test name
Test status
Simulation time 3711266154 ps
CPU time 4.26 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204836 kb
Host smart-9180f25b-7b04-4f05-9d3b-f1d5cbac09aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2466508953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2466508953
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1739830641
Short name T1457
Test name
Test status
Simulation time 13381497229 ps
CPU time 13.44 seconds
Started Jun 11 12:43:58 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204804 kb
Host smart-10016acf-7617-471d-86e7-3e969cb6d845
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1739830641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1739830641
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1104102771
Short name T835
Test name
Test status
Simulation time 23426023222 ps
CPU time 25.83 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 205000 kb
Host smart-b2fc43bb-c8e3-4f64-905a-478855ada453
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1104102771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.1104102771
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.4256645031
Short name T1004
Test name
Test status
Simulation time 194970686 ps
CPU time 0.84 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204736 kb
Host smart-af459398-3cd1-477c-b8b5-0124152bd7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42566
45031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.4256645031
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.2144586609
Short name T63
Test name
Test status
Simulation time 236753487 ps
CPU time 0.89 seconds
Started Jun 11 12:44:03 PM PDT 24
Finished Jun 11 12:44:05 PM PDT 24
Peak memory 204732 kb
Host smart-a7805aa1-3db5-4c3a-84fc-a92bf88c5c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21445
86609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.2144586609
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.4077016809
Short name T1092
Test name
Test status
Simulation time 765291391 ps
CPU time 1.83 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:04 PM PDT 24
Peak memory 204968 kb
Host smart-2f811598-48e8-48b9-8568-de527c492bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40770
16809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.4077016809
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.881161948
Short name T1687
Test name
Test status
Simulation time 134540011 ps
CPU time 0.75 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204640 kb
Host smart-477be701-7a4d-4dd4-85e5-5840eb82c078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88116
1948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.881161948
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.258703942
Short name T535
Test name
Test status
Simulation time 50253973 ps
CPU time 0.65 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:17 PM PDT 24
Peak memory 204640 kb
Host smart-c43f3561-e6c9-4b97-b181-5cca97e1085f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25870
3942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.258703942
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.740720436
Short name T1558
Test name
Test status
Simulation time 964233599 ps
CPU time 2.39 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204940 kb
Host smart-7cbc7a6f-a34d-4592-98df-d85b59a2c0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74072
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.740720436
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.357808277
Short name T1964
Test name
Test status
Simulation time 232301931 ps
CPU time 1.6 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204876 kb
Host smart-19c9c509-46dc-4afb-96a1-543fdcff7982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35780
8277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.357808277
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.892615898
Short name T827
Test name
Test status
Simulation time 230245617 ps
CPU time 0.93 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204712 kb
Host smart-11c6d340-a575-466a-9d4a-7ff4e7c07d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89261
5898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.892615898
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2915811108
Short name T1840
Test name
Test status
Simulation time 139526937 ps
CPU time 0.74 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:17 PM PDT 24
Peak memory 204708 kb
Host smart-8a5a10fb-9850-4b7f-aff4-ac8585625df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29158
11108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2915811108
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.3832704101
Short name T2090
Test name
Test status
Simulation time 237268456 ps
CPU time 0.93 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204692 kb
Host smart-1b88097b-3af3-4476-9242-62b94b484f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38327
04101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.3832704101
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.313913416
Short name T125
Test name
Test status
Simulation time 160069706 ps
CPU time 0.78 seconds
Started Jun 11 12:43:45 PM PDT 24
Finished Jun 11 12:43:47 PM PDT 24
Peak memory 204744 kb
Host smart-94c8b618-b8c0-48cc-bd31-3328b4a5de5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31391
3416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.313913416
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3849995884
Short name T1447
Test name
Test status
Simulation time 3335394639 ps
CPU time 4.31 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204788 kb
Host smart-11b32039-be10-46c4-affa-45ad54cde77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499
95884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3849995884
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2340328234
Short name T1179
Test name
Test status
Simulation time 250225175 ps
CPU time 0.9 seconds
Started Jun 11 12:44:07 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204740 kb
Host smart-a333d9ae-84bb-4d3d-aa92-f6fb08969076
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2340328234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2340328234
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3943735779
Short name T1445
Test name
Test status
Simulation time 253336392 ps
CPU time 0.89 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204724 kb
Host smart-6f5fda87-56a6-49cf-8f31-52eb1070d7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39437
35779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3943735779
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2241782980
Short name T1139
Test name
Test status
Simulation time 15918201284 ps
CPU time 114.14 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 204960 kb
Host smart-c4f7ab9d-7fcd-4429-a58e-fb67ea9e832b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22417
82980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2241782980
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.4225398922
Short name T789
Test name
Test status
Simulation time 179328282 ps
CPU time 0.76 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204680 kb
Host smart-7ab4f38d-18cc-4dbb-ad60-8eb74f7c3f07
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4225398922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.4225398922
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1426600873
Short name T1521
Test name
Test status
Simulation time 163814011 ps
CPU time 0.82 seconds
Started Jun 11 12:43:58 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204720 kb
Host smart-bac70d9d-af29-4252-8391-792bf665ded9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
00873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1426600873
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.397281452
Short name T1570
Test name
Test status
Simulation time 228405581 ps
CPU time 0.88 seconds
Started Jun 11 12:43:57 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204716 kb
Host smart-0f191591-450b-4f68-b375-83625384b274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39728
1452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.397281452
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2618203855
Short name T1778
Test name
Test status
Simulation time 201355530 ps
CPU time 0.78 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204620 kb
Host smart-ce0cef81-fb40-47ab-a71a-28968ff0e0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26182
03855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2618203855
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.278858563
Short name T2106
Test name
Test status
Simulation time 156684058 ps
CPU time 0.78 seconds
Started Jun 11 12:44:09 PM PDT 24
Finished Jun 11 12:44:11 PM PDT 24
Peak memory 204700 kb
Host smart-71218d10-08ab-4320-86db-48c2cd800c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
8563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.278858563
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3918393512
Short name T1167
Test name
Test status
Simulation time 193906430 ps
CPU time 0.8 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204708 kb
Host smart-ff6ff490-b2e3-45d2-9b1e-be3f1460f726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39183
93512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3918393512
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.335790320
Short name T1444
Test name
Test status
Simulation time 171655275 ps
CPU time 0.76 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204612 kb
Host smart-b95713f7-079e-435a-ac9f-5f72ff28f03f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33579
0320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.335790320
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_eop_single_bit_handling.2384953291
Short name T764
Test name
Test status
Simulation time 250103290 ps
CPU time 0.89 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204700 kb
Host smart-71d664a3-8cfb-4d1d-aff1-92d17662a483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23849
53291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_eop_single_bit_handling.2384953291
Directory /workspace/40.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3450855543
Short name T1193
Test name
Test status
Simulation time 166699984 ps
CPU time 0.75 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204708 kb
Host smart-badd5ada-1da1-4748-9e57-d1a983a201d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34508
55543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3450855543
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2627732516
Short name T641
Test name
Test status
Simulation time 68419107 ps
CPU time 0.73 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:24 PM PDT 24
Peak memory 204716 kb
Host smart-d02ed74b-a998-4354-a632-28bee33d69ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
32516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2627732516
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1048789884
Short name T2006
Test name
Test status
Simulation time 14629734564 ps
CPU time 33.99 seconds
Started Jun 11 12:43:54 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 205008 kb
Host smart-05d67076-73d2-4cd8-a0d3-b39740fa6a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10487
89884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1048789884
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.4118228298
Short name T380
Test name
Test status
Simulation time 228194857 ps
CPU time 0.85 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204680 kb
Host smart-fc2cd53e-986e-42bf-8c28-2787eadafdb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41182
28298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.4118228298
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2778781291
Short name T2022
Test name
Test status
Simulation time 291099191 ps
CPU time 0.92 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:43:56 PM PDT 24
Peak memory 204724 kb
Host smart-3983355f-68a3-4275-9fc2-429742890ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27787
81291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2778781291
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.4269228404
Short name T1082
Test name
Test status
Simulation time 197179657 ps
CPU time 0.86 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204652 kb
Host smart-54da84c9-46c2-4b1b-8b5b-227a057ee2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692
28404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.4269228404
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3207346341
Short name T740
Test name
Test status
Simulation time 166272412 ps
CPU time 0.78 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:58 PM PDT 24
Peak memory 204680 kb
Host smart-bd467c68-413e-4db4-89ae-5e40de4947da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
46341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3207346341
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.528867910
Short name T1224
Test name
Test status
Simulation time 149996218 ps
CPU time 0.75 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204708 kb
Host smart-538a1ad3-bac4-413f-b83f-75b210e0198c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52886
7910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.528867910
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1355630524
Short name T442
Test name
Test status
Simulation time 144826064 ps
CPU time 0.73 seconds
Started Jun 11 12:44:00 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204692 kb
Host smart-9ff82e40-1536-4257-9a56-40852b9183f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13556
30524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1355630524
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3455836726
Short name T418
Test name
Test status
Simulation time 154122168 ps
CPU time 0.75 seconds
Started Jun 11 12:44:04 PM PDT 24
Finished Jun 11 12:44:06 PM PDT 24
Peak memory 204784 kb
Host smart-28edc244-1c84-4ee8-93e0-ca6adc9b97de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34558
36726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3455836726
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1375956495
Short name T1238
Test name
Test status
Simulation time 180400734 ps
CPU time 0.8 seconds
Started Jun 11 12:44:08 PM PDT 24
Finished Jun 11 12:44:10 PM PDT 24
Peak memory 204736 kb
Host smart-983862c5-5ddb-459a-adb0-4b40935e756f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13759
56495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1375956495
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1270657388
Short name T2005
Test name
Test status
Simulation time 153244897 ps
CPU time 0.74 seconds
Started Jun 11 12:43:50 PM PDT 24
Finished Jun 11 12:43:53 PM PDT 24
Peak memory 204716 kb
Host smart-69f5d9a1-b24d-4406-85e6-e85458205ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12706
57388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1270657388
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3045172868
Short name T796
Test name
Test status
Simulation time 150305025 ps
CPU time 0.77 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204688 kb
Host smart-fb9ef67e-a236-40f9-bc47-11d51e97e2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451
72868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3045172868
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1236822599
Short name T886
Test name
Test status
Simulation time 13732720422 ps
CPU time 363.61 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:49:59 PM PDT 24
Peak memory 205008 kb
Host smart-7467b607-527b-47c3-9590-045a95c445f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12368
22599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1236822599
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3378358902
Short name T2084
Test name
Test status
Simulation time 4305642753 ps
CPU time 4.86 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:05 PM PDT 24
Peak memory 203560 kb
Host smart-be916377-1da3-46ec-997d-ab4705c4a558
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3378358902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3378358902
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.519661384
Short name T569
Test name
Test status
Simulation time 13540838475 ps
CPU time 16.06 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 203752 kb
Host smart-a6fc9dd2-723a-4a1b-a3e8-9ce43255c162
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=519661384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.519661384
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2369149632
Short name T2058
Test name
Test status
Simulation time 23336205526 ps
CPU time 23.47 seconds
Started Jun 11 12:44:05 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 205052 kb
Host smart-09beee0d-9216-4514-b33b-7ee279e2eadb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2369149632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2369149632
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2754757580
Short name T1876
Test name
Test status
Simulation time 143640352 ps
CPU time 0.83 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204764 kb
Host smart-3b1032d6-c590-4525-b1a6-590f5533d9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27547
57580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2754757580
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1793139669
Short name T888
Test name
Test status
Simulation time 152742499 ps
CPU time 0.81 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204648 kb
Host smart-f8dd915b-80a4-4a1d-884a-291ab21f668f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17931
39669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1793139669
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.3803623921
Short name T1295
Test name
Test status
Simulation time 717415728 ps
CPU time 1.68 seconds
Started Jun 11 12:44:13 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204892 kb
Host smart-772114eb-efec-4ec2-9ba3-f2dc5ee9ddcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38036
23921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3803623921
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3858880409
Short name T560
Test name
Test status
Simulation time 162898896 ps
CPU time 0.79 seconds
Started Jun 11 12:44:00 PM PDT 24
Finished Jun 11 12:44:03 PM PDT 24
Peak memory 204672 kb
Host smart-be95e7cb-c5ac-4c9b-a14c-b30f129416d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
80409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3858880409
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.561688026
Short name T899
Test name
Test status
Simulation time 30348158 ps
CPU time 0.65 seconds
Started Jun 11 12:43:51 PM PDT 24
Finished Jun 11 12:43:55 PM PDT 24
Peak memory 204732 kb
Host smart-406f1275-41b1-4d2f-a574-7c12a1678b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56168
8026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.561688026
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.1076714160
Short name T1327
Test name
Test status
Simulation time 735588518 ps
CPU time 1.94 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204876 kb
Host smart-454bd28d-b0c8-4578-aa5c-215d918ebda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10767
14160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1076714160
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3991526539
Short name T939
Test name
Test status
Simulation time 277852544 ps
CPU time 1.68 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 205048 kb
Host smart-aa27b5dc-4909-4842-a192-e79fee25b3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
26539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3991526539
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3970603918
Short name T853
Test name
Test status
Simulation time 180469243 ps
CPU time 0.8 seconds
Started Jun 11 12:43:59 PM PDT 24
Finished Jun 11 12:44:02 PM PDT 24
Peak memory 204672 kb
Host smart-8c307a7c-2c7f-448d-9850-794c0e5d4a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39706
03918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3970603918
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2990622041
Short name T834
Test name
Test status
Simulation time 154309082 ps
CPU time 0.74 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204728 kb
Host smart-f5d2b5bf-13e6-4517-a633-8413925f71f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
22041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2990622041
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2818042059
Short name T1403
Test name
Test status
Simulation time 245240440 ps
CPU time 0.96 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204728 kb
Host smart-5a6b477a-356c-4c5a-bd68-cb47e8243c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
42059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2818042059
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.1895964639
Short name T1881
Test name
Test status
Simulation time 207079897 ps
CPU time 0.83 seconds
Started Jun 11 12:43:49 PM PDT 24
Finished Jun 11 12:43:52 PM PDT 24
Peak memory 204720 kb
Host smart-08af7c95-d95c-4253-a4c7-b76513eac3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18959
64639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.1895964639
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.559740939
Short name T519
Test name
Test status
Simulation time 3314733419 ps
CPU time 3.89 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:17 PM PDT 24
Peak memory 204808 kb
Host smart-4c30e250-ef2e-4162-9c22-1130ae0a8023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55974
0939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.559740939
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3002905580
Short name T1765
Test name
Test status
Simulation time 282711267 ps
CPU time 0.96 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 204780 kb
Host smart-56ec1f27-ea1a-4c43-9fd3-e409f7c59243
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3002905580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3002905580
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1661986590
Short name T801
Test name
Test status
Simulation time 269849637 ps
CPU time 0.9 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204704 kb
Host smart-f44a558a-1821-458d-968c-d39592b6c02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16619
86590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1661986590
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3071303548
Short name T1589
Test name
Test status
Simulation time 13631867252 ps
CPU time 100.56 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 204968 kb
Host smart-b10cbc8c-2226-4097-8e25-807c60b016e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30713
03548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3071303548
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2631647261
Short name T1070
Test name
Test status
Simulation time 161085543 ps
CPU time 0.76 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:17 PM PDT 24
Peak memory 204720 kb
Host smart-c97aa2c7-83a6-465d-90ae-9b43c73bc510
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2631647261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2631647261
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.266317999
Short name T1994
Test name
Test status
Simulation time 142178656 ps
CPU time 0.76 seconds
Started Jun 11 12:44:01 PM PDT 24
Finished Jun 11 12:44:04 PM PDT 24
Peak memory 204656 kb
Host smart-eb14ec5d-ce1b-43e9-a2c6-45e75057fadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26631
7999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.266317999
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1860614270
Short name T164
Test name
Test status
Simulation time 195099160 ps
CPU time 0.83 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204736 kb
Host smart-51e57b7d-2116-414d-a18a-0ad39be3bca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
14270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1860614270
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2090295896
Short name T1619
Test name
Test status
Simulation time 193387667 ps
CPU time 0.84 seconds
Started Jun 11 12:43:53 PM PDT 24
Finished Jun 11 12:43:57 PM PDT 24
Peak memory 204716 kb
Host smart-1920aaa4-095d-4569-866e-3e40817b25b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20902
95896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2090295896
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3053235488
Short name T35
Test name
Test status
Simulation time 190558083 ps
CPU time 0.81 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204604 kb
Host smart-422ec635-48d5-4b9c-8f74-c3c9074c2d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30532
35488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3053235488
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3078882354
Short name T471
Test name
Test status
Simulation time 189217096 ps
CPU time 0.79 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204616 kb
Host smart-c6aefc4e-7666-4a8b-ac2b-ab9852dba7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30788
82354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3078882354
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.744786269
Short name T954
Test name
Test status
Simulation time 159330651 ps
CPU time 0.8 seconds
Started Jun 11 12:44:29 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204744 kb
Host smart-b9fcc0d3-6e66-47de-a9ea-642f7965188d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74478
6269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.744786269
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_eop_single_bit_handling.1835180894
Short name T1356
Test name
Test status
Simulation time 159096634 ps
CPU time 0.74 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204652 kb
Host smart-5ce91580-3e23-454b-8b27-c254a8b5d413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18351
80894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_eop_single_bit_handling.1835180894
Directory /workspace/41.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4062092257
Short name T1600
Test name
Test status
Simulation time 139164709 ps
CPU time 0.79 seconds
Started Jun 11 12:44:07 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204656 kb
Host smart-29f78c74-90d0-4ffe-807f-663f18e60719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40620
92257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4062092257
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2269643660
Short name T1889
Test name
Test status
Simulation time 88712109 ps
CPU time 0.69 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:13 PM PDT 24
Peak memory 204656 kb
Host smart-991d973f-99d4-4a67-a15c-660e1920aad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22696
43660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2269643660
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3609450803
Short name T103
Test name
Test status
Simulation time 16087220007 ps
CPU time 33.28 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 205008 kb
Host smart-74b59cfd-2a87-4954-8cd4-49641314b7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
50803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3609450803
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.495336958
Short name T1469
Test name
Test status
Simulation time 178503751 ps
CPU time 0.85 seconds
Started Jun 11 12:44:13 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 204716 kb
Host smart-2d507dc2-a408-437a-abc1-a7ab9c8bacf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49533
6958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.495336958
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.4273687233
Short name T408
Test name
Test status
Simulation time 228487217 ps
CPU time 0.9 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 204700 kb
Host smart-c060e052-c076-40e6-950a-2683089bf6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42736
87233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.4273687233
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.185124530
Short name T956
Test name
Test status
Simulation time 235613617 ps
CPU time 0.88 seconds
Started Jun 11 12:44:04 PM PDT 24
Finished Jun 11 12:44:06 PM PDT 24
Peak memory 204728 kb
Host smart-3912e661-101a-43ea-9d42-d5a8a494951c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18512
4530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.185124530
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.815973120
Short name T1928
Test name
Test status
Simulation time 168995383 ps
CPU time 0.79 seconds
Started Jun 11 12:43:56 PM PDT 24
Finished Jun 11 12:44:01 PM PDT 24
Peak memory 204628 kb
Host smart-410a97b1-de6e-49bc-811d-bfd9c40bbf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81597
3120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.815973120
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.302412794
Short name T2000
Test name
Test status
Simulation time 129243298 ps
CPU time 0.73 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:43:59 PM PDT 24
Peak memory 204712 kb
Host smart-99ce9e0b-44d2-4e87-9819-15dc448eb41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30241
2794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.302412794
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2235832491
Short name T1798
Test name
Test status
Simulation time 150466304 ps
CPU time 0.78 seconds
Started Jun 11 12:44:05 PM PDT 24
Finished Jun 11 12:44:07 PM PDT 24
Peak memory 204724 kb
Host smart-9dfebbb0-d45c-48b5-bf63-9ec69f53205c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22358
32491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2235832491
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2441017221
Short name T914
Test name
Test status
Simulation time 163910508 ps
CPU time 0.82 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204728 kb
Host smart-cbff0b34-f67d-4e88-8820-e3bf8f8988d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24410
17221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2441017221
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.2854201107
Short name T947
Test name
Test status
Simulation time 204466619 ps
CPU time 0.87 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:13 PM PDT 24
Peak memory 204648 kb
Host smart-d0d1371c-a9d8-463b-a386-5c8bea8c33f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28542
01107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2854201107
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2411437893
Short name T1373
Test name
Test status
Simulation time 149199097 ps
CPU time 0.75 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 204768 kb
Host smart-a35edd3b-2113-4158-80d8-01bd400dba30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
37893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2411437893
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2867425301
Short name T1353
Test name
Test status
Simulation time 157713750 ps
CPU time 0.75 seconds
Started Jun 11 12:43:58 PM PDT 24
Finished Jun 11 12:44:06 PM PDT 24
Peak memory 204756 kb
Host smart-9439225f-07ea-4b60-98e8-9e1f85057de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28674
25301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2867425301
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.3979858829
Short name T994
Test name
Test status
Simulation time 7277442545 ps
CPU time 50.72 seconds
Started Jun 11 12:43:52 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204884 kb
Host smart-ad058472-3068-4e81-a3ae-cbae969cd3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39798
58829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.3979858829
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2552533127
Short name T427
Test name
Test status
Simulation time 3511406929 ps
CPU time 4.26 seconds
Started Jun 11 12:44:09 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204792 kb
Host smart-885f66db-6062-4603-877d-e20f192a5916
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2552533127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2552533127
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.1631651020
Short name T1703
Test name
Test status
Simulation time 13433077272 ps
CPU time 12.82 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 204992 kb
Host smart-e787b14c-cc4b-4212-8939-969d7a94845a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1631651020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.1631651020
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2576228141
Short name T880
Test name
Test status
Simulation time 23345968146 ps
CPU time 22.56 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 205040 kb
Host smart-9c5d0a59-1178-4cac-970c-cbc202f63a94
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2576228141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2576228141
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2694217034
Short name T999
Test name
Test status
Simulation time 159441079 ps
CPU time 0.86 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 204720 kb
Host smart-ffdade40-354b-4431-bcbc-cf2f18d0dc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26942
17034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2694217034
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3952348212
Short name T913
Test name
Test status
Simulation time 146408214 ps
CPU time 0.71 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204672 kb
Host smart-51e6197f-bdf8-42e5-9bc5-cc238bb7abc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
48212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3952348212
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.2117933128
Short name T1795
Test name
Test status
Simulation time 1646041334 ps
CPU time 3.45 seconds
Started Jun 11 12:44:10 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 204952 kb
Host smart-b20239b4-6cf8-4654-9d81-415d79812140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21179
33128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.2117933128
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2640570606
Short name T1612
Test name
Test status
Simulation time 133571318 ps
CPU time 0.73 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204736 kb
Host smart-417d6cba-c75b-4487-ac11-be9b121b303a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
70606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2640570606
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2664209232
Short name T1202
Test name
Test status
Simulation time 74390479 ps
CPU time 0.7 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:17 PM PDT 24
Peak memory 204692 kb
Host smart-a5b13080-371c-4e4d-92ff-b0ac277c639d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26642
09232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2664209232
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.907374599
Short name T356
Test name
Test status
Simulation time 971612302 ps
CPU time 2.55 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204892 kb
Host smart-b69b1d6a-8b93-43a2-b33d-8136f696c12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90737
4599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.907374599
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.4242985218
Short name T600
Test name
Test status
Simulation time 161721649 ps
CPU time 1.59 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 204908 kb
Host smart-d5bcbd85-d598-4c0c-a216-364ffafed963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
85218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.4242985218
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.1176336552
Short name T1310
Test name
Test status
Simulation time 235192763 ps
CPU time 0.89 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:22 PM PDT 24
Peak memory 204768 kb
Host smart-402ba748-f7da-475f-b867-b9dd7d0183f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11763
36552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.1176336552
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3748728166
Short name T497
Test name
Test status
Simulation time 145570255 ps
CPU time 0.76 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:24 PM PDT 24
Peak memory 204728 kb
Host smart-ddad7f59-c26c-4790-9976-ee754c06d36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37487
28166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3748728166
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2357041209
Short name T328
Test name
Test status
Simulation time 229406276 ps
CPU time 0.92 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204720 kb
Host smart-b1b6a8d8-6286-48e2-b0ec-db3de1a69d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23570
41209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2357041209
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.675056712
Short name T1510
Test name
Test status
Simulation time 294687909 ps
CPU time 0.94 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:24 PM PDT 24
Peak memory 204660 kb
Host smart-be4f20ff-9619-431f-8df5-92817bf1b801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67505
6712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.675056712
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2014733051
Short name T1887
Test name
Test status
Simulation time 3364248407 ps
CPU time 4.1 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204716 kb
Host smart-8f8a07bb-dd6a-47e3-84ef-22a82b25187e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20147
33051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2014733051
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1949282932
Short name T577
Test name
Test status
Simulation time 243798016 ps
CPU time 0.96 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204612 kb
Host smart-d2f690bd-e2be-4582-91b5-7b437021c684
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1949282932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1949282932
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.584435795
Short name T368
Test name
Test status
Simulation time 191657583 ps
CPU time 0.86 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204708 kb
Host smart-478191ab-645a-41b0-ae53-c64adf103b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58443
5795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.584435795
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.529502387
Short name T1464
Test name
Test status
Simulation time 4145725782 ps
CPU time 27.13 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 205052 kb
Host smart-9eb8a6c4-b8f4-41c2-91c8-da968ce1dc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52950
2387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.529502387
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3368976488
Short name T1604
Test name
Test status
Simulation time 161503008 ps
CPU time 0.79 seconds
Started Jun 11 12:44:08 PM PDT 24
Finished Jun 11 12:44:10 PM PDT 24
Peak memory 204712 kb
Host smart-dd87e0d2-0915-4688-bb6c-d1bc94a275df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3368976488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3368976488
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3392003863
Short name T303
Test name
Test status
Simulation time 169254015 ps
CPU time 0.79 seconds
Started Jun 11 12:44:13 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 204768 kb
Host smart-bca3e35f-3399-4f30-b7a8-f9c56b52fb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920
03863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3392003863
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1334349956
Short name T158
Test name
Test status
Simulation time 176042588 ps
CPU time 0.83 seconds
Started Jun 11 12:44:07 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204624 kb
Host smart-d010d639-72a4-4b2f-ab72-4ea826d9619b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
49956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1334349956
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2857201551
Short name T1493
Test name
Test status
Simulation time 184860063 ps
CPU time 0.83 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204704 kb
Host smart-81e59aa8-f5a0-4f6e-9dab-bcbee3501036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28572
01551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2857201551
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2746590712
Short name T504
Test name
Test status
Simulation time 172676749 ps
CPU time 0.79 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204776 kb
Host smart-d6e772e1-05a9-47ab-9792-1e1fd5694419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27465
90712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2746590712
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1296469651
Short name T31
Test name
Test status
Simulation time 156683559 ps
CPU time 0.76 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:22 PM PDT 24
Peak memory 204692 kb
Host smart-2763d466-8b03-4389-8f31-250624fbf554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12964
69651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1296469651
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3109319332
Short name T1923
Test name
Test status
Simulation time 168319495 ps
CPU time 0.78 seconds
Started Jun 11 12:43:55 PM PDT 24
Finished Jun 11 12:44:00 PM PDT 24
Peak memory 204640 kb
Host smart-5afc9f2d-feff-4779-a43f-a2fe0fd9a154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31093
19332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3109319332
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_eop_single_bit_handling.252583572
Short name T1977
Test name
Test status
Simulation time 188415944 ps
CPU time 0.88 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204716 kb
Host smart-1c56fb5c-5303-4384-a9cc-dc1070ff287a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
3572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_eop_single_bit_handling.252583572
Directory /workspace/42.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3492927866
Short name T723
Test name
Test status
Simulation time 169880898 ps
CPU time 0.76 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:24 PM PDT 24
Peak memory 204736 kb
Host smart-e025671a-dade-4fa3-a95a-90f747bd410c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
27866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3492927866
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2545838722
Short name T1100
Test name
Test status
Simulation time 41812114 ps
CPU time 0.66 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 205008 kb
Host smart-0480eac4-0b26-46c7-bf5f-ad1a2da756e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25458
38722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2545838722
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2008222337
Short name T1442
Test name
Test status
Simulation time 6453137175 ps
CPU time 14.42 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:39 PM PDT 24
Peak memory 205004 kb
Host smart-9d4c655d-41b9-483c-a541-9b819b7c0dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20082
22337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2008222337
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1073954099
Short name T1201
Test name
Test status
Simulation time 174741787 ps
CPU time 0.83 seconds
Started Jun 11 12:44:26 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204652 kb
Host smart-6372abe7-e21e-46ac-b4fc-94e9d9686f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739
54099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1073954099
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3759930054
Short name T1808
Test name
Test status
Simulation time 196736164 ps
CPU time 0.84 seconds
Started Jun 11 12:44:07 PM PDT 24
Finished Jun 11 12:44:09 PM PDT 24
Peak memory 204640 kb
Host smart-d6e93094-53e4-4153-bf11-87df0bbc201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37599
30054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3759930054
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2625589298
Short name T962
Test name
Test status
Simulation time 240721474 ps
CPU time 0.92 seconds
Started Jun 11 12:44:13 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204660 kb
Host smart-e149d2e2-7b2a-4b50-a2a1-717b0b84b8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
89298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2625589298
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.497209865
Short name T1078
Test name
Test status
Simulation time 208018664 ps
CPU time 0.91 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:22 PM PDT 24
Peak memory 204668 kb
Host smart-c36ad8e3-fad2-4ccf-b8ac-b074e04d97a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49720
9865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.497209865
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1536913418
Short name T1753
Test name
Test status
Simulation time 149300861 ps
CPU time 0.77 seconds
Started Jun 11 12:44:05 PM PDT 24
Finished Jun 11 12:44:07 PM PDT 24
Peak memory 204740 kb
Host smart-30cc04b2-4b97-4944-bfee-c0a1bb85416a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15369
13418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1536913418
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3831943414
Short name T1567
Test name
Test status
Simulation time 141363988 ps
CPU time 0.74 seconds
Started Jun 11 12:44:26 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204752 kb
Host smart-467196a5-d445-4d3d-9c06-c7de92dd7a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
43414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3831943414
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1588635557
Short name T799
Test name
Test status
Simulation time 155756444 ps
CPU time 0.77 seconds
Started Jun 11 12:44:02 PM PDT 24
Finished Jun 11 12:44:05 PM PDT 24
Peak memory 204744 kb
Host smart-865085c2-87d1-4284-8221-4f9f5acfe86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15886
35557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1588635557
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2810590529
Short name T1301
Test name
Test status
Simulation time 242099473 ps
CPU time 0.91 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204664 kb
Host smart-32ea5920-0575-4082-a0db-86bde484f5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28105
90529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2810590529
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3770121807
Short name T1101
Test name
Test status
Simulation time 176916334 ps
CPU time 0.76 seconds
Started Jun 11 12:44:29 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204576 kb
Host smart-b0ee8f34-6485-4aa8-9bd0-694a3c218e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37701
21807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3770121807
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2810940921
Short name T1020
Test name
Test status
Simulation time 9188398657 ps
CPU time 89.94 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 205060 kb
Host smart-0d9a026c-d276-4f3d-a48c-8c44f194b366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28109
40921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2810940921
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.3037443585
Short name T472
Test name
Test status
Simulation time 4439156147 ps
CPU time 5.39 seconds
Started Jun 11 12:44:33 PM PDT 24
Finished Jun 11 12:44:40 PM PDT 24
Peak memory 205072 kb
Host smart-4ec011ea-d8ce-4bcc-b598-a89bb60d9d91
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3037443585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.3037443585
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1862757405
Short name T1435
Test name
Test status
Simulation time 13376792730 ps
CPU time 15.28 seconds
Started Jun 11 12:44:01 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 205048 kb
Host smart-c4d21d84-2e88-490d-8b04-dd55f6ef69eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1862757405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1862757405
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3778565110
Short name T1737
Test name
Test status
Simulation time 23331505599 ps
CPU time 24.66 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 205012 kb
Host smart-1325513b-af0e-4a11-b156-c84938cfe80c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3778565110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3778565110
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2282561369
Short name T1108
Test name
Test status
Simulation time 160703203 ps
CPU time 0.76 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:44:14 PM PDT 24
Peak memory 204704 kb
Host smart-3de4f24a-1c90-429f-a953-ecaa5e826ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
61369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2282561369
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2333962803
Short name T1791
Test name
Test status
Simulation time 167120827 ps
CPU time 0.79 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204740 kb
Host smart-4adf4b71-82b1-4222-9677-6b578c3dfda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23339
62803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2333962803
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.2330358160
Short name T60
Test name
Test status
Simulation time 1272836920 ps
CPU time 2.82 seconds
Started Jun 11 12:44:08 PM PDT 24
Finished Jun 11 12:44:12 PM PDT 24
Peak memory 204976 kb
Host smart-bbd06ea1-3955-4e2a-93b8-4c292ef0349b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
58160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2330358160
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3022933087
Short name T1425
Test name
Test status
Simulation time 145793994 ps
CPU time 0.77 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204636 kb
Host smart-0a81099e-609b-4ee4-9e5d-96d6795b44e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
33087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3022933087
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1990961439
Short name T2071
Test name
Test status
Simulation time 36439472 ps
CPU time 0.63 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204684 kb
Host smart-f0c8b682-f15a-4554-b99f-b663ce76b9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19909
61439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1990961439
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3875496102
Short name T1346
Test name
Test status
Simulation time 903525705 ps
CPU time 2.21 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 205024 kb
Host smart-983dc3ea-368c-4b1d-9b5b-5cfa15fc8abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38754
96102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3875496102
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3569625753
Short name T1483
Test name
Test status
Simulation time 286311780 ps
CPU time 1.77 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204900 kb
Host smart-4b819f73-8827-4e1a-b810-88dcee649ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35696
25753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3569625753
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.118081517
Short name T787
Test name
Test status
Simulation time 184871824 ps
CPU time 0.82 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204692 kb
Host smart-6890d5fe-f1d4-4008-bcbd-e903a46377b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11808
1517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.118081517
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3547459353
Short name T1507
Test name
Test status
Simulation time 136750058 ps
CPU time 0.75 seconds
Started Jun 11 12:44:03 PM PDT 24
Finished Jun 11 12:44:05 PM PDT 24
Peak memory 204664 kb
Host smart-df5b2722-92bc-485f-b23e-85e48428a941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35474
59353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3547459353
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.573951191
Short name T1106
Test name
Test status
Simulation time 274977403 ps
CPU time 0.93 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 204708 kb
Host smart-9d86a72d-8f21-4d32-bc38-f48c1ba77e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57395
1191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.573951191
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.4011360156
Short name T1837
Test name
Test status
Simulation time 222059334 ps
CPU time 0.86 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204720 kb
Host smart-1dabae29-31ba-44b4-a1bc-4710f4ddd9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
60156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.4011360156
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.4208152434
Short name T1102
Test name
Test status
Simulation time 3296113679 ps
CPU time 3.85 seconds
Started Jun 11 12:44:01 PM PDT 24
Finished Jun 11 12:44:07 PM PDT 24
Peak memory 204764 kb
Host smart-437aa6e0-a4a9-4eab-9bcb-c05752b8c773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42081
52434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.4208152434
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.781504669
Short name T897
Test name
Test status
Simulation time 239536542 ps
CPU time 0.91 seconds
Started Jun 11 12:44:18 PM PDT 24
Finished Jun 11 12:44:21 PM PDT 24
Peak memory 204604 kb
Host smart-a4d10a26-d1d0-4a62-af89-1f75a742ef71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=781504669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.781504669
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2649479397
Short name T1772
Test name
Test status
Simulation time 186593966 ps
CPU time 0.92 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204652 kb
Host smart-f7551b75-32d4-4b2c-a8d8-35cda7b36d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
79397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2649479397
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2651440319
Short name T1279
Test name
Test status
Simulation time 11539906966 ps
CPU time 312.36 seconds
Started Jun 11 12:44:12 PM PDT 24
Finished Jun 11 12:49:25 PM PDT 24
Peak memory 205048 kb
Host smart-f28e15ad-9f7d-4145-844a-10cfa6be2734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
40319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2651440319
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.324159126
Short name T1542
Test name
Test status
Simulation time 156890869 ps
CPU time 0.81 seconds
Started Jun 11 12:44:29 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204772 kb
Host smart-d9a9a770-86e7-4308-990f-494e25a0844a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=324159126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.324159126
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.680975673
Short name T466
Test name
Test status
Simulation time 165718752 ps
CPU time 0.77 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:12 PM PDT 24
Peak memory 204668 kb
Host smart-442b23f2-8db9-4c96-b28c-1152cd2880da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68097
5673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.680975673
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2886451702
Short name T142
Test name
Test status
Simulation time 194052035 ps
CPU time 0.83 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:18 PM PDT 24
Peak memory 204728 kb
Host smart-21a64ba9-037e-46ab-a75d-ae4df3d7ebe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
51702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2886451702
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2946611773
Short name T1391
Test name
Test status
Simulation time 173067900 ps
CPU time 0.82 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:13 PM PDT 24
Peak memory 204716 kb
Host smart-72ba330c-723d-45b0-8223-50433eedb18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466
11773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2946611773
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1644368837
Short name T761
Test name
Test status
Simulation time 171046030 ps
CPU time 0.83 seconds
Started Jun 11 12:44:05 PM PDT 24
Finished Jun 11 12:44:07 PM PDT 24
Peak memory 204728 kb
Host smart-ee9dbfd7-9cf0-42e6-a93c-fcb3ad8c2c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16443
68837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1644368837
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3526148330
Short name T819
Test name
Test status
Simulation time 172408399 ps
CPU time 0.81 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 204668 kb
Host smart-3f66f6e9-a1cf-415a-89da-46378f8f2ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35261
48330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3526148330
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1000645310
Short name T126
Test name
Test status
Simulation time 176386791 ps
CPU time 0.77 seconds
Started Jun 11 12:44:18 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204724 kb
Host smart-3310c7ac-1209-4b94-8da7-5449bd36d4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10006
45310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1000645310
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_eop_single_bit_handling.3365231523
Short name T1302
Test name
Test status
Simulation time 157532171 ps
CPU time 0.79 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204724 kb
Host smart-be09124e-5067-4fef-b3f6-7c773273cbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652
31523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_eop_single_bit_handling.3365231523
Directory /workspace/43.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3771527794
Short name T1533
Test name
Test status
Simulation time 157603809 ps
CPU time 0.74 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204608 kb
Host smart-01b1dd1d-a348-47ec-a0b7-8b3db03fd317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
27794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3771527794
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.389800858
Short name T242
Test name
Test status
Simulation time 6040731090 ps
CPU time 13.28 seconds
Started Jun 11 12:44:29 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 204976 kb
Host smart-ce439dc3-1a30-456a-a57c-faa64b4b2242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38980
0858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.389800858
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1376691818
Short name T1643
Test name
Test status
Simulation time 156082332 ps
CPU time 0.76 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204704 kb
Host smart-283413b7-1220-4a8c-af01-949c856e98b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766
91818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1376691818
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.502726697
Short name T911
Test name
Test status
Simulation time 165221339 ps
CPU time 0.82 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:20 PM PDT 24
Peak memory 204624 kb
Host smart-95d859a8-96d4-4a98-86ab-f0fa82373e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50272
6697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.502726697
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1605933987
Short name T551
Test name
Test status
Simulation time 223036717 ps
CPU time 0.83 seconds
Started Jun 11 12:44:18 PM PDT 24
Finished Jun 11 12:44:21 PM PDT 24
Peak memory 204600 kb
Host smart-c990f1a9-01e6-4ae8-8495-e0b56b6d0c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16059
33987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1605933987
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1542071613
Short name T1127
Test name
Test status
Simulation time 182543590 ps
CPU time 0.78 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 204768 kb
Host smart-ab1b46db-2db6-4aa9-9a66-6f8494e68b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15420
71613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1542071613
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2807076342
Short name T1438
Test name
Test status
Simulation time 137103676 ps
CPU time 0.75 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204576 kb
Host smart-93356b56-ac5c-4857-849a-48d59152a253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070
76342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2807076342
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1576907127
Short name T503
Test name
Test status
Simulation time 152341566 ps
CPU time 0.86 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204652 kb
Host smart-8fb5636a-b537-4f8c-9b96-3ca32638922a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
07127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1576907127
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.983475113
Short name T753
Test name
Test status
Simulation time 150705808 ps
CPU time 0.79 seconds
Started Jun 11 12:44:31 PM PDT 24
Finished Jun 11 12:44:34 PM PDT 24
Peak memory 204652 kb
Host smart-c44c2536-07ed-468e-b51d-60ae3dc4f2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98347
5113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.983475113
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1732349225
Short name T867
Test name
Test status
Simulation time 196980024 ps
CPU time 0.88 seconds
Started Jun 11 12:44:09 PM PDT 24
Finished Jun 11 12:44:11 PM PDT 24
Peak memory 204712 kb
Host smart-185f744c-6445-4182-bdf9-9e4812247bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17323
49225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1732349225
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.4152557304
Short name T672
Test name
Test status
Simulation time 181882727 ps
CPU time 0.8 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:18 PM PDT 24
Peak memory 204728 kb
Host smart-8f163ed8-2d82-47da-a62c-cd4e2223cced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
57304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.4152557304
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.806683580
Short name T1973
Test name
Test status
Simulation time 182605080 ps
CPU time 0.79 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204728 kb
Host smart-71e13fa0-c674-4398-bbd6-9358722ee36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80668
3580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.806683580
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.4101520173
Short name T1545
Test name
Test status
Simulation time 13426391235 ps
CPU time 97.34 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 205008 kb
Host smart-db7e1b99-98b2-46c5-a696-bf81a50eb627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41015
20173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.4101520173
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1719150657
Short name T1170
Test name
Test status
Simulation time 4321044817 ps
CPU time 4.89 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204724 kb
Host smart-d36d27ec-7be1-4e40-bb28-44fc53dbadd9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1719150657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.1719150657
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1830404377
Short name T52
Test name
Test status
Simulation time 13315376242 ps
CPU time 13.67 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204784 kb
Host smart-81a70c5d-4981-4795-9d66-9a9f91767b75
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1830404377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1830404377
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3524738783
Short name T1326
Test name
Test status
Simulation time 148541398 ps
CPU time 0.75 seconds
Started Jun 11 12:44:06 PM PDT 24
Finished Jun 11 12:44:08 PM PDT 24
Peak memory 204728 kb
Host smart-d9336574-66ed-4204-b0e5-fa813d8614bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35247
38783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3524738783
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2107721550
Short name T446
Test name
Test status
Simulation time 598217523 ps
CPU time 1.49 seconds
Started Jun 11 12:44:18 PM PDT 24
Finished Jun 11 12:44:21 PM PDT 24
Peak memory 204716 kb
Host smart-821f46b7-96d8-465f-917c-1f2dacadadcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21077
21550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2107721550
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.4250213467
Short name T1786
Test name
Test status
Simulation time 147726118 ps
CPU time 0.73 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204708 kb
Host smart-768c24f7-53e5-4855-bc81-51e49eb89060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
13467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.4250213467
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3712586948
Short name T1239
Test name
Test status
Simulation time 54792638 ps
CPU time 0.7 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204568 kb
Host smart-92c887cb-2c5a-4cef-bf83-fdbad7f11ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
86948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3712586948
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3500209644
Short name T1920
Test name
Test status
Simulation time 943735518 ps
CPU time 2.4 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:28 PM PDT 24
Peak memory 204968 kb
Host smart-94ed1385-ff5b-4e09-8b8b-9aec8793bd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35002
09644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3500209644
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.254277148
Short name T745
Test name
Test status
Simulation time 330231010 ps
CPU time 2.39 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:28 PM PDT 24
Peak memory 204876 kb
Host smart-00db90aa-b778-4590-8e93-68dd1321ad3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25427
7148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.254277148
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2092792161
Short name T759
Test name
Test status
Simulation time 186041216 ps
CPU time 0.85 seconds
Started Jun 11 12:44:25 PM PDT 24
Finished Jun 11 12:44:28 PM PDT 24
Peak memory 204632 kb
Host smart-55608786-07d4-4dbd-9b25-25f304993de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20927
92161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2092792161
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2305341281
Short name T508
Test name
Test status
Simulation time 137567303 ps
CPU time 0.76 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204600 kb
Host smart-b41da2cc-400b-4613-927a-5cc8a98a7378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23053
41281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2305341281
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2842319459
Short name T1059
Test name
Test status
Simulation time 206903073 ps
CPU time 0.89 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:24 PM PDT 24
Peak memory 204732 kb
Host smart-d7952945-66de-42a7-9b15-2d896f1c57ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28423
19459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2842319459
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1866858246
Short name T1105
Test name
Test status
Simulation time 201447756 ps
CPU time 0.91 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204688 kb
Host smart-098757a2-d200-4e10-95aa-5209b27b8d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18668
58246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1866858246
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.4251860727
Short name T537
Test name
Test status
Simulation time 3299986245 ps
CPU time 4.94 seconds
Started Jun 11 12:44:28 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 204784 kb
Host smart-dc19c540-b1ae-471b-95b1-1482d1b22a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42518
60727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4251860727
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.655994654
Short name T2075
Test name
Test status
Simulation time 246917605 ps
CPU time 0.92 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 204728 kb
Host smart-979bcdda-64a7-4e32-abc1-9ec3df8c95e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=655994654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.655994654
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4097443666
Short name T1096
Test name
Test status
Simulation time 197840963 ps
CPU time 0.87 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204764 kb
Host smart-655a671a-d589-4b47-a4ec-1c18a88a26b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974
43666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4097443666
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1116962902
Short name T20
Test name
Test status
Simulation time 4427401947 ps
CPU time 119.13 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 205032 kb
Host smart-2b2b5d77-9eff-46b1-85ce-880da3b368cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11169
62902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1116962902
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2508266555
Short name T1943
Test name
Test status
Simulation time 177791500 ps
CPU time 0.86 seconds
Started Jun 11 12:44:13 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 204732 kb
Host smart-69d03baf-3f07-40f1-87d7-9b51692bb007
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2508266555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2508266555
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1753505250
Short name T347
Test name
Test status
Simulation time 148786813 ps
CPU time 0.81 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204664 kb
Host smart-81c75609-c5a2-4cfb-826b-5c6833835435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
05250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1753505250
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2465537126
Short name T139
Test name
Test status
Simulation time 194103064 ps
CPU time 0.88 seconds
Started Jun 11 12:44:18 PM PDT 24
Finished Jun 11 12:44:21 PM PDT 24
Peak memory 204708 kb
Host smart-ba3abf2a-cecd-4fd9-9e48-bfd305b5de6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24655
37126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2465537126
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2108914617
Short name T1578
Test name
Test status
Simulation time 148899510 ps
CPU time 0.78 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204708 kb
Host smart-a0ebb5b3-3758-4534-8319-cf2ad198b9da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21089
14617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2108914617
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3857807311
Short name T726
Test name
Test status
Simulation time 155278233 ps
CPU time 0.82 seconds
Started Jun 11 12:44:10 PM PDT 24
Finished Jun 11 12:44:11 PM PDT 24
Peak memory 204724 kb
Host smart-43dc36e8-8c9a-4a4d-9c46-81bbd420f89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38578
07311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3857807311
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2446727482
Short name T1430
Test name
Test status
Simulation time 152477782 ps
CPU time 0.75 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:37 PM PDT 24
Peak memory 204716 kb
Host smart-0f09abae-9028-4e44-a9b6-5f6394170694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24467
27482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2446727482
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.4066739750
Short name T1062
Test name
Test status
Simulation time 169586371 ps
CPU time 0.76 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 204768 kb
Host smart-bf793ab3-5abd-4deb-ba62-3a6749b1350c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40667
39750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.4066739750
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_eop_single_bit_handling.2369609481
Short name T2112
Test name
Test status
Simulation time 192029307 ps
CPU time 0.85 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204736 kb
Host smart-205031e0-c3b5-4407-86cb-3a2f232d7ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23696
09481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_eop_single_bit_handling.2369609481
Directory /workspace/44.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3152838317
Short name T1338
Test name
Test status
Simulation time 157718700 ps
CPU time 0.82 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:24 PM PDT 24
Peak memory 204672 kb
Host smart-7481dd48-757f-469c-a143-f1fa78583c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31528
38317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3152838317
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1781936385
Short name T1119
Test name
Test status
Simulation time 29786781 ps
CPU time 0.65 seconds
Started Jun 11 12:44:26 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204664 kb
Host smart-0438524a-fb8e-4c45-ba5e-fb53e7ad470c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17819
36385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1781936385
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2931484056
Short name T1579
Test name
Test status
Simulation time 18113355926 ps
CPU time 40.1 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 204988 kb
Host smart-9316ffb5-33a8-4dbc-82a1-19cc4b6e0d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29314
84056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2931484056
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.869198708
Short name T57
Test name
Test status
Simulation time 259111941 ps
CPU time 0.9 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:44:26 PM PDT 24
Peak memory 204740 kb
Host smart-f120c2b0-04a6-4893-88ca-0a855a442684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86919
8708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.869198708
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.3387841007
Short name T1007
Test name
Test status
Simulation time 212107481 ps
CPU time 0.87 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:15 PM PDT 24
Peak memory 204672 kb
Host smart-524df110-e9ec-4a00-8d8b-e8a3017fbe98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33878
41007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.3387841007
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1587774383
Short name T873
Test name
Test status
Simulation time 172054351 ps
CPU time 0.76 seconds
Started Jun 11 12:44:20 PM PDT 24
Finished Jun 11 12:44:23 PM PDT 24
Peak memory 204716 kb
Host smart-3cd48f51-ddee-4308-b5ae-6af71e9b0ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15877
74383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1587774383
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3000904436
Short name T712
Test name
Test status
Simulation time 194738850 ps
CPU time 0.86 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204756 kb
Host smart-837586c2-8bcf-4992-8861-8431758b4cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009
04436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3000904436
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.852909054
Short name T1587
Test name
Test status
Simulation time 145015598 ps
CPU time 0.74 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204576 kb
Host smart-de0b84f7-8edc-4288-8b9f-d9bbaceb47e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85290
9054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.852909054
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.264155258
Short name T1026
Test name
Test status
Simulation time 168345078 ps
CPU time 0.78 seconds
Started Jun 11 12:44:24 PM PDT 24
Finished Jun 11 12:44:27 PM PDT 24
Peak memory 204628 kb
Host smart-e61863a2-b855-4dd2-bd4f-7d2744de37a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415
5258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.264155258
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.242562198
Short name T990
Test name
Test status
Simulation time 150963644 ps
CPU time 0.77 seconds
Started Jun 11 12:44:28 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204740 kb
Host smart-43cc510d-1a17-498e-8325-c7109c0bd2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24256
2198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.242562198
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.10099370
Short name T1725
Test name
Test status
Simulation time 200012552 ps
CPU time 0.88 seconds
Started Jun 11 12:44:11 PM PDT 24
Finished Jun 11 12:44:13 PM PDT 24
Peak memory 204740 kb
Host smart-e91df625-401e-4b9b-b5be-488cf2a2c743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10099
370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.10099370
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.953789002
Short name T916
Test name
Test status
Simulation time 189276210 ps
CPU time 0.93 seconds
Started Jun 11 12:44:33 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 204704 kb
Host smart-1d0edce9-cda7-4c0c-b11e-56f7e944589d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95378
9002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.953789002
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1459817021
Short name T953
Test name
Test status
Simulation time 181372808 ps
CPU time 0.82 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 204776 kb
Host smart-8eb9809e-94f9-4f37-a9f9-736cbe879cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14598
17021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1459817021
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2646003200
Short name T613
Test name
Test status
Simulation time 12196005854 ps
CPU time 113.4 seconds
Started Jun 11 12:44:29 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 204972 kb
Host smart-5ca59c8b-30e2-4dcf-b84f-745dcd158b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26460
03200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2646003200
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.298513241
Short name T591
Test name
Test status
Simulation time 3458718894 ps
CPU time 4.29 seconds
Started Jun 11 12:44:23 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 205236 kb
Host smart-b438bc3d-32e4-4dd8-b8bb-9668ad728a00
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=298513241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.298513241
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2190933457
Short name T1866
Test name
Test status
Simulation time 13370072792 ps
CPU time 15.01 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:37 PM PDT 24
Peak memory 204800 kb
Host smart-318d5e94-954b-45c7-b22b-a13fb7e41bd4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2190933457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2190933457
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2030702993
Short name T950
Test name
Test status
Simulation time 23380803418 ps
CPU time 26.18 seconds
Started Jun 11 12:44:40 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 205104 kb
Host smart-ebfe7d05-a71d-4465-bd64-fbefaa7d97b3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2030702993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.2030702993
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4102071616
Short name T902
Test name
Test status
Simulation time 156800349 ps
CPU time 0.73 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204684 kb
Host smart-3703dea4-a5d2-44f2-bfa9-862d64fc6878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41020
71616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4102071616
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1453546734
Short name T895
Test name
Test status
Simulation time 1293930486 ps
CPU time 2.76 seconds
Started Jun 11 12:44:28 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204972 kb
Host smart-09419596-4e4b-4495-9649-1f07240c2c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14535
46734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1453546734
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.3722713230
Short name T562
Test name
Test status
Simulation time 139234588 ps
CPU time 0.75 seconds
Started Jun 11 12:44:25 PM PDT 24
Finished Jun 11 12:44:28 PM PDT 24
Peak memory 204652 kb
Host smart-6ddb6c5b-ff5c-4eea-9c6a-534462f4bf8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37227
13230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3722713230
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2420566200
Short name T858
Test name
Test status
Simulation time 51783241 ps
CPU time 0.66 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204716 kb
Host smart-80478733-e653-4d87-bde6-416924a45c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24205
66200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2420566200
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1850073669
Short name T949
Test name
Test status
Simulation time 794991400 ps
CPU time 2.01 seconds
Started Jun 11 12:44:43 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204920 kb
Host smart-605de970-62a8-4208-835c-8308e5bae75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
73669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1850073669
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1244811643
Short name T389
Test name
Test status
Simulation time 262794498 ps
CPU time 1.32 seconds
Started Jun 11 12:44:14 PM PDT 24
Finished Jun 11 12:44:16 PM PDT 24
Peak memory 204912 kb
Host smart-1d881362-eb28-4793-8640-b475786de8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
11643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1244811643
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.44163099
Short name T1953
Test name
Test status
Simulation time 211933096 ps
CPU time 0.82 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 204744 kb
Host smart-45802232-6af9-4ca0-9eff-759beed474c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44163
099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.44163099
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2723573331
Short name T1452
Test name
Test status
Simulation time 165934582 ps
CPU time 0.77 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204604 kb
Host smart-80c30bed-2424-4e3f-a011-f4358029ffde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27235
73331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2723573331
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2582228672
Short name T703
Test name
Test status
Simulation time 323176246 ps
CPU time 1.04 seconds
Started Jun 11 12:44:18 PM PDT 24
Finished Jun 11 12:44:21 PM PDT 24
Peak memory 204724 kb
Host smart-c0d898ae-834f-41e3-b236-3aeb66c7e445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25822
28672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2582228672
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3672784142
Short name T1807
Test name
Test status
Simulation time 251097852 ps
CPU time 0.93 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204728 kb
Host smart-31678ae5-972b-4833-8897-4859487058e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36727
84142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3672784142
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3411173834
Short name T495
Test name
Test status
Simulation time 3344267192 ps
CPU time 4.17 seconds
Started Jun 11 12:44:29 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204720 kb
Host smart-afa8da0b-73e0-48a2-93ec-19cfc4652c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34111
73834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3411173834
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2605509290
Short name T501
Test name
Test status
Simulation time 237271705 ps
CPU time 0.9 seconds
Started Jun 11 12:44:51 PM PDT 24
Finished Jun 11 12:44:53 PM PDT 24
Peak memory 204720 kb
Host smart-2d0c0f72-f0f2-4e83-967e-3fb5b8ae4829
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2605509290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2605509290
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3594020798
Short name T1903
Test name
Test status
Simulation time 198622593 ps
CPU time 0.84 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:44:22 PM PDT 24
Peak memory 204756 kb
Host smart-6bb644b1-2cc0-40b8-9bde-79ff7f37b73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35940
20798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3594020798
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.4120461404
Short name T2098
Test name
Test status
Simulation time 4756827820 ps
CPU time 45.88 seconds
Started Jun 11 12:44:19 PM PDT 24
Finished Jun 11 12:45:13 PM PDT 24
Peak memory 204892 kb
Host smart-59fb49d0-b5ce-4299-97e7-48eb7ada4c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41204
61404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.4120461404
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2285036268
Short name T629
Test name
Test status
Simulation time 177536734 ps
CPU time 0.82 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204712 kb
Host smart-c50cd843-31b8-4fca-b98a-b7c17efb689b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2285036268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2285036268
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.259345442
Short name T839
Test name
Test status
Simulation time 196522777 ps
CPU time 0.8 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204708 kb
Host smart-1663daf5-8e66-469b-b5cd-23ac30b66d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
5442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.259345442
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1158464049
Short name T1459
Test name
Test status
Simulation time 185192636 ps
CPU time 0.83 seconds
Started Jun 11 12:44:26 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204732 kb
Host smart-d565e433-7a9c-4297-9456-f456944e77b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11584
64049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1158464049
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3869353096
Short name T1572
Test name
Test status
Simulation time 183108916 ps
CPU time 0.83 seconds
Started Jun 11 12:44:09 PM PDT 24
Finished Jun 11 12:44:11 PM PDT 24
Peak memory 204716 kb
Host smart-76d9ab2b-fe65-4c05-9c37-e5b2a654c7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38693
53096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3869353096
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3442124886
Short name T770
Test name
Test status
Simulation time 189073153 ps
CPU time 0.8 seconds
Started Jun 11 12:44:21 PM PDT 24
Finished Jun 11 12:44:25 PM PDT 24
Peak memory 204740 kb
Host smart-4598f92f-2ec6-4e25-9d43-455b059c513e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34421
24886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3442124886
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2194836084
Short name T2109
Test name
Test status
Simulation time 179012206 ps
CPU time 0.84 seconds
Started Jun 11 12:44:15 PM PDT 24
Finished Jun 11 12:44:18 PM PDT 24
Peak memory 204752 kb
Host smart-11fa0672-2116-4e7a-9b52-630908380030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21948
36084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2194836084
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1474334572
Short name T2069
Test name
Test status
Simulation time 156480224 ps
CPU time 0.77 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:40 PM PDT 24
Peak memory 204688 kb
Host smart-045c0507-57f3-47ca-bf24-3eadf94e3bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14743
34572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1474334572
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_eop_single_bit_handling.3547594829
Short name T763
Test name
Test status
Simulation time 183922350 ps
CPU time 0.83 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204704 kb
Host smart-a844a161-d6c4-4596-a9fd-479e71ff17b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35475
94829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_eop_single_bit_handling.3547594829
Directory /workspace/45.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2697325448
Short name T1883
Test name
Test status
Simulation time 142935410 ps
CPU time 0.71 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:55 PM PDT 24
Peak memory 204608 kb
Host smart-d213da7a-44e7-4db1-bb97-18e92fd8296d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26973
25448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2697325448
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.492103044
Short name T44
Test name
Test status
Simulation time 45114538 ps
CPU time 0.66 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204732 kb
Host smart-8506de9b-4f60-44fb-afb5-a17e2765f964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49210
3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.492103044
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2104226028
Short name T1256
Test name
Test status
Simulation time 9088269246 ps
CPU time 19.32 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:54 PM PDT 24
Peak memory 205104 kb
Host smart-2903d444-bb15-485b-b7d9-6fa4232c8145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21042
26028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2104226028
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2270483840
Short name T338
Test name
Test status
Simulation time 233622805 ps
CPU time 0.85 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:37 PM PDT 24
Peak memory 204736 kb
Host smart-5d8da320-1efe-42a2-b8e3-9b09f324b21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22704
83840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2270483840
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.2814113064
Short name T454
Test name
Test status
Simulation time 166469043 ps
CPU time 0.82 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:37 PM PDT 24
Peak memory 204776 kb
Host smart-f39d2b38-7bdc-4c69-b223-235671ea7346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
13064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2814113064
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.4136219003
Short name T1995
Test name
Test status
Simulation time 176710105 ps
CPU time 0.78 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 204700 kb
Host smart-82cfa0f6-2bc8-4156-9731-45b6dc4a8a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41362
19003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.4136219003
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3816826574
Short name T998
Test name
Test status
Simulation time 175072816 ps
CPU time 0.88 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204628 kb
Host smart-255cb95b-7c85-4a01-b25c-b151f4c810ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38168
26574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3816826574
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2158718918
Short name T1262
Test name
Test status
Simulation time 153008325 ps
CPU time 0.74 seconds
Started Jun 11 12:44:17 PM PDT 24
Finished Jun 11 12:44:19 PM PDT 24
Peak memory 204704 kb
Host smart-d820ee01-2eb5-479e-8311-ce5c4860b8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21587
18918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2158718918
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3747070942
Short name T631
Test name
Test status
Simulation time 160925033 ps
CPU time 0.83 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204732 kb
Host smart-30980f94-dea5-4deb-8ba9-7b353ce255e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37470
70942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3747070942
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1237423919
Short name T395
Test name
Test status
Simulation time 148214183 ps
CPU time 0.76 seconds
Started Jun 11 12:44:26 PM PDT 24
Finished Jun 11 12:44:29 PM PDT 24
Peak memory 204712 kb
Host smart-36392aea-a045-48bd-a0ea-aea8b47878fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12374
23919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1237423919
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.477266645
Short name T1975
Test name
Test status
Simulation time 198212913 ps
CPU time 0.85 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204704 kb
Host smart-1a460318-965e-477f-8c5a-544397843227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47726
6645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.477266645
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1363030071
Short name T644
Test name
Test status
Simulation time 183320409 ps
CPU time 0.81 seconds
Started Jun 11 12:44:40 PM PDT 24
Finished Jun 11 12:44:43 PM PDT 24
Peak memory 204692 kb
Host smart-5a09cc24-3a5b-4a77-966e-b4196b067cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
30071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1363030071
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.321052570
Short name T597
Test name
Test status
Simulation time 171803271 ps
CPU time 0.83 seconds
Started Jun 11 12:44:16 PM PDT 24
Finished Jun 11 12:44:18 PM PDT 24
Peak memory 204720 kb
Host smart-46ab53f6-a364-4450-b5d5-1060835f6f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32105
2570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.321052570
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1661182893
Short name T1385
Test name
Test status
Simulation time 12541101960 ps
CPU time 88.66 seconds
Started Jun 11 12:44:13 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 204944 kb
Host smart-7f05086c-a305-4986-8fc7-9fd16b0015b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16611
82893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1661182893
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.465530661
Short name T1546
Test name
Test status
Simulation time 3602038540 ps
CPU time 4.32 seconds
Started Jun 11 12:44:37 PM PDT 24
Finished Jun 11 12:44:43 PM PDT 24
Peak memory 204816 kb
Host smart-fdb35374-7af6-44c4-a1ed-5c335474c138
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=465530661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.465530661
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3026936899
Short name T1140
Test name
Test status
Simulation time 13468800048 ps
CPU time 13.36 seconds
Started Jun 11 12:44:31 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204824 kb
Host smart-b793cb56-b153-44e4-9f87-a0e104ac9ee8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026936899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3026936899
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.745418951
Short name T1584
Test name
Test status
Simulation time 23406614123 ps
CPU time 23.92 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:45:05 PM PDT 24
Peak memory 204772 kb
Host smart-c4e14fb3-5d7e-4016-9130-628012a2d188
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=745418951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.745418951
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1568478584
Short name T460
Test name
Test status
Simulation time 141933644 ps
CPU time 0.78 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204692 kb
Host smart-5f3858dd-7860-4d57-86b7-73cddbf6df61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15684
78584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1568478584
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1915946943
Short name T1762
Test name
Test status
Simulation time 153969921 ps
CPU time 0.76 seconds
Started Jun 11 12:44:49 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 204700 kb
Host smart-da66f368-253f-4aa2-9818-30863eb7d7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19159
46943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1915946943
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1232364102
Short name T1242
Test name
Test status
Simulation time 1481310950 ps
CPU time 3.13 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204940 kb
Host smart-d40d4dc6-35e7-4e80-a8a9-9d1cbb60a279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12323
64102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1232364102
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1084565057
Short name T1227
Test name
Test status
Simulation time 154145172 ps
CPU time 0.75 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204624 kb
Host smart-6463459d-0727-4d7b-bcaf-22f3a8c43741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10845
65057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1084565057
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.281818258
Short name T701
Test name
Test status
Simulation time 52170186 ps
CPU time 0.69 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204680 kb
Host smart-3f930757-a1c6-4f78-adfa-0ec4263a9e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
8258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.281818258
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3064536309
Short name T496
Test name
Test status
Simulation time 842456576 ps
CPU time 2.03 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 205184 kb
Host smart-6daa0c43-2b87-4911-b118-9b8353264672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30645
36309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3064536309
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3562285864
Short name T767
Test name
Test status
Simulation time 345122693 ps
CPU time 2.08 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204908 kb
Host smart-feb3e3b3-e139-4d60-8204-d1c22fad50d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622
85864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3562285864
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.216941672
Short name T81
Test name
Test status
Simulation time 188392476 ps
CPU time 0.86 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 204732 kb
Host smart-80c13e50-a204-4c9e-881e-5ba6b3714199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21694
1672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.216941672
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3563420877
Short name T1237
Test name
Test status
Simulation time 156174721 ps
CPU time 0.78 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204636 kb
Host smart-17c98e3b-3024-4ddb-a815-ac8c4b99b08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
20877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3563420877
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3098957374
Short name T1736
Test name
Test status
Simulation time 249622866 ps
CPU time 0.93 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204684 kb
Host smart-a80cb865-c33d-48b0-9108-aa02ed58af82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30989
57374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3098957374
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3414396845
Short name T1729
Test name
Test status
Simulation time 210389624 ps
CPU time 0.83 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204684 kb
Host smart-32098f16-e306-4582-baa0-2892660eebd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34143
96845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3414396845
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2556283191
Short name T2099
Test name
Test status
Simulation time 3321303406 ps
CPU time 3.71 seconds
Started Jun 11 12:44:42 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204756 kb
Host smart-937ee3d5-a849-4e65-89a2-bc1fb8fab966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25562
83191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2556283191
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.385696688
Short name T800
Test name
Test status
Simulation time 236209338 ps
CPU time 0.86 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204752 kb
Host smart-090ca6b9-bda5-4d8e-a763-69e3eabb0852
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=385696688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.385696688
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.974282737
Short name T1491
Test name
Test status
Simulation time 188321155 ps
CPU time 0.84 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:44:37 PM PDT 24
Peak memory 204736 kb
Host smart-b5a7b1ad-7628-474b-bdce-7ff8b2b2bff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97428
2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.974282737
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3406555705
Short name T2108
Test name
Test status
Simulation time 11692590795 ps
CPU time 79.04 seconds
Started Jun 11 12:44:22 PM PDT 24
Finished Jun 11 12:45:44 PM PDT 24
Peak memory 205024 kb
Host smart-0c6d54f5-12a6-4153-8ab4-357a0647a037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34065
55705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3406555705
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2203655298
Short name T29
Test name
Test status
Simulation time 161904078 ps
CPU time 0.78 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204740 kb
Host smart-7b982454-8b33-4f32-bd7b-d2293efef308
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2203655298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2203655298
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3010701724
Short name T377
Test name
Test status
Simulation time 182623005 ps
CPU time 0.79 seconds
Started Jun 11 12:44:47 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 204740 kb
Host smart-871dfa36-181b-4b89-b3c9-86ab276830a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30107
01724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3010701724
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.183528312
Short name T155
Test name
Test status
Simulation time 221248514 ps
CPU time 0.87 seconds
Started Jun 11 12:44:40 PM PDT 24
Finished Jun 11 12:44:43 PM PDT 24
Peak memory 204656 kb
Host smart-cf424a60-9261-41ed-8c41-e01aff662a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352
8312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.183528312
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2338178632
Short name T1715
Test name
Test status
Simulation time 176686212 ps
CPU time 0.83 seconds
Started Jun 11 12:44:31 PM PDT 24
Finished Jun 11 12:44:34 PM PDT 24
Peak memory 204736 kb
Host smart-912969c6-3cca-476c-879f-5d254b439bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23381
78632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2338178632
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2095019097
Short name T2118
Test name
Test status
Simulation time 170682430 ps
CPU time 0.78 seconds
Started Jun 11 12:44:51 PM PDT 24
Finished Jun 11 12:44:53 PM PDT 24
Peak memory 204664 kb
Host smart-757bdfb6-aa25-4ae7-90fd-48d24421738f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
19097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2095019097
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3452232792
Short name T43
Test name
Test status
Simulation time 189694073 ps
CPU time 0.81 seconds
Started Jun 11 12:44:42 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 204612 kb
Host smart-5b379340-3ccf-48de-aaec-4386bd98d334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34522
32792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3452232792
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.2275651624
Short name T1281
Test name
Test status
Simulation time 154733016 ps
CPU time 0.81 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 204752 kb
Host smart-c9fa637d-ec54-41f6-bcc0-9b5a5ee547c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
51624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.2275651624
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_eop_single_bit_handling.1743728511
Short name T1804
Test name
Test status
Simulation time 179376837 ps
CPU time 0.81 seconds
Started Jun 11 12:44:37 PM PDT 24
Finished Jun 11 12:44:40 PM PDT 24
Peak memory 204676 kb
Host smart-eddf3edf-d336-4139-945b-0979433542bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17437
28511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_eop_single_bit_handling.1743728511
Directory /workspace/46.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.234392309
Short name T877
Test name
Test status
Simulation time 140004639 ps
CPU time 0.75 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204704 kb
Host smart-2fe8e22b-4e41-4c20-bcf8-5503aade2b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23439
2309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.234392309
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3252382468
Short name T765
Test name
Test status
Simulation time 47935999 ps
CPU time 0.65 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204724 kb
Host smart-f514ada7-9249-4ec3-b661-4c35074c89b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32523
82468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3252382468
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1024857144
Short name T499
Test name
Test status
Simulation time 9809637861 ps
CPU time 20.9 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:58 PM PDT 24
Peak memory 204932 kb
Host smart-d529a5fe-c3a7-4a11-98c8-793272b994ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
57144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1024857144
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.4146456940
Short name T2045
Test name
Test status
Simulation time 173413016 ps
CPU time 0.8 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204744 kb
Host smart-b0335952-8741-42ce-8c40-4343ca46572d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
56940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4146456940
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4150862568
Short name T2088
Test name
Test status
Simulation time 232516704 ps
CPU time 0.98 seconds
Started Jun 11 12:44:31 PM PDT 24
Finished Jun 11 12:44:34 PM PDT 24
Peak memory 204692 kb
Host smart-49e62dcc-4707-4e4f-b9c1-41d211f5ba24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41508
62568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4150862568
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2539817403
Short name T1002
Test name
Test status
Simulation time 244333624 ps
CPU time 0.94 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:39 PM PDT 24
Peak memory 204716 kb
Host smart-e7ff8f16-d951-4687-92a6-3641205accd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25398
17403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2539817403
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.933388536
Short name T1212
Test name
Test status
Simulation time 195211615 ps
CPU time 0.89 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204744 kb
Host smart-29e785e0-7d01-4a29-9055-97e766867445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93338
8536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.933388536
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.1074566835
Short name T1952
Test name
Test status
Simulation time 140148187 ps
CPU time 0.78 seconds
Started Jun 11 12:44:40 PM PDT 24
Finished Jun 11 12:44:43 PM PDT 24
Peak memory 204680 kb
Host smart-d00fc860-71f8-4d5f-b50a-b79e0cccecd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10745
66835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1074566835
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3551974644
Short name T76
Test name
Test status
Simulation time 152160153 ps
CPU time 0.74 seconds
Started Jun 11 12:44:40 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 204728 kb
Host smart-acea50d9-8752-4d8f-9e7a-8652c6ead840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
74644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3551974644
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1075308108
Short name T1413
Test name
Test status
Simulation time 184108898 ps
CPU time 0.8 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204716 kb
Host smart-2a452d91-6d69-4348-b7d0-d53b4cc5c7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10753
08108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1075308108
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1285875754
Short name T1121
Test name
Test status
Simulation time 226800007 ps
CPU time 0.9 seconds
Started Jun 11 12:44:27 PM PDT 24
Finished Jun 11 12:44:30 PM PDT 24
Peak memory 204744 kb
Host smart-c1acee8f-6d26-4220-b323-87d9da75f368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12858
75754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1285875754
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.706922461
Short name T721
Test name
Test status
Simulation time 210250270 ps
CPU time 0.81 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204724 kb
Host smart-2a81be75-1618-4212-a0ed-a335bf70bde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70692
2461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.706922461
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.98139540
Short name T1013
Test name
Test status
Simulation time 178269130 ps
CPU time 0.81 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204716 kb
Host smart-842d2bab-56db-48bb-a28e-6f751ecc4d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98139
540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.98139540
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.674733151
Short name T98
Test name
Test status
Simulation time 13292294146 ps
CPU time 96.07 seconds
Started Jun 11 12:44:52 PM PDT 24
Finished Jun 11 12:46:30 PM PDT 24
Peak memory 204948 kb
Host smart-3aa8453c-9343-4fbf-88bf-d143fe2644eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67473
3151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.674733151
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2279593375
Short name T1051
Test name
Test status
Simulation time 3461615029 ps
CPU time 4.08 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 204784 kb
Host smart-ce482858-f708-48e0-800c-f5ce41a2476d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2279593375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2279593375
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.474380472
Short name T7
Test name
Test status
Simulation time 13352725622 ps
CPU time 12.49 seconds
Started Jun 11 12:44:36 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 204792 kb
Host smart-9b348dc1-cacc-4a68-b399-00aaaf50c459
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=474380472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.474380472
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2701601265
Short name T1979
Test name
Test status
Simulation time 23346724184 ps
CPU time 25.93 seconds
Started Jun 11 12:44:43 PM PDT 24
Finished Jun 11 12:45:11 PM PDT 24
Peak memory 204920 kb
Host smart-c7a62946-7755-4d5b-94d9-5dd8a01f5057
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2701601265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2701601265
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3364650996
Short name T1984
Test name
Test status
Simulation time 157429321 ps
CPU time 0.77 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204776 kb
Host smart-3e9ff050-e361-4390-b217-3ccfce47837d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33646
50996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3364650996
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1621495169
Short name T130
Test name
Test status
Simulation time 156236006 ps
CPU time 0.76 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 204688 kb
Host smart-4597179d-bf0b-4545-929d-a1f1ee524f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16214
95169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1621495169
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2376722462
Short name T878
Test name
Test status
Simulation time 185536702 ps
CPU time 0.78 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204648 kb
Host smart-b35ae365-a962-4e78-8a04-f813b7af1e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23767
22462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2376722462
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1263557554
Short name T2116
Test name
Test status
Simulation time 88741443 ps
CPU time 0.71 seconds
Started Jun 11 12:44:36 PM PDT 24
Finished Jun 11 12:44:39 PM PDT 24
Peak memory 204740 kb
Host smart-e5c3a8b0-426c-4a83-9f3c-a327f12bc348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12635
57554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1263557554
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3769110867
Short name T390
Test name
Test status
Simulation time 916619799 ps
CPU time 2.1 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204932 kb
Host smart-1a1d3381-0d34-4638-8fd6-11e042cd4cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37691
10867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3769110867
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3667918334
Short name T1823
Test name
Test status
Simulation time 211666113 ps
CPU time 2.22 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 204888 kb
Host smart-0e8df29c-0f4d-4c02-bd3d-c670d5a79138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36679
18334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3667918334
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1866643849
Short name T934
Test name
Test status
Simulation time 262394721 ps
CPU time 0.89 seconds
Started Jun 11 12:44:57 PM PDT 24
Finished Jun 11 12:45:00 PM PDT 24
Peak memory 204716 kb
Host smart-1bd74b6e-d814-4360-9f5b-6eb79827d2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18666
43849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1866643849
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1789686712
Short name T862
Test name
Test status
Simulation time 143596052 ps
CPU time 0.77 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:44:47 PM PDT 24
Peak memory 204712 kb
Host smart-6526abb8-4546-437d-99ea-663eeb380628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17896
86712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1789686712
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2878920893
Short name T1738
Test name
Test status
Simulation time 209932510 ps
CPU time 0.88 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:44:56 PM PDT 24
Peak memory 204704 kb
Host smart-8c4f1229-ae4e-4269-bb5e-6e53c768353d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
20893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2878920893
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.4156768521
Short name T678
Test name
Test status
Simulation time 224772231 ps
CPU time 0.88 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204608 kb
Host smart-70a0572b-6845-4ebf-9ea1-df72fa548f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
68521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.4156768521
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.881144846
Short name T1888
Test name
Test status
Simulation time 3340471761 ps
CPU time 4.45 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 205044 kb
Host smart-e5d96be4-5643-4ab1-b992-6b0ce3e06e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88114
4846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.881144846
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.928916722
Short name T704
Test name
Test status
Simulation time 235338643 ps
CPU time 0.95 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204668 kb
Host smart-edcc1095-dc8c-410c-8df9-c171b82d253a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=928916722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.928916722
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.71135741
Short name T518
Test name
Test status
Simulation time 192313953 ps
CPU time 0.83 seconds
Started Jun 11 12:44:31 PM PDT 24
Finished Jun 11 12:44:33 PM PDT 24
Peak memory 204676 kb
Host smart-8bcf6c7f-9a4e-4499-931c-2a467a4a30c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71135
741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.71135741
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2275655445
Short name T1523
Test name
Test status
Simulation time 15289252119 ps
CPU time 431.91 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:51:48 PM PDT 24
Peak memory 204964 kb
Host smart-f995284f-2df9-4256-beaf-0c48fb875576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
55445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2275655445
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3914924710
Short name T1113
Test name
Test status
Simulation time 161178131 ps
CPU time 0.82 seconds
Started Jun 11 12:44:40 PM PDT 24
Finished Jun 11 12:44:43 PM PDT 24
Peak memory 204656 kb
Host smart-d613eaf6-e4d8-4c6c-b2bb-97c66afdc118
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3914924710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3914924710
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4229351274
Short name T1930
Test name
Test status
Simulation time 157814619 ps
CPU time 0.76 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204680 kb
Host smart-60ae9188-db9c-49a8-b0c4-989155c08e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
51274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4229351274
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2520915977
Short name T143
Test name
Test status
Simulation time 208879096 ps
CPU time 0.87 seconds
Started Jun 11 12:44:42 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 204688 kb
Host smart-c1f83d4f-366a-4211-8944-fd8d21e5812e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25209
15977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2520915977
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2055725607
Short name T1245
Test name
Test status
Simulation time 189338585 ps
CPU time 0.79 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204668 kb
Host smart-39f5cdc2-b24f-42f9-a559-41a28d9a0936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
25607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2055725607
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2886965080
Short name T924
Test name
Test status
Simulation time 186700854 ps
CPU time 0.83 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204728 kb
Host smart-6e356650-fce8-45a7-8345-b2552a9ad8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
65080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2886965080
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3340829518
Short name T1770
Test name
Test status
Simulation time 178600014 ps
CPU time 0.82 seconds
Started Jun 11 12:44:30 PM PDT 24
Finished Jun 11 12:44:32 PM PDT 24
Peak memory 204668 kb
Host smart-47c6e7c7-4b20-4c53-adda-f38628c592f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33408
29518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3340829518
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.2410427663
Short name T1825
Test name
Test status
Simulation time 158433224 ps
CPU time 0.75 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204732 kb
Host smart-a44ccee0-27b1-4695-8e64-4eed0ab91c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24104
27663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.2410427663
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_eop_single_bit_handling.4186153156
Short name T1390
Test name
Test status
Simulation time 227911752 ps
CPU time 0.96 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 204712 kb
Host smart-85c3799d-ea9b-4571-9e6a-4d8a5a5abd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41861
53156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_eop_single_bit_handling.4186153156
Directory /workspace/47.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1267899116
Short name T26
Test name
Test status
Simulation time 40523960 ps
CPU time 0.64 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204692 kb
Host smart-d926041a-59f0-442f-9042-fc8814c81ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12678
99116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1267899116
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2388927612
Short name T1176
Test name
Test status
Simulation time 12637814418 ps
CPU time 25.91 seconds
Started Jun 11 12:44:50 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 204968 kb
Host smart-86c37973-cfc2-41c9-8bfe-eae2413f9dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889
27612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2388927612
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3233097718
Short name T443
Test name
Test status
Simulation time 167868111 ps
CPU time 0.81 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:56 PM PDT 24
Peak memory 204776 kb
Host smart-ce32f315-7d0a-4062-b5ea-ff9c6eca5032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32330
97718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3233097718
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2357610684
Short name T1749
Test name
Test status
Simulation time 227547203 ps
CPU time 0.87 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 204636 kb
Host smart-2ac31a19-62ac-4e53-9a13-2f91afaf7550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23576
10684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2357610684
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2949193816
Short name T1684
Test name
Test status
Simulation time 207930324 ps
CPU time 0.88 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204736 kb
Host smart-f65d28ac-283a-4d19-b7e2-2223d0d88fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29491
93816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2949193816
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3818530915
Short name T1568
Test name
Test status
Simulation time 155857848 ps
CPU time 0.79 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:00 PM PDT 24
Peak memory 204524 kb
Host smart-088b0c00-26db-44f9-88c6-849958c9ce85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38185
30915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3818530915
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.549006177
Short name T68
Test name
Test status
Simulation time 147223333 ps
CPU time 0.73 seconds
Started Jun 11 12:44:37 PM PDT 24
Finished Jun 11 12:44:40 PM PDT 24
Peak memory 204748 kb
Host smart-ce11aa18-7862-4f21-a49c-e586d6cba2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54900
6177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.549006177
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2967182495
Short name T1846
Test name
Test status
Simulation time 146764574 ps
CPU time 0.79 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204744 kb
Host smart-f0a73a8e-d21d-4aa6-9f87-0c8b663d8b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29671
82495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2967182495
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3552373368
Short name T1146
Test name
Test status
Simulation time 165598511 ps
CPU time 0.86 seconds
Started Jun 11 12:44:52 PM PDT 24
Finished Jun 11 12:44:55 PM PDT 24
Peak memory 204708 kb
Host smart-2ce6cc48-2878-40d6-aa2e-1b8466cb372a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523
73368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3552373368
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3157182589
Short name T173
Test name
Test status
Simulation time 207565357 ps
CPU time 0.89 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204744 kb
Host smart-be26e659-54fa-41a9-8f14-7cad876fbdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31571
82589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3157182589
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2654287718
Short name T1606
Test name
Test status
Simulation time 180365034 ps
CPU time 0.78 seconds
Started Jun 11 12:44:47 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 204740 kb
Host smart-91ec199b-ad3c-4476-9ec6-61bee4fa70b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26542
87718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2654287718
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1693355342
Short name T1775
Test name
Test status
Simulation time 256357425 ps
CPU time 0.86 seconds
Started Jun 11 12:44:49 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 204648 kb
Host smart-7003e738-a784-4bdb-86f3-59aa5dc2ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933
55342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1693355342
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.907884481
Short name T1451
Test name
Test status
Simulation time 7437818621 ps
CPU time 49.44 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:45:33 PM PDT 24
Peak memory 204924 kb
Host smart-a1d965bf-1723-4bfe-81b1-ffbaa13a031b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90788
4481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.907884481
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1339796165
Short name T1539
Test name
Test status
Simulation time 3712479366 ps
CPU time 4.43 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 204760 kb
Host smart-a66fd226-2ca5-4d98-a30e-2c45713b84f3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1339796165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1339796165
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3491410064
Short name T1733
Test name
Test status
Simulation time 13354894823 ps
CPU time 12.74 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:45:00 PM PDT 24
Peak memory 205004 kb
Host smart-552bec25-6b35-4a50-b484-131523a6a4b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3491410064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3491410064
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.880241013
Short name T8
Test name
Test status
Simulation time 23415922987 ps
CPU time 25.95 seconds
Started Jun 11 12:44:53 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 204968 kb
Host smart-e0f1870e-3c77-489b-88ab-cb675ae0246e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=880241013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.880241013
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1352287305
Short name T1289
Test name
Test status
Simulation time 142861510 ps
CPU time 0.8 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 204668 kb
Host smart-cd38ece2-8553-451e-abc5-e57b38e32833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13522
87305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1352287305
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1457839535
Short name T72
Test name
Test status
Simulation time 199915193 ps
CPU time 0.87 seconds
Started Jun 11 12:44:50 PM PDT 24
Finished Jun 11 12:44:53 PM PDT 24
Peak memory 204672 kb
Host smart-41e07100-33cb-429c-bad4-ae678fd63414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
39535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1457839535
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2655583889
Short name T530
Test name
Test status
Simulation time 383461217 ps
CPU time 1.03 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204752 kb
Host smart-0b4e58ea-fc7c-4894-92e8-39e57cb07a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
83889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2655583889
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3156492096
Short name T1328
Test name
Test status
Simulation time 144163723 ps
CPU time 0.79 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:56 PM PDT 24
Peak memory 204576 kb
Host smart-7657ed7e-4113-4952-805f-49a815b04e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31564
92096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3156492096
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.57236915
Short name T1819
Test name
Test status
Simulation time 87985228 ps
CPU time 0.69 seconds
Started Jun 11 12:44:52 PM PDT 24
Finished Jun 11 12:44:55 PM PDT 24
Peak memory 204600 kb
Host smart-fcae830d-bd0a-491e-b2e6-492bc69b37b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57236
915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.57236915
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3853358113
Short name T989
Test name
Test status
Simulation time 835091025 ps
CPU time 2.03 seconds
Started Jun 11 12:44:51 PM PDT 24
Finished Jun 11 12:44:55 PM PDT 24
Peak memory 205056 kb
Host smart-17a22b42-1543-43e3-b5cf-a96ef601f100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38533
58113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3853358113
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3535937102
Short name T1925
Test name
Test status
Simulation time 304894288 ps
CPU time 1.86 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 204992 kb
Host smart-8ddee791-44fe-43e4-9147-d2d55851b37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35359
37102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3535937102
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2012092202
Short name T1595
Test name
Test status
Simulation time 211634508 ps
CPU time 0.88 seconds
Started Jun 11 12:44:43 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204648 kb
Host smart-bf170971-c09f-4624-9fbd-649994b94039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
92202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2012092202
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2645610073
Short name T1300
Test name
Test status
Simulation time 136404081 ps
CPU time 0.76 seconds
Started Jun 11 12:44:50 PM PDT 24
Finished Jun 11 12:44:53 PM PDT 24
Peak memory 204692 kb
Host smart-2bc156d5-499a-427c-836c-cd15f75f5af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26456
10073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2645610073
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1272861893
Short name T868
Test name
Test status
Simulation time 212737815 ps
CPU time 0.9 seconds
Started Jun 11 12:44:39 PM PDT 24
Finished Jun 11 12:44:42 PM PDT 24
Peak memory 204732 kb
Host smart-3bb21834-b8af-4af6-8ae8-d1105ffa83dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12728
61893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1272861893
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1770442338
Short name T534
Test name
Test status
Simulation time 169163973 ps
CPU time 0.78 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204672 kb
Host smart-159f819d-42a0-48da-84d5-a8bd26e0dab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
42338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1770442338
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3001026467
Short name T633
Test name
Test status
Simulation time 3360740239 ps
CPU time 3.71 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:03 PM PDT 24
Peak memory 204620 kb
Host smart-5a5c18ac-f1ca-4324-9d4d-bfbc6e9f249b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30010
26467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3001026467
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.4111494678
Short name T312
Test name
Test status
Simulation time 291845904 ps
CPU time 0.95 seconds
Started Jun 11 12:45:10 PM PDT 24
Finished Jun 11 12:45:13 PM PDT 24
Peak memory 204704 kb
Host smart-c5647275-98ca-4c14-976b-7db0f727ae07
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4111494678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.4111494678
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2155495234
Short name T1111
Test name
Test status
Simulation time 233170590 ps
CPU time 0.92 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204664 kb
Host smart-6af6f5dc-71da-4857-a40d-cc67e64014b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554
95234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2155495234
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3975813824
Short name T910
Test name
Test status
Simulation time 13735874971 ps
CPU time 126.19 seconds
Started Jun 11 12:44:34 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 204992 kb
Host smart-568c4834-13bb-4c9e-8900-014e34c0284c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39758
13824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3975813824
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.421912026
Short name T1805
Test name
Test status
Simulation time 167512832 ps
CPU time 0.79 seconds
Started Jun 11 12:44:43 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204692 kb
Host smart-6151c185-daea-4f77-9606-16269bfe9d4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=421912026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.421912026
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2683120737
Short name T2063
Test name
Test status
Simulation time 138729450 ps
CPU time 0.74 seconds
Started Jun 11 12:44:43 PM PDT 24
Finished Jun 11 12:44:46 PM PDT 24
Peak memory 204636 kb
Host smart-7270460d-dd10-4888-bd26-a20445603feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26831
20737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2683120737
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2750162607
Short name T1692
Test name
Test status
Simulation time 243450652 ps
CPU time 0.9 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 204980 kb
Host smart-1d3730ba-3502-408c-bf52-fc0fd34e4cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27501
62607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2750162607
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.1835638276
Short name T1665
Test name
Test status
Simulation time 170579742 ps
CPU time 0.82 seconds
Started Jun 11 12:44:52 PM PDT 24
Finished Jun 11 12:44:55 PM PDT 24
Peak memory 204564 kb
Host smart-5250c070-2096-4801-aaa1-2ba61165749f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18356
38276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1835638276
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3352512973
Short name T1331
Test name
Test status
Simulation time 149269633 ps
CPU time 0.76 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204708 kb
Host smart-76d9aaa8-7fbf-4eb1-9c55-d46089cd34ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33525
12973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3352512973
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.349181202
Short name T1950
Test name
Test status
Simulation time 182967678 ps
CPU time 0.79 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 204760 kb
Host smart-278fec9e-c7f7-45c5-a440-96f58f685948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34918
1202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.349181202
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1426209153
Short name T1858
Test name
Test status
Simulation time 156234965 ps
CPU time 0.75 seconds
Started Jun 11 12:44:35 PM PDT 24
Finished Jun 11 12:44:38 PM PDT 24
Peak memory 204752 kb
Host smart-8afbc659-b7ca-4fdb-a769-bfab0ca34ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
09153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1426209153
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_eop_single_bit_handling.1973645143
Short name T774
Test name
Test status
Simulation time 193812791 ps
CPU time 0.84 seconds
Started Jun 11 12:44:51 PM PDT 24
Finished Jun 11 12:44:54 PM PDT 24
Peak memory 204736 kb
Host smart-c6af8bea-f033-45ce-954f-565881e09f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19736
45143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_eop_single_bit_handling.1973645143
Directory /workspace/48.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1280245235
Short name T1850
Test name
Test status
Simulation time 198706598 ps
CPU time 0.74 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:04 PM PDT 24
Peak memory 204760 kb
Host smart-e9469c25-e14c-4549-8381-f69dd1cb4d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12802
45235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1280245235
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3653569399
Short name T887
Test name
Test status
Simulation time 43856596 ps
CPU time 0.66 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204720 kb
Host smart-5d1b3539-d916-49e4-8aef-95ecb0e18335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36535
69399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3653569399
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3462190818
Short name T1068
Test name
Test status
Simulation time 17373796746 ps
CPU time 38.69 seconds
Started Jun 11 12:44:37 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 204988 kb
Host smart-75ba1257-e4ef-4017-9538-61b25fd74c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34621
90818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3462190818
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2523314563
Short name T1937
Test name
Test status
Simulation time 147417362 ps
CPU time 0.76 seconds
Started Jun 11 12:44:32 PM PDT 24
Finished Jun 11 12:44:35 PM PDT 24
Peak memory 204720 kb
Host smart-2b386e3a-6ed9-4dfb-9bbe-9baf8b24a7bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25233
14563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2523314563
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.198926695
Short name T465
Test name
Test status
Simulation time 235767228 ps
CPU time 0.87 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204716 kb
Host smart-460666a7-dc8c-4da5-8cd9-425a2f3fa35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
6695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.198926695
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.820521652
Short name T425
Test name
Test status
Simulation time 173251519 ps
CPU time 0.83 seconds
Started Jun 11 12:44:58 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 204972 kb
Host smart-c894122c-5776-408a-9fcb-b73be788022a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82052
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.820521652
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1349905562
Short name T411
Test name
Test status
Simulation time 186512141 ps
CPU time 0.86 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 204672 kb
Host smart-683f720c-f581-41bb-8049-97d907f2d9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13499
05562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1349905562
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.853407196
Short name T816
Test name
Test status
Simulation time 136472825 ps
CPU time 0.77 seconds
Started Jun 11 12:44:38 PM PDT 24
Finished Jun 11 12:44:41 PM PDT 24
Peak memory 204704 kb
Host smart-ec6d3999-af09-4043-b9c8-c32973a677c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85340
7196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.853407196
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.4000700162
Short name T1511
Test name
Test status
Simulation time 155607317 ps
CPU time 0.77 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:44:58 PM PDT 24
Peak memory 204668 kb
Host smart-14a62e78-3175-4e41-859e-cbb2ee2b9547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007
00162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.4000700162
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2314462182
Short name T2031
Test name
Test status
Simulation time 150748881 ps
CPU time 0.81 seconds
Started Jun 11 12:44:36 PM PDT 24
Finished Jun 11 12:44:39 PM PDT 24
Peak memory 204728 kb
Host smart-f6e4d49d-5f7f-44a9-836a-bb7f6aa38290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23144
62182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2314462182
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2488095593
Short name T1574
Test name
Test status
Simulation time 282222700 ps
CPU time 0.95 seconds
Started Jun 11 12:44:33 PM PDT 24
Finished Jun 11 12:44:36 PM PDT 24
Peak memory 204712 kb
Host smart-ee28ae8f-d6e4-4c77-a971-6cf993ebe589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880
95593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2488095593
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2049722679
Short name T1054
Test name
Test status
Simulation time 158603940 ps
CPU time 0.74 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:44:47 PM PDT 24
Peak memory 204728 kb
Host smart-1ec87524-cc76-4e24-a4a0-62d68c8cc83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20497
22679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2049722679
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.1283703402
Short name T1699
Test name
Test status
Simulation time 161407883 ps
CPU time 0.76 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 204700 kb
Host smart-0e09d7ff-20bd-42a3-9598-142a26b7ae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12837
03402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.1283703402
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3707860954
Short name T374
Test name
Test status
Simulation time 13692626264 ps
CPU time 389.26 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:51:31 PM PDT 24
Peak memory 204980 kb
Host smart-1f6b2fd6-62b6-402d-aaa5-2ecad790c53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37078
60954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3707860954
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.897320944
Short name T1958
Test name
Test status
Simulation time 4122273213 ps
CPU time 4.69 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:07 PM PDT 24
Peak memory 204716 kb
Host smart-b025cbcd-8308-4519-bcc3-159712c158be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=897320944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.897320944
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.4221967207
Short name T2002
Test name
Test status
Simulation time 13305420542 ps
CPU time 16.34 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:45:14 PM PDT 24
Peak memory 204772 kb
Host smart-ae0effd1-9ac3-4580-ab52-ec0589c99c44
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4221967207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.4221967207
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.256222781
Short name T1420
Test name
Test status
Simulation time 23427431555 ps
CPU time 25.34 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:45:23 PM PDT 24
Peak memory 204992 kb
Host smart-f8425900-9024-494f-803c-ead43fe0070c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=256222781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.256222781
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3447442860
Short name T1087
Test name
Test status
Simulation time 161993055 ps
CPU time 0.81 seconds
Started Jun 11 12:45:04 PM PDT 24
Finished Jun 11 12:45:06 PM PDT 24
Peak memory 204700 kb
Host smart-ec03a886-5263-40e9-acc9-ff99859e933e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34474
42860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3447442860
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4290464458
Short name T818
Test name
Test status
Simulation time 146751381 ps
CPU time 0.79 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 204772 kb
Host smart-5b8436f7-3ccb-4151-bf23-86b0b7c2e631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42904
64458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4290464458
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2131695456
Short name T1022
Test name
Test status
Simulation time 1130623226 ps
CPU time 2.43 seconds
Started Jun 11 12:44:47 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 204944 kb
Host smart-d5083925-a077-4d08-b622-b5869fa66cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21316
95456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2131695456
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2529875722
Short name T1629
Test name
Test status
Simulation time 150360362 ps
CPU time 0.76 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204648 kb
Host smart-8c7a17d6-716b-449b-8aab-72c3af4fb8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25298
75722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2529875722
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2611332806
Short name T792
Test name
Test status
Simulation time 48178829 ps
CPU time 0.62 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:44:47 PM PDT 24
Peak memory 204756 kb
Host smart-be50e511-c4bd-4648-a4d4-fdaa2f61e1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26113
32806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2611332806
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3460741444
Short name T2094
Test name
Test status
Simulation time 1050648932 ps
CPU time 2.59 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204884 kb
Host smart-fb154723-fd89-45cd-b091-66c958dc123f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
41444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3460741444
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2801052853
Short name T687
Test name
Test status
Simulation time 282144222 ps
CPU time 1.57 seconds
Started Jun 11 12:44:41 PM PDT 24
Finished Jun 11 12:44:44 PM PDT 24
Peak memory 204948 kb
Host smart-93e5d897-5fbc-4f6f-923e-6ffdb765c7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28010
52853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2801052853
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.682581164
Short name T458
Test name
Test status
Simulation time 226230404 ps
CPU time 0.82 seconds
Started Jun 11 12:44:56 PM PDT 24
Finished Jun 11 12:44:58 PM PDT 24
Peak memory 204656 kb
Host smart-0ac38b52-7915-4032-91ee-e159fc14cb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68258
1164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.682581164
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1545697089
Short name T2040
Test name
Test status
Simulation time 134394803 ps
CPU time 0.75 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 204736 kb
Host smart-ceb16f86-a1e6-4680-8807-eadc47c1e2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15456
97089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1545697089
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2093340249
Short name T1219
Test name
Test status
Simulation time 248265588 ps
CPU time 0.92 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:01 PM PDT 24
Peak memory 204700 kb
Host smart-29119e8d-5895-4566-bd1d-427dba401cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20933
40249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2093340249
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3591723490
Short name T1771
Test name
Test status
Simulation time 220414862 ps
CPU time 0.85 seconds
Started Jun 11 12:44:43 PM PDT 24
Finished Jun 11 12:44:47 PM PDT 24
Peak memory 204640 kb
Host smart-8cd48d09-f9d8-4524-8638-4e042728adf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
23490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3591723490
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.26370385
Short name T1494
Test name
Test status
Simulation time 3326914110 ps
CPU time 4 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:54 PM PDT 24
Peak memory 204828 kb
Host smart-4a35b0f5-e5f5-4149-8350-85cc2f718739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26370
385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.26370385
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1415348225
Short name T1322
Test name
Test status
Simulation time 237892729 ps
CPU time 1.05 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 204744 kb
Host smart-d2fd4f14-eea9-4daa-a787-14b24e91bbe2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1415348225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1415348225
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.883058580
Short name T307
Test name
Test status
Simulation time 193350819 ps
CPU time 0.87 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204644 kb
Host smart-5a425514-5976-4b69-acc2-8ebdb3fed904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88305
8580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.883058580
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1186338114
Short name T1726
Test name
Test status
Simulation time 7702292442 ps
CPU time 72.82 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:46:10 PM PDT 24
Peak memory 204916 kb
Host smart-e67d646d-c8b8-4b91-b680-d2e5722923d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11863
38114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1186338114
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2039604449
Short name T441
Test name
Test status
Simulation time 166442050 ps
CPU time 0.83 seconds
Started Jun 11 12:44:54 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 204680 kb
Host smart-d1fa2259-4d2e-431e-809b-8d5782ccee34
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2039604449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2039604449
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3396970669
Short name T1173
Test name
Test status
Simulation time 145801415 ps
CPU time 0.79 seconds
Started Jun 11 12:45:01 PM PDT 24
Finished Jun 11 12:45:04 PM PDT 24
Peak memory 204684 kb
Host smart-474f89ff-29fb-4781-aece-a204b8d27178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33969
70669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3396970669
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2950240306
Short name T1799
Test name
Test status
Simulation time 237514971 ps
CPU time 0.84 seconds
Started Jun 11 12:44:45 PM PDT 24
Finished Jun 11 12:44:49 PM PDT 24
Peak memory 204640 kb
Host smart-7a84baef-d06b-4566-9f03-537a30d70e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29502
40306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2950240306
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1416411884
Short name T2016
Test name
Test status
Simulation time 188209114 ps
CPU time 0.86 seconds
Started Jun 11 12:44:51 PM PDT 24
Finished Jun 11 12:44:54 PM PDT 24
Peak memory 204696 kb
Host smart-8a693a26-ab3f-4d29-83d5-d9b13fbb2003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14164
11884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1416411884
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1994283860
Short name T1003
Test name
Test status
Simulation time 222841415 ps
CPU time 0.88 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:12 PM PDT 24
Peak memory 204692 kb
Host smart-92dcfa5c-c6ad-4dde-a0e5-befcb097cffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19942
83860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1994283860
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.4114996446
Short name T352
Test name
Test status
Simulation time 179527939 ps
CPU time 0.8 seconds
Started Jun 11 12:44:52 PM PDT 24
Finished Jun 11 12:44:54 PM PDT 24
Peak memory 204708 kb
Host smart-c521a9a5-278f-4be8-b2d3-881e1dbb8147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41149
96446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.4114996446
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.419119029
Short name T1752
Test name
Test status
Simulation time 155186138 ps
CPU time 0.77 seconds
Started Jun 11 12:44:49 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 204732 kb
Host smart-e3677681-1789-42ef-aae2-77625bfff08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41911
9029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.419119029
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_eop_single_bit_handling.2061786935
Short name T821
Test name
Test status
Simulation time 175740418 ps
CPU time 0.8 seconds
Started Jun 11 12:44:49 PM PDT 24
Finished Jun 11 12:44:52 PM PDT 24
Peak memory 204756 kb
Host smart-75f928ee-bb05-47d3-a46d-cf3e15d5bb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
86935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_eop_single_bit_handling.2061786935
Directory /workspace/49.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.220044191
Short name T1492
Test name
Test status
Simulation time 145743255 ps
CPU time 0.72 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:44:47 PM PDT 24
Peak memory 204672 kb
Host smart-1e41e767-fb43-4175-a7ed-46fb6f37624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22004
4191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.220044191
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1305977922
Short name T714
Test name
Test status
Simulation time 30193056 ps
CPU time 0.64 seconds
Started Jun 11 12:44:48 PM PDT 24
Finished Jun 11 12:44:50 PM PDT 24
Peak memory 204652 kb
Host smart-61a45d1f-68fd-4154-851c-e1a7ee6d7c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059
77922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1305977922
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.145042386
Short name T901
Test name
Test status
Simulation time 14270893811 ps
CPU time 32.44 seconds
Started Jun 11 12:44:46 PM PDT 24
Finished Jun 11 12:45:21 PM PDT 24
Peak memory 205100 kb
Host smart-dee827e6-58ee-447f-aa1f-dab82745d98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14504
2386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.145042386
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2737505035
Short name T760
Test name
Test status
Simulation time 160578962 ps
CPU time 0.78 seconds
Started Jun 11 12:44:47 PM PDT 24
Finished Jun 11 12:44:51 PM PDT 24
Peak memory 204648 kb
Host smart-4af0c918-a917-4c46-9cab-e02ffe2a552c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27375
05035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2737505035
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.851366420
Short name T1686
Test name
Test status
Simulation time 162338522 ps
CPU time 0.78 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:44:48 PM PDT 24
Peak memory 204636 kb
Host smart-f779b677-c5e9-47ad-b4d4-4e826b0a828a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85136
6420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.851366420
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.4030988410
Short name T1214
Test name
Test status
Simulation time 176498292 ps
CPU time 0.79 seconds
Started Jun 11 12:45:00 PM PDT 24
Finished Jun 11 12:45:04 PM PDT 24
Peak memory 204708 kb
Host smart-06973ad8-4f1b-4dfa-991c-8e22a8247809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
88410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.4030988410
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.108692446
Short name T743
Test name
Test status
Simulation time 191757163 ps
CPU time 0.94 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 204668 kb
Host smart-2f1ede39-baaa-4b36-af84-dfd4db01874e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10869
2446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.108692446
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3644246992
Short name T1916
Test name
Test status
Simulation time 138507607 ps
CPU time 0.77 seconds
Started Jun 11 12:44:55 PM PDT 24
Finished Jun 11 12:44:57 PM PDT 24
Peak memory 204740 kb
Host smart-fe97eb7c-38ad-42cc-a784-87bc63d39742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36442
46992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3644246992
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2440573836
Short name T1659
Test name
Test status
Simulation time 154830181 ps
CPU time 0.76 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:02 PM PDT 24
Peak memory 204596 kb
Host smart-29198d79-cd05-4243-a0a5-167a22235aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24405
73836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2440573836
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2371079922
Short name T494
Test name
Test status
Simulation time 141649180 ps
CPU time 0.8 seconds
Started Jun 11 12:45:18 PM PDT 24
Finished Jun 11 12:45:22 PM PDT 24
Peak memory 204720 kb
Host smart-92821753-b743-499a-be52-5632eb809c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23710
79922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2371079922
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3966898437
Short name T981
Test name
Test status
Simulation time 198094828 ps
CPU time 0.85 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:16 PM PDT 24
Peak memory 204768 kb
Host smart-38212dbc-dcbf-4ae3-a00b-f6d0db7d85ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39668
98437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3966898437
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1288920849
Short name T860
Test name
Test status
Simulation time 166475153 ps
CPU time 0.77 seconds
Started Jun 11 12:44:59 PM PDT 24
Finished Jun 11 12:45:03 PM PDT 24
Peak memory 204732 kb
Host smart-97be20bd-42b5-4c47-b6dd-c0d90e830af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
20849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1288920849
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1328813970
Short name T1592
Test name
Test status
Simulation time 157282788 ps
CPU time 0.79 seconds
Started Jun 11 12:44:57 PM PDT 24
Finished Jun 11 12:44:59 PM PDT 24
Peak memory 204716 kb
Host smart-6da63bf7-25be-4211-b3bc-55a72bd44876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13288
13970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1328813970
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2489818788
Short name T1151
Test name
Test status
Simulation time 10721243185 ps
CPU time 80.97 seconds
Started Jun 11 12:44:44 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 204964 kb
Host smart-508d4e58-a247-47e2-b57f-d705e955e6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24898
18788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2489818788
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1789651315
Short name T2055
Test name
Test status
Simulation time 3570637589 ps
CPU time 4.43 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:32 PM PDT 24
Peak memory 204828 kb
Host smart-b4d13e46-e6cd-4d4b-981d-6c4be2cc9d2f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1789651315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1789651315
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2471753760
Short name T376
Test name
Test status
Simulation time 13408535027 ps
CPU time 13.82 seconds
Started Jun 11 12:40:26 PM PDT 24
Finished Jun 11 12:40:41 PM PDT 24
Peak memory 204988 kb
Host smart-9b95360b-8c77-4302-bd01-1b4f9abed756
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2471753760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2471753760
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3800417155
Short name T1090
Test name
Test status
Simulation time 23410850512 ps
CPU time 23.06 seconds
Started Jun 11 12:40:32 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204868 kb
Host smart-f20f05cf-e199-417c-8b04-a2db96f9ff5e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3800417155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3800417155
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2674746189
Short name T1277
Test name
Test status
Simulation time 156319704 ps
CPU time 0.79 seconds
Started Jun 11 12:40:24 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204668 kb
Host smart-7b9331b4-d8fe-4e22-878a-04d30d300d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
46189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2674746189
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.931122957
Short name T1783
Test name
Test status
Simulation time 145234606 ps
CPU time 0.74 seconds
Started Jun 11 12:40:26 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204760 kb
Host smart-bbf67c8d-0e7e-4e03-a002-ba69ca43c928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93112
2957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.931122957
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1627797903
Short name T852
Test name
Test status
Simulation time 151619982 ps
CPU time 0.76 seconds
Started Jun 11 12:40:26 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204660 kb
Host smart-2e5f7acd-f95c-4124-9f65-d401a055bffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
97903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1627797903
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2289363935
Short name T1565
Test name
Test status
Simulation time 45936587 ps
CPU time 0.65 seconds
Started Jun 11 12:40:36 PM PDT 24
Finished Jun 11 12:40:37 PM PDT 24
Peak memory 204740 kb
Host smart-8af9356c-6277-4b1e-890c-8a84c7855d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22893
63935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2289363935
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.435014662
Short name T1369
Test name
Test status
Simulation time 828803982 ps
CPU time 2.04 seconds
Started Jun 11 12:40:28 PM PDT 24
Finished Jun 11 12:40:32 PM PDT 24
Peak memory 204952 kb
Host smart-070a7d0f-1cd2-4a0a-93cf-d38876d7eb07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43501
4662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.435014662
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3025802325
Short name T381
Test name
Test status
Simulation time 374277604 ps
CPU time 2.15 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:29 PM PDT 24
Peak memory 204892 kb
Host smart-ef567302-49e8-465d-a1dc-4b68d738e299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
02325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3025802325
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.4134169784
Short name T1168
Test name
Test status
Simulation time 194948680 ps
CPU time 0.84 seconds
Started Jun 11 12:40:46 PM PDT 24
Finished Jun 11 12:40:48 PM PDT 24
Peak memory 204764 kb
Host smart-ef75144e-a08c-4295-ae03-2360b2bd444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41341
69784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.4134169784
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.191312050
Short name T634
Test name
Test status
Simulation time 153304573 ps
CPU time 0.75 seconds
Started Jun 11 12:40:35 PM PDT 24
Finished Jun 11 12:40:37 PM PDT 24
Peak memory 204704 kb
Host smart-7e02aa00-d4de-4a94-a7d0-ae7f22dbd89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
2050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.191312050
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1018926646
Short name T1971
Test name
Test status
Simulation time 166804908 ps
CPU time 0.8 seconds
Started Jun 11 12:40:35 PM PDT 24
Finished Jun 11 12:40:36 PM PDT 24
Peak memory 204748 kb
Host smart-f93af680-dc29-4e27-9a80-9851c32c9c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10189
26646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1018926646
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1269172103
Short name T1671
Test name
Test status
Simulation time 242373803 ps
CPU time 0.88 seconds
Started Jun 11 12:40:41 PM PDT 24
Finished Jun 11 12:40:43 PM PDT 24
Peak memory 204716 kb
Host smart-9be78c12-38fc-41b7-8d08-0dd0acbb7738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
72103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1269172103
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2135557289
Short name T2033
Test name
Test status
Simulation time 3271148504 ps
CPU time 4.64 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:51 PM PDT 24
Peak memory 204776 kb
Host smart-29200d11-3d7f-42b1-b0f4-bc46d85d0494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21355
57289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2135557289
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2125735152
Short name T848
Test name
Test status
Simulation time 244370909 ps
CPU time 0.91 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204708 kb
Host smart-d3b7e6ae-ba05-45ba-91ee-d26caa1c8d8f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2125735152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2125735152
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1378031221
Short name T1290
Test name
Test status
Simulation time 227539769 ps
CPU time 0.91 seconds
Started Jun 11 12:40:35 PM PDT 24
Finished Jun 11 12:40:37 PM PDT 24
Peak memory 204728 kb
Host smart-e5e84361-99d1-4c6b-bcff-65ca8d9c9a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13780
31221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1378031221
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2139626569
Short name T1449
Test name
Test status
Simulation time 3827237889 ps
CPU time 27.06 seconds
Started Jun 11 12:40:27 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 205012 kb
Host smart-4fadce55-bde7-46d0-8c35-ae621e1949a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21396
26569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2139626569
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.801766807
Short name T741
Test name
Test status
Simulation time 163849732 ps
CPU time 0.76 seconds
Started Jun 11 12:40:37 PM PDT 24
Finished Jun 11 12:40:39 PM PDT 24
Peak memory 204732 kb
Host smart-66a9ec62-9447-4a7a-ac92-1b247a698256
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=801766807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.801766807
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.988199797
Short name T1267
Test name
Test status
Simulation time 136529835 ps
CPU time 0.78 seconds
Started Jun 11 12:40:24 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204700 kb
Host smart-057992cc-0e5c-4194-b585-bbccb5a97ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98819
9797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.988199797
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.748196651
Short name T2010
Test name
Test status
Simulation time 193090431 ps
CPU time 0.82 seconds
Started Jun 11 12:40:26 PM PDT 24
Finished Jun 11 12:40:29 PM PDT 24
Peak memory 204772 kb
Host smart-85c49569-e2d9-4fa9-a2ff-17963817964f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74819
6651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.748196651
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1213378
Short name T423
Test name
Test status
Simulation time 153465694 ps
CPU time 0.74 seconds
Started Jun 11 12:40:26 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204700 kb
Host smart-3c5e5bd8-f00c-40f1-9b4a-96da6f9d9f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12133
78 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1213378
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.706816325
Short name T715
Test name
Test status
Simulation time 194171277 ps
CPU time 0.83 seconds
Started Jun 11 12:40:29 PM PDT 24
Finished Jun 11 12:40:31 PM PDT 24
Peak memory 204728 kb
Host smart-3f51139b-b518-4082-83fa-8f7f6f4ce9b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70681
6325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.706816325
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.522432736
Short name T1343
Test name
Test status
Simulation time 244205774 ps
CPU time 0.89 seconds
Started Jun 11 12:40:29 PM PDT 24
Finished Jun 11 12:40:30 PM PDT 24
Peak memory 204732 kb
Host smart-a06cf077-5c19-40ab-9945-fed8ceabb816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52243
2736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.522432736
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1838387301
Short name T1039
Test name
Test status
Simulation time 229493627 ps
CPU time 0.83 seconds
Started Jun 11 12:40:35 PM PDT 24
Finished Jun 11 12:40:37 PM PDT 24
Peak memory 204736 kb
Host smart-a4c9bcf0-24d8-4007-b20b-c91346afa032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18383
87301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1838387301
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_eop_single_bit_handling.4232295799
Short name T2009
Test name
Test status
Simulation time 179568048 ps
CPU time 0.82 seconds
Started Jun 11 12:40:38 PM PDT 24
Finished Jun 11 12:40:40 PM PDT 24
Peak memory 204708 kb
Host smart-7817fa00-f27f-46ee-b3c1-f2c7d8100aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
95799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_eop_single_bit_handling.4232295799
Directory /workspace/5.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1658959801
Short name T106
Test name
Test status
Simulation time 145450176 ps
CPU time 0.76 seconds
Started Jun 11 12:40:35 PM PDT 24
Finished Jun 11 12:40:37 PM PDT 24
Peak memory 204768 kb
Host smart-90ec4438-dc3f-4457-9c88-ca9cdf61792a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16589
59801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1658959801
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3525343961
Short name T2064
Test name
Test status
Simulation time 37974906 ps
CPU time 0.66 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 204724 kb
Host smart-e1243719-c1d7-4c8e-99c9-3b33ed50da8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35253
43961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3525343961
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4038816352
Short name T1392
Test name
Test status
Simulation time 7205014954 ps
CPU time 18.36 seconds
Started Jun 11 12:40:30 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 204984 kb
Host smart-50f315cc-b953-46d6-8836-d8670aaa6c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40388
16352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4038816352
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2435247592
Short name T1624
Test name
Test status
Simulation time 183708504 ps
CPU time 0.84 seconds
Started Jun 11 12:40:39 PM PDT 24
Finished Jun 11 12:40:41 PM PDT 24
Peak memory 204744 kb
Host smart-64cd6f2f-f1af-4ec4-93dd-ea8f1aeaf8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24352
47592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2435247592
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.2373258987
Short name T511
Test name
Test status
Simulation time 200724207 ps
CPU time 0.84 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204736 kb
Host smart-240fd2ca-a67f-4dbb-878e-afd3853c6dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23732
58987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2373258987
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3489659688
Short name T210
Test name
Test status
Simulation time 18029553755 ps
CPU time 140.51 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:43:01 PM PDT 24
Peak memory 204992 kb
Host smart-d39b9581-1785-4540-9434-29f5f7404cd3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3489659688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3489659688
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.95281539
Short name T568
Test name
Test status
Simulation time 24403997512 ps
CPU time 190.46 seconds
Started Jun 11 12:40:38 PM PDT 24
Finished Jun 11 12:43:50 PM PDT 24
Peak memory 205040 kb
Host smart-beca2d20-091a-434b-8f40-d20110bf84c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=95281539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.95281539
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2619001802
Short name T350
Test name
Test status
Simulation time 195840237 ps
CPU time 0.83 seconds
Started Jun 11 12:40:24 PM PDT 24
Finished Jun 11 12:40:27 PM PDT 24
Peak memory 204716 kb
Host smart-e5927818-f9b3-4b36-9f07-9f06ae93dead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26190
01802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2619001802
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2608949432
Short name T875
Test name
Test status
Simulation time 184519190 ps
CPU time 0.86 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204764 kb
Host smart-16b12a56-0761-4de9-8088-f4dd7f53da01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26089
49432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2608949432
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3541121504
Short name T1708
Test name
Test status
Simulation time 180331637 ps
CPU time 0.79 seconds
Started Jun 11 12:40:30 PM PDT 24
Finished Jun 11 12:40:32 PM PDT 24
Peak memory 204676 kb
Host smart-b4aaa330-0350-4b56-b22e-c418c03e6f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35411
21504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3541121504
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2539064780
Short name T1490
Test name
Test status
Simulation time 142639352 ps
CPU time 0.72 seconds
Started Jun 11 12:40:42 PM PDT 24
Finished Jun 11 12:40:44 PM PDT 24
Peak memory 204644 kb
Host smart-e706fcbd-1a35-4da9-9ae2-b931dfe82b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25390
64780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2539064780
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.285937768
Short name T88
Test name
Test status
Simulation time 161177285 ps
CPU time 0.77 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 204732 kb
Host smart-e3a86f55-6fef-43d8-a9a6-fc62538b7f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28593
7768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.285937768
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1274181478
Short name T1561
Test name
Test status
Simulation time 229417081 ps
CPU time 0.94 seconds
Started Jun 11 12:40:32 PM PDT 24
Finished Jun 11 12:40:34 PM PDT 24
Peak memory 204760 kb
Host smart-6ce19d29-11d2-4508-89fd-c665782da810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12741
81478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1274181478
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2953084604
Short name T1076
Test name
Test status
Simulation time 164977466 ps
CPU time 0.85 seconds
Started Jun 11 12:40:28 PM PDT 24
Finished Jun 11 12:40:30 PM PDT 24
Peak memory 204768 kb
Host smart-6c82c089-aed9-4c62-82eb-28a53c2b2e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
84604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2953084604
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.220697235
Short name T2113
Test name
Test status
Simulation time 180595033 ps
CPU time 0.86 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204740 kb
Host smart-6bd50cc6-b274-4355-9c98-85445571b7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22069
7235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.220697235
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3300579999
Short name T1849
Test name
Test status
Simulation time 14002128577 ps
CPU time 139.71 seconds
Started Jun 11 12:40:32 PM PDT 24
Finished Jun 11 12:42:52 PM PDT 24
Peak memory 205032 kb
Host smart-ed2d40a4-84b8-4291-a880-9afb838e76f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33005
79999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3300579999
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.782244834
Short name T2023
Test name
Test status
Simulation time 4242025766 ps
CPU time 5.72 seconds
Started Jun 11 12:40:42 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 205004 kb
Host smart-4b4123e6-52c3-4520-b32f-3b0ab52cd631
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=782244834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.782244834
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1644772709
Short name T1649
Test name
Test status
Simulation time 13460409202 ps
CPU time 15.7 seconds
Started Jun 11 12:40:32 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 205040 kb
Host smart-d2aa47b7-19b3-4939-ad53-ec4078ce962e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1644772709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1644772709
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3838483668
Short name T1829
Test name
Test status
Simulation time 23361932469 ps
CPU time 28.25 seconds
Started Jun 11 12:40:24 PM PDT 24
Finished Jun 11 12:40:54 PM PDT 24
Peak memory 204920 kb
Host smart-2a5718ab-d98d-4718-9e4f-78a7dd13420d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3838483668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3838483668
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3750284482
Short name T840
Test name
Test status
Simulation time 177143728 ps
CPU time 0.86 seconds
Started Jun 11 12:40:25 PM PDT 24
Finished Jun 11 12:40:28 PM PDT 24
Peak memory 204692 kb
Host smart-b286f736-e4f3-468a-8f1d-016d50b08def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
84482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3750284482
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.4203758101
Short name T866
Test name
Test status
Simulation time 139925664 ps
CPU time 0.78 seconds
Started Jun 11 12:40:42 PM PDT 24
Finished Jun 11 12:40:44 PM PDT 24
Peak memory 204648 kb
Host smart-bb2d576b-fa37-444e-a1d3-dc1f47e5543a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42037
58101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.4203758101
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1393560228
Short name T1573
Test name
Test status
Simulation time 937652466 ps
CPU time 2.17 seconds
Started Jun 11 12:40:36 PM PDT 24
Finished Jun 11 12:40:40 PM PDT 24
Peak memory 204900 kb
Host smart-9a7fac42-8487-4e25-af35-afced10f021b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13935
60228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1393560228
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.991703591
Short name T640
Test name
Test status
Simulation time 143530610 ps
CPU time 0.76 seconds
Started Jun 11 12:40:41 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 204740 kb
Host smart-3191a9e4-7ad5-4cb6-92a7-34d6de3a0feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99170
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.991703591
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3182120984
Short name T2041
Test name
Test status
Simulation time 50979946 ps
CPU time 0.65 seconds
Started Jun 11 12:40:55 PM PDT 24
Finished Jun 11 12:40:58 PM PDT 24
Peak memory 204672 kb
Host smart-16c2e678-95b7-4e33-a49d-72ced8470b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31821
20984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3182120984
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3539856349
Short name T653
Test name
Test status
Simulation time 906380412 ps
CPU time 2.07 seconds
Started Jun 11 12:40:46 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204880 kb
Host smart-b28cc504-eeef-48ba-8677-e770cff4fba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35398
56349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3539856349
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3696756457
Short name T1666
Test name
Test status
Simulation time 328400268 ps
CPU time 2.08 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:40:43 PM PDT 24
Peak memory 204884 kb
Host smart-3aefa650-17b1-4d8c-87e3-e609e265951b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36967
56457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3696756457
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1241331605
Short name T1816
Test name
Test status
Simulation time 224540397 ps
CPU time 0.89 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:47 PM PDT 24
Peak memory 204740 kb
Host smart-2e9d4496-76d1-4fda-a9c0-1b306591997e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
31605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1241331605
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3347448836
Short name T758
Test name
Test status
Simulation time 158129364 ps
CPU time 0.8 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:47 PM PDT 24
Peak memory 204704 kb
Host smart-17517dcf-c8b6-4e9f-b5e3-99df7d7c3b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33474
48836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3347448836
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.653443614
Short name T592
Test name
Test status
Simulation time 273817258 ps
CPU time 0.93 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204644 kb
Host smart-6252c089-2f9d-4378-ac05-80a14fe6814f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65344
3614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.653443614
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1193914351
Short name T979
Test name
Test status
Simulation time 181410651 ps
CPU time 0.81 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:40:41 PM PDT 24
Peak memory 204672 kb
Host smart-8642cbba-9015-47a9-bbe7-88fe367cd5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11939
14351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1193914351
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.254979938
Short name T2015
Test name
Test status
Simulation time 3276912203 ps
CPU time 3.73 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204712 kb
Host smart-82ad29cb-0781-49c8-b037-d28f6734067f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25497
9938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.254979938
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.172033611
Short name T1709
Test name
Test status
Simulation time 284972241 ps
CPU time 0.95 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204740 kb
Host smart-c53a7d85-2775-4ae7-94a9-22db475c9370
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=172033611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.172033611
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1531222368
Short name T553
Test name
Test status
Simulation time 223425293 ps
CPU time 0.86 seconds
Started Jun 11 12:40:42 PM PDT 24
Finished Jun 11 12:40:44 PM PDT 24
Peak memory 204656 kb
Host smart-22ea3dff-f77c-4d0c-94cf-fd2aca5554b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15312
22368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1531222368
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3221304799
Short name T1927
Test name
Test status
Simulation time 4963034044 ps
CPU time 137.55 seconds
Started Jun 11 12:40:46 PM PDT 24
Finished Jun 11 12:43:06 PM PDT 24
Peak memory 205028 kb
Host smart-43d894b1-3a7e-4e12-bc2d-4fe59e0f64b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32213
04799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3221304799
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2700466470
Short name T709
Test name
Test status
Simulation time 154299966 ps
CPU time 0.83 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204728 kb
Host smart-99e48ce6-8f62-4e0f-bea2-e28e0502d971
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2700466470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2700466470
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.848231561
Short name T2103
Test name
Test status
Simulation time 150466431 ps
CPU time 0.79 seconds
Started Jun 11 12:40:27 PM PDT 24
Finished Jun 11 12:40:29 PM PDT 24
Peak memory 204752 kb
Host smart-c4647b0d-a5f7-4a8e-93c2-a3925be1ea52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84823
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.848231561
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.2428420743
Short name T136
Test name
Test status
Simulation time 208391335 ps
CPU time 0.84 seconds
Started Jun 11 12:40:34 PM PDT 24
Finished Jun 11 12:40:36 PM PDT 24
Peak memory 204712 kb
Host smart-943d9047-72bd-4380-990e-3ab1ca9d7751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24284
20743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.2428420743
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.30311658
Short name T755
Test name
Test status
Simulation time 152925944 ps
CPU time 0.85 seconds
Started Jun 11 12:40:34 PM PDT 24
Finished Jun 11 12:40:35 PM PDT 24
Peak memory 204672 kb
Host smart-5ef9a9b1-6fc2-4283-b959-4ba14faca7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30311
658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.30311658
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3890053293
Short name T93
Test name
Test status
Simulation time 178734217 ps
CPU time 0.83 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 204668 kb
Host smart-d56322b5-693f-4a4c-aadb-3d4128de283d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38900
53293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3890053293
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4245129737
Short name T1006
Test name
Test status
Simulation time 191897647 ps
CPU time 0.76 seconds
Started Jun 11 12:40:40 PM PDT 24
Finished Jun 11 12:40:42 PM PDT 24
Peak memory 204716 kb
Host smart-42ed3942-647f-4bac-af58-e11e5915878b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42451
29737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4245129737
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2627485868
Short name T1410
Test name
Test status
Simulation time 167234719 ps
CPU time 0.84 seconds
Started Jun 11 12:41:00 PM PDT 24
Finished Jun 11 12:41:05 PM PDT 24
Peak memory 205020 kb
Host smart-be01a0c3-20e4-4f2e-b6b4-3553bc7e48a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26274
85868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2627485868
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_eop_single_bit_handling.2574114601
Short name T872
Test name
Test status
Simulation time 236380009 ps
CPU time 0.86 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:54 PM PDT 24
Peak memory 204704 kb
Host smart-c0126062-6171-4191-91ea-5ca3d0267878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
14601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_eop_single_bit_handling.2574114601
Directory /workspace/6.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.984186758
Short name T1700
Test name
Test status
Simulation time 142610720 ps
CPU time 0.73 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204664 kb
Host smart-960f3b16-310d-4953-b009-80f28c55d4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98418
6758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.984186758
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1213217815
Short name T716
Test name
Test status
Simulation time 32352237 ps
CPU time 0.65 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:54 PM PDT 24
Peak memory 204728 kb
Host smart-4ee09ba2-c07a-4d62-b594-739c5994b6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12132
17815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1213217815
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.960439771
Short name T243
Test name
Test status
Simulation time 16234508959 ps
CPU time 37.1 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:43 PM PDT 24
Peak memory 204948 kb
Host smart-816e52d1-d72c-4ff5-9623-7573af7780d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96043
9771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.960439771
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1140025708
Short name T1947
Test name
Test status
Simulation time 168573061 ps
CPU time 0.84 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204704 kb
Host smart-43411e9b-9ffc-49a7-ad6b-7ffe37b8f945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11400
25708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1140025708
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2503127068
Short name T987
Test name
Test status
Simulation time 220207071 ps
CPU time 0.91 seconds
Started Jun 11 12:40:58 PM PDT 24
Finished Jun 11 12:41:03 PM PDT 24
Peak memory 204744 kb
Host smart-dbdd1b21-d7da-450b-a594-d98c2627e99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
27068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2503127068
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2145031007
Short name T1711
Test name
Test status
Simulation time 25770568197 ps
CPU time 628.82 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:51:19 PM PDT 24
Peak memory 205084 kb
Host smart-ec557cb0-6376-4cfb-9b2d-11d2ab442cb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2145031007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2145031007
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2779219449
Short name T434
Test name
Test status
Simulation time 19064446914 ps
CPU time 512.13 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:49:24 PM PDT 24
Peak memory 205308 kb
Host smart-449c21cd-e9fc-499b-a776-65d930e40064
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2779219449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2779219449
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2575901757
Short name T1586
Test name
Test status
Simulation time 15722265784 ps
CPU time 108 seconds
Started Jun 11 12:40:41 PM PDT 24
Finished Jun 11 12:42:30 PM PDT 24
Peak memory 205028 kb
Host smart-9d7225dc-5acd-4460-8eed-ec15252367dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2575901757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2575901757
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2393847470
Short name T1647
Test name
Test status
Simulation time 161194431 ps
CPU time 0.84 seconds
Started Jun 11 12:40:43 PM PDT 24
Finished Jun 11 12:40:45 PM PDT 24
Peak memory 204724 kb
Host smart-84cbbba1-f1f2-4d15-a535-1fc1cea9a687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
47470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2393847470
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1290078465
Short name T1802
Test name
Test status
Simulation time 158771577 ps
CPU time 0.8 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:47 PM PDT 24
Peak memory 204772 kb
Host smart-3c225668-e97d-4f11-8bd8-222f34530de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
78465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1290078465
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3280412034
Short name T1867
Test name
Test status
Simulation time 179708934 ps
CPU time 0.81 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204624 kb
Host smart-3f4bbd2f-0b85-4a25-aed1-8d853c0043a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32804
12034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3280412034
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.524148348
Short name T1066
Test name
Test status
Simulation time 175741790 ps
CPU time 0.77 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 204700 kb
Host smart-456d1302-eb40-410f-9f5b-f53bd2fed75d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52414
8348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.524148348
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1559530801
Short name T362
Test name
Test status
Simulation time 173913043 ps
CPU time 0.76 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:40:55 PM PDT 24
Peak memory 204672 kb
Host smart-11888f50-0301-4f3c-8b99-7153fc843abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15595
30801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1559530801
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3848994290
Short name T195
Test name
Test status
Simulation time 214054508 ps
CPU time 0.88 seconds
Started Jun 11 12:40:32 PM PDT 24
Finished Jun 11 12:40:34 PM PDT 24
Peak memory 204632 kb
Host smart-589b1cc8-f25e-4cf2-85bf-9e16dfb9983c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
94290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3848994290
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.2770355685
Short name T920
Test name
Test status
Simulation time 180849423 ps
CPU time 0.82 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 204656 kb
Host smart-73b62a61-8b6e-43c0-8d92-1392ea5f3332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27703
55685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.2770355685
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3019297819
Short name T538
Test name
Test status
Simulation time 161431816 ps
CPU time 0.85 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204648 kb
Host smart-d8c6da28-caaf-458c-b253-10efb4255d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30192
97819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3019297819
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.4040959948
Short name T1914
Test name
Test status
Simulation time 7503196269 ps
CPU time 192.45 seconds
Started Jun 11 12:40:55 PM PDT 24
Finished Jun 11 12:44:10 PM PDT 24
Peak memory 205064 kb
Host smart-09af867d-535f-4f02-bd1c-24b5d8dfd002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409
59948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.4040959948
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2761439002
Short name T13
Test name
Test status
Simulation time 3509669965 ps
CPU time 4.54 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:51 PM PDT 24
Peak memory 204996 kb
Host smart-84bae045-018a-4aff-80f0-1f8c408bbb5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761439002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2761439002
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2760677667
Short name T452
Test name
Test status
Simulation time 13310839492 ps
CPU time 13.73 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:41:01 PM PDT 24
Peak memory 204804 kb
Host smart-b060d305-1210-44ae-b1ff-a1ca87f76a22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2760677667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2760677667
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.4168006256
Short name T1109
Test name
Test status
Simulation time 23415686273 ps
CPU time 23.63 seconds
Started Jun 11 12:40:44 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204968 kb
Host smart-71227f0b-73f3-4897-8d35-a0b3496a2746
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4168006256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.4168006256
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1597709543
Short name T1416
Test name
Test status
Simulation time 152894014 ps
CPU time 0.78 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:58 PM PDT 24
Peak memory 204768 kb
Host smart-99ec5395-eb07-48e0-a192-cac425e6b21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15977
09543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1597709543
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3660069928
Short name T1160
Test name
Test status
Simulation time 165197733 ps
CPU time 0.81 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:00 PM PDT 24
Peak memory 204748 kb
Host smart-1924a5e8-79d9-4ce8-b287-acb0edc94767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36600
69928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3660069928
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.4093800778
Short name T1299
Test name
Test status
Simulation time 505435781 ps
CPU time 1.35 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204668 kb
Host smart-2fee3cd7-7a84-4eb4-9de5-1104ffb1c215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40938
00778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.4093800778
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.4014981916
Short name T1138
Test name
Test status
Simulation time 143235985 ps
CPU time 0.76 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:53 PM PDT 24
Peak memory 204700 kb
Host smart-1f540289-ee04-4b08-9f20-3d58578745c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
81916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.4014981916
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2526312352
Short name T2083
Test name
Test status
Simulation time 59081709 ps
CPU time 0.69 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204756 kb
Host smart-8260cb10-f223-4a32-8ae5-c4dfc38d95b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25263
12352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2526312352
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2878873307
Short name T742
Test name
Test status
Simulation time 940147417 ps
CPU time 2.18 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204944 kb
Host smart-cd09c89d-0c0b-4917-8bfb-69b059e0fb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28788
73307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2878873307
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1909890179
Short name T814
Test name
Test status
Simulation time 311310299 ps
CPU time 2.22 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:40:53 PM PDT 24
Peak memory 204888 kb
Host smart-7573dea8-f78c-4651-809a-a505c4c76440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
90179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1909890179
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3660767511
Short name T2115
Test name
Test status
Simulation time 208376733 ps
CPU time 0.89 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204736 kb
Host smart-e5ec6ad0-d8e5-451a-a0f5-b29956fb1c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36607
67511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3660767511
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1524616445
Short name T1032
Test name
Test status
Simulation time 163417263 ps
CPU time 0.73 seconds
Started Jun 11 12:40:50 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204700 kb
Host smart-55b5ba9f-7159-4065-9c91-06be7762a823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15246
16445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1524616445
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3203243166
Short name T1710
Test name
Test status
Simulation time 256797105 ps
CPU time 0.96 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204732 kb
Host smart-9259c124-f957-4979-b48d-e8314d9e63ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32032
43166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3203243166
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.4174459779
Short name T59
Test name
Test status
Simulation time 189152866 ps
CPU time 0.85 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204704 kb
Host smart-6de09876-a98a-48ca-9f64-c2d819accf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
59779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.4174459779
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2063472611
Short name T864
Test name
Test status
Simulation time 3392735756 ps
CPU time 3.95 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:40:53 PM PDT 24
Peak memory 204816 kb
Host smart-0d927f7f-4641-40d3-a166-18f0aa6344ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20634
72611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2063472611
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.4065916500
Short name T2104
Test name
Test status
Simulation time 230731134 ps
CPU time 0.88 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:40:51 PM PDT 24
Peak memory 204748 kb
Host smart-08c1da97-f858-4156-ad7b-6c0040f58c0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4065916500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.4065916500
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2216343119
Short name T1336
Test name
Test status
Simulation time 192956618 ps
CPU time 0.83 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:54 PM PDT 24
Peak memory 204668 kb
Host smart-2cd8b6b9-091c-407f-b689-4a4d3729d9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163
43119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2216343119
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3203890199
Short name T1135
Test name
Test status
Simulation time 8857778791 ps
CPU time 81.89 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:42:17 PM PDT 24
Peak memory 205000 kb
Host smart-93d186b9-51b5-41ce-9b7e-289cdcaa57ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
90199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3203890199
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.654370196
Short name T555
Test name
Test status
Simulation time 164305525 ps
CPU time 0.78 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204644 kb
Host smart-c525dd3e-f8cf-4d39-bdc0-f63969931e83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=654370196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.654370196
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1131476276
Short name T697
Test name
Test status
Simulation time 150409061 ps
CPU time 0.77 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204720 kb
Host smart-e446a1a2-27fe-44e7-a799-e2b3d481d7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
76276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1131476276
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1803427405
Short name T147
Test name
Test status
Simulation time 230206443 ps
CPU time 0.97 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:47 PM PDT 24
Peak memory 205016 kb
Host smart-2f39ea04-b74f-46a8-b9b1-096326a02bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
27405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1803427405
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2895872755
Short name T1844
Test name
Test status
Simulation time 190267451 ps
CPU time 0.85 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204196 kb
Host smart-3838c026-9c31-4ef3-a1f5-52bd96efeac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
72755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2895872755
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1722295266
Short name T1895
Test name
Test status
Simulation time 187963849 ps
CPU time 0.79 seconds
Started Jun 11 12:40:58 PM PDT 24
Finished Jun 11 12:41:02 PM PDT 24
Peak memory 204764 kb
Host smart-8b1ae902-f064-4952-a4a0-255475999faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17222
95266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1722295266
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.2635845516
Short name T1017
Test name
Test status
Simulation time 185217790 ps
CPU time 0.84 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204728 kb
Host smart-d9c39da9-e644-4cc8-9864-f18a04bf134a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26358
45516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.2635845516
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.434737380
Short name T1446
Test name
Test status
Simulation time 157342850 ps
CPU time 0.76 seconds
Started Jun 11 12:40:50 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204744 kb
Host smart-66f91562-2dd6-49e7-9640-6d44433e3285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43473
7380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.434737380
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_eop_single_bit_handling.508878625
Short name T32
Test name
Test status
Simulation time 178156057 ps
CPU time 0.84 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204720 kb
Host smart-84b9af53-afd6-4b31-9b6e-a7cc27217046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50887
8625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_eop_single_bit_handling.508878625
Directory /workspace/7.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.576445907
Short name T626
Test name
Test status
Simulation time 160052123 ps
CPU time 0.76 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:00 PM PDT 24
Peak memory 204784 kb
Host smart-1f18cfa2-c90d-4926-beac-de7ce77bb399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57644
5907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.576445907
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.4197128276
Short name T1661
Test name
Test status
Simulation time 43206972 ps
CPU time 0.65 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:47 PM PDT 24
Peak memory 204728 kb
Host smart-d2f1d029-ce0b-4e63-8b91-834b40805f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41971
28276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.4197128276
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3852583791
Short name T1382
Test name
Test status
Simulation time 10865225586 ps
CPU time 27.55 seconds
Started Jun 11 12:40:46 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 205108 kb
Host smart-e9874a63-a949-4a8d-8c66-e48d24a86cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38525
83791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3852583791
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.951516613
Short name T1599
Test name
Test status
Simulation time 192661013 ps
CPU time 0.86 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204716 kb
Host smart-a2b8724c-d4f3-4cd4-a8bd-d86bc54d6aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95151
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.951516613
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4140926059
Short name T1965
Test name
Test status
Simulation time 217225039 ps
CPU time 0.89 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:01 PM PDT 24
Peak memory 204732 kb
Host smart-446df717-47bb-41ef-9c9e-125e7838e674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
26059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4140926059
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.303676772
Short name T203
Test name
Test status
Simulation time 10764523652 ps
CPU time 53.52 seconds
Started Jun 11 12:40:50 PM PDT 24
Finished Jun 11 12:41:45 PM PDT 24
Peak memory 205064 kb
Host smart-aaf47849-9405-47e0-aa5b-f9858ddc9d70
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=303676772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.303676772
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.494657238
Short name T1456
Test name
Test status
Simulation time 28918825403 ps
CPU time 233.75 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:44:45 PM PDT 24
Peak memory 204568 kb
Host smart-f6797a54-22d2-432d-baa6-6ad540f0d485
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=494657238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.494657238
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2676568125
Short name T1743
Test name
Test status
Simulation time 16832719662 ps
CPU time 118.62 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:42:47 PM PDT 24
Peak memory 204964 kb
Host smart-f7aa1b6c-1cfb-46d7-9a0a-24af7262a379
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2676568125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2676568125
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3808349566
Short name T397
Test name
Test status
Simulation time 236028309 ps
CPU time 0.88 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204748 kb
Host smart-d6a4b4fc-2a59-4e34-882c-bf906cccbd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38083
49566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3808349566
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1695729352
Short name T1724
Test name
Test status
Simulation time 182241522 ps
CPU time 0.84 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:40:55 PM PDT 24
Peak memory 204716 kb
Host smart-5904494b-460f-4454-889c-12f7f6aece1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
29352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1695729352
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2382066441
Short name T682
Test name
Test status
Simulation time 135661516 ps
CPU time 0.74 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204752 kb
Host smart-210a1cc3-ec72-4f74-ac2e-9f2455e4b5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23820
66441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2382066441
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.599118783
Short name T826
Test name
Test status
Simulation time 161834819 ps
CPU time 0.77 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204752 kb
Host smart-19cff8db-ac40-4bb1-99c1-35cb310ff4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59911
8783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.599118783
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.558891849
Short name T1857
Test name
Test status
Simulation time 159065080 ps
CPU time 0.78 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:53 PM PDT 24
Peak memory 204692 kb
Host smart-45c2f3db-b3e9-477d-a2a7-30e8c606a6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55889
1849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.558891849
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2487604503
Short name T1963
Test name
Test status
Simulation time 214584106 ps
CPU time 0.94 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:40:51 PM PDT 24
Peak memory 204724 kb
Host smart-37458cbf-6968-4482-9e8f-cda64e1b6048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24876
04503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2487604503
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2425790984
Short name T1091
Test name
Test status
Simulation time 230876213 ps
CPU time 0.86 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204648 kb
Host smart-09015580-111c-4cb9-9124-d433259d7218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
90984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2425790984
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.64196170
Short name T1465
Test name
Test status
Simulation time 203013651 ps
CPU time 0.81 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204768 kb
Host smart-b4cc1d4a-4e43-483a-afd1-be0befc07e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64196
170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.64196170
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3453834924
Short name T1698
Test name
Test status
Simulation time 4285270932 ps
CPU time 31.87 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 205052 kb
Host smart-2584cf2f-7ba3-4a57-8dc6-136ae8a126ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
34924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3453834924
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.3178613581
Short name T329
Test name
Test status
Simulation time 4168670055 ps
CPU time 4.9 seconds
Started Jun 11 12:40:45 PM PDT 24
Finished Jun 11 12:40:51 PM PDT 24
Peak memory 204752 kb
Host smart-d096302e-3f1b-4281-b739-22cd95c21fe0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3178613581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.3178613581
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2966016862
Short name T624
Test name
Test status
Simulation time 13451464218 ps
CPU time 13.37 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204772 kb
Host smart-36ded020-8b2f-4323-a338-a1957ecf66a3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2966016862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2966016862
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.369699887
Short name T2080
Test name
Test status
Simulation time 23370385809 ps
CPU time 26.26 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:41:16 PM PDT 24
Peak memory 204952 kb
Host smart-00a8c51d-96d0-491b-9793-766df529413a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=369699887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.369699887
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3175028259
Short name T917
Test name
Test status
Simulation time 181543207 ps
CPU time 0.85 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204772 kb
Host smart-2a77abef-a8db-40fc-866b-9d4c9d3211d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
28259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3175028259
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2051109125
Short name T791
Test name
Test status
Simulation time 184468613 ps
CPU time 0.82 seconds
Started Jun 11 12:40:50 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204712 kb
Host smart-fe193ac8-6a12-402c-96f1-4ec0a557a456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20511
09125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2051109125
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.942547247
Short name T1198
Test name
Test status
Simulation time 1302746561 ps
CPU time 3.07 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204948 kb
Host smart-a7794929-3e1b-4689-9efd-cc5a0e8bfc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94254
7247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.942547247
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.4215048416
Short name T1124
Test name
Test status
Simulation time 156633434 ps
CPU time 0.75 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204692 kb
Host smart-7c13cd47-2007-43ab-baab-0611a922d142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42150
48416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.4215048416
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1973490003
Short name T1495
Test name
Test status
Simulation time 63035678 ps
CPU time 0.68 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:54 PM PDT 24
Peak memory 204624 kb
Host smart-e4e1414d-5fad-44d9-8152-ba011fe3d20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19734
90003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1973490003
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.488595926
Short name T980
Test name
Test status
Simulation time 929401183 ps
CPU time 2.15 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204888 kb
Host smart-c00f7e68-bd3e-403a-b7a3-c967774e9fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48859
5926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.488595926
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1404160173
Short name T941
Test name
Test status
Simulation time 309414126 ps
CPU time 2.29 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:58 PM PDT 24
Peak memory 204880 kb
Host smart-d47ebf7e-c899-4f1f-bcb6-cf2a039081be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14041
60173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1404160173
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1376774474
Short name T587
Test name
Test status
Simulation time 204956402 ps
CPU time 0.84 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204752 kb
Host smart-ce935b61-ec95-4f7d-b801-8c8d49e5d338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13767
74474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1376774474
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.459699614
Short name T306
Test name
Test status
Simulation time 165388189 ps
CPU time 0.76 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:40:55 PM PDT 24
Peak memory 204972 kb
Host smart-c1304580-4f51-43dd-8d3b-c0538fe31ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45969
9614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.459699614
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2286518689
Short name T385
Test name
Test status
Simulation time 167492276 ps
CPU time 0.8 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:06 PM PDT 24
Peak memory 204636 kb
Host smart-27ada509-bddc-42c8-88cb-382dc5e9b435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
18689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2286518689
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1809518
Short name T1529
Test name
Test status
Simulation time 243179096 ps
CPU time 0.95 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:50 PM PDT 24
Peak memory 204640 kb
Host smart-c395a493-2d4f-43f7-bfeb-742fac028ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18095
18 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1809518
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.50031905
Short name T744
Test name
Test status
Simulation time 3360475327 ps
CPU time 4 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204808 kb
Host smart-63216910-839a-4e48-8e97-6224f7cae254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50031
905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.50031905
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3959598665
Short name T1815
Test name
Test status
Simulation time 252405791 ps
CPU time 0.89 seconds
Started Jun 11 12:41:00 PM PDT 24
Finished Jun 11 12:41:05 PM PDT 24
Peak memory 204700 kb
Host smart-9d88f948-d9cb-4b2e-9614-61dc6d069026
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3959598665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3959598665
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2995180273
Short name T1911
Test name
Test status
Simulation time 191281175 ps
CPU time 0.87 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204704 kb
Host smart-f73da7c7-4944-4a4a-8ba7-1462daec0f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
80273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2995180273
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3344080103
Short name T849
Test name
Test status
Simulation time 4160285773 ps
CPU time 29.83 seconds
Started Jun 11 12:40:49 PM PDT 24
Finished Jun 11 12:41:21 PM PDT 24
Peak memory 204956 kb
Host smart-1b3620c8-bec7-409c-90c5-2b68fcb179ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33440
80103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3344080103
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3309000082
Short name T1515
Test name
Test status
Simulation time 156223244 ps
CPU time 0.79 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:40:55 PM PDT 24
Peak memory 204700 kb
Host smart-831ddb5b-a39d-453f-9d12-c00ef7db35d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3309000082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3309000082
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2500628017
Short name T1205
Test name
Test status
Simulation time 173106284 ps
CPU time 0.78 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204736 kb
Host smart-ae9b42ce-191a-42de-895e-0ee4f6b51b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25006
28017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2500628017
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.4119864024
Short name T138
Test name
Test status
Simulation time 183099222 ps
CPU time 0.82 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204716 kb
Host smart-571c719c-f050-4b30-8619-c149bd6ed37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41198
64024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.4119864024
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1181950711
Short name T986
Test name
Test status
Simulation time 176141571 ps
CPU time 0.81 seconds
Started Jun 11 12:40:47 PM PDT 24
Finished Jun 11 12:40:49 PM PDT 24
Peak memory 204728 kb
Host smart-6075314d-6272-4851-9d40-cb0fd5f918c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11819
50711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1181950711
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.559575216
Short name T1962
Test name
Test status
Simulation time 190816066 ps
CPU time 0.82 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204692 kb
Host smart-1d0a6e62-ffa6-4640-addf-3d831d643b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55957
5216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.559575216
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3950910668
Short name T360
Test name
Test status
Simulation time 185777754 ps
CPU time 0.83 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204744 kb
Host smart-954d6302-9f29-4f94-860b-e09c02e6454c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
10668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3950910668
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.231266676
Short name T197
Test name
Test status
Simulation time 240825346 ps
CPU time 0.85 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204660 kb
Host smart-e255756f-1419-4269-9344-51119a2e5500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
6676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.231266676
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_eop_single_bit_handling.2659941436
Short name T1188
Test name
Test status
Simulation time 190674609 ps
CPU time 0.89 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:03 PM PDT 24
Peak memory 204696 kb
Host smart-472c3a8e-c18c-41b4-9df0-88b09a405186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599
41436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_eop_single_bit_handling.2659941436
Directory /workspace/8.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2341966515
Short name T1419
Test name
Test status
Simulation time 173407939 ps
CPU time 0.76 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:04 PM PDT 24
Peak memory 204716 kb
Host smart-125088b7-3583-499b-8c90-a83fb370d02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23419
66515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2341966515
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3728647776
Short name T47
Test name
Test status
Simulation time 41513958 ps
CPU time 0.64 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:06 PM PDT 24
Peak memory 204716 kb
Host smart-d773dc82-e20e-4103-ad74-782592ded3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
47776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3728647776
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3333619867
Short name T1196
Test name
Test status
Simulation time 17133074920 ps
CPU time 39.33 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:41:33 PM PDT 24
Peak memory 205108 kb
Host smart-ee731eb5-1f6b-43ab-ae7e-07744b91a1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33336
19867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3333619867
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.149635590
Short name T618
Test name
Test status
Simulation time 176509621 ps
CPU time 0.83 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204744 kb
Host smart-47612742-88d6-4126-9596-a7f3e1613ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14963
5590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.149635590
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.730183336
Short name T1787
Test name
Test status
Simulation time 186823978 ps
CPU time 0.83 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204740 kb
Host smart-37291de3-876c-4686-a782-004898d0ef63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73018
3336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.730183336
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.984945414
Short name T212
Test name
Test status
Simulation time 26546668952 ps
CPU time 749.66 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:53:23 PM PDT 24
Peak memory 205032 kb
Host smart-62034694-0e61-46e6-99d7-4625442c0e57
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=984945414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.984945414
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.4050028920
Short name T1263
Test name
Test status
Simulation time 24992202171 ps
CPU time 151.46 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:43:39 PM PDT 24
Peak memory 205036 kb
Host smart-fee035da-20f3-4153-a9e3-dc99376de74c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4050028920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.4050028920
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3403174753
Short name T1662
Test name
Test status
Simulation time 189169447 ps
CPU time 0.82 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204696 kb
Host smart-c6ca026b-5740-41ca-8b21-e1c77b3971b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34031
74753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3403174753
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.519899877
Short name T435
Test name
Test status
Simulation time 182687841 ps
CPU time 0.84 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:03 PM PDT 24
Peak memory 204716 kb
Host smart-1a7877ae-9990-4e2b-9c2a-e5fc315de79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51989
9877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.519899877
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3118845522
Short name T585
Test name
Test status
Simulation time 161942651 ps
CPU time 0.81 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204712 kb
Host smart-4afa9818-a8e7-42b9-a8e6-5e20b4feff4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31188
45522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3118845522
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2796087390
Short name T198
Test name
Test status
Simulation time 158592009 ps
CPU time 0.79 seconds
Started Jun 11 12:41:10 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204720 kb
Host smart-a1c52868-e758-4c54-be47-1d5492127ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27960
87390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2796087390
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.4034500013
Short name T1863
Test name
Test status
Simulation time 154076828 ps
CPU time 0.76 seconds
Started Jun 11 12:40:51 PM PDT 24
Finished Jun 11 12:40:53 PM PDT 24
Peak memory 204712 kb
Host smart-cf7c0bef-423a-472c-8e7a-964e367ac0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40345
00013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.4034500013
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1268713652
Short name T1025
Test name
Test status
Simulation time 223002301 ps
CPU time 0.9 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:40:55 PM PDT 24
Peak memory 204600 kb
Host smart-ac28618d-17e3-437a-afbb-167d57f2c28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12687
13652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1268713652
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2896718876
Short name T337
Test name
Test status
Simulation time 187510371 ps
CPU time 0.79 seconds
Started Jun 11 12:40:50 PM PDT 24
Finished Jun 11 12:40:53 PM PDT 24
Peak memory 204776 kb
Host smart-5be212f0-7473-445e-b3ac-d0d1831805b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28967
18876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2896718876
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1432865183
Short name T822
Test name
Test status
Simulation time 181674251 ps
CPU time 0.79 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:40:57 PM PDT 24
Peak memory 204708 kb
Host smart-7e13aa23-0bc3-4148-ac3d-5fb884525e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14328
65183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1432865183
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1339160507
Short name T810
Test name
Test status
Simulation time 4173301988 ps
CPU time 38.04 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:41:34 PM PDT 24
Peak memory 205000 kb
Host smart-7b100f42-006c-4a23-97f9-ac79c92f055e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13391
60507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1339160507
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1336891139
Short name T1375
Test name
Test status
Simulation time 3704261926 ps
CPU time 4.32 seconds
Started Jun 11 12:41:01 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204812 kb
Host smart-6e123761-6a6c-4dd1-acf3-3fe4dc42ee53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1336891139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1336891139
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1174433878
Short name T1652
Test name
Test status
Simulation time 13337347777 ps
CPU time 14.15 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204736 kb
Host smart-a581856a-87e2-4649-b2e6-78cb2006885c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1174433878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1174433878
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.483607641
Short name T679
Test name
Test status
Simulation time 23396257022 ps
CPU time 26.95 seconds
Started Jun 11 12:40:54 PM PDT 24
Finished Jun 11 12:41:23 PM PDT 24
Peak memory 204844 kb
Host smart-08b5c2f6-ae7c-4a2d-b301-68dc764b4f7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=483607641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.483607641
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.753487310
Short name T1847
Test name
Test status
Simulation time 149406175 ps
CPU time 0.78 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:00 PM PDT 24
Peak memory 204624 kb
Host smart-1ad1c902-9005-48f6-b94a-e27ec4ab51cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75348
7310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.753487310
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.70552947
Short name T1185
Test name
Test status
Simulation time 147056829 ps
CPU time 0.78 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:40:56 PM PDT 24
Peak memory 204664 kb
Host smart-cb2f26ab-775b-45cd-bc81-42d97f06217a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70552
947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.70552947
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2394524981
Short name T1689
Test name
Test status
Simulation time 586453860 ps
CPU time 1.49 seconds
Started Jun 11 12:40:43 PM PDT 24
Finished Jun 11 12:40:46 PM PDT 24
Peak memory 204768 kb
Host smart-8381ce7f-d234-42ec-99c7-9892f03058d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23945
24981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2394524981
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1885443742
Short name T42
Test name
Test status
Simulation time 166604060 ps
CPU time 0.81 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204728 kb
Host smart-f2f9d8c1-a3c9-49b0-a4c8-cfc74f4b1f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18854
43742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1885443742
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1441258528
Short name T502
Test name
Test status
Simulation time 33728669 ps
CPU time 0.63 seconds
Started Jun 11 12:40:44 PM PDT 24
Finished Jun 11 12:40:46 PM PDT 24
Peak memory 204704 kb
Host smart-d04a0f73-29f7-47ae-a561-86e65c9d9d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
58528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1441258528
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2937221097
Short name T406
Test name
Test status
Simulation time 752272513 ps
CPU time 1.83 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204932 kb
Host smart-533f463f-6552-43ef-b901-fa3cd2d6c583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29372
21097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2937221097
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3075229575
Short name T869
Test name
Test status
Simulation time 172368009 ps
CPU time 1.59 seconds
Started Jun 11 12:40:48 PM PDT 24
Finished Jun 11 12:40:52 PM PDT 24
Peak memory 204788 kb
Host smart-168b220d-e3ff-484d-8bd5-9417e8e4ee71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
29575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3075229575
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1253435761
Short name T1617
Test name
Test status
Simulation time 208965627 ps
CPU time 0.87 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204672 kb
Host smart-6421ed54-4b7d-40db-8b06-f540ab01d742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12534
35761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1253435761
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.4192216294
Short name T473
Test name
Test status
Simulation time 136448279 ps
CPU time 0.78 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:04 PM PDT 24
Peak memory 204664 kb
Host smart-70f7bcc5-bb2d-4084-a03c-19132e021b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41922
16294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.4192216294
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3652918150
Short name T1667
Test name
Test status
Simulation time 251654568 ps
CPU time 0.94 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204712 kb
Host smart-a7a745c4-4a15-4df8-9b56-6175605987fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36529
18150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3652918150
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1757633521
Short name T2102
Test name
Test status
Simulation time 215498667 ps
CPU time 0.87 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:14 PM PDT 24
Peak memory 204640 kb
Host smart-94d1e9c7-e624-48a6-b867-6bfa59465511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
33521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1757633521
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3047725101
Short name T1069
Test name
Test status
Simulation time 3338990108 ps
CPU time 3.79 seconds
Started Jun 11 12:41:06 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204808 kb
Host smart-a758a8ff-e4ba-4bcf-8d9e-549af4aad401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30477
25101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3047725101
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3645300186
Short name T428
Test name
Test status
Simulation time 239660435 ps
CPU time 0.88 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:07 PM PDT 24
Peak memory 204672 kb
Host smart-41b2b137-9fc6-44db-bff7-0180da61e0f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3645300186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3645300186
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.202474141
Short name T762
Test name
Test status
Simulation time 184152087 ps
CPU time 0.85 seconds
Started Jun 11 12:40:52 PM PDT 24
Finished Jun 11 12:40:55 PM PDT 24
Peak memory 204784 kb
Host smart-6b387e68-01d3-40e7-8110-edae18da146b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
4141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.202474141
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.31999595
Short name T321
Test name
Test status
Simulation time 4740122606 ps
CPU time 45.05 seconds
Started Jun 11 12:40:59 PM PDT 24
Finished Jun 11 12:41:48 PM PDT 24
Peak memory 205008 kb
Host smart-c681298d-3c0d-47b4-a90f-1e90fcd28179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31999
595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.31999595
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2448693808
Short name T750
Test name
Test status
Simulation time 177090282 ps
CPU time 0.79 seconds
Started Jun 11 12:41:09 PM PDT 24
Finished Jun 11 12:41:13 PM PDT 24
Peak memory 204636 kb
Host smart-15cc973d-96aa-4aed-b115-23cdb035af2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2448693808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2448693808
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2573693811
Short name T900
Test name
Test status
Simulation time 150380292 ps
CPU time 0.82 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204724 kb
Host smart-ccd9fa0b-6260-47af-8627-cb8ba43a9d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25736
93811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2573693811
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1212007517
Short name T145
Test name
Test status
Simulation time 199130240 ps
CPU time 0.83 seconds
Started Jun 11 12:41:08 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204748 kb
Host smart-be74ae4e-668f-468f-bbd9-efa7a634d9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120
07517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1212007517
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3840287807
Short name T1284
Test name
Test status
Simulation time 155358543 ps
CPU time 0.76 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:41:10 PM PDT 24
Peak memory 204720 kb
Host smart-b982d55f-0b98-4a5a-a5f6-0dbc06bd3e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38402
87807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3840287807
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3533819323
Short name T1271
Test name
Test status
Simulation time 190950677 ps
CPU time 0.84 seconds
Started Jun 11 12:41:16 PM PDT 24
Finished Jun 11 12:41:22 PM PDT 24
Peak memory 204628 kb
Host smart-23e67cde-9efb-4be6-83e1-ef1a9329415f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35338
19323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3533819323
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.28958489
Short name T1164
Test name
Test status
Simulation time 204338683 ps
CPU time 0.88 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:01 PM PDT 24
Peak memory 204768 kb
Host smart-de976005-3592-482e-be21-8ba86f67568f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.28958489
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1129615742
Short name T181
Test name
Test status
Simulation time 160444194 ps
CPU time 0.81 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:41:08 PM PDT 24
Peak memory 204640 kb
Host smart-5504b04a-59c7-42c0-85f4-3679903c1530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
15742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1129615742
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_eop_single_bit_handling.3956722181
Short name T1115
Test name
Test status
Simulation time 167902293 ps
CPU time 0.79 seconds
Started Jun 11 12:41:00 PM PDT 24
Finished Jun 11 12:41:05 PM PDT 24
Peak memory 204688 kb
Host smart-b0c6e77f-68c6-433e-be68-34626d9bc9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39567
22181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_eop_single_bit_handling.3956722181
Directory /workspace/9.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3812726659
Short name T1530
Test name
Test status
Simulation time 138136392 ps
CPU time 0.74 seconds
Started Jun 11 12:40:56 PM PDT 24
Finished Jun 11 12:40:59 PM PDT 24
Peak memory 204724 kb
Host smart-7a3d67ea-8168-4ed0-ac94-73128a757474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
26659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3812726659
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.228753958
Short name T978
Test name
Test status
Simulation time 47304373 ps
CPU time 0.67 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:01 PM PDT 24
Peak memory 204664 kb
Host smart-6c5ae944-3175-4aff-a054-788579995898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22875
3958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.228753958
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.1595646878
Short name T1785
Test name
Test status
Simulation time 19021906402 ps
CPU time 42.86 seconds
Started Jun 11 12:41:03 PM PDT 24
Finished Jun 11 12:41:50 PM PDT 24
Peak memory 205024 kb
Host smart-7e4f8cbf-29ab-40ac-b993-460bec5b02d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15956
46878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.1595646878
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3295817671
Short name T520
Test name
Test status
Simulation time 173320858 ps
CPU time 0.8 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204668 kb
Host smart-3bc59ad5-7503-4ca5-b73a-423d51b496fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
17671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3295817671
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.508095224
Short name T731
Test name
Test status
Simulation time 205157486 ps
CPU time 0.85 seconds
Started Jun 11 12:41:07 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204624 kb
Host smart-8a3b5330-79b5-4a75-a711-3276c519dbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50809
5224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.508095224
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3996091570
Short name T1934
Test name
Test status
Simulation time 16101847079 ps
CPU time 140.05 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:43:26 PM PDT 24
Peak memory 205056 kb
Host smart-cf123450-2942-496d-ace4-a9640871b81a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3996091570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3996091570
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3080020493
Short name T204
Test name
Test status
Simulation time 22831150457 ps
CPU time 591.31 seconds
Started Jun 11 12:41:05 PM PDT 24
Finished Jun 11 12:51:00 PM PDT 24
Peak memory 205084 kb
Host smart-cec30e1e-4f10-4a42-92eb-e6fcc4b309b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3080020493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3080020493
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.241479444
Short name T1067
Test name
Test status
Simulation time 25313455776 ps
CPU time 585.72 seconds
Started Jun 11 12:40:50 PM PDT 24
Finished Jun 11 12:50:37 PM PDT 24
Peak memory 205076 kb
Host smart-451ea5d2-67a3-454f-bb38-a6f5390443af
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=241479444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.241479444
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.919067225
Short name T1395
Test name
Test status
Simulation time 214497176 ps
CPU time 0.89 seconds
Started Jun 11 12:41:02 PM PDT 24
Finished Jun 11 12:41:12 PM PDT 24
Peak memory 204712 kb
Host smart-a8cf8ff5-9df7-4548-a7f2-22041d1d7cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91906
7225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.919067225
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.93084582
Short name T437
Test name
Test status
Simulation time 171646120 ps
CPU time 0.8 seconds
Started Jun 11 12:40:58 PM PDT 24
Finished Jun 11 12:41:02 PM PDT 24
Peak memory 204732 kb
Host smart-3041b99e-fe86-49cd-986b-a2795cbd105e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93084
582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.93084582
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1266954872
Short name T1258
Test name
Test status
Simulation time 150004167 ps
CPU time 0.81 seconds
Started Jun 11 12:40:57 PM PDT 24
Finished Jun 11 12:41:00 PM PDT 24
Peak memory 204688 kb
Host smart-7fb8f19e-bf5f-4ff9-ad21-70cd88a018e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12669
54872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1266954872
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.4113685937
Short name T1626
Test name
Test status
Simulation time 154503123 ps
CPU time 0.77 seconds
Started Jun 11 12:41:19 PM PDT 24
Finished Jun 11 12:41:25 PM PDT 24
Peak memory 204624 kb
Host smart-8238969e-2779-42b4-8687-b5fdfb2a6bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41136
85937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.4113685937
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1925232307
Short name T609
Test name
Test status
Simulation time 144314443 ps
CPU time 0.78 seconds
Started Jun 11 12:41:13 PM PDT 24
Finished Jun 11 12:41:19 PM PDT 24
Peak memory 204704 kb
Host smart-7caf5dee-5803-4e18-b6f3-7ec1257344a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19252
32307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1925232307
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3270225275
Short name T190
Test name
Test status
Simulation time 311565993 ps
CPU time 1.02 seconds
Started Jun 11 12:40:58 PM PDT 24
Finished Jun 11 12:41:02 PM PDT 24
Peak memory 204984 kb
Host smart-a8c07255-9316-4e7e-b385-85699e5b9825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32702
25275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3270225275
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2005368181
Short name T1265
Test name
Test status
Simulation time 160648847 ps
CPU time 0.84 seconds
Started Jun 11 12:41:04 PM PDT 24
Finished Jun 11 12:41:09 PM PDT 24
Peak memory 204736 kb
Host smart-e406f763-d53d-42dd-a10c-cea7cb651793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20053
68181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2005368181
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.263079795
Short name T730
Test name
Test status
Simulation time 187893019 ps
CPU time 0.79 seconds
Started Jun 11 12:41:11 PM PDT 24
Finished Jun 11 12:41:15 PM PDT 24
Peak memory 204672 kb
Host smart-2906bedc-5441-4c9e-8898-963193dbfd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26307
9795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.263079795
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.84744253
Short name T364
Test name
Test status
Simulation time 14685935827 ps
CPU time 102.68 seconds
Started Jun 11 12:40:53 PM PDT 24
Finished Jun 11 12:42:38 PM PDT 24
Peak memory 204912 kb
Host smart-eb6458ed-37d9-49c5-aade-a2eb463c42fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84744
253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.84744253
Directory /workspace/9.usbdev_streaming_out/latest
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