Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19666983	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19997846	1		T1	20		T2	14		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39130782	1		T1	20		T2	129		T3	3
values[0x0]	267073	1		T1	4		T2	9		T3	6
values[0x1]	266974	1		T1	7		T2	9		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15687151	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	23977678	1		T1	24		T2	63		T3	7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	117532	1		T27	1		T7	2		T77	3
valid_sources[0x01]	115308	1		T77	1		T5	318		T6	1032
valid_sources[0x02]	115726	1		T7	4		T5	244		T6	1069
valid_sources[0x03]	117256	1		T8	3		T77	4		T5	443
valid_sources[0x04]	274298	1		T1	1		T27	3		T5	290
valid_sources[0x05]	116675	1		T27	4		T7	2		T29	1
valid_sources[0x06]	134815	1		T7	2		T8	6		T29	2
valid_sources[0x07]	117544	1		T8	2		T81	1		T77	2
valid_sources[0x08]	316726	1		T27	2		T77	7		T5	250
valid_sources[0x09]	367167	1		T65	1		T77	3		T5	213
valid_sources[0x0a]	114876	1		T27	1		T7	2		T77	1
valid_sources[0x0b]	117196	1		T7	1		T77	6		T5	315
valid_sources[0x0c]	155139	1		T19	1		T27	1		T29	1
valid_sources[0x0d]	116664	1		T8	5		T79	1		T77	4
valid_sources[0x0e]	117700	1		T7	8		T8	1		T29	1
valid_sources[0x0f]	115926	1		T2	5		T27	1		T8	4
valid_sources[0x10]	117759	1		T2	2		T27	2		T7	11
valid_sources[0x11]	116397	1		T19	1		T27	2		T77	14
valid_sources[0x12]	117910	1		T1	1		T27	1		T7	6
valid_sources[0x13]	210118	1		T27	4		T7	1		T77	1
valid_sources[0x14]	115451	1		T7	10		T8	2		T77	6
valid_sources[0x15]	115458	1		T81	1		T77	10		T5	156
valid_sources[0x16]	116877	1		T7	20		T8	3		T81	2
valid_sources[0x17]	116745	1		T2	1		T7	3		T8	3
valid_sources[0x18]	216087	1		T2	3		T7	7		T77	3
valid_sources[0x19]	133297	1		T27	1		T77	2		T5	245
valid_sources[0x1a]	115579	1		T8	1		T77	4		T5	346
valid_sources[0x1b]	231620	1		T17	1		T8	4		T5	209
valid_sources[0x1c]	117184	1		T17	1		T27	1		T7	8
valid_sources[0x1d]	116727	1		T1	1		T22	1		T27	1
valid_sources[0x1e]	117928	1		T27	2		T79	2		T77	2
valid_sources[0x1f]	118492	1		T7	6		T8	2		T77	5
valid_sources[0x20]	115573	1		T7	1		T77	2		T5	541
valid_sources[0x21]	282243	1		T27	2		T77	11		T5	126
valid_sources[0x22]	117591	1		T27	2		T7	1		T77	3
valid_sources[0x23]	117646	1		T3	1		T8	2		T77	2
valid_sources[0x24]	118660	1		T3	4		T7	13		T77	4
valid_sources[0x25]	540894	1		T27	3		T8	1		T77	4
valid_sources[0x26]	116466	1		T19	1		T7	1		T77	10
valid_sources[0x27]	117808	1		T21	1		T27	2		T7	24
valid_sources[0x28]	116628	1		T1	1		T27	2		T7	1
valid_sources[0x29]	117669	1		T8	3		T77	4		T5	209
valid_sources[0x2a]	117971	1		T77	3		T5	268		T6	1085
valid_sources[0x2b]	116824	1		T27	2		T7	14		T8	2
valid_sources[0x2c]	247014	1		T77	4		T5	462		T6	1011
valid_sources[0x2d]	116146	1		T1	1		T27	1		T7	5
valid_sources[0x2e]	115463	1		T27	2		T77	11		T5	160
valid_sources[0x2f]	116519	1		T2	5		T19	1		T7	3
valid_sources[0x30]	116924	1		T2	13		T17	2		T8	3
valid_sources[0x31]	117627	1		T27	1		T8	2		T77	3
valid_sources[0x32]	117876	1		T8	1		T77	1		T5	220
valid_sources[0x33]	117545	1		T2	7		T17	2		T27	1
valid_sources[0x34]	370206	1		T18	2		T7	8		T8	2
valid_sources[0x35]	114558	1		T19	1		T27	2		T7	2
valid_sources[0x36]	145428	1		T1	1		T19	1		T27	1
valid_sources[0x37]	116687	1		T2	6		T19	1		T8	9
valid_sources[0x38]	153418	1		T1	1		T2	3		T27	1
valid_sources[0x39]	117699	1		T27	1		T8	3		T77	1
valid_sources[0x3a]	115584	1		T2	10		T27	1		T77	2
valid_sources[0x3b]	116233	1		T27	1		T7	4		T8	3
valid_sources[0x3c]	116655	1		T27	2		T8	2		T5	404
valid_sources[0x3d]	116873	1		T29	1		T77	6		T5	112
valid_sources[0x3e]	162168	1		T27	2		T7	2		T8	1
valid_sources[0x3f]	118122	1		T1	1		T77	2		T5	311
valid_sources[0x40]	115093	1		T3	1		T18	1		T19	1
valid_sources[0x41]	117184	1		T77	11		T5	274		T6	1193
valid_sources[0x42]	116219	1		T27	1		T7	2		T29	1
valid_sources[0x43]	117584	1		T19	1		T27	1		T7	11
valid_sources[0x44]	116093	1		T8	2		T28	9		T77	3
valid_sources[0x45]	117868	1		T27	1		T7	9		T8	1
valid_sources[0x46]	148514	1		T7	8		T8	8		T65	1
valid_sources[0x47]	116770	1		T27	1		T7	5		T77	6
valid_sources[0x48]	113723	1		T22	3		T7	3		T8	1
valid_sources[0x49]	377473	1		T27	1		T8	2		T29	1
valid_sources[0x4a]	654091	1		T1	1		T2	6		T7	1
valid_sources[0x4b]	116942	1		T27	1		T7	4		T8	4
valid_sources[0x4c]	117751	1		T7	3		T8	1		T77	4
valid_sources[0x4d]	116855	1		T2	4		T27	1		T77	12
valid_sources[0x4e]	144041	1		T7	15		T8	5		T5	291
valid_sources[0x4f]	497122	1		T1	1		T27	1		T8	1
valid_sources[0x50]	117649	1		T19	1		T27	1		T7	1
valid_sources[0x51]	116515	1		T7	10		T77	5		T5	297
valid_sources[0x52]	116907	1		T7	1		T77	8		T5	271
valid_sources[0x53]	115821	1		T27	1		T77	8		T5	389
valid_sources[0x54]	118060	1		T19	1		T21	1		T7	1
valid_sources[0x55]	117891	1		T18	1		T21	1		T29	1
valid_sources[0x56]	115525	1		T27	2		T29	1		T79	1
valid_sources[0x57]	339921	1		T2	1		T7	4		T8	1
valid_sources[0x58]	116642	1		T27	2		T29	1		T77	2
valid_sources[0x59]	118658	1		T8	1		T29	2		T77	1
valid_sources[0x5a]	115698	1		T27	2		T5	232		T6	1057
valid_sources[0x5b]	172466	1		T27	2		T7	3		T77	1
valid_sources[0x5c]	117060	1		T22	2		T77	3		T5	363
valid_sources[0x5d]	115353	1		T21	1		T7	1		T8	1
valid_sources[0x5e]	288819	1		T2	2		T27	1		T77	17
valid_sources[0x5f]	116317	1		T8	2		T77	3		T5	318
valid_sources[0x60]	116065	1		T2	6		T7	1		T8	1
valid_sources[0x61]	115576	1		T7	1		T8	2		T77	1
valid_sources[0x62]	187119	1		T27	1		T77	2		T5	92
valid_sources[0x63]	116612	1		T8	1		T77	4		T5	177
valid_sources[0x64]	115902	1		T7	7		T77	5		T5	144
valid_sources[0x65]	119085	1		T79	1		T77	3		T5	287
valid_sources[0x66]	168918	1		T27	1		T8	1		T77	1
valid_sources[0x67]	116609	1		T19	1		T7	5		T8	5
valid_sources[0x68]	122323	1		T1	1		T7	6		T29	1
valid_sources[0x69]	116583	1		T7	12		T8	1		T77	1
valid_sources[0x6a]	117569	1		T19	1		T7	8		T75	2
valid_sources[0x6b]	420370	1		T7	1		T77	1		T5	100
valid_sources[0x6c]	117847	1		T21	1		T77	10		T5	467
valid_sources[0x6d]	116411	1		T19	1		T7	7		T8	1
valid_sources[0x6e]	117132	1		T7	6		T8	3		T77	5
valid_sources[0x6f]	179406	1		T7	6		T65	2		T103	2
valid_sources[0x70]	117041	1		T27	2		T8	11		T29	1
valid_sources[0x71]	342478	1		T7	13		T4	223849		T77	5
valid_sources[0x72]	116626	1		T27	2		T75	1		T77	3
valid_sources[0x73]	116467	1		T27	1		T7	7		T8	4
valid_sources[0x74]	117123	1		T8	2		T77	1		T5	193
valid_sources[0x75]	118406	1		T2	3		T7	8		T8	8
valid_sources[0x76]	116164	1		T1	1		T3	1		T27	1
valid_sources[0x77]	185663	1		T27	3		T7	10		T8	1
valid_sources[0x78]	118308	1		T27	1		T77	2		T5	175
valid_sources[0x79]	117021	1		T2	5		T7	11		T77	4
valid_sources[0x7a]	116096	1		T27	2		T7	4		T103	3
valid_sources[0x7b]	117450	1		T1	2		T17	1		T18	1
valid_sources[0x7c]	117073	1		T8	4		T5	281		T6	1152
valid_sources[0x7d]	115733	1		T27	1		T7	5		T77	14
valid_sources[0x7e]	116207	1		T7	7		T77	4		T5	380
valid_sources[0x7f]	116816	1		T1	1		T19	1		T8	1
valid_sources[0x80]	116923	1		T2	4		T27	1		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19583119

1

T1

14

T2

2

T3

1

values[0x0]

all_enables

biggest_size

214441

1

T1

3

T2

5

T3

4

values[0x1]

all_enables

biggest_size

200286

1

T1

3

T2

7

T3

1