Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19680642	1		T1	11		T2	133		T3	6
full_word	19998835	1		T1	20		T2	14		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	39679167	1		T1	31		T2	147		T3	12
auto[TlIntgErrCmd]	117	1		T203	6		T227	5		T228	9
auto[TlIntgErrData]	99	1		T203	10		T228	6		T285	7
auto[TlIntgErrBoth]	94	1		T203	4		T227	5		T228	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39132610	1		T1	20		T2	129		T3	3
auto[1]	546867	1		T1	11		T2	18		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19549207	1		T1	6		T2	127		T3	2
auto[TlIntgErrNone]	partial	auto[1]	131142	1		T1	5		T2	6		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	19583279	1		T1	14		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	415539	1		T1	6		T2	12		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T203	3		T227	1		T228	2
auto[TlIntgErrCmd]	partial	auto[1]	71	1		T203	2		T227	4		T228	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T203	1		T287	1		T241	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T290	1		T291	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1		T203	1		T228	3		T285	3
auto[TlIntgErrData]	partial	auto[1]	46	1		T203	7		T228	3		T285	4
auto[TlIntgErrData]	full_word	auto[0]	2	1		T203	1		T241	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1		T203	1		T290	2		T287	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T203	1		T227	2		T228	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T203	3		T227	3		T228	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T286	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T286	1		T235	1		T292	1