Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	395926667	10254	0	0
ep_in_enable_rd_A	395926667	3527	0	0
ep_out_enable_rd_A	395926667	3058	0	0
in_iso_rd_A	395926667	3198	0	0
intr_enable_rd_A	395926667	3722	0	0
out_iso_rd_A	395926667	2970	0	0
phy_config_rd_A	395926667	2207	0	0
phy_pins_drive_rd_A	395926667	2878	0	0
rxenable_setup_rd_A	395926667	3218	0	0
set_nak_out_rd_A	395926667	3118	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	10254	0	0
T198	8281	337	0	0
T199	2720	359	0	0
T200	9458	618	0	0
T202	9737	18	0	0
T203	41021	3	0	0
T228	44149	3	0	0
T229	4605	699	0	0
T233	3849	381	0	0
T237	7555	10	0	0
T240	6846	13	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	3527	0	0
T198	8281	9	0	0
T202	9737	89	0	0
T203	41021	495	0	0
T228	44149	592	0	0
T237	7555	14	0	0
T240	6846	74	0	0
T251	10079	82	0	0
T260	16017	10	0	0
T262	2615	44	0	0
T266	5694	4	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	3058	0	0
T202	9737	69	0	0
T203	41021	480	0	0
T228	44149	375	0	0
T237	7555	8	0	0
T240	6846	67	0	0
T251	10079	92	0	0
T252	20441	80	0	0
T260	16017	7	0	0
T262	2615	48	0	0
T266	5694	55	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	3198	0	0
T202	9737	37	0	0
T203	41021	525	0	0
T228	44149	554	0	0
T237	7555	14	0	0
T240	6846	11	0	0
T251	10079	64	0	0
T252	20441	97	0	0
T260	16017	16	0	0
T262	2615	6	0	0
T266	5694	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	3722	0	0
T202	9737	155	0	0
T203	41021	375	0	0
T208	2051	9	0	0
T228	44149	718	0	0
T237	7555	3	0	0
T240	6846	8	0	0
T260	16017	30	0	0
T267	2165	31	0	0
T268	1995	6	0	0
T269	1979	26	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	2970	0	0
T202	9737	114	0	0
T203	41021	390	0	0
T228	44149	471	0	0
T237	7555	44	0	0
T240	6846	18	0	0
T251	10079	85	0	0
T252	20441	110	0	0
T260	16017	7	0	0
T262	2615	4	0	0
T266	5694	4	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	2207	0	0
T198	8281	5	0	0
T202	9737	48	0	0
T203	41021	195	0	0
T228	44149	374	0	0
T237	7555	5	0	0
T240	6846	25	0	0
T251	10079	116	0	0
T252	20441	86	0	0
T260	16017	33	0	0
T262	2615	22	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	2878	0	0
T202	9737	48	0	0
T203	41021	376	0	0
T228	44149	349	0	0
T237	7555	35	0	0
T240	6846	59	0	0
T251	10079	73	0	0
T252	20441	135	0	0
T260	16017	49	0	0
T262	2615	34	0	0
T266	5694	12	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	3218	0	0
T202	9737	48	0	0
T203	41021	517	0	0
T228	44149	472	0	0
T237	7555	13	0	0
T240	6846	101	0	0
T251	10079	85	0	0
T252	20441	77	0	0
T260	16017	28	0	0
T262	2615	62	0	0
T266	5694	4	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395926667	3118	0	0
T202	9737	66	0	0
T203	41021	390	0	0
T228	44149	563	0	0
T237	7555	10	0	0
T240	6846	22	0	0
T251	10079	73	0	0
T252	20441	79	0	0
T260	16017	17	0	0
T262	2615	29	0	0
T266	5694	23	0	0