Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T77,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T77,T43 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T60,T61,T82 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T77,T43 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T4,T77,T43 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T43,T5 |
Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T77,T43 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
171945631 |
0 |
0 |
T4 |
454488 |
448398 |
0 |
0 |
T5 |
0 |
939116 |
0 |
0 |
T6 |
0 |
732153 |
0 |
0 |
T8 |
178189 |
0 |
0 |
0 |
T28 |
10360 |
0 |
0 |
0 |
T29 |
11370 |
0 |
0 |
0 |
T43 |
0 |
568 |
0 |
0 |
T44 |
0 |
567 |
0 |
0 |
T65 |
10159 |
0 |
0 |
0 |
T73 |
0 |
675873 |
0 |
0 |
T75 |
8685 |
0 |
0 |
0 |
T76 |
8788 |
0 |
0 |
0 |
T77 |
0 |
2332 |
0 |
0 |
T79 |
10570 |
0 |
0 |
0 |
T80 |
6803 |
0 |
0 |
0 |
T81 |
7140 |
0 |
0 |
0 |
T83 |
0 |
424624 |
0 |
0 |
T84 |
0 |
104406 |
0 |
0 |
T85 |
0 |
562 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
171945631 |
0 |
0 |
T4 |
454488 |
448398 |
0 |
0 |
T5 |
0 |
939116 |
0 |
0 |
T6 |
0 |
732153 |
0 |
0 |
T8 |
178189 |
0 |
0 |
0 |
T28 |
10360 |
0 |
0 |
0 |
T29 |
11370 |
0 |
0 |
0 |
T43 |
0 |
568 |
0 |
0 |
T44 |
0 |
567 |
0 |
0 |
T65 |
10159 |
0 |
0 |
0 |
T73 |
0 |
675873 |
0 |
0 |
T75 |
8685 |
0 |
0 |
0 |
T76 |
8788 |
0 |
0 |
0 |
T77 |
0 |
2332 |
0 |
0 |
T79 |
10570 |
0 |
0 |
0 |
T80 |
6803 |
0 |
0 |
0 |
T81 |
7140 |
0 |
0 |
0 |
T83 |
0 |
424624 |
0 |
0 |
T84 |
0 |
104406 |
0 |
0 |
T85 |
0 |
562 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
| Total | Covered | Percent |
Conditions | 14 | 10 | 71.43 |
Logical | 14 | 10 | 71.43 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T77,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T62,T86 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_avoutfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
199112650 |
0 |
0 |
T1 |
13762 |
1783 |
0 |
0 |
T2 |
641687 |
1006 |
0 |
0 |
T3 |
10010 |
1240 |
0 |
0 |
T16 |
7202 |
310 |
0 |
0 |
T17 |
8976 |
2445 |
0 |
0 |
T18 |
6830 |
1099 |
0 |
0 |
T19 |
9784 |
1936 |
0 |
0 |
T20 |
12809 |
4759 |
0 |
0 |
T21 |
8373 |
2612 |
0 |
0 |
T22 |
8543 |
2390 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
199112650 |
0 |
0 |
T1 |
13762 |
1783 |
0 |
0 |
T2 |
641687 |
1006 |
0 |
0 |
T3 |
10010 |
1240 |
0 |
0 |
T16 |
7202 |
310 |
0 |
0 |
T17 |
8976 |
2445 |
0 |
0 |
T18 |
6830 |
1099 |
0 |
0 |
T19 |
9784 |
1936 |
0 |
0 |
T20 |
12809 |
4759 |
0 |
0 |
T21 |
8373 |
2612 |
0 |
0 |
T22 |
8543 |
2390 |
0 |
0 |
Line Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T48,T49,T50 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T16 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.usbdev_rxfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
20713591 |
0 |
0 |
T1 |
13762 |
89 |
0 |
0 |
T2 |
641687 |
108 |
0 |
0 |
T3 |
10010 |
2293 |
0 |
0 |
T4 |
0 |
1659 |
0 |
0 |
T7 |
0 |
108 |
0 |
0 |
T8 |
0 |
108 |
0 |
0 |
T16 |
7202 |
91 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
91 |
0 |
0 |
T20 |
12809 |
109 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
1068 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
20713591 |
0 |
0 |
T1 |
13762 |
89 |
0 |
0 |
T2 |
641687 |
108 |
0 |
0 |
T3 |
10010 |
2293 |
0 |
0 |
T4 |
0 |
1659 |
0 |
0 |
T7 |
0 |
108 |
0 |
0 |
T8 |
0 |
108 |
0 |
0 |
T16 |
7202 |
91 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
91 |
0 |
0 |
T20 |
12809 |
109 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
1068 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
40020111 |
0 |
0 |
T1 |
13762 |
31 |
0 |
0 |
T2 |
641687 |
147 |
0 |
0 |
T3 |
10010 |
12 |
0 |
0 |
T16 |
7202 |
12 |
0 |
0 |
T17 |
8976 |
11 |
0 |
0 |
T18 |
6830 |
10 |
0 |
0 |
T19 |
9784 |
26 |
0 |
0 |
T20 |
12809 |
14 |
0 |
0 |
T21 |
8373 |
10 |
0 |
0 |
T22 |
8543 |
10 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2607 |
2607 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
52810016 |
0 |
0 |
T1 |
13762 |
31 |
0 |
0 |
T2 |
641687 |
450 |
0 |
0 |
T3 |
10010 |
46 |
0 |
0 |
T16 |
7202 |
12 |
0 |
0 |
T17 |
8976 |
59 |
0 |
0 |
T18 |
6830 |
10 |
0 |
0 |
T19 |
9784 |
26 |
0 |
0 |
T20 |
12809 |
65 |
0 |
0 |
T21 |
8373 |
10 |
0 |
0 |
T22 |
8543 |
27 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2607 |
2607 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
417804 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
15 |
0 |
0 |
T44 |
0 |
13 |
0 |
0 |
T72 |
0 |
5870 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2607 |
2607 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
965473 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
15 |
0 |
0 |
T44 |
0 |
13 |
0 |
0 |
T72 |
0 |
26512 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2607 |
2607 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
39529824 |
0 |
0 |
T1 |
13762 |
19 |
0 |
0 |
T2 |
641687 |
147 |
0 |
0 |
T3 |
10010 |
12 |
0 |
0 |
T16 |
7202 |
12 |
0 |
0 |
T17 |
8976 |
11 |
0 |
0 |
T18 |
6830 |
10 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
14 |
0 |
0 |
T21 |
8373 |
10 |
0 |
0 |
T22 |
8543 |
10 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2607 |
2607 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
51844543 |
0 |
0 |
T1 |
13762 |
19 |
0 |
0 |
T2 |
641687 |
450 |
0 |
0 |
T3 |
10010 |
46 |
0 |
0 |
T16 |
7202 |
12 |
0 |
0 |
T17 |
8976 |
59 |
0 |
0 |
T18 |
6830 |
10 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
65 |
0 |
0 |
T21 |
8373 |
10 |
0 |
0 |
T22 |
8543 |
27 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
395926667 |
395681006 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2607 |
2607 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T20 |
1 |
1 |
0 |
0 |
T21 |
1 |
1 |
0 |
0 |
T22 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T19,T27 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T19,T27 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T19,T27 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T75,T76,T29 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T19,T27 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T19,T27 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T19,T27 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T19,T27 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
905787 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
15 |
0 |
0 |
T44 |
0 |
13 |
0 |
0 |
T72 |
0 |
26512 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
905787 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
15 |
0 |
0 |
T44 |
0 |
13 |
0 |
0 |
T72 |
0 |
26512 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T19,T27 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T19,T27 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T19,T27 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T19,T27 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T19,T27 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T19,T27 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T19,T27 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
218838 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T44 |
0 |
9 |
0 |
0 |
T72 |
0 |
3501 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
218838 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T44 |
0 |
9 |
0 |
0 |
T72 |
0 |
3501 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T72,T73,T74 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T19,T27 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T19,T27 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T75,T76,T29 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T19,T27 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T19,T27 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T19,T27 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T72,T73,T74 |
1 | 0 | Covered | T1,T19,T27 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T19,T27 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T19,T27 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T19,T27 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T19,T27 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
520069 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T44 |
0 |
9 |
0 |
0 |
T72 |
0 |
15835 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
393901825 |
0 |
0 |
T1 |
13762 |
13704 |
0 |
0 |
T2 |
641687 |
641614 |
0 |
0 |
T3 |
10010 |
9954 |
0 |
0 |
T16 |
7202 |
7123 |
0 |
0 |
T17 |
8976 |
8923 |
0 |
0 |
T18 |
6830 |
6775 |
0 |
0 |
T19 |
9784 |
9708 |
0 |
0 |
T20 |
12809 |
12758 |
0 |
0 |
T21 |
8373 |
8293 |
0 |
0 |
T22 |
8543 |
8470 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
394092123 |
520069 |
0 |
0 |
T1 |
13762 |
12 |
0 |
0 |
T2 |
641687 |
0 |
0 |
0 |
T3 |
10010 |
0 |
0 |
0 |
T16 |
7202 |
0 |
0 |
0 |
T17 |
8976 |
0 |
0 |
0 |
T18 |
6830 |
0 |
0 |
0 |
T19 |
9784 |
13 |
0 |
0 |
T20 |
12809 |
0 |
0 |
0 |
T21 |
8373 |
0 |
0 |
0 |
T22 |
8543 |
0 |
0 |
0 |
T27 |
0 |
80 |
0 |
0 |
T29 |
0 |
15 |
0 |
0 |
T43 |
0 |
4 |
0 |
0 |
T44 |
0 |
9 |
0 |
0 |
T72 |
0 |
15835 |
0 |
0 |
T75 |
0 |
2 |
0 |
0 |
T76 |
0 |
16 |
0 |
0 |
T78 |
0 |
6 |
0 |
0 |