Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	377	1		T1	5		T7	8		T8	2
all_values[1]	377	1		T1	5		T7	8		T8	2
all_values[2]	377	1		T1	5		T7	8		T8	2
all_values[3]	377	1		T1	5		T7	8		T8	2
all_values[4]	377	1		T1	5		T7	8		T8	2
all_values[5]	377	1		T1	5		T7	8		T8	2
all_values[6]	377	1		T1	5		T7	8		T8	2
all_values[7]	377	1		T1	5		T7	8		T8	2
all_values[8]	377	1		T1	5		T7	8		T8	2
all_values[9]	377	1		T1	5		T7	8		T8	2
all_values[10]	377	1		T1	5		T7	8		T8	2
all_values[11]	377	1		T1	5		T7	8		T8	2
all_values[12]	377	1		T1	5		T7	8		T8	2
all_values[13]	377	1		T1	5		T7	8		T8	2
all_values[14]	377	1		T1	5		T7	8		T8	2
all_values[15]	377	1		T1	5		T7	8		T8	2
all_values[16]	377	1		T1	5		T7	8		T8	2
all_values[17]	377	1		T1	5		T7	8		T8	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3734	1		T1	41		T7	73		T8	36
auto[1]	3052	1		T1	49		T7	71		T9	74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1597	1		T1	37		T7	13		T8	36
auto[1]	5189	1		T1	53		T7	131		T9	118

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	68	1		T1	3		T7	2		T8	2
all_values[0]	auto[0]	auto[1]	174	1		T7	1		T9	7		T16	6
all_values[0]	auto[1]	auto[0]	22	1		T1	2		T7	1		T68	1
all_values[0]	auto[1]	auto[1]	113	1		T7	4		T9	1		T16	2
all_values[1]	auto[0]	auto[0]	58	1		T1	3		T8	2		T10	2
all_values[1]	auto[0]	auto[1]	147	1		T7	4		T9	4		T16	2
all_values[1]	auto[1]	auto[0]	25	1		T1	2		T69	4		T70	4
all_values[1]	auto[1]	auto[1]	147	1		T7	4		T9	4		T16	6
all_values[2]	auto[0]	auto[0]	69	1		T1	1		T8	2		T9	1
all_values[2]	auto[0]	auto[1]	148	1		T7	7		T16	8		T66	4
all_values[2]	auto[1]	auto[0]	37	1		T1	4		T9	7		T68	1
all_values[2]	auto[1]	auto[1]	123	1		T7	1		T66	1		T68	2
all_values[3]	auto[0]	auto[0]	76	1		T8	2		T10	2		T20	2
all_values[3]	auto[0]	auto[1]	102	1		T1	5		T9	4		T16	7
all_values[3]	auto[1]	auto[0]	35	1		T7	2		T71	1		T69	5
all_values[3]	auto[1]	auto[1]	164	1		T7	6		T9	4		T16	1
all_values[4]	auto[0]	auto[0]	58	1		T8	2		T9	1		T10	2
all_values[4]	auto[0]	auto[1]	143	1		T7	6		T9	4		T16	4
all_values[4]	auto[1]	auto[0]	22	1		T1	1		T9	3		T66	5
all_values[4]	auto[1]	auto[1]	154	1		T1	4		T7	2		T16	4
all_values[5]	auto[0]	auto[0]	67	1		T8	2		T10	2		T20	2
all_values[5]	auto[0]	auto[1]	148	1		T1	4		T7	2		T9	5
all_values[5]	auto[1]	auto[0]	21	1		T1	1		T16	3		T68	2
all_values[5]	auto[1]	auto[1]	141	1		T7	6		T9	3		T16	4
all_values[6]	auto[0]	auto[0]	68	1		T8	2		T16	1		T10	2
all_values[6]	auto[0]	auto[1]	143	1		T7	5		T9	2		T16	2
all_values[6]	auto[1]	auto[0]	34	1		T1	5		T7	1		T9	1
all_values[6]	auto[1]	auto[1]	132	1		T7	2		T9	5		T16	5
all_values[7]	auto[0]	auto[0]	68	1		T7	2		T8	2		T9	2
all_values[7]	auto[0]	auto[1]	152	1		T1	1		T7	1		T9	4
all_values[7]	auto[1]	auto[0]	23	1		T66	1		T72	1		T73	1
all_values[7]	auto[1]	auto[1]	134	1		T1	4		T7	5		T9	2
all_values[8]	auto[0]	auto[0]	76	1		T1	4		T8	2		T9	2
all_values[8]	auto[0]	auto[1]	130	1		T7	7		T9	4		T16	6
all_values[8]	auto[1]	auto[0]	17	1		T1	1		T9	1		T16	1
all_values[8]	auto[1]	auto[1]	154	1		T7	1		T9	1		T16	1
all_values[9]	auto[0]	auto[0]	65	1		T1	1		T7	1		T8	2
all_values[9]	auto[0]	auto[1]	171	1		T1	3		T7	2		T9	7
all_values[9]	auto[1]	auto[0]	15	1		T7	1		T16	1		T66	1
all_values[9]	auto[1]	auto[1]	126	1		T1	1		T7	4		T9	1
all_values[10]	auto[0]	auto[0]	65	1		T8	2		T10	2		T20	2
all_values[10]	auto[0]	auto[1]	144	1		T1	2		T7	5		T9	4
all_values[10]	auto[1]	auto[0]	16	1		T66	1		T74	1		T69	1
all_values[10]	auto[1]	auto[1]	152	1		T1	3		T7	3		T9	4
all_values[11]	auto[0]	auto[0]	65	1		T8	2		T9	2		T10	2
all_values[11]	auto[0]	auto[1]	117	1		T7	6		T9	2		T66	5
all_values[11]	auto[1]	auto[0]	20	1		T16	1		T74	5		T70	2
all_values[11]	auto[1]	auto[1]	175	1		T1	5		T7	2		T9	4
all_values[12]	auto[0]	auto[0]	62	1		T8	2		T10	2		T20	2
all_values[12]	auto[0]	auto[1]	128	1		T9	2		T16	2		T66	3
all_values[12]	auto[1]	auto[0]	21	1		T75	1		T76	1		T77	1
all_values[12]	auto[1]	auto[1]	166	1		T1	5		T7	8		T9	6
all_values[13]	auto[0]	auto[0]	56	1		T1	3		T8	2		T10	2
all_values[13]	auto[0]	auto[1]	144	1		T7	2		T9	4		T16	7
all_values[13]	auto[1]	auto[0]	20	1		T1	2		T16	1		T66	1
all_values[13]	auto[1]	auto[1]	157	1		T7	6		T9	4		T66	1
all_values[14]	auto[0]	auto[0]	64	1		T1	1		T8	2		T16	2
all_values[14]	auto[0]	auto[1]	143	1		T1	3		T7	5		T9	1
all_values[14]	auto[1]	auto[0]	27	1		T1	1		T9	1		T66	2
all_values[14]	auto[1]	auto[1]	143	1		T7	3		T9	6		T16	2
all_values[15]	auto[0]	auto[0]	55	1		T8	2		T10	2		T20	2
all_values[15]	auto[0]	auto[1]	149	1		T1	4		T7	6		T9	1
all_values[15]	auto[1]	auto[0]	20	1		T66	1		T74	1		T78	1
all_values[15]	auto[1]	auto[1]	153	1		T1	1		T7	2		T9	7
all_values[16]	auto[0]	auto[0]	69	1		T1	1		T8	2		T9	1
all_values[16]	auto[0]	auto[1]	131	1		T1	1		T7	3		T9	3
all_values[16]	auto[1]	auto[0]	35	1		T7	3		T9	1		T16	2
all_values[16]	auto[1]	auto[1]	142	1		T1	3		T7	2		T9	3
all_values[17]	auto[0]	auto[0]	59	1		T1	1		T8	2		T9	2
all_values[17]	auto[0]	auto[1]	152	1		T7	6		T9	1		T16	2
all_values[17]	auto[1]	auto[0]	19	1		T9	1		T70	1		T75	1
all_values[17]	auto[1]	auto[1]	147	1		T1	4		T7	2		T9	4