Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
68.29 66.31 60.02 87.21 0.00 70.24 98.04 96.22


Total tests in report: 175
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.53 52.53 60.88 60.88 49.41 49.41 85.56 85.56 0.00 0.00 62.70 62.70 93.30 93.30 15.86 15.86 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3046631617
59.86 7.33 62.90 2.03 50.71 1.30 89.79 4.23 0.00 0.00 63.27 0.57 93.58 0.28 58.74 42.88 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4022615095
63.39 3.53 63.89 0.98 53.53 2.82 90.85 1.06 0.00 0.00 63.36 0.08 95.53 1.96 76.58 17.84 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2720429513
65.99 2.60 65.33 1.44 59.25 5.72 93.43 2.58 0.00 0.00 69.79 6.43 96.65 1.12 77.48 0.90 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3954418826
66.95 0.96 65.33 0.00 59.25 0.00 93.66 0.23 0.00 0.00 69.79 0.00 96.65 0.00 83.96 6.49 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3830348249
67.70 0.75 65.37 0.04 59.34 0.09 94.37 0.70 0.00 0.00 69.87 0.08 96.65 0.00 88.29 4.32 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3837485756
68.12 0.42 66.31 0.95 59.76 0.42 95.31 0.94 0.00 0.00 70.24 0.37 96.93 0.28 88.29 0.00 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1628672179
68.49 0.37 66.31 0.00 59.76 0.00 95.31 0.00 0.00 0.00 70.24 0.00 97.21 0.28 90.63 2.34 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3066215813
68.75 0.26 66.31 0.00 59.76 0.00 95.31 0.00 0.00 0.00 70.24 0.00 97.21 0.00 92.43 1.80 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2365980097
68.91 0.15 66.31 0.00 59.76 0.00 95.31 0.00 0.00 0.00 70.24 0.00 97.21 0.00 93.51 1.08 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3705398668
69.06 0.15 66.31 0.00 59.76 0.00 95.54 0.23 0.00 0.00 70.24 0.00 97.49 0.28 94.05 0.54 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.824601883
69.16 0.11 66.31 0.00 59.76 0.00 95.54 0.00 0.00 0.00 70.24 0.00 98.04 0.56 94.23 0.18 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3117331781
69.24 0.08 66.31 0.00 59.76 0.00 95.54 0.00 0.00 0.00 70.24 0.00 98.04 0.00 94.77 0.54 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1062988007
69.32 0.08 66.31 0.00 59.76 0.00 95.54 0.00 0.00 0.00 70.24 0.00 98.04 0.00 95.32 0.54 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.487512796
69.38 0.07 66.31 0.00 59.76 0.00 96.01 0.47 0.00 0.00 70.24 0.00 98.04 0.00 95.32 0.00 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4231651518
69.43 0.05 66.31 0.00 59.76 0.00 96.01 0.00 0.00 0.00 70.24 0.00 98.04 0.00 95.68 0.36 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2036128428
69.49 0.05 66.31 0.00 59.76 0.00 96.01 0.00 0.00 0.00 70.24 0.00 98.04 0.00 96.04 0.36 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2927510849
69.52 0.03 66.31 0.00 60.00 0.23 96.01 0.00 0.00 0.00 70.24 0.00 98.04 0.00 96.04 0.00 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2719870447
69.54 0.03 66.31 0.00 60.00 0.00 96.01 0.00 0.00 0.00 70.24 0.00 98.04 0.00 96.22 0.18 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2874451264
69.55 0.01 66.31 0.00 60.02 0.02 96.01 0.00 0.00 0.00 70.24 0.00 98.04 0.00 96.22 0.00 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3820533330

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2976773580
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1647007796
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2065557816
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1430542462
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.242672638
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1189502286
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4054207854
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3332584764
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3340369170
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2294072315
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3189785619
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3774439699
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3959528566
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1780662882
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3696260244
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3568517979
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2189052372
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1035501574
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2499086785
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3266042348
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3043879544
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2154680340
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.929237548
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2661793363
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.311384258
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2004944602
/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1067444101
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2487577122
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3780962630
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1750463794
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1756519782
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1462558579
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4041995254
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.2218060294
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3455575333
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3217341980
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.76931320
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4130188837
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.4128264406
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1731045042
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1700313286
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.177406228
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.240610382
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3970381231
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.244117274
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2561988277
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1973586286
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1279601457
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3899485419
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2702664779
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.3096506836
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3355925814
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.972377047
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4098553451
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1999859299
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2151449259
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1119834728
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1055762917
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3970079788
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2966157415
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.554472139
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1690083997
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2994286869
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1011921891
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.61354640
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3512154284
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2938170156
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.447312238
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2113911993
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2010697119
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1985805331
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3171698532
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1398097457
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2501527760
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4168107561
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4020179105
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1235994400
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1394899447
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3974835546
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.698247346
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.1548794919
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.631906867
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3361477859
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.920404356
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.311640023
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.3194727996
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3493225993
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.1320177622
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.143283424
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3223698164
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3948717327
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3871470349
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.4281808748
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2091893430
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.309402275
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3665262660
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3827064480
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3045070697
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1654652369
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.1238528188
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.2325269873
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3097830632
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1118679221
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.4221898777
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2435143083
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2065526020
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3454958795
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.2116508757
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2415866529
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.48901388
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2252364708
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.923089543
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.102975412
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.849377658
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.99037919
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1947658119
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1402087564
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1176779857
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2087354557
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.4288545204
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2184848550
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.1594924741
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.4102276846
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.163478098
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.4164527558
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3489205099
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3251966073
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2594418039
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2098690710
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.2931795297
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.486769163
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.470235456
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1229508650
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3501801862
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1888898236
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.3366051989
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2656006711
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2916752089
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2838286256
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.4218019803
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3830878188
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.3904422235
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3627168547
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.684254295
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3340065359
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2101596360
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2517755205
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2312399299
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4270323251
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3852605366
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1332368653
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1863490116
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1557297186
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3309498787
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2720187369



Total test records in report: 175
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2365980097 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:23 PM PDT 24 40239345 ps
T2 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3046631617 Jun 22 04:33:13 PM PDT 24 Jun 22 04:33:15 PM PDT 24 109230835 ps
T3 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2415866529 Jun 22 04:33:07 PM PDT 24 Jun 22 04:33:11 PM PDT 24 361785656 ps
T7 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4022615095 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:13 PM PDT 24 59114157 ps
T8 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2916752089 Jun 22 04:33:16 PM PDT 24 Jun 22 04:33:19 PM PDT 24 96716211 ps
T11 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1780662882 Jun 22 04:32:55 PM PDT 24 Jun 22 04:32:57 PM PDT 24 78130293 ps
T9 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3830348249 Jun 22 04:33:14 PM PDT 24 Jun 22 04:33:16 PM PDT 24 66636626 ps
T16 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2931795297 Jun 22 04:33:08 PM PDT 24 Jun 22 04:33:09 PM PDT 24 49048219 ps
T10 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3827064480 Jun 22 04:33:09 PM PDT 24 Jun 22 04:33:11 PM PDT 24 60695752 ps
T17 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3568517979 Jun 22 04:33:08 PM PDT 24 Jun 22 04:33:11 PM PDT 24 274916456 ps
T25 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.143283424 Jun 22 04:33:07 PM PDT 24 Jun 22 04:33:11 PM PDT 24 376356735 ps
T4 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1067444101 Jun 22 04:33:17 PM PDT 24 Jun 22 04:33:21 PM PDT 24 502988563 ps
T5 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3665262660 Jun 22 04:33:03 PM PDT 24 Jun 22 04:33:05 PM PDT 24 211191010 ps
T6 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3954418826 Jun 22 04:33:08 PM PDT 24 Jun 22 04:33:10 PM PDT 24 85844659 ps
T18 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3117331781 Jun 22 04:33:00 PM PDT 24 Jun 22 04:33:03 PM PDT 24 197251929 ps
T19 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3948717327 Jun 22 04:32:59 PM PDT 24 Jun 22 04:33:02 PM PDT 24 72558363 ps
T20 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2720429513 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:34 PM PDT 24 109514233 ps
T30 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3871470349 Jun 22 04:32:59 PM PDT 24 Jun 22 04:33:01 PM PDT 24 158428972 ps
T42 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2994286869 Jun 22 04:33:31 PM PDT 24 Jun 22 04:33:33 PM PDT 24 255252517 ps
T31 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3355925814 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:30 PM PDT 24 232070451 ps
T21 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3340369170 Jun 22 04:33:05 PM PDT 24 Jun 22 04:33:08 PM PDT 24 91846219 ps
T66 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3066215813 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:29 PM PDT 24 35547817 ps
T57 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3837485756 Jun 22 04:33:16 PM PDT 24 Jun 22 04:33:21 PM PDT 24 1034657189 ps
T68 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3194727996 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:23 PM PDT 24 47029315 ps
T74 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3454958795 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:27 PM PDT 24 45609257 ps
T43 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2561988277 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:23 PM PDT 24 131408790 ps
T44 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3043879544 Jun 22 04:33:13 PM PDT 24 Jun 22 04:33:15 PM PDT 24 101129872 ps
T72 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1690083997 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:26 PM PDT 24 43148842 ps
T22 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1394899447 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:15 PM PDT 24 143519101 ps
T23 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4054207854 Jun 22 04:33:05 PM PDT 24 Jun 22 04:33:08 PM PDT 24 152738118 ps
T29 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2036128428 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:28 PM PDT 24 494310667 ps
T67 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1654652369 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:23 PM PDT 24 101539680 ps
T24 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.61354640 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:24 PM PDT 24 98421249 ps
T45 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3512154284 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:25 PM PDT 24 68100330 ps
T73 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4221898777 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:28 PM PDT 24 39446353 ps
T71 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2927510849 Jun 22 04:32:59 PM PDT 24 Jun 22 04:33:00 PM PDT 24 38852826 ps
T69 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4288545204 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:25 PM PDT 24 31009718 ps
T32 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4168107561 Jun 22 04:32:59 PM PDT 24 Jun 22 04:33:02 PM PDT 24 220331936 ps
T37 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2517755205 Jun 22 04:33:14 PM PDT 24 Jun 22 04:33:16 PM PDT 24 115295756 ps
T26 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3501801862 Jun 22 04:33:13 PM PDT 24 Jun 22 04:33:16 PM PDT 24 282875881 ps
T91 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1235994400 Jun 22 04:33:18 PM PDT 24 Jun 22 04:33:20 PM PDT 24 128714797 ps
T27 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3959528566 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:58 PM PDT 24 53919803 ps
T70 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3493225993 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:25 PM PDT 24 36423451 ps
T28 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.240610382 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:27 PM PDT 24 164626996 ps
T63 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4270323251 Jun 22 04:33:18 PM PDT 24 Jun 22 04:33:20 PM PDT 24 176006710 ps
T64 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3970381231 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:24 PM PDT 24 97968149 ps
T82 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2113911993 Jun 22 04:33:19 PM PDT 24 Jun 22 04:33:25 PM PDT 24 2028509542 ps
T75 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3251966073 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:27 PM PDT 24 61880363 ps
T58 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3217341980 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:18 PM PDT 24 150796235 ps
T83 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1279601457 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:28 PM PDT 24 624228614 ps
T92 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1947658119 Jun 22 04:33:04 PM PDT 24 Jun 22 04:33:08 PM PDT 24 405228671 ps
T33 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1863490116 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:17 PM PDT 24 45685098 ps
T65 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1731045042 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:18 PM PDT 24 201496580 ps
T34 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.554472139 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:23 PM PDT 24 78178726 ps
T55 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.824601883 Jun 22 04:33:18 PM PDT 24 Jun 22 04:33:22 PM PDT 24 586071065 ps
T60 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.972377047 Jun 22 04:33:28 PM PDT 24 Jun 22 04:33:32 PM PDT 24 102757070 ps
T93 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.486769163 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:12 PM PDT 24 186609079 ps
T78 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2116508757 Jun 22 04:33:20 PM PDT 24 Jun 22 04:33:22 PM PDT 24 58716253 ps
T56 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1332368653 Jun 22 04:33:14 PM PDT 24 Jun 22 04:33:16 PM PDT 24 128396387 ps
T84 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1062988007 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:31 PM PDT 24 978293772 ps
T94 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.4218019803 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:14 PM PDT 24 60163682 ps
T61 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1700313286 Jun 22 04:33:20 PM PDT 24 Jun 22 04:33:24 PM PDT 24 128007326 ps
T86 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2087354557 Jun 22 04:33:12 PM PDT 24 Jun 22 04:33:16 PM PDT 24 354943644 ps
T35 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2702664779 Jun 22 04:33:32 PM PDT 24 Jun 22 04:33:33 PM PDT 24 74704663 ps
T36 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3780962630 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:17 PM PDT 24 68018452 ps
T79 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2325269873 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:26 PM PDT 24 63671142 ps
T95 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.311640023 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:29 PM PDT 24 74215890 ps
T59 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3820533330 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:17 PM PDT 24 726504027 ps
T80 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.631906867 Jun 22 04:33:50 PM PDT 24 Jun 22 04:33:52 PM PDT 24 84563304 ps
T85 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3974835546 Jun 22 04:33:03 PM PDT 24 Jun 22 04:33:07 PM PDT 24 974981389 ps
T96 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1320177622 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:26 PM PDT 24 114217435 ps
T97 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1119834728 Jun 22 04:33:20 PM PDT 24 Jun 22 04:33:23 PM PDT 24 190524958 ps
T98 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1462558579 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:26 PM PDT 24 100389585 ps
T81 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.698247346 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:28 PM PDT 24 55777260 ps
T38 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1999859299 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:22 PM PDT 24 74593944 ps
T99 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4102276846 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:24 PM PDT 24 37438561 ps
T12 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2252364708 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:12 PM PDT 24 57773597 ps
T39 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.102975412 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:22 PM PDT 24 126313784 ps
T100 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1750463794 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:11 PM PDT 24 46157471 ps
T62 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2004944602 Jun 22 04:33:18 PM PDT 24 Jun 22 04:33:21 PM PDT 24 107801908 ps
T101 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2312399299 Jun 22 04:33:16 PM PDT 24 Jun 22 04:33:17 PM PDT 24 54163075 ps
T102 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4128264406 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:22 PM PDT 24 51529816 ps
T103 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2501527760 Jun 22 04:33:06 PM PDT 24 Jun 22 04:33:08 PM PDT 24 110808418 ps
T40 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1985805331 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:15 PM PDT 24 175703601 ps
T104 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2101596360 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:18 PM PDT 24 94927092 ps
T105 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4098553451 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:26 PM PDT 24 207531624 ps
T106 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3332584764 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:13 PM PDT 24 188385514 ps
T41 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.48901388 Jun 22 04:33:12 PM PDT 24 Jun 22 04:33:21 PM PDT 24 1261028741 ps
T107 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3097830632 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:22 PM PDT 24 74362441 ps
T108 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4130188837 Jun 22 04:33:17 PM PDT 24 Jun 22 04:33:19 PM PDT 24 90072542 ps
T89 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2874451264 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:21 PM PDT 24 698288054 ps
T109 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1398097457 Jun 22 04:32:58 PM PDT 24 Jun 22 04:33:00 PM PDT 24 140666755 ps
T110 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3455575333 Jun 22 04:33:13 PM PDT 24 Jun 22 04:33:16 PM PDT 24 78288845 ps
T90 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3970079788 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:26 PM PDT 24 849100927 ps
T76 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1238528188 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:28 PM PDT 24 39729862 ps
T77 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3705398668 Jun 22 04:33:17 PM PDT 24 Jun 22 04:33:19 PM PDT 24 35738861 ps
T111 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1118679221 Jun 22 04:33:20 PM PDT 24 Jun 22 04:33:21 PM PDT 24 48215864 ps
T87 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3340065359 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:19 PM PDT 24 529128335 ps
T112 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3096506836 Jun 22 04:33:37 PM PDT 24 Jun 22 04:33:39 PM PDT 24 54436846 ps
T13 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4231651518 Jun 22 04:33:00 PM PDT 24 Jun 22 04:33:02 PM PDT 24 136723484 ps
T14 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3171698532 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:14 PM PDT 24 106334441 ps
T15 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1628672179 Jun 22 04:32:57 PM PDT 24 Jun 22 04:32:59 PM PDT 24 63600551 ps
T46 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.487512796 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:28 PM PDT 24 43099608 ps
T47 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2838286256 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:19 PM PDT 24 395793614 ps
T48 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2065557816 Jun 22 04:32:58 PM PDT 24 Jun 22 04:33:00 PM PDT 24 150464315 ps
T49 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2294072315 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:56 PM PDT 24 2557723430 ps
T50 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2966157415 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:29 PM PDT 24 202797617 ps
T51 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2435143083 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:27 PM PDT 24 62458212 ps
T52 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2719870447 Jun 22 04:33:19 PM PDT 24 Jun 22 04:33:21 PM PDT 24 152195380 ps
T53 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1548794919 Jun 22 04:33:30 PM PDT 24 Jun 22 04:33:32 PM PDT 24 38635749 ps
T54 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3899485419 Jun 22 04:33:27 PM PDT 24 Jun 22 04:33:30 PM PDT 24 198993097 ps
T113 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2151449259 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:23 PM PDT 24 53294843 ps
T114 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1176779857 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:13 PM PDT 24 166172112 ps
T115 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2091893430 Jun 22 04:33:09 PM PDT 24 Jun 22 04:33:13 PM PDT 24 182132897 ps
T116 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1189502286 Jun 22 04:33:07 PM PDT 24 Jun 22 04:33:09 PM PDT 24 57130451 ps
T117 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2189052372 Jun 22 04:33:06 PM PDT 24 Jun 22 04:33:08 PM PDT 24 91276689 ps
T118 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.311384258 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:17 PM PDT 24 213054299 ps
T119 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2154680340 Jun 22 04:33:12 PM PDT 24 Jun 22 04:33:17 PM PDT 24 248642443 ps
T120 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2661793363 Jun 22 04:33:17 PM PDT 24 Jun 22 04:33:19 PM PDT 24 52965946 ps
T121 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3774439699 Jun 22 04:33:00 PM PDT 24 Jun 22 04:33:05 PM PDT 24 804826043 ps
T122 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.684254295 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:13 PM PDT 24 266626217 ps
T123 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1055762917 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:25 PM PDT 24 158887479 ps
T88 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.177406228 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:16 PM PDT 24 715717794 ps
T124 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1402087564 Jun 22 04:33:13 PM PDT 24 Jun 22 04:33:16 PM PDT 24 97321337 ps
T125 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1011921891 Jun 22 04:33:25 PM PDT 24 Jun 22 04:33:30 PM PDT 24 405350456 ps
T126 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2720187369 Jun 22 04:33:17 PM PDT 24 Jun 22 04:33:20 PM PDT 24 412625804 ps
T127 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.244117274 Jun 22 04:33:24 PM PDT 24 Jun 22 04:33:26 PM PDT 24 37414979 ps
T128 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1594924741 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:25 PM PDT 24 35517005 ps
T129 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1888898236 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:13 PM PDT 24 74902303 ps
T130 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2656006711 Jun 22 04:33:12 PM PDT 24 Jun 22 04:33:15 PM PDT 24 82324379 ps
T131 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4020179105 Jun 22 04:32:56 PM PDT 24 Jun 22 04:33:01 PM PDT 24 507329963 ps
T132 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4281808748 Jun 22 04:33:01 PM PDT 24 Jun 22 04:33:03 PM PDT 24 53987036 ps
T133 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.849377658 Jun 22 04:33:09 PM PDT 24 Jun 22 04:33:11 PM PDT 24 45272620 ps
T134 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1557297186 Jun 22 04:33:18 PM PDT 24 Jun 22 04:33:21 PM PDT 24 274011000 ps
T135 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2487577122 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:23 PM PDT 24 52551925 ps
T136 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.242672638 Jun 22 04:32:53 PM PDT 24 Jun 22 04:32:54 PM PDT 24 54358987 ps
T137 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2976773580 Jun 22 04:32:51 PM PDT 24 Jun 22 04:32:55 PM PDT 24 186964953 ps
T138 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3696260244 Jun 22 04:32:57 PM PDT 24 Jun 22 04:32:58 PM PDT 24 41766054 ps
T139 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3904422235 Jun 22 04:33:20 PM PDT 24 Jun 22 04:33:27 PM PDT 24 31878461 ps
T140 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2184848550 Jun 22 04:33:21 PM PDT 24 Jun 22 04:33:22 PM PDT 24 41260442 ps
T141 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2065526020 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:24 PM PDT 24 78631270 ps
T142 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2010697119 Jun 22 04:34:20 PM PDT 24 Jun 22 04:34:25 PM PDT 24 156424035 ps
T143 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3309498787 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:15 PM PDT 24 227551903 ps
T144 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.309402275 Jun 22 04:33:06 PM PDT 24 Jun 22 04:33:10 PM PDT 24 156178995 ps
T145 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4164527558 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:28 PM PDT 24 48001469 ps
T146 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4041995254 Jun 22 04:33:14 PM PDT 24 Jun 22 04:33:16 PM PDT 24 54138590 ps
T147 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.447312238 Jun 22 04:33:26 PM PDT 24 Jun 22 04:33:28 PM PDT 24 95349773 ps
T148 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2499086785 Jun 22 04:33:13 PM PDT 24 Jun 22 04:33:18 PM PDT 24 715927042 ps
T149 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.920404356 Jun 22 04:33:23 PM PDT 24 Jun 22 04:33:25 PM PDT 24 56591365 ps
T150 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3489205099 Jun 22 04:33:22 PM PDT 24 Jun 22 04:33:26 PM PDT 24 50027804 ps
T151 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2098690710 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:17 PM PDT 24 62769383 ps
T152 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3627168547 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:12 PM PDT 24 103191099 ps
T153 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1973586286 Jun 22 04:33:19 PM PDT 24 Jun 22 04:33:23 PM PDT 24 121888947 ps
T154 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3830878188 Jun 22 04:33:10 PM PDT 24 Jun 22 04:33:11 PM PDT 24 139049979 ps
T155 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.470235456 Jun 22 04:33:02 PM PDT 24 Jun 22 04:33:05 PM PDT 24 198244526 ps
T156 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.99037919 Jun 22 04:33:12 PM PDT 24 Jun 22 04:33:15 PM PDT 24 121073960 ps
T157 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3266042348 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:14 PM PDT 24 64125367 ps
T158 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2938170156 Jun 22 04:33:33 PM PDT 24 Jun 22 04:33:34 PM PDT 24 47415249 ps
T159 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.76931320 Jun 22 04:33:16 PM PDT 24 Jun 22 04:33:19 PM PDT 24 174247072 ps
T160 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.929237548 Jun 22 04:33:18 PM PDT 24 Jun 22 04:33:21 PM PDT 24 98362201 ps
T161 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1647007796 Jun 22 04:33:07 PM PDT 24 Jun 22 04:33:12 PM PDT 24 1014231245 ps
T162 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1035501574 Jun 22 04:33:04 PM PDT 24 Jun 22 04:33:06 PM PDT 24 156939940 ps
T163 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3223698164 Jun 22 04:32:56 PM PDT 24 Jun 22 04:33:05 PM PDT 24 1148435058 ps
T164 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1229508650 Jun 22 04:33:07 PM PDT 24 Jun 22 04:33:10 PM PDT 24 437412182 ps
T165 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2594418039 Jun 22 04:33:12 PM PDT 24 Jun 22 04:33:15 PM PDT 24 108727878 ps
T166 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1430542462 Jun 22 04:32:52 PM PDT 24 Jun 22 04:32:53 PM PDT 24 56885629 ps
T167 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3366051989 Jun 22 04:33:05 PM PDT 24 Jun 22 04:33:07 PM PDT 24 71590584 ps
T168 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.923089543 Jun 22 04:33:16 PM PDT 24 Jun 22 04:33:19 PM PDT 24 165892197 ps
T169 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3852605366 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:13 PM PDT 24 90485998 ps
T170 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2218060294 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:17 PM PDT 24 42027759 ps
T171 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3361477859 Jun 22 04:33:29 PM PDT 24 Jun 22 04:33:31 PM PDT 24 43279889 ps
T172 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1756519782 Jun 22 04:33:11 PM PDT 24 Jun 22 04:33:13 PM PDT 24 163454483 ps
T173 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3189785619 Jun 22 04:33:06 PM PDT 24 Jun 22 04:33:10 PM PDT 24 426841949 ps
T174 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.163478098 Jun 22 04:33:32 PM PDT 24 Jun 22 04:33:33 PM PDT 24 54168078 ps
T175 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3045070697 Jun 22 04:33:15 PM PDT 24 Jun 22 04:33:19 PM PDT 24 836585360 ps

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3046631617
Short name T2
Test name
Test status
Simulation time 109230835 ps
CPU time 1.08 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 206124 kb
Host smart-dab3d920-ea37-4b38-bac0-d1a7f38482ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3046631617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3046631617
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.4022615095
Short name T7
Test name
Test status
Simulation time 59114157 ps
CPU time 0.76 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 205824 kb
Host smart-d11f2280-33a5-45c2-af49-4ff5fbab92a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4022615095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.4022615095
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.2720429513
Short name T20
Test name
Test status
Simulation time 109514233 ps
CPU time 2.37 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 222612 kb
Host smart-c719f5d1-d4d5-4f37-b8c8-144b1e56e6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2720429513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.2720429513
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3954418826
Short name T6
Test name
Test status
Simulation time 85844659 ps
CPU time 0.89 seconds
Started Jun 22 04:33:08 PM PDT 24
Finished Jun 22 04:33:10 PM PDT 24
Peak memory 205928 kb
Host smart-4b6b8009-5d07-44d2-8580-92814bb53b06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3954418826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3954418826
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3830348249
Short name T9
Test name
Test status
Simulation time 66636626 ps
CPU time 0.69 seconds
Started Jun 22 04:33:14 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 205832 kb
Host smart-036e8c26-054d-4ff8-985f-73712ada6c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3830348249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3830348249
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3837485756
Short name T57
Test name
Test status
Simulation time 1034657189 ps
CPU time 3.39 seconds
Started Jun 22 04:33:16 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 206152 kb
Host smart-8582bb91-172a-4c9f-b4b3-4029ef201839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3837485756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3837485756
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1628672179
Short name T15
Test name
Test status
Simulation time 63600551 ps
CPU time 0.77 seconds
Started Jun 22 04:32:57 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 205928 kb
Host smart-7c538b19-16cd-49c9-aeb3-72d0cd408075
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1628672179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1628672179
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3066215813
Short name T66
Test name
Test status
Simulation time 35547817 ps
CPU time 0.65 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 205828 kb
Host smart-05dac9b9-430b-46a9-9075-43fbbebd5c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3066215813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3066215813
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2365980097
Short name T1
Test name
Test status
Simulation time 40239345 ps
CPU time 0.64 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 205828 kb
Host smart-718f707e-6978-42cb-ae93-7bc6107039f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2365980097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2365980097
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3705398668
Short name T77
Test name
Test status
Simulation time 35738861 ps
CPU time 0.69 seconds
Started Jun 22 04:33:17 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 205908 kb
Host smart-a8db9b9f-4892-4537-9ea1-2e23c48e567f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3705398668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3705398668
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.824601883
Short name T55
Test name
Test status
Simulation time 586071065 ps
CPU time 2.67 seconds
Started Jun 22 04:33:18 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 206152 kb
Host smart-e94b36e0-5bd8-4719-8aa5-a59d80e80ff3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=824601883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.824601883
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3117331781
Short name T18
Test name
Test status
Simulation time 197251929 ps
CPU time 2.36 seconds
Started Jun 22 04:33:00 PM PDT 24
Finished Jun 22 04:33:03 PM PDT 24
Peak memory 215492 kb
Host smart-7fd8f9fb-563d-442d-94b5-9fd6795d9bd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3117331781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3117331781
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1062988007
Short name T84
Test name
Test status
Simulation time 978293772 ps
CPU time 3.13 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:31 PM PDT 24
Peak memory 206132 kb
Host smart-bee38b21-347d-4435-b155-99b8df43c9ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1062988007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1062988007
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.487512796
Short name T46
Test name
Test status
Simulation time 43099608 ps
CPU time 0.66 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 205772 kb
Host smart-e708e1ed-365d-47d5-be1f-ba7100b0624b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=487512796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.487512796
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4231651518
Short name T13
Test name
Test status
Simulation time 136723484 ps
CPU time 0.9 seconds
Started Jun 22 04:33:00 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 205928 kb
Host smart-5ee68e18-aeff-4f9f-bf16-14f0055aeca1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4231651518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.4231651518
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2036128428
Short name T29
Test name
Test status
Simulation time 494310667 ps
CPU time 2.49 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 206144 kb
Host smart-83b1dc43-d008-4d3a-a7f3-24b09a67eb2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2036128428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2036128428
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2927510849
Short name T71
Test name
Test status
Simulation time 38852826 ps
CPU time 0.61 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 205832 kb
Host smart-1f2610de-3e35-45bc-9bac-81a4d00fc2c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2927510849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2927510849
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2719870447
Short name T52
Test name
Test status
Simulation time 152195380 ps
CPU time 1.86 seconds
Started Jun 22 04:33:19 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 221916 kb
Host smart-06a6ddd8-53dd-4463-9ca3-4a8587a5ef49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2719870447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2719870447
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2874451264
Short name T89
Test name
Test status
Simulation time 698288054 ps
CPU time 4.45 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 206204 kb
Host smart-f3e1e9a2-11ad-47e5-a75b-1d257b51fce7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2874451264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2874451264
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3820533330
Short name T59
Test name
Test status
Simulation time 726504027 ps
CPU time 4.75 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 206112 kb
Host smart-995d3ecf-9521-4031-9803-32c378b96f93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3820533330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3820533330
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2976773580
Short name T137
Test name
Test status
Simulation time 186964953 ps
CPU time 3.2 seconds
Started Jun 22 04:32:51 PM PDT 24
Finished Jun 22 04:32:55 PM PDT 24
Peak memory 206160 kb
Host smart-743b33ce-2168-4c85-8606-2c9a16f13868
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2976773580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2976773580
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1647007796
Short name T161
Test name
Test status
Simulation time 1014231245 ps
CPU time 4.96 seconds
Started Jun 22 04:33:07 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 206164 kb
Host smart-7add6b9c-0d10-4a04-916b-b780eed8c351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1647007796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1647007796
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2065557816
Short name T48
Test name
Test status
Simulation time 150464315 ps
CPU time 1.31 seconds
Started Jun 22 04:32:58 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 215844 kb
Host smart-7e3c47d6-35e9-4fcd-9fa9-20f74cab9a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065557816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2065557816
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1430542462
Short name T166
Test name
Test status
Simulation time 56885629 ps
CPU time 0.82 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 205960 kb
Host smart-21a99b26-fbc6-4f15-9574-db256a9ea1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1430542462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1430542462
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.242672638
Short name T136
Test name
Test status
Simulation time 54358987 ps
CPU time 0.66 seconds
Started Jun 22 04:32:53 PM PDT 24
Finished Jun 22 04:32:54 PM PDT 24
Peak memory 205832 kb
Host smart-926e1c40-a964-405d-9f2d-52fb986f7bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=242672638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.242672638
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1189502286
Short name T116
Test name
Test status
Simulation time 57130451 ps
CPU time 1.38 seconds
Started Jun 22 04:33:07 PM PDT 24
Finished Jun 22 04:33:09 PM PDT 24
Peak memory 214412 kb
Host smart-48b0b4e6-c119-4e76-8e38-8c91825ff9a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1189502286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1189502286
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4054207854
Short name T23
Test name
Test status
Simulation time 152738118 ps
CPU time 2.46 seconds
Started Jun 22 04:33:05 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 206156 kb
Host smart-d91f96f2-7333-4b09-859d-b176aae208a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4054207854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4054207854
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3332584764
Short name T106
Test name
Test status
Simulation time 188385514 ps
CPU time 1.33 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 206136 kb
Host smart-a24e71e8-209b-42da-8daa-3ed6a43a89e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3332584764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3332584764
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3340369170
Short name T21
Test name
Test status
Simulation time 91846219 ps
CPU time 2.5 seconds
Started Jun 22 04:33:05 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 214380 kb
Host smart-967f6243-56f8-40d9-bf64-d83958995dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3340369170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3340369170
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2294072315
Short name T49
Test name
Test status
Simulation time 2557723430 ps
CPU time 6.34 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:56 PM PDT 24
Peak memory 206224 kb
Host smart-20046147-ab4e-4ae0-b14e-2aa1c60434f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2294072315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2294072315
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3189785619
Short name T173
Test name
Test status
Simulation time 426841949 ps
CPU time 3.51 seconds
Started Jun 22 04:33:06 PM PDT 24
Finished Jun 22 04:33:10 PM PDT 24
Peak memory 206128 kb
Host smart-0562496b-e2f4-4685-98be-d9a32a1a5fef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3189785619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3189785619
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3774439699
Short name T121
Test name
Test status
Simulation time 804826043 ps
CPU time 4.64 seconds
Started Jun 22 04:33:00 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 206124 kb
Host smart-a997d474-eeb9-41c0-88ff-11c1c54d19d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3774439699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3774439699
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3959528566
Short name T27
Test name
Test status
Simulation time 53919803 ps
CPU time 1.13 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 214264 kb
Host smart-4f6e5c5c-43e3-4801-bd05-5959266a6684
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959528566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3959528566
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1780662882
Short name T11
Test name
Test status
Simulation time 78130293 ps
CPU time 1.09 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 206148 kb
Host smart-91ea191c-9620-4014-bbd4-6723db8d1cba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1780662882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1780662882
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3696260244
Short name T138
Test name
Test status
Simulation time 41766054 ps
CPU time 0.66 seconds
Started Jun 22 04:32:57 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 206252 kb
Host smart-77c539ba-0af4-46c0-a052-8a07b063f4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696260244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3696260244
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3568517979
Short name T17
Test name
Test status
Simulation time 274916456 ps
CPU time 2.61 seconds
Started Jun 22 04:33:08 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 206156 kb
Host smart-afc8a05a-cb9d-47f1-ab92-bc0ef4ebd753
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3568517979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3568517979
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2189052372
Short name T117
Test name
Test status
Simulation time 91276689 ps
CPU time 1.14 seconds
Started Jun 22 04:33:06 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 206096 kb
Host smart-a2e17e69-83ce-4cf3-9a27-c06d1135a73e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2189052372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2189052372
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1035501574
Short name T162
Test name
Test status
Simulation time 156939940 ps
CPU time 1.64 seconds
Started Jun 22 04:33:04 PM PDT 24
Finished Jun 22 04:33:06 PM PDT 24
Peak memory 206108 kb
Host smart-88f2d48d-115f-4ca3-9628-b0531337ea7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1035501574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1035501574
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2499086785
Short name T148
Test name
Test status
Simulation time 715927042 ps
CPU time 4.16 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:18 PM PDT 24
Peak memory 206252 kb
Host smart-d2df9334-2e3c-4b5c-a848-a718ec50f705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2499086785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2499086785
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3266042348
Short name T157
Test name
Test status
Simulation time 64125367 ps
CPU time 1.28 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:14 PM PDT 24
Peak memory 214328 kb
Host smart-83430d2c-b805-4c7a-b74f-7f667e1437e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266042348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3266042348
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3043879544
Short name T44
Test name
Test status
Simulation time 101129872 ps
CPU time 1.04 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 206184 kb
Host smart-b423b238-10c0-418e-a552-502eb571b852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3043879544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3043879544
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2154680340
Short name T119
Test name
Test status
Simulation time 248642443 ps
CPU time 2.92 seconds
Started Jun 22 04:33:12 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 222024 kb
Host smart-ecdf3542-898a-4c1a-9d9d-402f1c02114a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2154680340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2154680340
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.929237548
Short name T160
Test name
Test status
Simulation time 98362201 ps
CPU time 1.23 seconds
Started Jun 22 04:33:18 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 214332 kb
Host smart-779d6faa-6d8b-4c23-8171-e1760a70a96d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929237548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.929237548
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2661793363
Short name T120
Test name
Test status
Simulation time 52965946 ps
CPU time 0.73 seconds
Started Jun 22 04:33:17 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 205924 kb
Host smart-3d5e09c3-ab70-4d36-8b71-a2196a5c6035
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2661793363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2661793363
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.311384258
Short name T118
Test name
Test status
Simulation time 213054299 ps
CPU time 1.27 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 206128 kb
Host smart-8f6ff951-cbf4-47e9-91a7-ff97a6a7e5f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=311384258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.311384258
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2004944602
Short name T62
Test name
Test status
Simulation time 107801908 ps
CPU time 2.79 seconds
Started Jun 22 04:33:18 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 206160 kb
Host smart-1a43ed6a-78f6-4d87-bbb7-6b32e0bdd7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2004944602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2004944602
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1067444101
Short name T4
Test name
Test status
Simulation time 502988563 ps
CPU time 2.51 seconds
Started Jun 22 04:33:17 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 206212 kb
Host smart-07a52540-6155-4cd4-81d8-6936e96d9b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1067444101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1067444101
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2487577122
Short name T135
Test name
Test status
Simulation time 52551925 ps
CPU time 1.32 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 214280 kb
Host smart-d286c567-8bd8-4160-b10a-ca6b53919f0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487577122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.2487577122
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3780962630
Short name T36
Test name
Test status
Simulation time 68018452 ps
CPU time 0.93 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 206212 kb
Host smart-d7d85031-65c0-4af6-a630-b9e83c71fce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3780962630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3780962630
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1750463794
Short name T100
Test name
Test status
Simulation time 46157471 ps
CPU time 0.68 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 205828 kb
Host smart-2cba74ca-3009-4bf7-b336-79e37c66568d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1750463794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1750463794
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1756519782
Short name T172
Test name
Test status
Simulation time 163454483 ps
CPU time 1.21 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 206144 kb
Host smart-da588d60-492e-41ac-981b-9d8b591041fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1756519782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1756519782
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1462558579
Short name T98
Test name
Test status
Simulation time 100389585 ps
CPU time 1.28 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 216232 kb
Host smart-c8583c5f-8e74-40b8-98ef-b0e2e220fda4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462558579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1462558579
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.4041995254
Short name T146
Test name
Test status
Simulation time 54138590 ps
CPU time 0.98 seconds
Started Jun 22 04:33:14 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 206172 kb
Host smart-bca26ce0-e0e5-47a6-84ac-e0499f0aecb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4041995254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.4041995254
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2218060294
Short name T170
Test name
Test status
Simulation time 42027759 ps
CPU time 0.66 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 205804 kb
Host smart-752b0810-c805-4a35-a832-1b0a68189abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2218060294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2218060294
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3455575333
Short name T110
Test name
Test status
Simulation time 78288845 ps
CPU time 1.15 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 206180 kb
Host smart-81655935-1670-473f-85c6-1c43360d3c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3455575333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3455575333
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3217341980
Short name T58
Test name
Test status
Simulation time 150796235 ps
CPU time 2.65 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:18 PM PDT 24
Peak memory 206148 kb
Host smart-1c0b2daa-0b0d-4388-9b6a-7caaa14b8bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217341980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3217341980
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.76931320
Short name T159
Test name
Test status
Simulation time 174247072 ps
CPU time 1.84 seconds
Started Jun 22 04:33:16 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 214296 kb
Host smart-a780dc44-9aa5-44bc-ab37-af44966fb2ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76931320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev
_csr_mem_rw_with_rand_reset.76931320
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4130188837
Short name T108
Test name
Test status
Simulation time 90072542 ps
CPU time 1.02 seconds
Started Jun 22 04:33:17 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 206152 kb
Host smart-0ad11b7d-40e7-4203-896f-92d4a1984e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4130188837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4130188837
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.4128264406
Short name T102
Test name
Test status
Simulation time 51529816 ps
CPU time 0.69 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 205828 kb
Host smart-fe05a596-caa9-4d35-9de7-6f3721747398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4128264406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.4128264406
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1731045042
Short name T65
Test name
Test status
Simulation time 201496580 ps
CPU time 1.51 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:18 PM PDT 24
Peak memory 206192 kb
Host smart-20f06546-031d-4e69-bc33-11e7556284b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1731045042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1731045042
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1700313286
Short name T61
Test name
Test status
Simulation time 128007326 ps
CPU time 2.57 seconds
Started Jun 22 04:33:20 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 222140 kb
Host smart-1b5bef73-f82e-4530-9d54-74d1aff637b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1700313286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1700313286
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.177406228
Short name T88
Test name
Test status
Simulation time 715717794 ps
CPU time 4.25 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 206180 kb
Host smart-894b43cd-5502-4aa5-ad84-48a560798ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=177406228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.177406228
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.240610382
Short name T28
Test name
Test status
Simulation time 164626996 ps
CPU time 1.85 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 214336 kb
Host smart-efdc1774-a592-4fff-afa9-373fcc58dbae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240610382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.240610382
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3970381231
Short name T64
Test name
Test status
Simulation time 97968149 ps
CPU time 0.88 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 205924 kb
Host smart-29345a5d-e1e9-4f32-93d7-8dae18b6bd88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3970381231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3970381231
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.244117274
Short name T127
Test name
Test status
Simulation time 37414979 ps
CPU time 0.66 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 205784 kb
Host smart-99ba9da9-2cbd-427a-aa5f-a9165e705bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=244117274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.244117274
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2561988277
Short name T43
Test name
Test status
Simulation time 131408790 ps
CPU time 1.1 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 206224 kb
Host smart-36ae12f8-c760-4bf0-8bed-792273a0567f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2561988277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2561988277
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1973586286
Short name T153
Test name
Test status
Simulation time 121888947 ps
CPU time 3.05 seconds
Started Jun 22 04:33:19 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 222252 kb
Host smart-0f58d3d4-7027-436c-9294-feb642a57915
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1973586286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1973586286
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1279601457
Short name T83
Test name
Test status
Simulation time 624228614 ps
CPU time 4.18 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 206192 kb
Host smart-7ab7fa68-8685-47a4-84ec-61151694806a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1279601457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1279601457
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3899485419
Short name T54
Test name
Test status
Simulation time 198993097 ps
CPU time 1.4 seconds
Started Jun 22 04:33:27 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 214276 kb
Host smart-37d89465-69af-4a5c-863c-38d1145b0b42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899485419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3899485419
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2702664779
Short name T35
Test name
Test status
Simulation time 74704663 ps
CPU time 0.94 seconds
Started Jun 22 04:33:32 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 206144 kb
Host smart-5c2ba47d-09de-4125-82cf-483e3bc74e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2702664779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2702664779
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3096506836
Short name T112
Test name
Test status
Simulation time 54436846 ps
CPU time 0.66 seconds
Started Jun 22 04:33:37 PM PDT 24
Finished Jun 22 04:33:39 PM PDT 24
Peak memory 205828 kb
Host smart-b31bdb27-df66-42f0-836b-cf40d7be3914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3096506836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3096506836
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3355925814
Short name T31
Test name
Test status
Simulation time 232070451 ps
CPU time 1.74 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 206128 kb
Host smart-8b97f166-034c-4d93-805c-ad2209576882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3355925814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3355925814
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.972377047
Short name T60
Test name
Test status
Simulation time 102757070 ps
CPU time 2.77 seconds
Started Jun 22 04:33:28 PM PDT 24
Finished Jun 22 04:33:32 PM PDT 24
Peak memory 214336 kb
Host smart-1028885f-6b2e-4ad6-be79-0b9cc187cfaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=972377047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.972377047
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4098553451
Short name T105
Test name
Test status
Simulation time 207531624 ps
CPU time 1.96 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 218084 kb
Host smart-4c9b0f60-a411-433c-b781-962bc9ecc18a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098553451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.4098553451
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1999859299
Short name T38
Test name
Test status
Simulation time 74593944 ps
CPU time 0.96 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 206172 kb
Host smart-a0a5a9cb-7a42-434c-8e9d-9811402d5fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1999859299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1999859299
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2151449259
Short name T113
Test name
Test status
Simulation time 53294843 ps
CPU time 0.67 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 205836 kb
Host smart-457eacb9-d134-414f-a730-87cde7447db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2151449259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2151449259
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1119834728
Short name T97
Test name
Test status
Simulation time 190524958 ps
CPU time 1.67 seconds
Started Jun 22 04:33:20 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 206168 kb
Host smart-4f67ea49-5937-4d98-b37e-2c1665479981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1119834728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1119834728
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1055762917
Short name T123
Test name
Test status
Simulation time 158887479 ps
CPU time 1.81 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 214364 kb
Host smart-fc8bc1e1-4d09-4478-86f8-3c4bcf72e3de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1055762917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1055762917
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3970079788
Short name T90
Test name
Test status
Simulation time 849100927 ps
CPU time 3.22 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 206132 kb
Host smart-3bc113f4-1ce2-4a04-b6b9-c2b8681bdd0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3970079788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3970079788
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2966157415
Short name T50
Test name
Test status
Simulation time 202797617 ps
CPU time 1.93 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 214260 kb
Host smart-3af56c75-dfb5-4815-ade6-a76450de5b44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966157415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2966157415
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.554472139
Short name T34
Test name
Test status
Simulation time 78178726 ps
CPU time 0.99 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 206092 kb
Host smart-113c847d-6e30-4239-813b-be153ac034be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=554472139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.554472139
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1690083997
Short name T72
Test name
Test status
Simulation time 43148842 ps
CPU time 0.63 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 205824 kb
Host smart-0704f687-f17a-489f-978d-4c31f6e13b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1690083997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1690083997
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2994286869
Short name T42
Test name
Test status
Simulation time 255252517 ps
CPU time 1.5 seconds
Started Jun 22 04:33:31 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 206164 kb
Host smart-267e2c98-5abc-4686-bea2-0de3a1d1d948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2994286869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2994286869
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1011921891
Short name T125
Test name
Test status
Simulation time 405350456 ps
CPU time 3.71 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:30 PM PDT 24
Peak memory 222444 kb
Host smart-752b7ce4-cb34-442c-923a-81f5313fe75f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1011921891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1011921891
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.61354640
Short name T24
Test name
Test status
Simulation time 98421249 ps
CPU time 1.31 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 215924 kb
Host smart-e479ade1-89e9-428a-945f-1e7de1d3e245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61354640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev
_csr_mem_rw_with_rand_reset.61354640
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3512154284
Short name T45
Test name
Test status
Simulation time 68100330 ps
CPU time 0.96 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 206076 kb
Host smart-3a02de52-d55b-467c-b20e-a0cc2bbf1380
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3512154284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3512154284
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2938170156
Short name T158
Test name
Test status
Simulation time 47415249 ps
CPU time 0.68 seconds
Started Jun 22 04:33:33 PM PDT 24
Finished Jun 22 04:33:34 PM PDT 24
Peak memory 205824 kb
Host smart-d89a4954-91c7-457e-9251-7733715c2cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2938170156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2938170156
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.447312238
Short name T147
Test name
Test status
Simulation time 95349773 ps
CPU time 1.08 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 206124 kb
Host smart-5ba13151-3345-4c84-87a5-281a6044296f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=447312238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.447312238
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2113911993
Short name T82
Test name
Test status
Simulation time 2028509542 ps
CPU time 5.6 seconds
Started Jun 22 04:33:19 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 206172 kb
Host smart-80988a48-2bd8-4ed0-ade7-87559e58e831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2113911993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2113911993
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2010697119
Short name T142
Test name
Test status
Simulation time 156424035 ps
CPU time 3.21 seconds
Started Jun 22 04:34:20 PM PDT 24
Finished Jun 22 04:34:25 PM PDT 24
Peak memory 206164 kb
Host smart-0955b14f-2825-435b-a562-9d411f13e735
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2010697119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2010697119
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1985805331
Short name T40
Test name
Test status
Simulation time 175703601 ps
CPU time 3.6 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 206028 kb
Host smart-2c07a0aa-02cd-4055-ada6-2a6efed10eb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1985805331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1985805331
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3171698532
Short name T14
Test name
Test status
Simulation time 106334441 ps
CPU time 0.94 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:14 PM PDT 24
Peak memory 205956 kb
Host smart-4e60720b-34fa-4d53-ab7e-6812c91a76dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3171698532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3171698532
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1398097457
Short name T109
Test name
Test status
Simulation time 140666755 ps
CPU time 1.71 seconds
Started Jun 22 04:32:58 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 217936 kb
Host smart-f8fec507-85b5-416c-9393-2ca835921eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398097457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1398097457
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2501527760
Short name T103
Test name
Test status
Simulation time 110808418 ps
CPU time 1.04 seconds
Started Jun 22 04:33:06 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 206164 kb
Host smart-7e7be9a0-2aea-43f0-b73b-5a836170abec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2501527760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2501527760
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4168107561
Short name T32
Test name
Test status
Simulation time 220331936 ps
CPU time 2.5 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 215244 kb
Host smart-c1e108ac-2c9a-428b-9fe4-d8c49241bcbe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4168107561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4168107561
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.4020179105
Short name T131
Test name
Test status
Simulation time 507329963 ps
CPU time 4.36 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 206240 kb
Host smart-5a648a47-f14b-4ad6-aabb-3da889467978
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4020179105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.4020179105
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1235994400
Short name T91
Test name
Test status
Simulation time 128714797 ps
CPU time 1.11 seconds
Started Jun 22 04:33:18 PM PDT 24
Finished Jun 22 04:33:20 PM PDT 24
Peak memory 206112 kb
Host smart-35ee4883-41ec-4432-9ab0-f1faac87ada0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1235994400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1235994400
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1394899447
Short name T22
Test name
Test status
Simulation time 143519101 ps
CPU time 1.94 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 214444 kb
Host smart-e0334808-d52b-448b-a09b-c7e71b2098b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1394899447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1394899447
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3974835546
Short name T85
Test name
Test status
Simulation time 974981389 ps
CPU time 3.59 seconds
Started Jun 22 04:33:03 PM PDT 24
Finished Jun 22 04:33:07 PM PDT 24
Peak memory 206192 kb
Host smart-895b785f-1435-4e53-8df9-59b9729a3608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3974835546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3974835546
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.698247346
Short name T81
Test name
Test status
Simulation time 55777260 ps
CPU time 0.7 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 205828 kb
Host smart-efa7e652-4189-4476-830e-43ef6d4ecca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=698247346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.698247346
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1548794919
Short name T53
Test name
Test status
Simulation time 38635749 ps
CPU time 0.66 seconds
Started Jun 22 04:33:30 PM PDT 24
Finished Jun 22 04:33:32 PM PDT 24
Peak memory 205828 kb
Host smart-2ee1377e-ee39-4676-842e-ad921eca2102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1548794919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1548794919
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.631906867
Short name T80
Test name
Test status
Simulation time 84563304 ps
CPU time 0.69 seconds
Started Jun 22 04:33:50 PM PDT 24
Finished Jun 22 04:33:52 PM PDT 24
Peak memory 205808 kb
Host smart-3ed8becb-bbc8-497d-93e5-ac8be1449c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=631906867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.631906867
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3361477859
Short name T171
Test name
Test status
Simulation time 43279889 ps
CPU time 0.68 seconds
Started Jun 22 04:33:29 PM PDT 24
Finished Jun 22 04:33:31 PM PDT 24
Peak memory 205824 kb
Host smart-1b9384fe-2f41-4a03-ba16-be9023903f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3361477859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3361477859
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.920404356
Short name T149
Test name
Test status
Simulation time 56591365 ps
CPU time 0.72 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 205852 kb
Host smart-818bdf65-05b6-4c99-9a79-027b7fed9a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=920404356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.920404356
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.311640023
Short name T95
Test name
Test status
Simulation time 74215890 ps
CPU time 0.68 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:29 PM PDT 24
Peak memory 205836 kb
Host smart-446f742f-23b7-40bd-9e2a-2102a48e7ce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=311640023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.311640023
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3194727996
Short name T68
Test name
Test status
Simulation time 47029315 ps
CPU time 0.7 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 205820 kb
Host smart-e9e36705-b6ef-438f-9452-d28e9b0da262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3194727996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3194727996
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3493225993
Short name T70
Test name
Test status
Simulation time 36423451 ps
CPU time 0.64 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 205836 kb
Host smart-5cdee068-aebe-40fd-b1b6-c9cb44709c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3493225993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3493225993
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1320177622
Short name T96
Test name
Test status
Simulation time 114217435 ps
CPU time 0.71 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 205828 kb
Host smart-961f02ad-57ee-4a2a-af16-85d00b472390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1320177622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1320177622
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.143283424
Short name T25
Test name
Test status
Simulation time 376356735 ps
CPU time 3.6 seconds
Started Jun 22 04:33:07 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 206156 kb
Host smart-aa620e1c-1da6-4503-a804-1dfdd1da009b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=143283424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.143283424
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3223698164
Short name T163
Test name
Test status
Simulation time 1148435058 ps
CPU time 8 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 206152 kb
Host smart-6be0aafc-3938-4908-9261-5e9190f58576
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3223698164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3223698164
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3948717327
Short name T19
Test name
Test status
Simulation time 72558363 ps
CPU time 1.72 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 214160 kb
Host smart-7c44c185-e977-4441-8046-0ab8243f97e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948717327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3948717327
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3871470349
Short name T30
Test name
Test status
Simulation time 158428972 ps
CPU time 0.95 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 205920 kb
Host smart-eb4a7d94-96fb-4312-b3e4-44b8dd693ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3871470349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3871470349
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.4281808748
Short name T132
Test name
Test status
Simulation time 53987036 ps
CPU time 0.67 seconds
Started Jun 22 04:33:01 PM PDT 24
Finished Jun 22 04:33:03 PM PDT 24
Peak memory 205836 kb
Host smart-bccd67eb-323e-4a8b-a21a-d2e33ce65b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4281808748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.4281808748
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2091893430
Short name T115
Test name
Test status
Simulation time 182132897 ps
CPU time 2.34 seconds
Started Jun 22 04:33:09 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 215368 kb
Host smart-955471f2-e787-4c5c-a05e-ea77fbe1f215
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2091893430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2091893430
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.309402275
Short name T144
Test name
Test status
Simulation time 156178995 ps
CPU time 3.72 seconds
Started Jun 22 04:33:06 PM PDT 24
Finished Jun 22 04:33:10 PM PDT 24
Peak memory 206060 kb
Host smart-b6e64749-4d75-4f5b-be20-8008d25b1008
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=309402275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.309402275
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3665262660
Short name T5
Test name
Test status
Simulation time 211191010 ps
CPU time 1.7 seconds
Started Jun 22 04:33:03 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 206180 kb
Host smart-6c109d3d-d108-44c6-b750-d02a524ab25b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3665262660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3665262660
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3827064480
Short name T10
Test name
Test status
Simulation time 60695752 ps
CPU time 1.42 seconds
Started Jun 22 04:33:09 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 206064 kb
Host smart-6e695977-0c1e-480a-85da-25ea0ecf9ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3827064480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3827064480
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3045070697
Short name T175
Test name
Test status
Simulation time 836585360 ps
CPU time 2.98 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 206108 kb
Host smart-7ffd44ad-63e7-4f20-b77e-d08c90c1a5a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3045070697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3045070697
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.1654652369
Short name T67
Test name
Test status
Simulation time 101539680 ps
CPU time 0.77 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:23 PM PDT 24
Peak memory 205872 kb
Host smart-00457464-6126-41aa-8606-627f006fd872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1654652369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1654652369
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1238528188
Short name T76
Test name
Test status
Simulation time 39729862 ps
CPU time 0.66 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 205768 kb
Host smart-c43f0290-f866-4e15-86e0-a85019c15315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1238528188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1238528188
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2325269873
Short name T79
Test name
Test status
Simulation time 63671142 ps
CPU time 0.66 seconds
Started Jun 22 04:33:24 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 205820 kb
Host smart-43c60ea3-41b9-415f-b86a-25ebd9be7afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2325269873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2325269873
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3097830632
Short name T107
Test name
Test status
Simulation time 74362441 ps
CPU time 0.7 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 205904 kb
Host smart-bbecd5bc-61df-4c4e-8928-c3cf08f96fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3097830632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3097830632
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1118679221
Short name T111
Test name
Test status
Simulation time 48215864 ps
CPU time 0.67 seconds
Started Jun 22 04:33:20 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 205824 kb
Host smart-e5ec4e99-9fcb-4046-b593-cdf926fcb7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1118679221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1118679221
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4221898777
Short name T73
Test name
Test status
Simulation time 39446353 ps
CPU time 0.67 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 205812 kb
Host smart-1f2736c1-be4b-4c42-af6d-d72d9bc7def7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4221898777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4221898777
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2435143083
Short name T51
Test name
Test status
Simulation time 62458212 ps
CPU time 0.66 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 205776 kb
Host smart-430f3d8b-a717-4230-9c5f-c18be4f67963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2435143083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2435143083
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2065526020
Short name T141
Test name
Test status
Simulation time 78631270 ps
CPU time 0.7 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 205880 kb
Host smart-220caeee-59a9-4eb6-80a2-5d1fd35290a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2065526020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2065526020
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3454958795
Short name T74
Test name
Test status
Simulation time 45609257 ps
CPU time 0.68 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 205784 kb
Host smart-df76dab1-a745-47c9-9c5b-b2ca79108617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3454958795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3454958795
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2116508757
Short name T78
Test name
Test status
Simulation time 58716253 ps
CPU time 0.68 seconds
Started Jun 22 04:33:20 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 205820 kb
Host smart-01a9ace8-78fa-4c02-bf29-22279b730f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2116508757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2116508757
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2415866529
Short name T3
Test name
Test status
Simulation time 361785656 ps
CPU time 3.6 seconds
Started Jun 22 04:33:07 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 206128 kb
Host smart-094bfee7-d3e2-4452-bfe0-039799c23da1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2415866529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2415866529
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.48901388
Short name T41
Test name
Test status
Simulation time 1261028741 ps
CPU time 7.54 seconds
Started Jun 22 04:33:12 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 206132 kb
Host smart-7c3e39fb-f37b-494f-ba00-f1f3a6326ec0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=48901388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.48901388
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2252364708
Short name T12
Test name
Test status
Simulation time 57773597 ps
CPU time 0.77 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 205924 kb
Host smart-21ab0cc3-d00f-4d54-94fd-c689f56be82e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2252364708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2252364708
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.923089543
Short name T168
Test name
Test status
Simulation time 165892197 ps
CPU time 1.49 seconds
Started Jun 22 04:33:16 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 214284 kb
Host smart-6a16d528-c845-48b2-b02f-ec2f1b5b0858
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923089543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.923089543
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.102975412
Short name T39
Test name
Test status
Simulation time 126313784 ps
CPU time 1.03 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 206212 kb
Host smart-b75b8f63-2640-48d3-8a0a-6f782b48aa4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=102975412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.102975412
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.849377658
Short name T133
Test name
Test status
Simulation time 45272620 ps
CPU time 0.71 seconds
Started Jun 22 04:33:09 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 205776 kb
Host smart-96f230f8-ec01-4439-9bb6-fd2cbe94d507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=849377658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.849377658
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.99037919
Short name T156
Test name
Test status
Simulation time 121073960 ps
CPU time 1.57 seconds
Started Jun 22 04:33:12 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 214624 kb
Host smart-1ded00a6-e79d-4c64-bfc0-920a76bcc1b1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=99037919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.99037919
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1947658119
Short name T92
Test name
Test status
Simulation time 405228671 ps
CPU time 2.87 seconds
Started Jun 22 04:33:04 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 206236 kb
Host smart-551d73c7-4743-4d8f-bb27-3b6bfa299107
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1947658119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1947658119
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1402087564
Short name T124
Test name
Test status
Simulation time 97321337 ps
CPU time 1.47 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 206188 kb
Host smart-ba1277cc-1557-4c68-bb4b-c42f241bda83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1402087564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1402087564
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1176779857
Short name T114
Test name
Test status
Simulation time 166172112 ps
CPU time 1.83 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 221824 kb
Host smart-cf7073ab-11c3-47a6-8e16-d3b1ea5c0141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1176779857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1176779857
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2087354557
Short name T86
Test name
Test status
Simulation time 354943644 ps
CPU time 2.56 seconds
Started Jun 22 04:33:12 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 206204 kb
Host smart-873efbd3-2040-44d7-8e47-7fb204af5148
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2087354557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2087354557
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.4288545204
Short name T69
Test name
Test status
Simulation time 31009718 ps
CPU time 0.65 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 205828 kb
Host smart-0843e57b-4de5-47b3-b0df-d100b6b655fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288545204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.4288545204
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2184848550
Short name T140
Test name
Test status
Simulation time 41260442 ps
CPU time 0.68 seconds
Started Jun 22 04:33:21 PM PDT 24
Finished Jun 22 04:33:22 PM PDT 24
Peak memory 205900 kb
Host smart-b27f96f9-cee6-4485-b574-7dfa997eede2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2184848550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2184848550
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1594924741
Short name T128
Test name
Test status
Simulation time 35517005 ps
CPU time 0.68 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:25 PM PDT 24
Peak memory 205824 kb
Host smart-9638d5da-209c-4016-84f5-33f10a8b345a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1594924741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1594924741
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4102276846
Short name T99
Test name
Test status
Simulation time 37438561 ps
CPU time 0.69 seconds
Started Jun 22 04:33:23 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 205884 kb
Host smart-9b141a91-4ab4-4877-ad50-b7b24b22a9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4102276846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4102276846
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.163478098
Short name T174
Test name
Test status
Simulation time 54168078 ps
CPU time 0.69 seconds
Started Jun 22 04:33:32 PM PDT 24
Finished Jun 22 04:33:33 PM PDT 24
Peak memory 205836 kb
Host smart-5d12d3ab-b43c-4a52-946e-d71071c83eac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=163478098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.163478098
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4164527558
Short name T145
Test name
Test status
Simulation time 48001469 ps
CPU time 0.67 seconds
Started Jun 22 04:33:26 PM PDT 24
Finished Jun 22 04:33:28 PM PDT 24
Peak memory 206208 kb
Host smart-74792710-562b-4ddc-80f0-2eff282300db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4164527558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4164527558
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3489205099
Short name T150
Test name
Test status
Simulation time 50027804 ps
CPU time 0.64 seconds
Started Jun 22 04:33:22 PM PDT 24
Finished Jun 22 04:33:26 PM PDT 24
Peak memory 205756 kb
Host smart-e03cf4e0-63ff-4741-bc30-8713a9f0b2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489205099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3489205099
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3251966073
Short name T75
Test name
Test status
Simulation time 61880363 ps
CPU time 0.66 seconds
Started Jun 22 04:33:25 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 205768 kb
Host smart-087e20b5-61a3-4598-b491-126402d7ccd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3251966073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3251966073
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2594418039
Short name T165
Test name
Test status
Simulation time 108727878 ps
CPU time 1.29 seconds
Started Jun 22 04:33:12 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 214332 kb
Host smart-45dd577f-5fa0-47a7-98ea-17d0f0e6537a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594418039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2594418039
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2098690710
Short name T151
Test name
Test status
Simulation time 62769383 ps
CPU time 0.83 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 205956 kb
Host smart-39405210-7b98-44e8-9286-82ca00a26d0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2098690710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2098690710
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2931795297
Short name T16
Test name
Test status
Simulation time 49048219 ps
CPU time 0.72 seconds
Started Jun 22 04:33:08 PM PDT 24
Finished Jun 22 04:33:09 PM PDT 24
Peak memory 205856 kb
Host smart-a4b30fc7-0875-40ba-b973-9fa945f24f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2931795297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2931795297
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.486769163
Short name T93
Test name
Test status
Simulation time 186609079 ps
CPU time 1.63 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 206216 kb
Host smart-4df84049-6774-48c8-bb20-e64439eb9e6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=486769163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.486769163
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.470235456
Short name T155
Test name
Test status
Simulation time 198244526 ps
CPU time 2.56 seconds
Started Jun 22 04:33:02 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 214376 kb
Host smart-9ad04959-1a9c-4cde-b140-b904ee9bf24b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=470235456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.470235456
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1229508650
Short name T164
Test name
Test status
Simulation time 437412182 ps
CPU time 2.82 seconds
Started Jun 22 04:33:07 PM PDT 24
Finished Jun 22 04:33:10 PM PDT 24
Peak memory 206164 kb
Host smart-ee2f4bcb-0928-4b6f-bd78-41bfe398ce55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1229508650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1229508650
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3501801862
Short name T26
Test name
Test status
Simulation time 282875881 ps
CPU time 1.99 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 214264 kb
Host smart-bc9aefc9-ee40-4f10-bfd0-9bfa4f427bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501801862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3501801862
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1888898236
Short name T129
Test name
Test status
Simulation time 74902303 ps
CPU time 0.99 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 206128 kb
Host smart-293edf43-10f0-487c-a1b0-b44a7444db7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1888898236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1888898236
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3366051989
Short name T167
Test name
Test status
Simulation time 71590584 ps
CPU time 0.71 seconds
Started Jun 22 04:33:05 PM PDT 24
Finished Jun 22 04:33:07 PM PDT 24
Peak memory 205832 kb
Host smart-fd90aa80-87f1-40c0-bd54-392d0974ce2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3366051989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3366051989
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2656006711
Short name T130
Test name
Test status
Simulation time 82324379 ps
CPU time 1.05 seconds
Started Jun 22 04:33:12 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 206120 kb
Host smart-0eb8c3b8-79a0-4668-bda1-3237dbadb1e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2656006711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2656006711
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2916752089
Short name T8
Test name
Test status
Simulation time 96716211 ps
CPU time 1.78 seconds
Started Jun 22 04:33:16 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 206208 kb
Host smart-a2520cd4-3681-4f5a-9827-25837e4baa3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2916752089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2916752089
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2838286256
Short name T47
Test name
Test status
Simulation time 395793614 ps
CPU time 2.54 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 206116 kb
Host smart-23dacb40-d7e3-40a9-9cda-cb4d628ffcf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2838286256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2838286256
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.4218019803
Short name T94
Test name
Test status
Simulation time 60163682 ps
CPU time 1.34 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:14 PM PDT 24
Peak memory 214284 kb
Host smart-0f8cd670-e380-47fa-aace-0c30007edd2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218019803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.4218019803
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3830878188
Short name T154
Test name
Test status
Simulation time 139049979 ps
CPU time 1.17 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 206140 kb
Host smart-b1419b6f-aac3-4898-b70b-60f7df950f99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3830878188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3830878188
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3904422235
Short name T139
Test name
Test status
Simulation time 31878461 ps
CPU time 0.63 seconds
Started Jun 22 04:33:20 PM PDT 24
Finished Jun 22 04:33:27 PM PDT 24
Peak memory 205828 kb
Host smart-ac8550d1-b433-4561-bab8-be45a192ffeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3904422235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3904422235
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3627168547
Short name T152
Test name
Test status
Simulation time 103191099 ps
CPU time 1.17 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:12 PM PDT 24
Peak memory 206172 kb
Host smart-7655956c-f7ca-42b9-847d-b0fd09bc6172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3627168547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3627168547
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.684254295
Short name T122
Test name
Test status
Simulation time 266626217 ps
CPU time 2.94 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 214372 kb
Host smart-a9f782f9-3299-4db7-92fb-83d84dc6a744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=684254295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.684254295
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3340065359
Short name T87
Test name
Test status
Simulation time 529128335 ps
CPU time 2.86 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:19 PM PDT 24
Peak memory 206172 kb
Host smart-1a929107-6eb8-4694-b948-ef61df51d42b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3340065359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3340065359
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2101596360
Short name T104
Test name
Test status
Simulation time 94927092 ps
CPU time 1.71 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:18 PM PDT 24
Peak memory 214284 kb
Host smart-dab84de0-2c65-48ee-9d8b-bf586450a4ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101596360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2101596360
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2517755205
Short name T37
Test name
Test status
Simulation time 115295756 ps
CPU time 1.11 seconds
Started Jun 22 04:33:14 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 206156 kb
Host smart-d1425354-f9c2-4a35-b941-5d727abdcd63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2517755205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2517755205
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2312399299
Short name T101
Test name
Test status
Simulation time 54163075 ps
CPU time 0.68 seconds
Started Jun 22 04:33:16 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 205836 kb
Host smart-73efc353-d89f-4178-ae0f-6ac47732429d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2312399299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2312399299
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4270323251
Short name T63
Test name
Test status
Simulation time 176006710 ps
CPU time 1.18 seconds
Started Jun 22 04:33:18 PM PDT 24
Finished Jun 22 04:33:20 PM PDT 24
Peak memory 206212 kb
Host smart-96d279e4-8140-4517-9c24-c8eb208b97e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4270323251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4270323251
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3852605366
Short name T169
Test name
Test status
Simulation time 90485998 ps
CPU time 1.4 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 206216 kb
Host smart-46967768-66e3-4d55-b459-05556aff938d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3852605366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3852605366
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1332368653
Short name T56
Test name
Test status
Simulation time 128396387 ps
CPU time 1.62 seconds
Started Jun 22 04:33:14 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 214284 kb
Host smart-3697e4b7-a5bd-4019-8849-83dcce30696d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332368653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1332368653
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1863490116
Short name T33
Test name
Test status
Simulation time 45685098 ps
CPU time 0.98 seconds
Started Jun 22 04:33:15 PM PDT 24
Finished Jun 22 04:33:17 PM PDT 24
Peak memory 206188 kb
Host smart-36fccf20-8ce4-4766-a06d-aeeeb95da3da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1863490116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1863490116
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1557297186
Short name T134
Test name
Test status
Simulation time 274011000 ps
CPU time 1.68 seconds
Started Jun 22 04:33:18 PM PDT 24
Finished Jun 22 04:33:21 PM PDT 24
Peak memory 206440 kb
Host smart-1b459eab-e7ce-41f5-9bc4-da472c1bfe33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1557297186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1557297186
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3309498787
Short name T143
Test name
Test status
Simulation time 227551903 ps
CPU time 2.39 seconds
Started Jun 22 04:33:11 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 222184 kb
Host smart-123c1636-f61c-440d-b8de-4dd5c65a368c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3309498787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3309498787
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2720187369
Short name T126
Test name
Test status
Simulation time 412625804 ps
CPU time 2.78 seconds
Started Jun 22 04:33:17 PM PDT 24
Finished Jun 22 04:33:20 PM PDT 24
Peak memory 206132 kb
Host smart-6d642b7f-82e5-43ac-8e4c-70271b7d9dcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2720187369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2720187369
Directory /workspace/9.usbdev_tl_intg_err/latest
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