Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	377	1		T1	5		T7	8		T8	2
all_pins[1]	377	1		T1	5		T7	8		T8	2
all_pins[2]	377	1		T1	5		T7	8		T8	2
all_pins[3]	377	1		T1	5		T7	8		T8	2
all_pins[4]	377	1		T1	5		T7	8		T8	2
all_pins[5]	377	1		T1	5		T7	8		T8	2
all_pins[6]	377	1		T1	5		T7	8		T8	2
all_pins[7]	377	1		T1	5		T7	8		T8	2
all_pins[8]	377	1		T1	5		T7	8		T8	2
all_pins[9]	377	1		T1	5		T7	8		T8	2
all_pins[10]	377	1		T1	5		T7	8		T8	2
all_pins[11]	377	1		T1	5		T7	8		T8	2
all_pins[12]	377	1		T1	5		T7	8		T8	2
all_pins[13]	377	1		T1	5		T7	8		T8	2
all_pins[14]	377	1		T1	5		T7	8		T8	2
all_pins[15]	377	1		T1	5		T7	8		T8	2
all_pins[16]	377	1		T1	5		T7	8		T8	2
all_pins[17]	377	1		T1	5		T7	8		T8	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5589	1		T1	72		T7	103		T8	36
values[0x1]	1197	1		T1	18		T7	41		T9	25
transitions[0x0=>0x1]	865	1		T1	11		T7	24		T9	19
transitions[0x1=>0x0]	876	1		T1	11		T7	25		T9	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	327	1		T1	5		T7	7		T8	2
all_pins[0]	values[0x1]	50	1		T7	1		T9	1		T16	2
all_pins[0]	transitions[0x0=>0x1]	32	1		T9	1		T16	1		T68	2
all_pins[0]	transitions[0x1=>0x0]	46	1		T7	2		T9	1		T16	1
all_pins[1]	values[0x0]	313	1		T1	5		T7	5		T8	2
all_pins[1]	values[0x1]	64	1		T7	3		T9	1		T16	2
all_pins[1]	transitions[0x0=>0x1]	50	1		T7	2		T9	1		T16	2
all_pins[1]	transitions[0x1=>0x0]	44	1		T68	2		T67	2		T73	6
all_pins[2]	values[0x0]	319	1		T1	5		T7	7		T8	2
all_pins[2]	values[0x1]	58	1		T7	1		T68	2		T67	2
all_pins[2]	transitions[0x0=>0x1]	42	1		T7	1		T68	1		T67	2
all_pins[2]	transitions[0x1=>0x0]	49	1		T7	5		T9	1		T66	1
all_pins[3]	values[0x0]	312	1		T1	5		T7	3		T8	2
all_pins[3]	values[0x1]	65	1		T7	5		T9	1		T66	1
all_pins[3]	transitions[0x0=>0x1]	41	1		T7	3		T9	1		T66	1
all_pins[3]	transitions[0x1=>0x0]	46	1		T1	1		T16	3		T68	2
all_pins[4]	values[0x0]	307	1		T1	4		T7	6		T8	2
all_pins[4]	values[0x1]	70	1		T1	1		T7	2		T16	3
all_pins[4]	transitions[0x0=>0x1]	56	1		T1	1		T7	1		T16	3
all_pins[4]	transitions[0x1=>0x0]	52	1		T7	3		T9	1		T16	1
all_pins[5]	values[0x0]	311	1		T1	5		T7	4		T8	2
all_pins[5]	values[0x1]	66	1		T7	4		T9	1		T16	1
all_pins[5]	transitions[0x0=>0x1]	48	1		T7	3		T9	1		T16	1
all_pins[5]	transitions[0x1=>0x0]	43	1		T9	1		T16	1		T66	1
all_pins[6]	values[0x0]	316	1		T1	5		T7	7		T8	2
all_pins[6]	values[0x1]	61	1		T7	1		T9	1		T16	1
all_pins[6]	transitions[0x0=>0x1]	53	1		T9	1		T16	1		T66	1
all_pins[6]	transitions[0x1=>0x0]	51	1		T1	2		T7	2		T9	2
all_pins[7]	values[0x0]	318	1		T1	3		T7	5		T8	2
all_pins[7]	values[0x1]	59	1		T1	2		T7	3		T9	2
all_pins[7]	transitions[0x0=>0x1]	43	1		T1	2		T7	3		T9	1
all_pins[7]	transitions[0x1=>0x0]	50	1		T66	2		T68	2		T74	1
all_pins[8]	values[0x0]	311	1		T1	5		T7	8		T8	2
all_pins[8]	values[0x1]	66	1		T9	1		T16	1		T66	2
all_pins[8]	transitions[0x0=>0x1]	53	1		T9	1		T16	1		T66	2
all_pins[8]	transitions[0x1=>0x0]	48	1		T1	1		T7	1		T16	3
all_pins[9]	values[0x0]	316	1		T1	4		T7	7		T8	2
all_pins[9]	values[0x1]	61	1		T1	1		T7	1		T16	3
all_pins[9]	transitions[0x0=>0x1]	37	1		T1	1		T68	2		T74	2
all_pins[9]	transitions[0x1=>0x0]	48	1		T1	2		T7	2		T9	3
all_pins[10]	values[0x0]	305	1		T1	3		T7	5		T8	2
all_pins[10]	values[0x1]	72	1		T1	2		T7	3		T9	3
all_pins[10]	transitions[0x0=>0x1]	47	1		T7	3		T9	3		T16	2
all_pins[10]	transitions[0x1=>0x0]	65	1		T1	2		T9	1		T16	1
all_pins[11]	values[0x0]	287	1		T1	1		T7	8		T8	2
all_pins[11]	values[0x1]	90	1		T1	4		T9	1		T16	3
all_pins[11]	transitions[0x0=>0x1]	55	1		T16	1		T68	3		T67	3
all_pins[11]	transitions[0x1=>0x0]	65	1		T7	5		T9	3		T16	1
all_pins[12]	values[0x0]	277	1		T1	1		T7	3		T8	2
all_pins[12]	values[0x1]	100	1		T1	4		T7	5		T9	4
all_pins[12]	transitions[0x0=>0x1]	71	1		T1	4		T7	1		T9	2
all_pins[12]	transitions[0x1=>0x0]	41	1		T7	1		T66	1		T68	2
all_pins[13]	values[0x0]	307	1		T1	5		T7	3		T8	2
all_pins[13]	values[0x1]	70	1		T7	5		T9	2		T66	1
all_pins[13]	transitions[0x0=>0x1]	48	1		T7	3		T9	1		T66	1
all_pins[13]	transitions[0x1=>0x0]	43	1		T16	1		T74	1		T72	3
all_pins[14]	values[0x0]	312	1		T1	5		T7	6		T8	2
all_pins[14]	values[0x1]	65	1		T7	2		T9	1		T16	1
all_pins[14]	transitions[0x0=>0x1]	52	1		T7	1		T74	2		T72	3
all_pins[14]	transitions[0x1=>0x0]	47	1		T7	1		T9	4		T16	1
all_pins[15]	values[0x0]	317	1		T1	5		T7	6		T8	2
all_pins[15]	values[0x1]	60	1		T7	2		T9	5		T16	2
all_pins[15]	transitions[0x0=>0x1]	49	1		T7	1		T9	5		T16	2
all_pins[15]	transitions[0x1=>0x0]	54	1		T1	2		T7	1		T74	3
all_pins[16]	values[0x0]	312	1		T1	3		T7	6		T8	2
all_pins[16]	values[0x1]	65	1		T1	2		T7	2		T74	3
all_pins[16]	transitions[0x0=>0x1]	54	1		T1	1		T7	2		T74	2
all_pins[16]	transitions[0x1=>0x0]	44	1		T1	1		T7	1		T9	1
all_pins[17]	values[0x0]	322	1		T1	3		T7	7		T8	2
all_pins[17]	values[0x1]	55	1		T1	2		T7	1		T9	1
all_pins[17]	transitions[0x0=>0x1]	34	1		T1	2		T9	1		T16	1
all_pins[17]	transitions[0x1=>0x0]	40	1		T7	1		T9	1		T16	1