Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1		T1	4		T7	7		T9	7
all_values[1]	287	1		T1	4		T7	7		T9	7
all_values[2]	287	1		T1	4		T7	7		T9	7
all_values[3]	287	1		T1	4		T7	7		T9	7
all_values[4]	287	1		T1	4		T7	7		T9	7
all_values[5]	287	1		T1	4		T7	7		T9	7
all_values[6]	287	1		T1	4		T7	7		T9	7
all_values[7]	287	1		T1	4		T7	7		T9	7
all_values[8]	287	1		T1	4		T7	7		T9	7
all_values[9]	287	1		T1	4		T7	7		T9	7
all_values[10]	287	1		T1	4		T7	7		T9	7
all_values[11]	287	1		T1	4		T7	7		T9	7
all_values[12]	287	1		T1	4		T7	7		T9	7
all_values[13]	287	1		T1	4		T7	7		T9	7
all_values[14]	287	1		T1	4		T7	7		T9	7
all_values[15]	287	1		T1	4		T7	7		T9	7
all_values[16]	287	1		T1	4		T7	7		T9	7
all_values[17]	287	1		T1	4		T7	7		T9	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2757	1		T1	32		T7	62		T9	69
auto[1]	2409	1		T1	40		T7	64		T9	57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	823	1		T1	31		T7	13		T9	25
auto[1]	4343	1		T1	41		T7	113		T9	101

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2989	1		T1	47		T7	70		T9	75
auto[1]	2177	1		T1	25		T7	56		T9	51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	33	1		T1	2		T7	2		T68	1
all_values[0]	auto[0]	auto[0]	auto[1]	77	1		T7	1		T9	2		T16	3
all_values[0]	auto[0]	auto[1]	auto[0]	15	1		T1	2		T7	1		T68	1
all_values[0]	auto[0]	auto[1]	auto[1]	43	1		T7	1		T74	2		T72	1
all_values[0]	auto[1]	auto[0]	auto[1]	71	1		T9	3		T16	3		T66	1
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T7	2		T9	2		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	24	1		T1	2		T73	1		T69	2
all_values[1]	auto[0]	auto[0]	auto[1]	60	1		T7	2		T9	2		T16	1
all_values[1]	auto[0]	auto[1]	auto[0]	15	1		T1	2		T69	2		T70	3
all_values[1]	auto[0]	auto[1]	auto[1]	58	1		T7	1		T9	1		T16	3
all_values[1]	auto[1]	auto[0]	auto[1]	76	1		T9	3		T16	2		T66	1
all_values[1]	auto[1]	auto[1]	auto[1]	54	1		T7	4		T9	1		T16	1
all_values[2]	auto[0]	auto[0]	auto[0]	31	1		T1	1		T9	2		T72	2
all_values[2]	auto[0]	auto[0]	auto[1]	57	1		T7	3		T16	3		T66	1
all_values[2]	auto[0]	auto[1]	auto[0]	29	1		T1	3		T9	5		T68	1
all_values[2]	auto[0]	auto[1]	auto[1]	55	1		T66	1		T74	1		T67	2
all_values[2]	auto[1]	auto[0]	auto[1]	66	1		T7	3		T16	4		T66	1
all_values[2]	auto[1]	auto[1]	auto[1]	49	1		T7	1		T66	1		T68	3
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T73	1		T75	4		T79	2
all_values[3]	auto[0]	auto[0]	auto[1]	44	1		T1	2		T9	1		T16	3
all_values[3]	auto[0]	auto[1]	auto[0]	27	1		T7	2		T71	1		T69	4
all_values[3]	auto[0]	auto[1]	auto[1]	74	1		T7	3		T9	4		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	52	1		T1	2		T9	1		T16	3
all_values[3]	auto[1]	auto[1]	auto[1]	54	1		T7	2		T9	1		T66	1
all_values[4]	auto[0]	auto[0]	auto[0]	21	1		T9	1		T66	1		T74	1
all_values[4]	auto[0]	auto[0]	auto[1]	59	1		T7	2		T9	2		T16	2
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T1	1		T9	3		T66	3
all_values[4]	auto[0]	auto[1]	auto[1]	63	1		T1	2		T7	1		T16	1
all_values[4]	auto[1]	auto[0]	auto[1]	66	1		T7	3		T16	2		T68	3
all_values[4]	auto[1]	auto[1]	auto[1]	61	1		T1	1		T7	1		T9	1
all_values[5]	auto[0]	auto[0]	auto[0]	28	1		T66	1		T68	1		T72	2
all_values[5]	auto[0]	auto[0]	auto[1]	64	1		T1	1		T7	2		T9	3
all_values[5]	auto[0]	auto[1]	auto[0]	16	1		T1	1		T16	3		T68	2
all_values[5]	auto[0]	auto[1]	auto[1]	63	1		T7	2		T9	2		T16	1
all_values[5]	auto[1]	auto[0]	auto[1]	62	1		T1	2		T7	1		T9	1
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T7	2		T9	1		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	34	1		T9	1		T16	1		T74	1
all_values[6]	auto[0]	auto[0]	auto[1]	59	1		T7	1		T9	1		T66	2
all_values[6]	auto[0]	auto[1]	auto[0]	26	1		T1	4		T7	1		T68	2
all_values[6]	auto[0]	auto[1]	auto[1]	57	1		T7	1		T9	1		T16	2
all_values[6]	auto[1]	auto[0]	auto[1]	57	1		T7	3		T9	1		T16	2
all_values[6]	auto[1]	auto[1]	auto[1]	54	1		T7	1		T9	3		T16	2
all_values[7]	auto[0]	auto[0]	auto[0]	29	1		T7	2		T9	2		T66	1
all_values[7]	auto[0]	auto[0]	auto[1]	70	1		T7	1		T9	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	18	1		T72	1		T70	2		T80	1
all_values[7]	auto[0]	auto[1]	auto[1]	61	1		T1	1		T7	1		T16	3
all_values[7]	auto[1]	auto[0]	auto[1]	61	1		T1	1		T7	1		T9	1
all_values[7]	auto[1]	auto[1]	auto[1]	48	1		T1	2		T7	2		T9	2
all_values[8]	auto[0]	auto[0]	auto[0]	39	1		T1	3		T9	2		T66	1
all_values[8]	auto[0]	auto[0]	auto[1]	61	1		T7	5		T9	1		T16	4
all_values[8]	auto[0]	auto[1]	auto[0]	11	1		T1	1		T9	1		T16	1
all_values[8]	auto[0]	auto[1]	auto[1]	60	1		T9	1		T66	1		T68	2
all_values[8]	auto[1]	auto[0]	auto[1]	53	1		T7	1		T9	2		T68	1
all_values[8]	auto[1]	auto[1]	auto[1]	63	1		T7	1		T16	2		T66	2
all_values[9]	auto[0]	auto[0]	auto[0]	23	1		T1	1		T7	1		T16	1
all_values[9]	auto[0]	auto[0]	auto[1]	72	1		T1	1		T7	1		T9	2
all_values[9]	auto[0]	auto[1]	auto[0]	14	1		T7	1		T16	1		T68	1
all_values[9]	auto[0]	auto[1]	auto[1]	53	1		T7	2		T16	2		T68	3
all_values[9]	auto[1]	auto[0]	auto[1]	82	1		T1	1		T7	2		T9	5
all_values[9]	auto[1]	auto[1]	auto[1]	43	1		T1	1		T16	1		T74	1
all_values[10]	auto[0]	auto[0]	auto[0]	31	1		T66	1		T74	2		T72	1
all_values[10]	auto[0]	auto[0]	auto[1]	58	1		T1	1		T7	3		T9	2
all_values[10]	auto[0]	auto[1]	auto[0]	10	1		T66	1		T69	1		T75	2
all_values[10]	auto[0]	auto[1]	auto[1]	60	1		T1	1		T7	2		T9	3
all_values[10]	auto[1]	auto[0]	auto[1]	63	1		T1	1		T7	1		T9	1
all_values[10]	auto[1]	auto[1]	auto[1]	65	1		T1	1		T7	1		T9	1
all_values[11]	auto[0]	auto[0]	auto[0]	23	1		T9	2		T74	3		T71	1
all_values[11]	auto[0]	auto[0]	auto[1]	41	1		T7	3		T9	2		T66	1
all_values[11]	auto[0]	auto[1]	auto[0]	19	1		T16	1		T74	4		T70	3
all_values[11]	auto[0]	auto[1]	auto[1]	76	1		T1	2		T7	1		T9	1
all_values[11]	auto[1]	auto[0]	auto[1]	67	1		T7	2		T9	1		T66	3
all_values[11]	auto[1]	auto[1]	auto[1]	61	1		T1	2		T7	1		T9	1
all_values[12]	auto[0]	auto[0]	auto[0]	27	1		T72	1		T79	1		T81	1
all_values[12]	auto[0]	auto[0]	auto[1]	55	1		T66	1		T68	1		T72	2
all_values[12]	auto[0]	auto[1]	auto[0]	14	1		T75	1		T76	1		T77	2
all_values[12]	auto[0]	auto[1]	auto[1]	63	1		T1	1		T7	3		T9	2
all_values[12]	auto[1]	auto[0]	auto[1]	67	1		T9	3		T16	1		T66	1
all_values[12]	auto[1]	auto[1]	auto[1]	61	1		T1	3		T7	4		T9	2
all_values[13]	auto[0]	auto[0]	auto[0]	21	1		T1	2		T66	1		T72	2
all_values[13]	auto[0]	auto[0]	auto[1]	63	1		T7	1		T9	2		T16	4
all_values[13]	auto[0]	auto[1]	auto[0]	12	1		T1	2		T16	1		T68	1
all_values[13]	auto[0]	auto[1]	auto[1]	61	1		T7	3		T9	2		T66	1
all_values[13]	auto[1]	auto[0]	auto[1]	68	1		T7	1		T9	1		T16	2
all_values[13]	auto[1]	auto[1]	auto[1]	62	1		T7	2		T9	2		T66	1
all_values[14]	auto[0]	auto[0]	auto[0]	31	1		T1	1		T9	1		T16	2
all_values[14]	auto[0]	auto[0]	auto[1]	46	1		T1	1		T7	1		T16	1
all_values[14]	auto[0]	auto[1]	auto[0]	17	1		T1	1		T66	1		T69	2
all_values[14]	auto[0]	auto[1]	auto[1]	66	1		T7	2		T9	2		T68	5
all_values[14]	auto[1]	auto[0]	auto[1]	65	1		T1	1		T7	2		T9	1
all_values[14]	auto[1]	auto[1]	auto[1]	62	1		T7	2		T9	3		T16	3
all_values[15]	auto[0]	auto[0]	auto[0]	21	1		T66	1		T74	1		T72	1
all_values[15]	auto[0]	auto[0]	auto[1]	64	1		T1	1		T7	2		T16	1
all_values[15]	auto[0]	auto[1]	auto[0]	13	1		T74	1		T46	1		T51	2
all_values[15]	auto[0]	auto[1]	auto[1]	68	1		T9	4		T16	3		T66	1
all_values[15]	auto[1]	auto[0]	auto[1]	70	1		T1	2		T7	3		T9	2
all_values[15]	auto[1]	auto[1]	auto[1]	51	1		T1	1		T7	2		T9	1
all_values[16]	auto[0]	auto[0]	auto[0]	33	1		T1	1		T9	2		T66	1
all_values[16]	auto[0]	auto[0]	auto[1]	56	1		T7	1		T9	2		T16	3
all_values[16]	auto[0]	auto[1]	auto[0]	28	1		T7	3		T16	2		T72	2
all_values[16]	auto[0]	auto[1]	auto[1]	51	1		T1	1		T7	1		T9	1
all_values[16]	auto[1]	auto[0]	auto[1]	60	1		T1	1		T9	2		T68	2
all_values[16]	auto[1]	auto[1]	auto[1]	59	1		T1	1		T7	2		T16	2
all_values[17]	auto[0]	auto[0]	auto[0]	24	1		T1	1		T9	2		T74	1
all_values[17]	auto[0]	auto[0]	auto[1]	63	1		T7	3		T9	1		T68	2
all_values[17]	auto[0]	auto[1]	auto[0]	13	1		T9	1		T70	1		T75	2
all_values[17]	auto[0]	auto[1]	auto[1]	65	1		T1	1		T7	1		T9	1
all_values[17]	auto[1]	auto[0]	auto[1]	73	1		T7	2		T9	1		T16	1
all_values[17]	auto[1]	auto[1]	auto[1]	49	1		T1	2		T7	1		T9	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal