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LINE 9293
EXPRESSION (addr_hit[33] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Not Covered | |
LINE 9294
EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9313
EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T8,T10,T21 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9326
EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9329
EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T8,T20,T21 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9336
EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9337
EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T8,T10,T21 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9350
EXPRESSION (addr_hit[40] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9351
EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T8,T20,T21 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9362
EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9363
EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T21,T22,T58 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9368
EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9369
EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T3,T8 |
| 1 | 1 | 0 | Covered | T60,T61,T62 |
| 1 | 1 | 1 | Covered | T2,T3,T11 |
LINE 9881
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T3,T11 |