Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	18144133	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18466265	1		T1	5		T2	5		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36085321	1		T1	2		T2	2		T3	4
values[0x0]	262288	1		T1	6		T2	5		T3	3
values[0x1]	262789	1		T1	2		T2	4		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14468890	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	22141508	1		T1	8		T2	7		T3	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	107024	1		T5	814		T31	33		T19	572
valid_sources[0x01]	107925	1		T5	775		T31	28		T7	1
valid_sources[0x02]	105834	1		T5	784		T31	24		T7	1
valid_sources[0x03]	106341	1		T5	819		T31	18		T19	605
valid_sources[0x04]	105086	1		T5	746		T31	12		T19	626
valid_sources[0x05]	294888	1		T5	754		T31	12		T7	6
valid_sources[0x06]	427386	1		T5	787		T31	17		T19	647
valid_sources[0x07]	105230	1		T5	779		T31	10		T19	651
valid_sources[0x08]	217648	1		T5	791		T31	30		T17	2
valid_sources[0x09]	175196	1		T5	744		T31	19		T7	2
valid_sources[0x0a]	106835	1		T2	1		T5	783		T31	20
valid_sources[0x0b]	748841	1		T5	787		T31	12		T7	2
valid_sources[0x0c]	397444	1		T1	1		T2	1		T5	805
valid_sources[0x0d]	105703	1		T5	735		T31	10		T17	1
valid_sources[0x0e]	106024	1		T5	784		T31	19		T7	5
valid_sources[0x0f]	162519	1		T5	834		T31	33		T19	646
valid_sources[0x10]	106286	1		T5	767		T31	15		T7	3
valid_sources[0x11]	155030	1		T5	795		T31	23		T17	2
valid_sources[0x12]	106809	1		T5	819		T31	15		T17	3
valid_sources[0x13]	108518	1		T5	735		T31	27		T7	5
valid_sources[0x14]	106402	1		T5	774		T31	11		T19	616
valid_sources[0x15]	106573	1		T5	786		T31	23		T7	2
valid_sources[0x16]	107169	1		T5	788		T31	29		T7	1
valid_sources[0x17]	107528	1		T5	789		T31	17		T17	7
valid_sources[0x18]	138964	1		T5	816		T31	9		T17	1
valid_sources[0x19]	107780	1		T29	1		T5	786		T31	21
valid_sources[0x1a]	106818	1		T5	826		T31	23		T19	647
valid_sources[0x1b]	107950	1		T5	799		T31	10		T19	613
valid_sources[0x1c]	106946	1		T5	753		T31	23		T19	576
valid_sources[0x1d]	105926	1		T5	742		T31	27		T19	621
valid_sources[0x1e]	106407	1		T5	773		T31	8		T19	640
valid_sources[0x1f]	107317	1		T5	810		T31	28		T19	596
valid_sources[0x20]	209798	1		T5	741		T31	14		T17	2
valid_sources[0x21]	105779	1		T5	748		T31	8		T19	633
valid_sources[0x22]	331371	1		T5	792		T31	29		T17	4
valid_sources[0x23]	106381	1		T5	804		T31	9		T17	1
valid_sources[0x24]	247815	1		T5	785		T31	19		T17	1
valid_sources[0x25]	106604	1		T5	747		T30	16		T31	9
valid_sources[0x26]	106611	1		T5	752		T31	9		T7	2
valid_sources[0x27]	106447	1		T5	815		T31	32		T19	592
valid_sources[0x28]	108082	1		T5	759		T31	25		T19	599
valid_sources[0x29]	248871	1		T4	121873		T29	1		T5	796
valid_sources[0x2a]	108492	1		T5	815		T31	31		T19	676
valid_sources[0x2b]	107996	1		T5	809		T31	23		T17	4
valid_sources[0x2c]	109142	1		T5	788		T31	24		T19	626
valid_sources[0x2d]	105145	1		T5	774		T31	28		T17	1
valid_sources[0x2e]	348558	1		T5	819		T31	17		T7	7
valid_sources[0x2f]	106907	1		T5	778		T31	22		T7	2
valid_sources[0x30]	106190	1		T5	824		T31	21		T17	2
valid_sources[0x31]	106919	1		T5	778		T31	6		T19	626
valid_sources[0x32]	176236	1		T5	745		T31	33		T17	2
valid_sources[0x33]	106705	1		T5	758		T31	11		T19	599
valid_sources[0x34]	108546	1		T5	852		T31	36		T7	1
valid_sources[0x35]	106720	1		T29	1		T5	763		T31	22
valid_sources[0x36]	106673	1		T5	728		T31	14		T19	585
valid_sources[0x37]	106705	1		T5	811		T31	8		T17	11
valid_sources[0x38]	108042	1		T5	821		T31	9		T19	646
valid_sources[0x39]	157660	1		T5	761		T31	21		T19	606
valid_sources[0x3a]	108444	1		T5	750		T31	16		T7	2
valid_sources[0x3b]	106246	1		T5	762		T31	7		T7	1
valid_sources[0x3c]	107096	1		T5	781		T31	21		T7	1
valid_sources[0x3d]	107886	1		T5	753		T31	16		T19	642
valid_sources[0x3e]	104705	1		T5	744		T31	11		T19	633
valid_sources[0x3f]	105488	1		T5	736		T31	6		T17	2
valid_sources[0x40]	106604	1		T2	1		T5	760		T31	23
valid_sources[0x41]	105882	1		T5	828		T31	9		T32	1
valid_sources[0x42]	228057	1		T5	832		T31	28		T19	606
valid_sources[0x43]	171465	1		T5	789		T31	20		T17	2
valid_sources[0x44]	105737	1		T5	752		T31	19		T32	2
valid_sources[0x45]	106557	1		T5	833		T31	5		T17	8
valid_sources[0x46]	306519	1		T5	787		T31	29		T19	608
valid_sources[0x47]	142193	1		T5	783		T31	19		T7	3
valid_sources[0x48]	106648	1		T5	790		T31	12		T7	2
valid_sources[0x49]	106224	1		T5	731		T31	18		T7	2
valid_sources[0x4a]	238725	1		T5	761		T31	9		T19	662
valid_sources[0x4b]	106618	1		T5	796		T31	11		T19	599
valid_sources[0x4c]	176693	1		T5	778		T31	22		T19	597
valid_sources[0x4d]	214386	1		T29	1		T5	767		T31	21
valid_sources[0x4e]	108005	1		T5	833		T31	8		T17	1
valid_sources[0x4f]	106753	1		T5	782		T31	12		T17	1
valid_sources[0x50]	107058	1		T5	827		T31	34		T7	1
valid_sources[0x51]	107029	1		T5	798		T31	13		T7	1
valid_sources[0x52]	105541	1		T5	806		T31	29		T19	623
valid_sources[0x53]	107183	1		T5	758		T31	15		T17	1
valid_sources[0x54]	108735	1		T5	809		T31	24		T19	622
valid_sources[0x55]	104986	1		T2	1		T5	744		T31	7
valid_sources[0x56]	107240	1		T5	793		T31	16		T17	1
valid_sources[0x57]	106262	1		T5	779		T31	25		T7	3
valid_sources[0x58]	108786	1		T5	805		T31	10		T17	1
valid_sources[0x59]	106479	1		T5	808		T31	9		T17	4
valid_sources[0x5a]	105883	1		T5	773		T31	10		T32	1
valid_sources[0x5b]	349264	1		T5	785		T31	25		T32	3
valid_sources[0x5c]	106868	1		T5	785		T31	23		T7	1
valid_sources[0x5d]	105157	1		T5	773		T31	16		T19	643
valid_sources[0x5e]	107517	1		T5	790		T31	17		T17	1
valid_sources[0x5f]	106277	1		T3	8		T5	748		T31	9
valid_sources[0x60]	106408	1		T5	778		T31	21		T19	580
valid_sources[0x61]	108254	1		T5	820		T31	14		T17	6
valid_sources[0x62]	107389	1		T5	742		T31	20		T7	1
valid_sources[0x63]	107692	1		T5	765		T31	20		T17	1
valid_sources[0x64]	221916	1		T5	756		T31	4		T17	2
valid_sources[0x65]	110901	1		T5	798		T31	20		T7	1
valid_sources[0x66]	106196	1		T5	806		T31	10		T19	585
valid_sources[0x67]	105778	1		T5	786		T31	32		T19	611
valid_sources[0x68]	200558	1		T5	808		T31	26		T19	636
valid_sources[0x69]	107155	1		T5	848		T31	42		T19	620
valid_sources[0x6a]	105737	1		T5	804		T31	21		T19	621
valid_sources[0x6b]	109331	1		T5	838		T31	9		T7	1
valid_sources[0x6c]	105525	1		T5	786		T31	25		T17	1
valid_sources[0x6d]	107259	1		T5	820		T31	26		T17	1
valid_sources[0x6e]	106264	1		T5	817		T31	32		T19	594
valid_sources[0x6f]	110387	1		T5	819		T31	9		T19	587
valid_sources[0x70]	106603	1		T5	767		T31	16		T19	643
valid_sources[0x71]	106517	1		T5	761		T31	17		T7	1
valid_sources[0x72]	360591	1		T5	761		T31	7		T7	2
valid_sources[0x73]	157265	1		T5	783		T31	13		T19	615
valid_sources[0x74]	208500	1		T5	772		T31	22		T17	2
valid_sources[0x75]	106270	1		T5	782		T31	11		T19	637
valid_sources[0x76]	107513	1		T5	777		T31	4		T19	621
valid_sources[0x77]	127757	1		T5	821		T31	14		T7	2
valid_sources[0x78]	108008	1		T5	758		T31	17		T7	3
valid_sources[0x79]	150257	1		T5	777		T31	21		T19	599
valid_sources[0x7a]	105718	1		T5	766		T31	24		T7	3
valid_sources[0x7b]	107043	1		T5	783		T31	31		T17	7
valid_sources[0x7c]	107677	1		T5	763		T31	21		T19	588
valid_sources[0x7d]	107646	1		T5	753		T31	27		T19	626
valid_sources[0x7e]	105626	1		T5	840		T31	8		T17	1
valid_sources[0x7f]	106217	1		T5	792		T31	6		T19	629
valid_sources[0x80]	105936	1		T5	792		T31	16		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18057487

1

T1

1

T3

2

T4

60807

values[0x0]

all_enables

biggest_size

211226

1

T1

4

T2

4

T3

3

values[0x1]

all_enables

biggest_size

197552

1

T2

1

T3

1

T4

128