Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18159594	1		T1	5		T2	6		T3	7
full_word	18467270	1		T1	5		T2	5		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36626544	1		T1	10		T2	11		T3	13
auto[TlIntgErrCmd]	118	1		T189	4		T190	10		T213	4
auto[TlIntgErrData]	102	1		T189	4		T190	5		T213	4
auto[TlIntgErrBoth]	100	1		T189	2		T190	5		T213	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	36087294	1		T1	2		T2	2		T3	4
auto[1]	539570	1		T1	8		T2	9		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	18029480	1		T1	1		T2	2		T3	2
auto[TlIntgErrNone]	partial	auto[1]	129820	1		T1	4		T2	4		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	18057677	1		T1	1		T3	2		T4	60807
auto[TlIntgErrNone]	full_word	auto[1]	409567	1		T1	4		T2	5		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T189	2		T190	2		T213	3
auto[TlIntgErrCmd]	partial	auto[1]	68	1		T189	2		T190	7		T213	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T190	1		T250	1		T273	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T274	1		T275	1		T276	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T189	1		T190	1		T213	3
auto[TlIntgErrData]	partial	auto[1]	50	1		T189	3		T190	4		T213	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T274	1		T275	1		T268	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T277	1		T278	1		T269	2
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T189	1		T190	3		T225	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T190	2		T213	1		T225	7
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T272	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T189	1		T213	1		T275	1