Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	395092090	12174	0	0
ep_in_enable_rd_A	395092090	2725	0	0
ep_out_enable_rd_A	395092090	2375	0	0
in_iso_rd_A	395092090	2588	0	0
intr_enable_rd_A	395092090	3447	0	0
out_iso_rd_A	395092090	2105	0	0
phy_config_rd_A	395092090	1467	0	0
phy_pins_drive_rd_A	395092090	2087	0	0
rxenable_setup_rd_A	395092090	2647	0	0
set_nak_out_rd_A	395092090	2236	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	12174	0	0
T189	11925	1	0	0
T190	107180	6	0	0
T191	3775	551	0	0
T209	8126	18	0	0
T210	4476	187	0	0
T213	20701	1	0	0
T214	5538	259	0	0
T215	4825	692	0	0
T223	5715	12	0	0
T224	6426	8	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2725	0	0
T190	107180	618	0	0
T194	33975	124	0	0
T230	3079	18	0	0
T236	5196	19	0	0
T244	12312	21	0	0
T248	18061	96	0	0
T249	4808	5	0	0
T250	26401	251	0	0
T251	23343	40	0	0
T252	6679	69	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2375	0	0
T190	107180	550	0	0
T194	33975	145	0	0
T230	3079	36	0	0
T236	5196	10	0	0
T244	12312	23	0	0
T248	18061	124	0	0
T249	4808	4	0	0
T250	26401	327	0	0
T251	23343	39	0	0
T252	6679	12	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2588	0	0
T190	107180	539	0	0
T194	33975	141	0	0
T216	13776	3	0	0
T230	3079	32	0	0
T236	5196	12	0	0
T244	12312	38	0	0
T248	18061	123	0	0
T249	4808	42	0	0
T250	26401	316	0	0
T251	23343	43	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	3447	0	0
T190	107180	805	0	0
T194	33975	137	0	0
T196	1914	18	0	0
T198	2316	6	0	0
T230	3079	74	0	0
T244	12312	53	0	0
T248	18061	141	0	0
T249	4808	18	0	0
T250	26401	447	0	0
T253	3203	13	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2105	0	0
T190	107180	345	0	0
T194	33975	106	0	0
T230	3079	2	0	0
T236	5196	1	0	0
T244	12312	25	0	0
T248	18061	89	0	0
T249	4808	6	0	0
T250	26401	246	0	0
T251	23343	15	0	0
T252	6679	23	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	1467	0	0
T190	107180	243	0	0
T194	33975	117	0	0
T216	13776	2	0	0
T230	3079	21	0	0
T244	12312	46	0	0
T248	18061	134	0	0
T249	4808	4	0	0
T250	26401	124	0	0
T251	23343	21	0	0
T252	6679	20	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2087	0	0
T190	107180	204	0	0
T194	33975	143	0	0
T237	17436	111	0	0
T240	2569	38	0	0
T244	12312	30	0	0
T248	18061	89	0	0
T249	4808	33	0	0
T250	26401	267	0	0
T251	23343	17	0	0
T252	6679	11	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2647	0	0
T190	107180	554	0	0
T194	33975	151	0	0
T230	3079	49	0	0
T236	5196	17	0	0
T244	12312	39	0	0
T248	18061	74	0	0
T249	4808	23	0	0
T250	26401	251	0	0
T251	23343	11	0	0
T252	6679	42	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395092090	2236	0	0
T190	107180	534	0	0
T194	33975	105	0	0
T230	3079	48	0	0
T236	5196	20	0	0
T244	12312	39	0	0
T248	18061	127	0	0
T249	4808	4	0	0
T250	26401	127	0	0
T251	23343	28	0	0
T252	6679	27	0	0