Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T26,T27,T28 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T26,T27,T28 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12510173 |
12499540 |
0 |
0 |
T3 |
20 |
17 |
0 |
0 |
T4 |
21203 |
21198 |
0 |
0 |
T5 |
34434 |
34429 |
0 |
0 |
T6 |
16833 |
16828 |
0 |
0 |
T7 |
225 |
220 |
0 |
0 |
T17 |
48 |
46 |
0 |
0 |
T19 |
0 |
448 |
0 |
0 |
T20 |
0 |
2 |
0 |
0 |
T21 |
0 |
2 |
0 |
0 |
T29 |
22 |
17 |
0 |
0 |
T30 |
111 |
106 |
0 |
0 |
T31 |
10674 |
10669 |
0 |
0 |
T32 |
22 |
17 |
0 |
0 |
T33 |
22 |
17 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T29 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T29 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
Assertion Details
| | | | |
selKnown0 |
143228 |
141307 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
143228 |
141307 |
0 |
0 |
T4 |
175 |
174 |
0 |
0 |
T5 |
289 |
288 |
0 |
0 |
T6 |
162 |
161 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T17 |
24 |
23 |
0 |
0 |
T19 |
0 |
224 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
2 |
1 |
0 |
0 |
T31 |
309 |
308 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 6 | 66.67 |
Logical | 9 | 6 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T29 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T3,T4,T29 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
Assertion Details
| | | | |
selKnown0 |
4083283 |
4080849 |
0 |
0 |
selKnown1 |
0 |
0 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4083283 |
4080849 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
6964 |
6963 |
0 |
0 |
T5 |
11309 |
11308 |
0 |
0 |
T6 |
5517 |
5516 |
0 |
0 |
T7 |
74 |
73 |
0 |
0 |
T29 |
7 |
6 |
0 |
0 |
T30 |
36 |
35 |
0 |
0 |
T31 |
3355 |
3354 |
0 |
0 |
T32 |
7 |
6 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 7 | 77.78 |
Logical | 9 | 7 | 77.78 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T29 |
1 | 0 | Covered | T26,T27,T28 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T26,T27,T28 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T29 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
143229 |
141307 |
0 |
0 |
T4 |
175 |
174 |
0 |
0 |
T5 |
289 |
288 |
0 |
0 |
T6 |
162 |
161 |
0 |
0 |
T7 |
2 |
1 |
0 |
0 |
T17 |
24 |
23 |
0 |
0 |
T19 |
0 |
224 |
0 |
0 |
T20 |
0 |
1 |
0 |
0 |
T21 |
0 |
1 |
0 |
0 |
T29 |
1 |
0 |
0 |
0 |
T30 |
2 |
1 |
0 |
0 |
T31 |
309 |
308 |
0 |
0 |
T32 |
1 |
0 |
0 |
0 |
T33 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
50 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T29 |
1 | 0 | Covered | T26,T34,T35 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T34,T35 |
1 | 0 | Covered | T27,T28,T36 |
1 | 1 | Covered | T26,T34,T35 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T29 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4057150 |
4055228 |
0 |
0 |
T3 |
6 |
5 |
0 |
0 |
T4 |
6925 |
6924 |
0 |
0 |
T5 |
11238 |
11237 |
0 |
0 |
T6 |
5475 |
5474 |
0 |
0 |
T7 |
73 |
72 |
0 |
0 |
T29 |
6 |
5 |
0 |
0 |
T30 |
35 |
34 |
0 |
0 |
T31 |
3346 |
3345 |
0 |
0 |
T32 |
6 |
5 |
0 |
0 |
T33 |
6 |
5 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
27 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T29 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T26,T27,T28 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T37,T34,T38 |
1 | 1 | Covered | T26,T27,T28 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T27,T28 |
1 | 0 | Covered | T3,T4,T29 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
4083283 |
4080849 |
0 |
0 |
T3 |
7 |
6 |
0 |
0 |
T4 |
6964 |
6963 |
0 |
0 |
T5 |
11309 |
11308 |
0 |
0 |
T6 |
5517 |
5516 |
0 |
0 |
T7 |
74 |
73 |
0 |
0 |
T29 |
7 |
6 |
0 |
0 |
T30 |
36 |
35 |
0 |
0 |
T31 |
3355 |
3354 |
0 |
0 |
T32 |
7 |
6 |
0 |
0 |
T33 |
7 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23 |
0 |
0 |
0 |