Module Definition
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Module Instance : tb.dut.intr_hw_pkt_received

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_hw_pkt_sent

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_av_out_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_rx_full

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_av_setup_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_powered

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_link_suspend

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_link_resume

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_link_in_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_rx_pid_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_rx_bitstuff_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_frame

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.58 100.00 58.33 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_av_overflow

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_disconnected

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_host_lost

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_link_reset

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_link_out_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.intr_rx_crc_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.73 97.53 86.57 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
SCORELINE
86.94 90.00
tb.dut.intr_hw_pkt_received

SCORELINE
86.94 90.00
tb.dut.intr_hw_pkt_sent

SCORELINE
86.94 90.00
tb.dut.intr_av_out_empty

SCORELINE
86.94 90.00
tb.dut.intr_rx_full

SCORELINE
86.94 90.00
tb.dut.intr_av_setup_empty

Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
SCORELINE
93.75 100.00
tb.dut.intr_disconnected

SCORELINE
89.58 100.00
tb.dut.intr_powered

SCORELINE
93.75 100.00
tb.dut.intr_host_lost

SCORELINE
93.75 100.00
tb.dut.intr_link_reset

SCORELINE
89.58 100.00
tb.dut.intr_link_suspend

SCORELINE
89.58 100.00
tb.dut.intr_link_resume

SCORELINE
91.67 100.00
tb.dut.intr_av_overflow

SCORELINE
89.58 100.00
tb.dut.intr_link_in_err

SCORELINE
93.75 100.00
tb.dut.intr_link_out_err

SCORELINE
93.75 100.00
tb.dut.intr_rx_crc_err

SCORELINE
89.58 100.00
tb.dut.intr_rx_pid_err

SCORELINE
89.58 100.00
tb.dut.intr_rx_bitstuff_err

SCORELINE
89.58 100.00
tb.dut.intr_frame

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
SCORECOND
86.94 77.78
tb.dut.intr_hw_pkt_received

SCORECOND
86.94 77.78
tb.dut.intr_hw_pkt_sent

SCORECOND
86.94 77.78
tb.dut.intr_av_out_empty

SCORECOND
86.94 77.78
tb.dut.intr_rx_full

SCORECOND
86.94 77.78
tb.dut.intr_av_setup_empty

TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT7,T17,T18
10CoveredT1,T2,T3
11CoveredT7,T17,T18

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
SCORECOND
93.75 75.00
tb.dut.intr_disconnected

SCORECOND
89.58 58.33
tb.dut.intr_powered

SCORECOND
93.75 75.00
tb.dut.intr_host_lost

SCORECOND
93.75 75.00
tb.dut.intr_link_reset

SCORECOND
89.58 58.33
tb.dut.intr_link_suspend

SCORECOND
89.58 58.33
tb.dut.intr_link_resume

SCORECOND
91.67 66.67
tb.dut.intr_av_overflow

SCORECOND
89.58 58.33
tb.dut.intr_link_in_err

SCORECOND
93.75 75.00
tb.dut.intr_link_out_err

SCORECOND
93.75 75.00
tb.dut.intr_rx_crc_err

SCORECOND
89.58 58.33
tb.dut.intr_rx_pid_err

SCORECOND
89.58 58.33
tb.dut.intr_rx_bitstuff_err

SCORECOND
89.58 58.33
tb.dut.intr_frame

TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T40
10CoveredT1,T2,T3
11CoveredT1,T2,T40

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
SCOREBRANCH
86.94 80.00
tb.dut.intr_hw_pkt_received

SCOREBRANCH
86.94 80.00
tb.dut.intr_hw_pkt_sent

SCOREBRANCH
86.94 80.00
tb.dut.intr_av_out_empty

SCOREBRANCH
86.94 80.00
tb.dut.intr_rx_full

SCOREBRANCH
86.94 80.00
tb.dut.intr_av_setup_empty

Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
SCOREBRANCH
93.75 100.00
tb.dut.intr_disconnected

SCOREBRANCH
89.58 100.00
tb.dut.intr_powered

SCOREBRANCH
93.75 100.00
tb.dut.intr_host_lost

SCOREBRANCH
93.75 100.00
tb.dut.intr_link_reset

SCOREBRANCH
89.58 100.00
tb.dut.intr_link_suspend

SCOREBRANCH
89.58 100.00
tb.dut.intr_link_resume

SCOREBRANCH
91.67 100.00
tb.dut.intr_av_overflow

SCOREBRANCH
89.58 100.00
tb.dut.intr_link_in_err

SCOREBRANCH
93.75 100.00
tb.dut.intr_link_out_err

SCOREBRANCH
93.75 100.00
tb.dut.intr_rx_crc_err

SCOREBRANCH
89.58 100.00
tb.dut.intr_rx_pid_err

SCOREBRANCH
89.58 100.00
tb.dut.intr_rx_bitstuff_err

SCOREBRANCH
89.58 100.00
tb.dut.intr_frame

Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 43812 43812 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 43812 43812 0 0
T1 18 18 0 0
T2 18 18 0 0
T3 18 18 0 0
T4 18 18 0 0
T5 18 18 0 0
T6 18 18 0 0
T29 18 18 0 0
T30 18 18 0 0
T31 18 18 0 0
T32 18 18 0 0

Line Coverage for Instance : tb.dut.intr_hw_pkt_received
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_hw_pkt_received
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T5

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T4,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT18,T49,T50
10CoveredT3,T4,T5
11CoveredT18,T50,T51

Branch Coverage for Instance : tb.dut.intr_hw_pkt_received
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_hw_pkt_received
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_hw_pkt_sent
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_hw_pkt_sent
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T30

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT4,T5,T30

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT7,T17,T20
10CoveredT4,T5,T30
11CoveredT7,T17,T20

Branch Coverage for Instance : tb.dut.intr_hw_pkt_sent
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_hw_pkt_sent
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_av_out_empty
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_av_out_empty
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT52,T53,T54
10CoveredT1,T2,T3
11CoveredT52,T53,T54

Branch Coverage for Instance : tb.dut.intr_av_out_empty
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_av_out_empty
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_rx_full
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_rx_full
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT55,T56,T57

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT55,T56,T57

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT58
10CoveredT55,T56,T57
11CoveredT58

Branch Coverage for Instance : tb.dut.intr_rx_full
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_rx_full
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_av_setup_empty
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 2 2
76 1 2
MISSING_ELSE
81 1 1
83 1 1
88 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_av_setup_empty
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT59,T60
10CoveredT1,T2,T3
11CoveredT59,T60

Branch Coverage for Instance : tb.dut.intr_av_setup_empty
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 76 if (reg2hw_intr_test_qe_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_av_setup_empty
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_powered
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_powered
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

Branch Coverage for Instance : tb.dut.intr_powered
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_powered
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_link_suspend
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_link_suspend
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T39
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T39
10CoveredT6,T7,T39

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT6,T7,T39
11Not Covered

Branch Coverage for Instance : tb.dut.intr_link_suspend
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_link_suspend
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_link_resume
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_link_resume
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T39,T42
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T39,T42
10CoveredT6,T39,T42

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT6,T39,T42
11Not Covered

Branch Coverage for Instance : tb.dut.intr_link_resume
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_link_resume
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_link_in_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_link_in_err
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT61,T62,T63
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT61,T62,T63
10CoveredT61,T62,T63

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT61,T62,T63
11Not Covered

Branch Coverage for Instance : tb.dut.intr_link_in_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_link_in_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_rx_pid_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_rx_pid_err
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T64,T65
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T64,T65
10CoveredT6,T64,T65

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT6,T64,T65
11Not Covered

Branch Coverage for Instance : tb.dut.intr_rx_pid_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_rx_pid_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_rx_bitstuff_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_rx_bitstuff_err
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T66,T67
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T66,T67
10CoveredT6,T66,T67

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT6,T66,T67
11Not Covered

Branch Coverage for Instance : tb.dut.intr_rx_bitstuff_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_rx_bitstuff_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_frame
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_frame
TotalCoveredPercent
Conditions12758.33
Logical12758.33
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T5
10CoveredT2,T4,T5

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T5
11Not Covered

Branch Coverage for Instance : tb.dut.intr_frame
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_frame
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_av_overflow
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_av_overflow
TotalCoveredPercent
Conditions12866.67
Logical12866.67
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT68,T69,T70
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT2,T3,T4
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT68,T69,T70
10CoveredT68,T69,T70

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT68,T69,T70
10Not Covered
11CoveredT68,T69,T70

Branch Coverage for Instance : tb.dut.intr_av_overflow
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_av_overflow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_disconnected
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_disconnected
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT2,T40,T45
10CoveredT1,T2,T3
11CoveredT2,T40,T45

Branch Coverage for Instance : tb.dut.intr_disconnected
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_disconnected
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_host_lost
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_host_lost
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T31
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T5,T31
10CoveredT4,T5,T31

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT71
10CoveredT4,T5,T31
11CoveredT71

Branch Coverage for Instance : tb.dut.intr_host_lost
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_host_lost
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_link_reset
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_link_reset
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT72
10CoveredT1,T2,T3
11CoveredT72

Branch Coverage for Instance : tb.dut.intr_link_reset
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_link_reset
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_link_out_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_link_out_err
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T31,T6
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T31,T6
10CoveredT1,T31,T6

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT73,T74,T75
10CoveredT1,T31,T6
11CoveredT73,T74,T75

Branch Coverage for Instance : tb.dut.intr_link_out_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_link_out_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

Line Coverage for Instance : tb.dut.intr_rx_crc_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
62 1 1
64 1 1
67 1 1
69 1 1
95 1 1
96 1 1
98 1 1


Cond Coverage for Instance : tb.dut.intr_rx_crc_err
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T66
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T3,T4
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T66
10CoveredT1,T6,T66

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT1,T76,T77
10CoveredT6,T66,T67
11CoveredT1,T76,T77

Branch Coverage for Instance : tb.dut.intr_rx_crc_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 95 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.intr_rx_crc_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 2434 2434 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2434 2434 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%