Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19696892	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	20006052	1		T1	16		T2	7		T3	77

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	39178056	1		T1	16		T2	2		T3	53
values[0x0]	261589	1		T1	8		T2	4		T3	19
values[0x1]	263299	1		T1	3		T2	4		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15710182	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	23992762	1		T1	20		T2	7		T3	82

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	503661	1		T2	3		T3	2		T4	174
valid_sources[0x01]	136202	1		T4	156		T5	865		T23	3
valid_sources[0x02]	119671	1		T1	1		T4	246		T5	762
valid_sources[0x03]	121600	1		T4	169		T5	682		T6	118
valid_sources[0x04]	119605	1		T4	171		T5	676		T6	143
valid_sources[0x05]	119769	1		T3	1		T4	153		T5	799
valid_sources[0x06]	120055	1		T4	202		T5	717		T23	3
valid_sources[0x07]	120506	1		T4	144		T5	663		T6	138
valid_sources[0x08]	119163	1		T4	171		T5	609		T6	161
valid_sources[0x09]	120908	1		T1	1		T3	1		T4	197
valid_sources[0x0a]	120023	1		T3	1		T4	180		T5	621
valid_sources[0x0b]	119422	1		T4	161		T5	555		T19	1
valid_sources[0x0c]	118307	1		T4	169		T5	632		T6	175
valid_sources[0x0d]	118957	1		T4	174		T5	742		T20	1
valid_sources[0x0e]	118282	1		T3	1		T4	169		T5	732
valid_sources[0x0f]	122421	1		T4	184		T5	708		T19	1
valid_sources[0x10]	385474	1		T1	1		T4	199		T5	815
valid_sources[0x11]	160772	1		T2	1		T4	193		T5	669
valid_sources[0x12]	120253	1		T1	4		T4	146		T5	740
valid_sources[0x13]	146968	1		T4	164		T5	822		T19	2
valid_sources[0x14]	191758	1		T3	1		T4	165		T5	680
valid_sources[0x15]	166571	1		T4	186		T5	800		T23	33
valid_sources[0x16]	465690	1		T4	171		T5	590		T19	1
valid_sources[0x17]	119290	1		T4	170		T5	706		T6	127
valid_sources[0x18]	119749	1		T3	3		T4	154		T5	571
valid_sources[0x19]	121379	1		T4	179		T5	811		T22	1
valid_sources[0x1a]	120902	1		T3	1		T4	160		T5	649
valid_sources[0x1b]	118210	1		T3	1		T4	197		T5	641
valid_sources[0x1c]	223981	1		T3	1		T4	208		T5	638
valid_sources[0x1d]	272677	1		T4	223		T5	871		T6	101
valid_sources[0x1e]	119629	1		T4	161		T18	1		T5	731
valid_sources[0x1f]	121877	1		T4	157		T5	595		T6	131
valid_sources[0x20]	173040	1		T3	1		T4	178		T5	803
valid_sources[0x21]	119330	1		T4	170		T5	607		T6	132
valid_sources[0x22]	119105	1		T4	158		T5	761		T6	130
valid_sources[0x23]	118599	1		T4	186		T5	691		T6	138
valid_sources[0x24]	119618	1		T4	155		T5	676		T23	17
valid_sources[0x25]	122579	1		T7	7		T17	3		T4	191
valid_sources[0x26]	221759	1		T4	182		T5	753		T6	153
valid_sources[0x27]	117722	1		T4	204		T5	532		T6	157
valid_sources[0x28]	119167	1		T7	2		T4	151		T5	625
valid_sources[0x29]	154959	1		T4	205		T5	878		T23	5
valid_sources[0x2a]	152103	1		T4	154		T5	656		T6	141
valid_sources[0x2b]	118044	1		T2	1		T3	1		T4	159
valid_sources[0x2c]	118222	1		T3	2		T4	197		T5	786
valid_sources[0x2d]	121320	1		T4	208		T5	729		T6	164
valid_sources[0x2e]	122793	1		T4	198		T5	862		T6	167
valid_sources[0x2f]	121149	1		T4	160		T5	623		T20	1
valid_sources[0x30]	293596	1		T1	1		T4	149		T5	681
valid_sources[0x31]	161425	1		T4	211		T5	563		T29	10
valid_sources[0x32]	178692	1		T7	3		T4	167		T5	698
valid_sources[0x33]	119474	1		T3	1		T4	189		T5	587
valid_sources[0x34]	119798	1		T3	1		T7	3		T4	180
valid_sources[0x35]	118228	1		T4	179		T5	732		T23	1
valid_sources[0x36]	119192	1		T4	204		T5	733		T6	157
valid_sources[0x37]	119024	1		T4	239		T5	663		T6	173
valid_sources[0x38]	118567	1		T1	1		T4	152		T5	659
valid_sources[0x39]	121228	1		T7	3		T4	169		T5	626
valid_sources[0x3a]	119191	1		T4	182		T5	801		T6	162
valid_sources[0x3b]	118866	1		T4	218		T5	591		T23	9
valid_sources[0x3c]	122383	1		T4	182		T5	797		T20	1
valid_sources[0x3d]	119936	1		T4	157		T5	590		T6	148
valid_sources[0x3e]	152998	1		T4	178		T5	695		T23	16
valid_sources[0x3f]	120072	1		T3	1		T4	197		T5	671
valid_sources[0x40]	120263	1		T4	155		T5	795		T23	5
valid_sources[0x41]	119019	1		T7	4		T4	151		T18	2
valid_sources[0x42]	121225	1		T4	164		T5	703		T23	13
valid_sources[0x43]	120431	1		T4	154		T5	785		T6	148
valid_sources[0x44]	194119	1		T2	1		T4	142		T5	619
valid_sources[0x45]	120108	1		T4	172		T5	859		T6	141
valid_sources[0x46]	118032	1		T4	185		T5	684		T6	164
valid_sources[0x47]	118939	1		T1	1		T4	172		T5	574
valid_sources[0x48]	121026	1		T4	197		T5	638		T6	127
valid_sources[0x49]	557932	1		T1	1		T4	171		T5	520
valid_sources[0x4a]	119274	1		T4	168		T5	774		T6	133
valid_sources[0x4b]	118005	1		T4	182		T5	620		T23	1
valid_sources[0x4c]	119213	1		T4	148		T5	766		T19	1
valid_sources[0x4d]	121438	1		T4	185		T5	625		T6	135
valid_sources[0x4e]	491414	1		T3	1		T4	189		T5	645
valid_sources[0x4f]	153134	1		T3	1		T4	197		T5	589
valid_sources[0x50]	120972	1		T7	5		T4	175		T5	659
valid_sources[0x51]	119063	1		T4	160		T5	633		T6	166
valid_sources[0x52]	120528	1		T4	218		T5	658		T6	141
valid_sources[0x53]	190594	1		T4	177		T18	2		T5	706
valid_sources[0x54]	185623	1		T3	2		T4	222		T5	858
valid_sources[0x55]	481270	1		T4	215		T5	581		T6	136
valid_sources[0x56]	120330	1		T3	2		T4	186		T5	602
valid_sources[0x57]	119932	1		T2	1		T4	160		T5	776
valid_sources[0x58]	118689	1		T4	168		T5	859		T23	21
valid_sources[0x59]	120677	1		T1	1		T3	1		T4	165
valid_sources[0x5a]	121036	1		T4	194		T5	543		T21	1
valid_sources[0x5b]	119495	1		T4	203		T5	784		T6	158
valid_sources[0x5c]	119553	1		T3	2		T4	219		T5	551
valid_sources[0x5d]	218411	1		T4	182		T5	725		T6	103
valid_sources[0x5e]	119977	1		T4	165		T5	832		T238	3
valid_sources[0x5f]	119624	1		T4	152		T5	647		T6	128
valid_sources[0x60]	119656	1		T4	154		T5	686		T6	118
valid_sources[0x61]	119148	1		T4	199		T5	722		T6	109
valid_sources[0x62]	396834	1		T4	199		T5	702		T23	10
valid_sources[0x63]	120632	1		T7	10		T17	3		T4	216
valid_sources[0x64]	564034	1		T3	3		T4	154		T5	735
valid_sources[0x65]	119584	1		T3	2		T4	245		T5	588
valid_sources[0x66]	154019	1		T4	184		T5	814		T21	1
valid_sources[0x67]	118598	1		T4	183		T5	740		T6	134
valid_sources[0x68]	163562	1		T4	152		T5	716		T6	155
valid_sources[0x69]	120608	1		T4	142		T5	730		T6	152
valid_sources[0x6a]	121736	1		T7	16		T4	189		T5	579
valid_sources[0x6b]	120473	1		T3	1		T4	195		T5	844
valid_sources[0x6c]	121373	1		T4	174		T5	641		T23	31
valid_sources[0x6d]	121095	1		T4	186		T5	649		T6	126
valid_sources[0x6e]	120297	1		T7	3		T4	202		T5	669
valid_sources[0x6f]	204063	1		T4	216		T5	656		T6	139
valid_sources[0x70]	120468	1		T4	165		T5	598		T6	153
valid_sources[0x71]	119538	1		T4	176		T5	673		T6	130
valid_sources[0x72]	121264	1		T3	1		T4	167		T5	724
valid_sources[0x73]	147389	1		T4	213		T5	960		T20	3
valid_sources[0x74]	120432	1		T4	219		T5	644		T6	152
valid_sources[0x75]	120682	1		T4	140		T5	656		T21	2
valid_sources[0x76]	118949	1		T3	2		T4	194		T18	1
valid_sources[0x77]	120880	1		T4	163		T5	573		T6	119
valid_sources[0x78]	144191	1		T3	2		T4	187		T5	794
valid_sources[0x79]	118614	1		T1	1		T4	146		T5	578
valid_sources[0x7a]	118361	1		T4	158		T5	714		T23	10
valid_sources[0x7b]	118780	1		T4	163		T5	634		T6	147
valid_sources[0x7c]	120616	1		T4	200		T5	701		T6	127
valid_sources[0x7d]	119034	1		T2	2		T4	186		T5	659
valid_sources[0x7e]	118790	1		T3	3		T7	2		T4	182
valid_sources[0x7f]	120967	1		T4	202		T5	613		T23	11
valid_sources[0x80]	119366	1		T3	1		T7	1		T4	212

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19600910

1

T1

9

T2

1

T3

50

values[0x0]

all_enables

biggest_size

209162

1

T1

6

T2

4

T3

14

values[0x1]

all_enables

biggest_size

195980

1

T1

1

T2

2

T3

13