Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19712088	1		T1	11		T2	3		T3	14
full_word	20007044	1		T1	16		T2	7		T3	77

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	39718832	1		T1	27		T2	10		T3	91
auto[TlIntgErrCmd]	103	1		T227	5		T228	4		T229	3
auto[TlIntgErrData]	102	1		T227	9		T228	4		T229	4
auto[TlIntgErrBoth]	95	1		T227	6		T228	2		T229	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	39179955	1		T1	16		T2	2		T3	53
auto[1]	539177	1		T1	11		T2	8		T3	38

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	19578714	1		T1	7		T2	1		T3	3
auto[TlIntgErrNone]	partial	auto[1]	133091	1		T1	4		T2	2		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	19601087	1		T1	9		T2	1		T3	50
auto[TlIntgErrNone]	full_word	auto[1]	405940	1		T1	7		T2	6		T3	27
auto[TlIntgErrCmd]	partial	auto[0]	52	1		T227	5		T228	3		T229	2
auto[TlIntgErrCmd]	partial	auto[1]	45	1		T228	1		T229	1		T232	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T295	1		T298	1		T299	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T293	1		T300	1		T297	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T227	6		T228	3		T229	2
auto[TlIntgErrData]	partial	auto[1]	41	1		T227	3		T228	1		T229	2
auto[TlIntgErrData]	full_word	auto[0]	2	1		T232	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T301	1		T302	3		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T227	2		T228	1		T229	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T227	4		T228	1		T229	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T294	1		T296	1		T298	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T232	1		-	-		-	-